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Changed connectors Output Input BUS

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1 parent 8c28053 commit 1dca5b49c716f3ba13db316577447f394d1d4f77 @cachinchilla3000 cachinchilla3000 committed Dec 13, 2012
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@@ -1,4 +1,4 @@
-Cmp-Mod V01 Created by CvPcb (2012-oct-18)-testing date = Tue 27 Nov 2012 02:59:28 PM EST
+Cmp-Mod V01 Created by CvPcb (2012-nov-02)-testing date = Thu 13 Dec 2012 02:46:55 PM EST
BeginCmp
TimeStamp = /508A0752;
@@ -120,10 +120,10 @@ IdModule = SMD Microfit 2pin;
EndCmp
BeginCmp
-TimeStamp = /508A13E0;
+TimeStamp = /50CA2FDE;
Reference = P2;
-ValeurCmp = Output_BUS;
-IdModule = pin_array_8x1;
+ValeurCmp = OUT_BUS;
+IdModule = pin_array_4x2;
EndCmp
BeginCmp
@@ -169,6 +169,13 @@ IdModule = pin_array_7x1;
EndCmp
BeginCmp
+TimeStamp = /50CA2BC3;
+Reference = R1;
+ValeurCmp = 1M;
+IdModule = SM0805_NonPol;
+EndCmp
+
+BeginCmp
TimeStamp = /4F652722;
Reference = R2;
ValeurCmp = 10k;
@@ -1,4 +1,4 @@
-# EESchema Netlist Version 1.1 created Tue 27 Nov 2012 02:59:11 PM EST
+# EESchema Netlist Version 1.1 created Thu 13 Dec 2012 02:46:49 PM EST
(
( /4F652571 $noname R5 330 {Lib=R}
( 1 N-000049 )
@@ -118,16 +118,6 @@
( 2 /VLED )
( 3 VCC )
)
- ( /508A13E0 $noname P2 Output_BUS {Lib=CONN_8}
- ( 1 /11 )
- ( 2 /D9 )
- ( 3 /D10 )
- ( 4 /D3 )
- ( 5 /13 )
- ( 6 /VLED )
- ( 7 VCC )
- ( 8 GND )
- )
( /508A16CC $noname K3 5V {Lib=CONN_3}
( 1 VCC )
( 2 VCC )
@@ -221,6 +211,20 @@
( 6 ? )
( 7 ? )
)
+ ( /50CA2BC3 $noname R1 1M {Lib=R}
+ ( 1 /TOSC1 )
+ ( 2 /TOSC2 )
+ )
+ ( /50CA2FDE $noname P2 OUT_BUS {Lib=CONN_4X2}
+ ( 1 /D9 )
+ ( 2 /11 )
+ ( 3 /D10 )
+ ( 4 /VLED )
+ ( 5 /D3 )
+ ( 6 VCC )
+ ( 7 /13 )
+ ( 8 GND )
+ )
)
*
{ Allowed footprints by component:
@@ -316,168 +320,177 @@ $component VR1
TO263-5
TO263-5-D2PAK
$endlist
+$component R1
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 1 "VCC" "VCC"
- K3 1
- IC1 18
+ P2 6
+ J1 1
+ R2 1
+ VR1 4
+ P8 2
+ C3 1
+ U1 20
+ U1 4
K1 3
+ R4 2
K3 3
K3 2
- C6 1
- C3 1
- P7 2
- VR1 4
- C5 1
- U1 4
- P2 7
+ K3 1
+ IC1 18
IC1 6
- U1 20
- P8 2
IC1 4
- J1 1
- R4 2
C7 1
- R2 1
-Net 2 "GND" "GND"
- D2 2
- SW2 2
- P8 1
- SW1 1
- IC1 21
- IC1 5
- IC1 3
- C7 2
- C6 2
- U1 18
- U1 26
- U1 25
+ C6 1
+ C5 1
+ P7 2
+Net 5 "/12V" "12V"
+ VR1 2
+ K1 1
+ SW1 3
+ P1 2
+ K2 3
+ C1 1
+ K2 1
+ K2 2
+Net 7 "/EN_reg" "EN_reg"
+ C2 1
+ SW1 2
+ VR1 1
+Net 8 "GND" "GND"
C5 2
- C8 2
+ U1 25
+ U1 26
+ U1 18
D1 2
- J1 4
+ R3 2
+ IC1 21
+ J1 5
P7 6
+ C7 2
J1 6
- U1 21
- U1 11
+ C6 2
U1 7
X1 3
- J1 5
- VR1 3
- K4 1
- K4 2
- K4 3
- VR1 6
+ U1 11
+ C8 2
+ J1 4
+ SW2 2
+ D2 2
+ U1 21
P2 8
- C2 2
- P1 1
+ SW1 1
+ IC1 3
C1 2
+ K4 3
+ K4 2
+ K4 1
+ IC1 5
+ P1 1
C3 2
- R3 2
-Net 3 "/VLED" "VLED"
- K1 2
- P2 6
-Net 4 "/13" "13"
- P2 5
+ C2 2
+ P8 1
+ VR1 3
+ VR1 6
+Net 9 "/13" "13"
R5 2
P7 3
+ P2 7
IC1 17
-Net 5 "/D3" "D3"
+Net 10 "/D3" "D3"
IC1 1
+ P2 5
+Net 11 "/VLED" "VLED"
+ K1 2
P2 4
-Net 6 "/D10" "D10"
- IC1 14
+Net 12 "/D10" "D10"
P2 3
-Net 7 "/D9" "D9"
+ IC1 14
+Net 13 "/11" "11"
+ IC1 15
+ P7 4
P2 2
+Net 14 "/D9" "D9"
IC1 13
-Net 8 "/11" "11"
- IC1 15
P2 1
- P7 4
-Net 9 "/12V" "12V"
- VR1 2
- P1 2
- SW1 3
- K2 3
- K2 2
- K2 1
- C1 1
- K1 1
-Net 10 "/A5" "A5"
- P6 4
+Net 20 "/D6" "D6"
+ IC1 10
+ P4 2
+Net 21 "/A1" "A1"
+ P5 2
+ IC1 24
+Net 22 "/A0" "A0"
+ IC1 23
+ P5 1
+Net 23 "/A5" "A5"
IC1 28
-Net 13 "/A4" "A4"
- P6 3
+ P6 4
+Net 24 "/A4" "A4"
IC1 27
-Net 19 "/EN_reg" "EN_reg"
- SW1 2
- VR1 1
- C2 1
-Net 20 "/D7" "D7"
+ P6 3
+Net 25 "/A3" "A3"
+ IC1 26
+ P6 2
+Net 26 "/A2" "A2"
+ IC1 25
+ P6 1
+Net 27 "/D8" "D8"
+ IC1 12
+ P4 4
+Net 28 "/D7" "D7"
IC1 11
P4 3
-Net 21 "/D6" "D6"
- IC1 10
- P4 2
-Net 22 "/D5" "D5"
- IC1 9
+Net 29 "/D5" "D5"
P4 1
-Net 23 "/D4" "D4"
- IC1 2
+ IC1 9
+Net 30 "/D4" "D4"
P3 4
-Net 24 "/D2" "D2"
- IC1 32
+ IC1 2
+Net 31 "/D2" "D2"
P3 3
-Net 25 "/D0" "D0"
- IC1 30
+ IC1 32
+Net 32 "/D0" "D0"
P3 2
+ IC1 30
U1 1
-Net 26 "/D1" "D1"
- P3 1
+Net 33 "/D1" "D1"
U1 5
+ P3 1
IC1 31
-Net 27 "/D8" "D8"
- P4 4
- IC1 12
-Net 30 "/A1" "A1"
- IC1 24
- P5 2
-Net 31 "/A0" "A0"
- P5 1
- IC1 23
-Net 32 "/A3" "A3"
- P6 2
- IC1 26
-Net 33 "/A2" "A2"
- IC1 25
- P6 1
Net 37 "/D-" "D-"
- J1 2
U1 16
+ J1 2
Net 42 "/12" "12"
IC1 16
P7 1
Net 48 "/RESET" "RESET"
- P7 5
SW2 1
- IC1 29
C4 1
+ P7 5
R2 2
+ IC1 29
Net 49 "" ""
R5 1
D2 1
Net 50 "/DTR" "DTR"
+ R3 1
C4 2
U1 2
- R3 1
Net 51 "/TOSC1" "TOSC1"
X1 2
IC1 7
+ R1 1
Net 52 "/TOSC2" "TOSC2"
X1 1
IC1 8
+ R1 2
Net 53 "" ""
D1 1
R4 1
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