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  1. 组成原理课程实验:MIPS 流水线CPU,实现36条指令,转发,冒险检测

    Verilog 3 1

  2. 编译原理课程实验:拓展的PL0编译器

    C

  3. 操作系统原理与设计课程实验:在一个简单的操作系统Nachos上进行功能补全

    C++

  4. 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,分支预测器或简化Cache(待实现)

    Verilog

  5. Forked from ustcwpz/USTC-CS-Courses-Resource

    ❤️中国科学技术大学计算机学院课程资源(https://mbinary.coding.me/ustc-cs/)

    C++ 1 2

  6. SE Project1

    HTML 1

105 contributions in the last year

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Contribution activity

June 2019

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May 2019

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