3fc02: f6 c0 rjmp .+492 ; 0x3fdf0 0003fc04

: 3fc04: 1f 92 push r1 3fc06: cd b7 in r28, 0x3d ; 61 3fc08: de b7 in r29, 0x3e ; 62 3fc0a: 11 24 eor r1, r1 3fc0c: 84 b7 in r24, 0x34 ; 52 3fc0e: 88 23 and r24, r24 3fc10: 49 f0 breq .+18 ; 0x3fc24 3fc12: 98 2f mov r25, r24 3fc14: 9a 70 andi r25, 0x0A ; 10 3fc16: 92 30 cpi r25, 0x02 ; 2 3fc18: 29 f0 breq .+10 ; 0x3fc24 3fc1a: 81 ff sbrs r24, 1 3fc1c: 02 c0 rjmp .+4 ; 0x3fc22 3fc1e: 97 ef ldi r25, 0xF7 ; 247 3fc20: 94 bf out 0x34, r25 ; 52 3fc22: 1e d1 rcall .+572 ; 0x3fe60 3fc24: 85 e0 ldi r24, 0x05 ; 5 3fc26: 80 93 81 00 sts 0x0081, r24 3fc2a: 82 e0 ldi r24, 0x02 ; 2 3fc2c: 80 93 c0 00 sts 0x00C0, r24 3fc30: 88 e1 ldi r24, 0x18 ; 24 3fc32: 80 93 c1 00 sts 0x00C1, r24 3fc36: 86 e0 ldi r24, 0x06 ; 6 3fc38: 80 93 c2 00 sts 0x00C2, r24 3fc3c: 80 e1 ldi r24, 0x10 ; 16 3fc3e: 80 93 c4 00 sts 0x00C4, r24 3fc42: 8f e0 ldi r24, 0x0F ; 15 3fc44: f8 d0 rcall .+496 ; 0x3fe36 3fc46: 25 9a sbi 0x04, 5 ; 4 3fc48: 26 e0 ldi r18, 0x06 ; 6 3fc4a: 80 e3 ldi r24, 0x30 ; 48 3fc4c: 9c ef ldi r25, 0xFC ; 252 3fc4e: 31 e0 ldi r19, 0x01 ; 1 3fc50: 90 93 85 00 sts 0x0085, r25 3fc54: 80 93 84 00 sts 0x0084, r24 3fc58: 36 bb out 0x16, r19 ; 22 3fc5a: b0 9b sbis 0x16, 0 ; 22 3fc5c: fe cf rjmp .-4 ; 0x3fc5a 3fc5e: 1d 9a sbi 0x03, 5 ; 3 3fc60: a8 95 wdr 3fc62: 21 50 subi r18, 0x01 ; 1 3fc64: a9 f7 brne .-22 ; 0x3fc50 3fc66: 81 2c mov r8, r1 3fc68: 91 2c mov r9, r1 3fc6a: d9 d0 rcall .+434 ; 0x3fe1e 3fc6c: 81 34 cpi r24, 0x41 ; 65 3fc6e: 71 f4 brne .+28 ; 0x3fc8c 3fc70: d6 d0 rcall .+428 ; 0x3fe1e 3fc72: 89 83 std Y+1, r24 ; 0x01 3fc74: e6 d0 rcall .+460 ; 0x3fe42 3fc76: 89 81 ldd r24, Y+1 ; 0x01 3fc78: 82 38 cpi r24, 0x82 ; 130 3fc7a: 09 f4 brne .+2 ; 0x3fc7e 3fc7c: af c0 rjmp .+350 ; 0x3fddc 3fc7e: 81 38 cpi r24, 0x81 ; 129 3fc80: 11 f4 brne .+4 ; 0x3fc86 3fc82: 86 e0 ldi r24, 0x06 ; 6 3fc84: 01 c0 rjmp .+2 ; 0x3fc88 3fc86: 83 e0 ldi r24, 0x03 ; 3 3fc88: c3 d0 rcall .+390 ; 0x3fe10 3fc8a: af c0 rjmp .+350 ; 0x3fdea 3fc8c: 82 34 cpi r24, 0x42 ; 66 3fc8e: 11 f4 brne .+4 ; 0x3fc94 3fc90: 84 e1 ldi r24, 0x14 ; 20 3fc92: 03 c0 rjmp .+6 ; 0x3fc9a 3fc94: 85 34 cpi r24, 0x45 ; 69 3fc96: 19 f4 brne .+6 ; 0x3fc9e 3fc98: 85 e0 ldi r24, 0x05 ; 5 3fc9a: db d0 rcall .+438 ; 0x3fe52 3fc9c: a6 c0 rjmp .+332 ; 0x3fdea 3fc9e: 85 35 cpi r24, 0x55 ; 85 3fca0: 79 f4 brne .+30 ; 0x3fcc0 3fca2: bd d0 rcall .+378 ; 0x3fe1e 3fca4: 88 2e mov r8, r24 3fca6: bb d0 rcall .+374 ; 0x3fe1e 3fca8: 91 2c mov r9, r1 3fcaa: 98 2a or r9, r24 3fcac: 8b b7 in r24, 0x3b ; 59 3fcae: 97 fe sbrs r9, 7 3fcb0: 02 c0 rjmp .+4 ; 0x3fcb6 3fcb2: 81 60 ori r24, 0x01 ; 1 3fcb4: 01 c0 rjmp .+2 ; 0x3fcb8 3fcb6: 8e 7f andi r24, 0xFE ; 254 3fcb8: 8b bf out 0x3b, r24 ; 59 3fcba: 88 0c add r8, r8 3fcbc: 99 1c adc r9, r9 3fcbe: 94 c0 rjmp .+296 ; 0x3fde8 3fcc0: 86 35 cpi r24, 0x56 ; 86 3fcc2: 81 f4 brne .+32 ; 0x3fce4 3fcc4: ac d0 rcall .+344 ; 0x3fe1e 3fcc6: 8d 34 cpi r24, 0x4D ; 77 3fcc8: 49 f4 brne .+18 ; 0x3fcdc 3fcca: a9 d0 rcall .+338 ; 0x3fe1e 3fccc: 1b b7 in r17, 0x3b ; 59 3fcce: a7 d0 rcall .+334 ; 0x3fe1e 3fcd0: 88 0f add r24, r24 3fcd2: 11 70 andi r17, 0x01 ; 1 3fcd4: 81 2b or r24, r17 3fcd6: 8b bf out 0x3b, r24 ; 59 3fcd8: 81 e0 ldi r24, 0x01 ; 1 3fcda: 01 c0 rjmp .+2 ; 0x3fcde 3fcdc: 83 e0 ldi r24, 0x03 ; 3 3fcde: b9 d0 rcall .+370 ; 0x3fe52 3fce0: 80 e0 ldi r24, 0x00 ; 0 3fce2: d2 cf rjmp .-92 ; 0x3fc88 3fce4: 84 36 cpi r24, 0x64 ; 100 3fce6: 09 f0 breq .+2 ; 0x3fcea 3fce8: 4c c0 rjmp .+152 ; 0x3fd82 3fcea: 99 d0 rcall .+306 ; 0x3fe1e 3fcec: e8 2e mov r14, r24 3fcee: f1 2c mov r15, r1 3fcf0: fe 2c mov r15, r14 3fcf2: ee 24 eor r14, r14 3fcf4: 94 d0 rcall .+296 ; 0x3fe1e 3fcf6: e8 2a or r14, r24 3fcf8: 92 d0 rcall .+292 ; 0x3fe1e 3fcfa: b8 2e mov r11, r24 3fcfc: 87 01 movw r16, r14 3fcfe: c1 2c mov r12, r1 3fd00: dd 24 eor r13, r13 3fd02: d3 94 inc r13 3fd04: 8c d0 rcall .+280 ; 0x3fe1e 3fd06: f6 01 movw r30, r12 3fd08: 81 93 st Z+, r24 3fd0a: 6f 01 movw r12, r30 3fd0c: 01 50 subi r16, 0x01 ; 1 3fd0e: 11 09 sbc r17, r1 3fd10: 01 15 cp r16, r1 3fd12: 11 05 cpc r17, r1 3fd14: b9 f7 brne .-18 ; 0x3fd04 3fd16: 95 d0 rcall .+298 ; 0x3fe42 3fd18: f5 e4 ldi r31, 0x45 ; 69 3fd1a: bf 12 cpse r11, r31 3fd1c: 12 c0 rjmp .+36 ; 0x3fd42 3fd1e: e8 0c add r14, r8 3fd20: f9 1c adc r15, r9 3fd22: 84 01 movw r16, r8 3fd24: c1 2c mov r12, r1 3fd26: dd 24 eor r13, r13 3fd28: d3 94 inc r13 3fd2a: 0e 15 cp r16, r14 3fd2c: 1f 05 cpc r17, r15 3fd2e: 09 f4 brne .+2 ; 0x3fd32 3fd30: 5c c0 rjmp .+184 ; 0x3fdea 3fd32: f6 01 movw r30, r12 3fd34: 61 91 ld r22, Z+ 3fd36: 6f 01 movw r12, r30 3fd38: c8 01 movw r24, r16 3fd3a: a0 d0 rcall .+320 ; 0x3fe7c <__eewr_byte_m2561> 3fd3c: 0f 5f subi r16, 0xFF ; 255 3fd3e: 1f 4f sbci r17, 0xFF ; 255 3fd40: f4 cf rjmp .-24 ; 0x3fd2a 3fd42: 40 e0 ldi r20, 0x00 ; 0 3fd44: 50 e0 ldi r21, 0x00 ; 0 3fd46: 63 e0 ldi r22, 0x03 ; 3 3fd48: c4 01 movw r24, r8 3fd4a: 52 d0 rcall .+164 ; 0x3fdf0 3fd4c: 00 e0 ldi r16, 0x00 ; 0 3fd4e: 10 e0 ldi r17, 0x00 ; 0 3fd50: f8 01 movw r30, r16 3fd52: f3 95 inc r31 3fd54: 40 81 ld r20, Z 3fd56: f8 01 movw r30, r16 3fd58: ef 5f subi r30, 0xFF ; 255 3fd5a: fe 4f sbci r31, 0xFE ; 254 3fd5c: 80 81 ld r24, Z 3fd5e: 50 e0 ldi r21, 0x00 ; 0 3fd60: 58 2b or r21, r24 3fd62: 61 e0 ldi r22, 0x01 ; 1 3fd64: c8 01 movw r24, r16 3fd66: 88 0d add r24, r8 3fd68: 99 1d adc r25, r9 3fd6a: 42 d0 rcall .+132 ; 0x3fdf0 3fd6c: 0e 5f subi r16, 0xFE ; 254 3fd6e: 1f 4f sbci r17, 0xFF ; 255 3fd70: e0 16 cp r14, r16 3fd72: f1 06 cpc r15, r17 3fd74: 69 f7 brne .-38 ; 0x3fd50 3fd76: 40 e0 ldi r20, 0x00 ; 0 3fd78: 50 e0 ldi r21, 0x00 ; 0 3fd7a: 65 e0 ldi r22, 0x05 ; 5 3fd7c: c4 01 movw r24, r8 3fd7e: 38 d0 rcall .+112 ; 0x3fdf0 3fd80: 34 c0 rjmp .+104 ; 0x3fdea 3fd82: 84 37 cpi r24, 0x74 ; 116 3fd84: 21 f5 brne .+72 ; 0x3fdce 3fd86: 4b d0 rcall .+150 ; 0x3fe1e 3fd88: 08 2f mov r16, r24 3fd8a: 10 e0 ldi r17, 0x00 ; 0 3fd8c: 10 2f mov r17, r16 3fd8e: 00 27 eor r16, r16 3fd90: 46 d0 rcall .+140 ; 0x3fe1e 3fd92: 08 2b or r16, r24 3fd94: 44 d0 rcall .+136 ; 0x3fe1e 3fd96: 89 83 std Y+1, r24 ; 0x01 3fd98: 54 d0 rcall .+168 ; 0x3fe42 3fd9a: 89 81 ldd r24, Y+1 ; 0x01 3fd9c: 74 01 movw r14, r8 3fd9e: 85 34 cpi r24, 0x45 ; 69 3fda0: 61 f4 brne .+24 ; 0x3fdba 3fda2: c7 01 movw r24, r14 3fda4: 63 d0 rcall .+198 ; 0x3fe6c <__eerd_byte_m2561> 3fda6: 34 d0 rcall .+104 ; 0x3fe10 3fda8: 01 50 subi r16, 0x01 ; 1 3fdaa: 11 09 sbc r17, r1 3fdac: ff ef ldi r31, 0xFF ; 255 3fdae: ef 1a sub r14, r31 3fdb0: ff 0a sbc r15, r31 3fdb2: 01 15 cp r16, r1 3fdb4: 11 05 cpc r17, r1 3fdb6: a9 f7 brne .-22 ; 0x3fda2 3fdb8: 18 c0 rjmp .+48 ; 0x3fdea 3fdba: f7 01 movw r30, r14 3fdbc: 87 91 elpm r24, Z+ 3fdbe: 7f 01 movw r14, r30 3fdc0: 27 d0 rcall .+78 ; 0x3fe10 3fdc2: 01 50 subi r16, 0x01 ; 1 3fdc4: 11 09 sbc r17, r1 3fdc6: 01 15 cp r16, r1 3fdc8: 11 05 cpc r17, r1 3fdca: b9 f7 brne .-18 ; 0x3fdba 3fdcc: 0e c0 rjmp .+28 ; 0x3fdea 3fdce: 85 37 cpi r24, 0x75 ; 117 3fdd0: 39 f4 brne .+14 ; 0x3fde0 3fdd2: 37 d0 rcall .+110 ; 0x3fe42 3fdd4: 8e e1 ldi r24, 0x1E ; 30 3fdd6: 1c d0 rcall .+56 ; 0x3fe10 3fdd8: 88 e9 ldi r24, 0x98 ; 152 3fdda: 1a d0 rcall .+52 ; 0x3fe10 3fddc: 82 e0 ldi r24, 0x02 ; 2 3fdde: 54 cf rjmp .-344 ; 0x3fc88 3fde0: 81 35 cpi r24, 0x51 ; 81 3fde2: 11 f4 brne .+4 ; 0x3fde8 3fde4: 88 e0 ldi r24, 0x08 ; 8 3fde6: 27 d0 rcall .+78 ; 0x3fe36 3fde8: 2c d0 rcall .+88 ; 0x3fe42 3fdea: 80 e1 ldi r24, 0x10 ; 16 3fdec: 11 d0 rcall .+34 ; 0x3fe10 3fdee: 3d cf rjmp .-390 ; 0x3fc6a 0003fdf0 : * you could do fill-erase-write sequence with data!=0 in ERASE and * data=0 in WRITE */ static void do_spm(uint16_t address, uint8_t command, uint16_t data) { // Do spm stuff asm volatile ( 3fdf0: fc 01 movw r30, r24 3fdf2: 0a 01 movw r0, r20 3fdf4: 67 bf out 0x37, r22 ; 55 3fdf6: e8 95 spm 3fdf8: 11 24 eor r1, r1 ); // wait for spm to complete // it doesn't have much sense for __BOOT_PAGE_FILL, // but it doesn't hurt and saves some bytes on 'if' boot_spm_busy_wait(); 3fdfa: 07 b6 in r0, 0x37 ; 55 3fdfc: 00 fc sbrc r0, 0 3fdfe: fd cf rjmp .-6 ; 0x3fdfa #if defined(RWWSRE) // this 'if' condition should be: (command == __BOOT_PAGE_WRITE || command == __BOOT_PAGE_ERASE)... // but it's tweaked a little assuming that in every command we are interested in here, there // must be also SELFPRGEN set. If we skip checking this bit, we save here 4B if ((command & (_BV(PGWRT)|_BV(PGERS))) && (data == 0) ) { 3fe00: 66 70 andi r22, 0x06 ; 6 3fe02: 29 f0 breq .+10 ; 0x3fe0e 3fe04: 45 2b or r20, r21 3fe06: 19 f4 brne .+6 ; 0x3fe0e // Reenable read access to flash boot_rww_enable(); 3fe08: 81 e1 ldi r24, 0x11 ; 17 3fe0a: 87 bf out 0x37, r24 ; 55 3fe0c: e8 95 spm 3fe0e: 08 95 ret 0003fe10 : } } void putch(char ch) { #ifndef SOFT_UART while (!(UART_SRA & _BV(UDRE0))); 3fe10: 90 91 c0 00 lds r25, 0x00C0 3fe14: 95 ff sbrs r25, 5 3fe16: fc cf rjmp .-8 ; 0x3fe10 UART_UDR = ch; 3fe18: 80 93 c6 00 sts 0x00C6, r24 3fe1c: 08 95 ret 0003fe1e : [uartBit] "I" (UART_RX_BIT) : "r25" ); #else while(!(UART_SRA & _BV(RXC0))) 3fe1e: 80 91 c0 00 lds r24, 0x00C0 3fe22: 87 ff sbrs r24, 7 3fe24: fc cf rjmp .-8 ; 0x3fe1e ; if (!(UART_SRA & _BV(FE0))) { 3fe26: 80 91 c0 00 lds r24, 0x00C0 3fe2a: 84 fd sbrc r24, 4 3fe2c: 01 c0 rjmp .+2 ; 0x3fe30 } #endif // Watchdog functions. These are only safe with interrupts turned off. void watchdogReset() { __asm__ __volatile__ ( 3fe2e: a8 95 wdr * don't care that an invalid char is returned...) */ watchdogReset(); } ch = UART_UDR; 3fe30: 80 91 c6 00 lds r24, 0x00C6 LED_PIN |= _BV(LED); #endif #endif return ch; } 3fe34: 08 95 ret 0003fe36 : "wdr\n" ); } void watchdogConfig(uint8_t x) { WDTCSR = _BV(WDCE) | _BV(WDE); 3fe36: e0 e6 ldi r30, 0x60 ; 96 3fe38: f0 e0 ldi r31, 0x00 ; 0 3fe3a: 98 e1 ldi r25, 0x18 ; 24 3fe3c: 90 83 st Z, r25 WDTCSR = x; 3fe3e: 80 83 st Z, r24 3fe40: 08 95 ret 0003fe42 : do getch(); while (--count); verifySpace(); } void verifySpace() { if (getch() != CRC_EOP) { 3fe42: ed df rcall .-38 ; 0x3fe1e 3fe44: 80 32 cpi r24, 0x20 ; 32 3fe46: 19 f0 breq .+6 ; 0x3fe4e 3fe48: 88 e0 ldi r24, 0x08 ; 8 watchdogConfig(WATCHDOG_16MS); // shorten WD timeout 3fe4a: f5 df rcall .-22 ; 0x3fe36 3fe4c: ff cf rjmp .-2 ; 0x3fe4c 3fe4e: 84 e1 ldi r24, 0x14 ; 20 3fe50: df cf rjmp .-66 ; 0x3fe10 0003fe52 : ::[count] "M" (UART_B_VALUE) ); } #endif void getNch(uint8_t count) { 3fe52: cf 93 push r28 3fe54: c8 2f mov r28, r24 do getch(); while (--count); 3fe56: e3 df rcall .-58 ; 0x3fe1e 3fe58: c1 50 subi r28, 0x01 ; 1 3fe5a: e9 f7 brne .-6 ; 0x3fe56 3fe5c: cf 91 pop r28 verifySpace(); } 3fe5e: f1 cf rjmp .-30 ; 0x3fe42 0003fe60 : void appStart(uint8_t rstFlags) { // save the reset flags in the designated register // This can be saved in a main program by putting code in .init0 (which // executes before normal c init code) to save R2 to a global variable. __asm__ __volatile__ ("mov r2, %0\n" :: "r" (rstFlags)); 3fe60: 28 2e mov r2, r24 watchdogConfig(WATCHDOG_OFF); 3fe62: 80 e0 ldi r24, 0x00 ; 0 3fe64: e8 df rcall .-48 ; 0x3fe36 3fe66: e0 e0 ldi r30, 0x00 ; 0 // Note that appstart_vec is defined so that this works with either // real or virtual boot partitions. __asm__ __volatile__ ( 3fe68: ff 27 eor r31, r31 3fe6a: 09 94 ijmp 0003fe6c <__eerd_byte_m2561>: 3fe6c: f9 99 sbic 0x1f, 1 ; 31 3fe6e: fe cf rjmp .-4 ; 0x3fe6c <__eerd_byte_m2561> 3fe70: 92 bd out 0x22, r25 ; 34 3fe72: 81 bd out 0x21, r24 ; 33 3fe74: f8 9a sbi 0x1f, 0 ; 31 3fe76: 99 27 eor r25, r25 3fe78: 80 b5 in r24, 0x20 ; 32 3fe7a: 08 95 ret 0003fe7c <__eewr_byte_m2561>: 3fe7c: 26 2f mov r18, r22 0003fe7e <__eewr_r18_m2561>: 3fe7e: f9 99 sbic 0x1f, 1 ; 31 3fe80: fe cf rjmp .-4 ; 0x3fe7e <__eewr_r18_m2561> 3fe82: 1f ba out 0x1f, r1 ; 31 3fe84: 92 bd out 0x22, r25 ; 34 3fe86: 81 bd out 0x21, r24 ; 33 3fe88: 20 bd out 0x20, r18 ; 32 3fe8a: 0f b6 in r0, 0x3f ; 63 3fe8c: f8 94 cli 3fe8e: fa 9a sbi 0x1f, 2 ; 31 3fe90: f9 9a sbi 0x1f, 1 ; 31 3fe92: 0f be out 0x3f, r0 ; 63 3fe94: 01 96 adiw r24, 0x01 ; 1 3fe96: 08 95 ret