MIPS Instruction Set

Igor Smirnov edited this page Nov 15, 2015 · 3 revisions

Instruction format

MIPS is a RISC processor, so every instruction has the same length — 32 bits (4 bytes). These bits have different meanings according to their displacement. They can be combined in following groups:

Name Size Symbol Used for
Opcode 6 bits O Specification of instruction
Register specifications 5 bits s,t,d see below
Shamt 5 bit S Constant value for shifts
Immediate constant value 16 bit C Immediate value for arithmetic and logical (AL) operations
Address 26 bit A Address for jumps and procedure calls
Funct 6 bit f Second part of opcode is used by instructions with zero 1st part
Note: Even 26-bit field is called Address, it is never used for loads and stores!

Register specificators

Register specificators are addresses of registers. They provide numbers of registers have source data and where machine should write result of instruction. MIPS supports instructions with up to 3 registers. They are named:

  • s-register (source)
  • t-register (target)
  • d-register (destination)
Note: s- and t- registers do not correspond to s0-s7 and t0-t7 registers described on MIPS Registers page. Here it is just notation

Address of register consists of 5 bits, so there can be 32 usable logical registers on one core.


Types of format

MIPS supports 3 main types of instruction format: R, I and J.

Type name Max amount of registers Immediate size Instruction bits Used for
R 3 5 bits 000000ss sssttttt dddddSSS SSffffff AL and shift operations on registers
I 2 16 bits OOOOOOss sssttttt CCCCCCCC CCCCCCCC AL operations with immediate values, load/stores, branches
J 0 26 bits OOOOOOAA AAAAAAAA AAAAAAAA AAAAAAAA Unconditional branches, procedure calls

Instructions Table

Legend format

  • 0|1 — plain bit values
  • - — ignored values
Name Assembly syntax Operation in C PC advance Type Opcode/Funct Full format
Add/subtract
add add $d, $s, $t d = t + s PC += 4 R 0x20 000000ss sssttttt ddddd--- --100000
add unsigned addu $d, $s, $t d = t + s PC += 4 R 0x21 000000ss sssttttt ddddd--- --100001
substract sub $d, $s, $t d = t - s PC += 4 R 0x22 000000ss sssttttt ddddd--- --100010
substract unsigned subu $d, $s, $t d = t - s PC += 4 R 0x23 000000ss sssttttt ddddd--- --100011
add immediate addi $t, $s, C t = s + C PC += 4 I 0x8 001000ss sssttttt CCCCCCCC CCCCCCCC
add immediate unsigned addiu $t, $s, C t = s + C PC += 4 I 0x9 001001ss sssttttt CCCCCCCC CCCCCCCC
Multiplication/division
multiply mult $s, $t LO = (s * t) & 0xFFFFFFFF; HI = (s * t) >> 0x20 PC += 4 R 0x18 000000ss sssttttt -------- --011000
multiply unsigned multu $s, $t LO = (s * t) & 0xFFFFFFFF; HI = (s * t) >> 0x20 PC += 4 R 0x19 000000ss sssttttt -------- --011001
divide div $s, $t LO = s / t; HI = s % t PC += 4 R 0x1A 000000ss sssttttt -------- --011010
divide unsigned divu $s, $t LO = s / t; HI = s % t PC += 4 R 0x1B 000000ss sssttttt -------- --011011
move from HI mfhi $d d = HI PC += 4 R 0x10 000000-- -------- ddddd--- --010000
move to HI mthi $s HI = s PC += 4 R 0x11 000000ss sss----- -------- --010001
move from LO mflo $d d = LO PC += 4 R 0x12 000000-- -------- ddddd--- --010010
move to LO mtlo $s LO = s PC += 4 R 0x13 000000ss sss----- -------- --010011
Shifts
shift left logical immediate sll $d, $t, S d = t << S PC += 4 R 0x0 000000-- ---ttttt dddddSSS SS000000
shift right logical immediate srl $d, $t, S d = t >> S PC += 4 R 0x2 000000-- ---ttttt dddddSSS SS000010
shift right arithmetic immediate sra $d, $t, S d = t ~>> S PC += 4 R 0x3 000000-- ---ttttt dddddSSS SS000011
shift left logical sllv $d, $t, $s d = t << s PC += 4 R 0x4 000000ss sssttttt ddddd--- --000100
shift right logical srlv $d, $t, $s d = t >> s PC += 4 R 0x6 000000ss sssttttt ddddd--- --000110
shift right arithmetic srav $d, $t, $s d = t ~>> s PC += 4 R 0x7 000000ss sssttttt ddddd--- --000111
load upper immediate lui $t, C t = C << 16 PC += 4 I 0xF 001111-- ---ttttt CCCCCCCC CCCCCCCC
Comparisons
set on less than slt $d, $t, $s d = (s < t) PC += 4 R 0x2A 000000ss sssttttt ddddd--- --101010
set on less than unsigned sltu $d, $t, $s d = (s < t) PC += 4 R 0x2B 000000ss sssttttt ddddd--- --101011
set on less than immediate slti $s, $t, C t = (s < C) PC += 4 I 0xA 001010ss sssttttt CCCCCCCC CCCCCCCC
set on less than immediate unsigned sltiu $s, $t, C t = (s < C) PC += 4 I 0xB 001011ss sssttttt CCCCCCCC CCCCCCCC
Logical operations
and and $d, $t, $s d = s & t PC += 4 R 0x24 000000ss sssttttt ddddd--- --100100
or or $d, $t, $s d = s | t PC += 4 R 0x25 000000ss sssttttt ddddd--- --100101
xor xor $d, $t, $s d = s ^ t PC += 4 R 0x26 000000ss sssttttt ddddd--- --100110
nor nor $d, $t, $s d = ~ (s | t) PC += 4 R 0x27 000000ss sssttttt ddddd--- --100111
and with immediate andi $s, $t, C t = s & C PC += 4 I 0xC 001100ss sssttttt CCCCCCCC CCCCCCCC
or with immediate ori $s, $t, C t = s | C PC += 4 I 0xD 001101ss sssttttt CCCCCCCC CCCCCCCC
xor with immediate xori $s, $t, C t = s ^ C PC += 4 I 0xE 001110ss sssttttt CCCCCCCC CCCCCCCC
Conditional branches
branch on equal beq $s, $t, C PC += 4; if (s == t) PC += (C << 2) I 0x4 000100ss sssttttt CCCCCCCC CCCCCCCC
branch on not equal bne $s, $t, C PC += 4; if (s != t) PC += (C << 2) I 0x5 000101ss sssttttt CCCCCCCC CCCCCCCC
branch less than zero or equal blez $s, C PC += 4; if (s <= 0) PC += (C << 2) I 0x6 000110ss sss----- CCCCCCCC CCCCCCCC
branch greater than zero bgtz $s, C PC += 4; if (s > 0) PC += (C << 2) I 0x7 000111ss sss----- CCCCCCCC CCCCCCCC
Unconditional jump
jump j A PC = (PC & 0xf0000000) | (A << 2) J 0x2 000010AA AAAAAAAA AAAAAAAA AAAAAAAA
jump and link jal A ra = PC + 4 PC = (PC & 0xf0000000) | (A << 2) J 0x3 000011AA AAAAAAAA AAAAAAAA AAAAAAAA
jump register jr $s PC = s R 0x8 000000ss sss----- -------- --001000
jump and link register jalr $s ra = PC + 4 PC = s R 0x9 000000ss sss----- -------- --001001
Loads
load byte lb $t, C($s) t = *(int8*)(s + C) PC += 4 I 0x20 100000ss sssttttt CCCCCCCC CCCCCCCC
load half word lh $t, C($s) t = *(int16*)(s + C) PC += 4 I 0x21 100001ss sssttttt CCCCCCCC CCCCCCCC
load word lw $t, C($s) t = *(int32*)(s + C) PC += 4 I 0x23 100011ss sssttttt CCCCCCCC CCCCCCCC
load byte unsigned lbu $t, C($s) t = *(uint8*)(s + C) PC += 4 I 0x24 100100ss sssttttt CCCCCCCC CCCCCCCC
load half word unsigned lhu $t, C($s) t = *(uint16*)(s + C) PC += 4 I 0x25 100101ss sssttttt CCCCCCCC CCCCCCCC
Stores
store byte sb $t, C($s) *(uint8*)(s + C) = (t & 0xff) PC += 4 I 0x28 101000ss sssttttt CCCCCCCC CCCCCCCC
store half sh $t, C($s) *(uint16*)(s + C) = (t & 0xffff) PC += 4 I 0x29 101000ss sssttttt CCCCCCCC CCCCCCCC
store word sw $t, C($s) *(uint32*)(s + C) = t PC += 4 I 0x2b 101011ss sssttttt CCCCCCCC CCCCCCCC
Special instructions
system call syscall syscall() PC += 4 R 0xC 000000-- -------- -------- --001100
breakpoint break break() PC += 4 R 0xD 000000-- -------- -------- --001101
trap trap A trap(A) PC += 4 J 0x1A 011010AA AAAAAAAA AAAAAAAA AAAAAAAA