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Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ar…

…m/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "People are back from the holiday breaks, and it shows.  Here are a
  bunch of fixes for a number of platforms:
   - A couple of small fixes for Nomadik
   - A larger set of changes for kirkwood/mvebu
     - uart driver selection, dt clocks, gpio-poweroff fixups, a few
       __init annotation fixes and some error handling improvement in
       their xor dma driver.
   - i.MX had a couple of minor fixes (and a critical one for flexcan2
     clock setup)
   - MXS has a small board fix and a framebuffer bugfix
   - A set of fixes for Samsung Exynos, fixing default bootargs and some
     Exynos5440 clock issues
   - A set of OMAP changes including PM fixes and a few sparse warning
     fixups

  All in all a bit more positive code delta than we'd ideally want to
  see here, mostly from the OMAP PM changes, but nothing overly crazy."

* tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (44 commits)
  ARM: clps711x: Fix bad merge of clockevents setup
  ARM: highbank: save and restore L2 cache and GIC on suspend
  ARM: highbank: add a power request clear
  ARM: highbank: fix secondary boot and hotplug
  ARM: highbank: fix typos with hignbank in power request functions
  ARM: dts: fix highbank cpu mpidr values
  ARM: dts: add device_type prop to cpu nodes on Calxeda platforms
  ARM: mx5: Fix MX53 flexcan2 clock
  ARM: OMAP2+: am33xx-hwmod: Fix wrongly terminated am33xx_usbss_mpu_irqs array
  pinctrl: mvebu: make pdma clock on dove mandatory
  ARM: Dove: Add pinctrl clock to DT
  dma: mv_xor: fix error handling for clocks
  dma: mv_xor: fix error handling of mv_xor_channel_add()
  arm: mvebu: Add missing ; for cpu node.
  arm: mvebu: Armada XP MV78230 has only three Ethernet interfaces
  arm: mvebu: Armada XP MV78230 has two cores, not one
  clk: mvebu: Remove inappropriate __init tagging
  ARM: Kirkwood: Use fixed-regulator instead of board gpio call
  ARM: Kirkwood: Fix missing sdio clock
  ARM: Kirkwood: Switch TWSI1 of 88f6282 to DT clock providers
  ...
  • Loading branch information...
commit 974b33586b4bbbdab33c666417f9ba9ef50b62c3 2 parents ca5c8a4 + 434fec1
Linus Torvalds authored January 08, 2013

Showing 53 changed files with 351 additions and 183 deletions. Show diff stats Hide diff stats

  1. 5  Documentation/devicetree/bindings/clock/imx23-clock.txt
  2. 4  Documentation/devicetree/bindings/clock/imx25-clock.txt
  3. 5  Documentation/devicetree/bindings/clock/imx28-clock.txt
  4. 4  Documentation/devicetree/bindings/clock/imx6q-clock.txt
  5. 20  Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
  6. 1  arch/arm/Kconfig
  7. 6  arch/arm/boot/dts/armada-370-xp.dtsi
  8. 9  arch/arm/boot/dts/armada-xp-mv78230.dtsi
  9. 8  arch/arm/boot/dts/armada-xp-mv78260.dtsi
  10. 8  arch/arm/boot/dts/armada-xp-mv78460.dtsi
  11. 14  arch/arm/boot/dts/armada-xp.dtsi
  12. 1  arch/arm/boot/dts/dove.dtsi
  13. 4  arch/arm/boot/dts/ecx-2000.dts
  14. 2  arch/arm/boot/dts/exynos4210-smdkv310.dts
  15. 2  arch/arm/boot/dts/exynos5250.dtsi
  16. 2  arch/arm/boot/dts/exynos5440-ssdk5440.dts
  17. 20  arch/arm/boot/dts/highbank.dts
  18. 8  arch/arm/boot/dts/imx23-olinuxino.dts
  19. 2  arch/arm/boot/dts/imx31-bug.dts
  20. 2  arch/arm/boot/dts/imx53.dtsi
  21. 1  arch/arm/boot/dts/kirkwood-6282.dtsi
  22. 17  arch/arm/boot/dts/kirkwood-topkick.dts
  23. 1  arch/arm/boot/dts/kirkwood.dtsi
  24. 4  arch/arm/configs/mvebu_defconfig
  25. 2  arch/arm/mach-exynos/Kconfig
  26. 7  arch/arm/mach-exynos/common.c
  27. 2  arch/arm/mach-highbank/highbank.c
  28. 2  arch/arm/mach-highbank/hotplug.c
  29. 12  arch/arm/mach-highbank/platsmp.c
  30. 19  arch/arm/mach-highbank/pm.c
  31. 23  arch/arm/mach-highbank/sysregs.h
  32. 4  arch/arm/mach-highbank/system.c
  33. 4  arch/arm/mach-kirkwood/board-dt.c
  34. 4  arch/arm/mach-kirkwood/board-usi_topkick.c
  35. 1  arch/arm/mach-nomadik/board-nhk8815.c
  36. 78  arch/arm/mach-nomadik/include/mach/irqs.h
  37. 2  arch/arm/mach-omap1/board-ams-delta.c
  38. 8  arch/arm/mach-omap1/usb.c
  39. 2  arch/arm/mach-omap2/cclock3xxx_data.c
  40. 6  arch/arm/mach-omap2/omap_hwmod_33xx_data.c
  41. 88  arch/arm/mach-omap2/prm2xxx.c
  42. 22  arch/arm/mach-omap2/prm2xxx_3xxx.c
  43. 28  arch/arm/mach-omap2/prm3xxx.c
  44. 6  arch/arm/mach-omap2/prm44xx.c
  45. 4  arch/arm/mach-omap2/prm44xx.h
  46. 2  arch/arm/plat-omap/counter_32k.c
  47. 2  arch/arm/plat-omap/sram.c
  48. 2  arch/arm/plat-samsung/include/plat/cpu.h
  49. 2  drivers/clk/mvebu/clk-gating-ctrl.c
  50. 9  drivers/dma/mv_xor.c
  51. 7  drivers/pinctrl/mvebu/pinctrl-dove.c
  52. 33  drivers/power/reset/gpio-poweroff.c
  53. 3  drivers/video/mxsfb.c
5  Documentation/devicetree/bindings/clock/imx23-clock.txt
@@ -60,11 +60,6 @@ clks: clkctrl@80040000 {
60 60
 	compatible = "fsl,imx23-clkctrl";
61 61
 	reg = <0x80040000 0x2000>;
62 62
 	#clock-cells = <1>;
63  
-	clock-output-names =
64  
-		...
65  
-		"uart",		/* 32 */
66  
-		...
67  
-		"end_of_list";
68 63
 };
69 64
 
70 65
 auart0: serial@8006c000 {
4  Documentation/devicetree/bindings/clock/imx25-clock.txt
@@ -146,10 +146,6 @@ clks: ccm@53f80000 {
146 146
 	compatible = "fsl,imx25-ccm";
147 147
 	reg = <0x53f80000 0x4000>;
148 148
 	interrupts = <31>;
149  
-	clock-output-names = ...
150  
-			"uart_ipg",
151  
-			"uart_serial",
152  
-			...;
153 149
 };
154 150
 
155 151
 uart1: serial@43f90000 {
5  Documentation/devicetree/bindings/clock/imx28-clock.txt
@@ -83,11 +83,6 @@ clks: clkctrl@80040000 {
83 83
 	compatible = "fsl,imx28-clkctrl";
84 84
 	reg = <0x80040000 0x2000>;
85 85
 	#clock-cells = <1>;
86  
-	clock-output-names =
87  
-		...
88  
-		"uart",		/* 45 */
89  
-		...
90  
-		"end_of_list";
91 86
 };
92 87
 
93 88
 auart0: serial@8006a000 {
4  Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -211,10 +211,6 @@ clks: ccm@020c4000 {
211 211
 	reg = <0x020c4000 0x4000>;
212 212
 	interrupts = <0 87 0x04 0 88 0x04>;
213 213
 	#clock-cells = <1>;
214  
-	clock-output-names = ...
215  
-			     "uart_ipg",
216  
-			     "uart_serial",
217  
-			     ...;
218 214
 };
219 215
 
220 216
 uart1: serial@02020000 {
20  Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
... ...
@@ -1,4 +1,19 @@
1  
-GPIO line that should be set high/low to power off a device
  1
+Driver a GPIO line that can be used to turn the power off.
  2
+
  3
+The driver supports both level triggered and edge triggered power off.
  4
+At driver load time, the driver will request the given gpio line and
  5
+install a pm_power_off handler. If the optional properties 'input' is
  6
+not found, the GPIO line will be driven in the inactive
  7
+state. Otherwise its configured as an input.
  8
+
  9
+When the pm_power_off is called, the gpio is configured as an output,
  10
+and drive active, so triggering a level triggered power off
  11
+condition. This will also cause an inactive->active edge condition, so
  12
+triggering positive edge triggered power off. After a delay of 100ms,
  13
+the GPIO is set to inactive, thus causing an active->inactive edge,
  14
+triggering negative edge triggered power off. After another 100ms
  15
+delay the GPIO is driver active again. If the power is still on and
  16
+the CPU still running after a 3000ms delay, a WARN_ON(1) is emitted.
2 17
 
3 18
 Required properties:
4 19
 - compatible : should be "gpio-poweroff".
@@ -13,10 +28,9 @@ Optional properties:
13 28
   property is not specified, the GPIO is initialized as an output in its
14 29
   inactive state.
15 30
 
16  
-
17 31
 Examples:
18 32
 
19 33
 gpio-poweroff {
20 34
 	compatible = "gpio-poweroff";
21  
-	gpios = <&gpio 4 0>; /* GPIO 4 Active Low */
  35
+	gpios = <&gpio 4 0>;
22 36
 };
1  arch/arm/Kconfig
@@ -371,7 +371,6 @@ config ARCH_CNS3XXX
371 371
 config ARCH_CLPS711X
372 372
 	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
373 373
 	select ARCH_REQUIRE_GPIOLIB
374  
-	select ARCH_USES_GETTIMEOFFSET
375 374
 	select AUTO_ZRELADDR
376 375
 	select CLKDEV_LOOKUP
377 376
 	select COMMON_CLK
6  arch/arm/boot/dts/armada-370-xp.dtsi
@@ -50,17 +50,19 @@
50 50
 		ranges;
51 51
 
52 52
 		serial@d0012000 {
53  
-				compatible = "ns16550";
  53
+				compatible = "snps,dw-apb-uart";
54 54
 				reg = <0xd0012000 0x100>;
55 55
 				reg-shift = <2>;
56 56
 				interrupts = <41>;
  57
+				reg-io-width = <4>;
57 58
 				status = "disabled";
58 59
 		};
59 60
 		serial@d0012100 {
60  
-				compatible = "ns16550";
  61
+				compatible = "snps,dw-apb-uart";
61 62
 				reg = <0xd0012100 0x100>;
62 63
 				reg-shift = <2>;
63 64
 				interrupts = <42>;
  65
+				reg-io-width = <4>;
64 66
 				status = "disabled";
65 67
 		};
66 68
 
9  arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -34,7 +34,14 @@
34 34
 		reg = <0>;
35 35
 		clocks = <&cpuclk 0>;
36 36
 	    };
37  
-	}
  37
+
  38
+	    cpu@1 {
  39
+		device_type = "cpu";
  40
+		compatible = "marvell,sheeva-v7";
  41
+		reg = <1>;
  42
+		clocks = <&cpuclk 1>;
  43
+	    };
  44
+	};
38 45
 
39 46
 	soc {
40 47
 		pinctrl {
8  arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -85,5 +85,13 @@
85 85
 			#interrupts-cells = <2>;
86 86
 			interrupts = <24>;
87 87
 		};
  88
+
  89
+		ethernet@d0034000 {
  90
+				compatible = "marvell,armada-370-neta";
  91
+				reg = <0xd0034000 0x2500>;
  92
+				interrupts = <14>;
  93
+				clocks = <&gateclk 1>;
  94
+				status = "disabled";
  95
+		};
88 96
 	};
89 97
 };
8  arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -100,5 +100,13 @@
100 100
 			#interrupts-cells = <2>;
101 101
 			interrupts = <24>;
102 102
 		};
  103
+
  104
+		ethernet@d0034000 {
  105
+				compatible = "marvell,armada-370-neta";
  106
+				reg = <0xd0034000 0x2500>;
  107
+				interrupts = <14>;
  108
+				clocks = <&gateclk 1>;
  109
+				status = "disabled";
  110
+		};
103 111
 	};
104 112
  };
14  arch/arm/boot/dts/armada-xp.dtsi
@@ -42,17 +42,19 @@
42 42
 
43 43
 	soc {
44 44
 		serial@d0012200 {
45  
-				compatible = "ns16550";
  45
+				compatible = "snps,dw-apb-uart";
46 46
 				reg = <0xd0012200 0x100>;
47 47
 				reg-shift = <2>;
48 48
 				interrupts = <43>;
  49
+				reg-io-width = <4>;
49 50
 				status = "disabled";
50 51
 		};
51 52
 		serial@d0012300 {
52  
-				compatible = "ns16550";
  53
+				compatible = "snps,dw-apb-uart";
53 54
 				reg = <0xd0012300 0x100>;
54 55
 				reg-shift = <2>;
55 56
 				interrupts = <44>;
  57
+				reg-io-width = <4>;
56 58
 				status = "disabled";
57 59
 		};
58 60
 
@@ -93,14 +95,6 @@
93 95
 				status = "disabled";
94 96
 		};
95 97
 
96  
-		ethernet@d0034000 {
97  
-				compatible = "marvell,armada-370-neta";
98  
-				reg = <0xd0034000 0x2500>;
99  
-				interrupts = <14>;
100  
-				clocks = <&gateclk 1>;
101  
-				status = "disabled";
102  
-		};
103  
-
104 98
 		xor@d0060900 {
105 99
 			compatible = "marvell,orion-xor";
106 100
 			reg = <0xd0060900 0x100
1  arch/arm/boot/dts/dove.dtsi
@@ -117,6 +117,7 @@
117 117
 		pinctrl: pinctrl@d0200 {
118 118
 			compatible = "marvell,dove-pinctrl";
119 119
 			reg = <0xd0200 0x10>;
  120
+			clocks = <&gate_clk 22>;
120 121
 		};
121 122
 
122 123
 		spi0: spi@10600 {
4  arch/arm/boot/dts/ecx-2000.dts
@@ -32,6 +32,7 @@
32 32
 
33 33
 		cpu@0 {
34 34
 			compatible = "arm,cortex-a15";
  35
+			device_type = "cpu";
35 36
 			reg = <0>;
36 37
 			clocks = <&a9pll>;
37 38
 			clock-names = "cpu";
@@ -39,6 +40,7 @@
39 40
 
40 41
 		cpu@1 {
41 42
 			compatible = "arm,cortex-a15";
  43
+			device_type = "cpu";
42 44
 			reg = <1>;
43 45
 			clocks = <&a9pll>;
44 46
 			clock-names = "cpu";
@@ -46,6 +48,7 @@
46 48
 
47 49
 		cpu@2 {
48 50
 			compatible = "arm,cortex-a15";
  51
+			device_type = "cpu";
49 52
 			reg = <2>;
50 53
 			clocks = <&a9pll>;
51 54
 			clock-names = "cpu";
@@ -53,6 +56,7 @@
53 56
 
54 57
 		cpu@3 {
55 58
 			compatible = "arm,cortex-a15";
  59
+			device_type = "cpu";
56 60
 			reg = <3>;
57 61
 			clocks = <&a9pll>;
58 62
 			clock-names = "cpu";
2  arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -26,7 +26,7 @@
26 26
 	};
27 27
 
28 28
 	chosen {
29  
-		bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
  29
+		bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
30 30
 	};
31 31
 
32 32
 	sdhci@12530000 {
2  arch/arm/boot/dts/exynos5250.dtsi
@@ -574,7 +574,7 @@
574 574
 
575 575
 	hdmi {
576 576
 		compatible = "samsung,exynos5-hdmi";
577  
-		reg = <0x14530000 0x100000>;
  577
+		reg = <0x14530000 0x70000>;
578 578
 		interrupts = <0 95 0>;
579 579
 	};
580 580
 
2  arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -21,7 +21,7 @@
21 21
 	};
22 22
 
23 23
 	chosen {
24  
-		bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC2,115200 init=/linuxrc";
  24
+		bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC0,115200 init=/linuxrc";
25 25
 	};
26 26
 
27 27
 	spi {
20  arch/arm/boot/dts/highbank.dts
@@ -30,33 +30,37 @@
30 30
 		#address-cells = <1>;
31 31
 		#size-cells = <0>;
32 32
 
33  
-		cpu@0 {
  33
+		cpu@900 {
34 34
 			compatible = "arm,cortex-a9";
35  
-			reg = <0>;
  35
+			device_type = "cpu";
  36
+			reg = <0x900>;
36 37
 			next-level-cache = <&L2>;
37 38
 			clocks = <&a9pll>;
38 39
 			clock-names = "cpu";
39 40
 		};
40 41
 
41  
-		cpu@1 {
  42
+		cpu@901 {
42 43
 			compatible = "arm,cortex-a9";
43  
-			reg = <1>;
  44
+			device_type = "cpu";
  45
+			reg = <0x901>;
44 46
 			next-level-cache = <&L2>;
45 47
 			clocks = <&a9pll>;
46 48
 			clock-names = "cpu";
47 49
 		};
48 50
 
49  
-		cpu@2 {
  51
+		cpu@902 {
50 52
 			compatible = "arm,cortex-a9";
51  
-			reg = <2>;
  53
+			device_type = "cpu";
  54
+			reg = <0x902>;
52 55
 			next-level-cache = <&L2>;
53 56
 			clocks = <&a9pll>;
54 57
 			clock-names = "cpu";
55 58
 		};
56 59
 
57  
-		cpu@3 {
  60
+		cpu@903 {
58 61
 			compatible = "arm,cortex-a9";
59  
-			reg = <3>;
  62
+			device_type = "cpu";
  63
+			reg = <0x903>;
60 64
 			next-level-cache = <&L2>;
61 65
 			clocks = <&a9pll>;
62 66
 			clock-names = "cpu";
8  arch/arm/boot/dts/imx23-olinuxino.dts
@@ -39,17 +39,17 @@
39 39
 				hog_pins_a: hog@0 {
40 40
 					reg = <0>;
41 41
 					fsl,pinmux-ids = <
42  
-						0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
  42
+						0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
43 43
 					>;
44 44
 					fsl,drive-strength = <0>;
45 45
 					fsl,voltage = <1>;
46 46
 					fsl,pull-up = <0>;
47 47
 				};
48 48
 
49  
-				led_pin_gpio0_17: led_gpio0_17@0 {
  49
+				led_pin_gpio2_1: led_gpio2_1@0 {
50 50
 					reg = <0>;
51 51
 					fsl,pinmux-ids = <
52  
-						0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
  52
+						0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
53 53
 					>;
54 54
 					fsl,drive-strength = <0>;
55 55
 					fsl,voltage = <1>;
@@ -110,7 +110,7 @@
110 110
 	leds {
111 111
 		compatible = "gpio-leds";
112 112
 		pinctrl-names = "default";
113  
-		pinctrl-0 = <&led_pin_gpio0_17>;
  113
+		pinctrl-0 = <&led_pin_gpio2_1>;
114 114
 
115 115
 		user {
116 116
 			label = "green";
2  arch/arm/boot/dts/imx31-bug.dts
@@ -14,7 +14,7 @@
14 14
 
15 15
 / {
16 16
 	model = "Buglabs i.MX31 Bug 1.x";
17  
-	compatible = "fsl,imx31-bug", "fsl,imx31";
  17
+	compatible = "buglabs,imx31-bug", "fsl,imx31";
18 18
 
19 19
 	memory {
20 20
 		reg = <0x80000000 0x8000000>; /* 128M */
2  arch/arm/boot/dts/imx53.dtsi
@@ -492,7 +492,7 @@
492 492
 				compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
493 493
 				reg = <0x53fcc000 0x4000>;
494 494
 				interrupts = <83>;
495  
-				clocks = <&clks 158>, <&clks 157>;
  495
+				clocks = <&clks 87>, <&clks 86>;
496 496
 				clock-names = "ipg", "per";
497 497
 				status = "disabled";
498 498
 			};
1  arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -39,6 +39,7 @@
39 39
 			#size-cells = <0>;
40 40
 			interrupts = <32>;
41 41
 			clock-frequency = <100000>;
  42
+			clocks = <&gate_clk 7>;
42 43
 			status = "disabled";
43 44
 		};
44 45
 	};
17  arch/arm/boot/dts/kirkwood-topkick.dts
@@ -82,4 +82,21 @@
82 82
 			gpios = <&gpio1 16 1>;
83 83
 		};
84 84
 	};
  85
+	regulators {
  86
+		compatible = "simple-bus";
  87
+		#address-cells = <1>;
  88
+		#size-cells = <0>;
  89
+
  90
+		sata0_power: regulator@1 {
  91
+			compatible = "regulator-fixed";
  92
+			reg = <1>;
  93
+			regulator-name = "SATA0 Power";
  94
+			regulator-min-microvolt = <5000000>;
  95
+			regulator-max-microvolt = <5000000>;
  96
+			enable-active-high;
  97
+			regulator-always-on;
  98
+			regulator-boot-on;
  99
+			gpio = <&gpio1 4 0>;
  100
+		};
  101
+	};
85 102
 };
1  arch/arm/boot/dts/kirkwood.dtsi
@@ -144,6 +144,7 @@
144 144
 			compatible = "marvell,orion-ehci";
145 145
 			reg = <0x50000 0x1000>;
146 146
 			interrupts = <19>;
  147
+			clocks = <&gate_clk 3>;
147 148
 			status = "okay";
148 149
 		};
149 150
 
4  arch/arm/configs/mvebu_defconfig
@@ -33,9 +33,7 @@ CONFIG_MVNETA=y
33 33
 CONFIG_MARVELL_PHY=y
34 34
 CONFIG_SERIAL_8250=y
35 35
 CONFIG_SERIAL_8250_CONSOLE=y
36  
-CONFIG_SERIAL_OF_PLATFORM=y
37  
-CONFIG_I2C=y
38  
-CONFIG_I2C_MV64XXX=y
  36
+CONFIG_SERIAL_8250_DW=y
39 37
 CONFIG_GPIOLIB=y
40 38
 CONFIG_GPIO_SYSFS=y
41 39
 # CONFIG_USB_SUPPORT is not set
2  arch/arm/mach-exynos/Kconfig
@@ -74,6 +74,8 @@ config SOC_EXYNOS5440
74 74
 	depends on ARCH_EXYNOS5
75 75
 	select ARM_ARCH_TIMER
76 76
 	select AUTO_ZRELADDR
  77
+	select PINCTRL
  78
+	select PINCTRL_EXYNOS5440
77 79
 	help
78 80
 	  Enable EXYNOS5440 SoC support
79 81
 
7  arch/arm/mach-exynos/common.c
@@ -424,11 +424,18 @@ static void __init exynos5_init_clocks(int xtal)
424 424
 {
425 425
 	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
426 426
 
  427
+	/* EXYNOS5440 can support only common clock framework */
  428
+
  429
+	if (soc_is_exynos5440())
  430
+		return;
  431
+
  432
+#ifdef CONFIG_SOC_EXYNOS5250
427 433
 	s3c24xx_register_baseclocks(xtal);
428 434
 	s5p_register_clocks(xtal);
429 435
 
430 436
 	exynos5_register_clocks();
431 437
 	exynos5_setup_clocks();
  438
+#endif
432 439
 }
433 440
 
434 441
 #define COMBINER_ENABLE_SET	0x0
2  arch/arm/mach-highbank/highbank.c
@@ -135,7 +135,7 @@ static struct sys_timer highbank_timer = {
135 135
 
136 136
 static void highbank_power_off(void)
137 137
 {
138  
-	hignbank_set_pwr_shutdown();
  138
+	highbank_set_pwr_shutdown();
139 139
 
140 140
 	while (1)
141 141
 		cpu_do_idle();
2  arch/arm/mach-highbank/hotplug.c
@@ -30,7 +30,7 @@ void __ref highbank_cpu_die(unsigned int cpu)
30 30
 {
31 31
 	flush_cache_all();
32 32
 
33  
-	highbank_set_cpu_jump(cpu, secondary_startup);
  33
+	highbank_set_cpu_jump(cpu, phys_to_virt(0));
34 34
 	highbank_set_core_pwr();
35 35
 
36 36
 	cpu_do_idle();
12  arch/arm/mach-highbank/platsmp.c
@@ -32,6 +32,7 @@ static void __cpuinit highbank_secondary_init(unsigned int cpu)
32 32
 
33 33
 static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
34 34
 {
  35
+	highbank_set_cpu_jump(cpu, secondary_startup);
35 36
 	gic_raise_softirq(cpumask_of(cpu), 0);
36 37
 	return 0;
37 38
 }
@@ -61,19 +62,8 @@ static void __init highbank_smp_init_cpus(void)
61 62
 
62 63
 static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
63 64
 {
64  
-	int i;
65  
-
66 65
 	if (scu_base_addr)
67 66
 		scu_enable(scu_base_addr);
68  
-
69  
-	/*
70  
-	 * Write the address of secondary startup into the jump table
71  
-	 * The cores are in wfi and wait until they receive a soft interrupt
72  
-	 * and a non-zero value to jump to. Then the secondary CPU branches
73  
-	 * to this address.
74  
-	 */
75  
-	for (i = 1; i < max_cpus; i++)
76  
-		highbank_set_cpu_jump(i, secondary_startup);
77 67
 }
78 68
 
79 69
 struct smp_operations highbank_smp_ops __initdata = {
19  arch/arm/mach-highbank/pm.c
@@ -14,10 +14,12 @@
14 14
  * this program.  If not, see <http://www.gnu.org/licenses/>.
15 15
  */
16 16
 
  17
+#include <linux/cpu_pm.h>
17 18
 #include <linux/init.h>
18 19
 #include <linux/io.h>
19 20
 #include <linux/suspend.h>
20 21
 
  22
+#include <asm/cacheflush.h>
21 23
 #include <asm/proc-fns.h>
22 24
 #include <asm/suspend.h>
23 25
 
@@ -26,16 +28,31 @@
26 28
 
27 29
 static int highbank_suspend_finish(unsigned long val)
28 30
 {
  31
+	outer_flush_all();
  32
+	outer_disable();
  33
+
  34
+	highbank_set_pwr_suspend();
  35
+
29 36
 	cpu_do_idle();
  37
+
  38
+	highbank_clear_pwr_request();
30 39
 	return 0;
31 40
 }
32 41
 
33 42
 static int highbank_pm_enter(suspend_state_t state)
34 43
 {
35  
-	hignbank_set_pwr_suspend();
  44
+	cpu_pm_enter();
  45
+	cpu_cluster_pm_enter();
  46
+
36 47
 	highbank_set_cpu_jump(0, cpu_resume);
37 48
 	cpu_suspend(0, highbank_suspend_finish);
38 49
 
  50
+	cpu_cluster_pm_exit();
  51
+	cpu_pm_exit();
  52
+
  53
+	highbank_smc1(0x102, 0x1);
  54
+	if (scu_base_addr)
  55
+		scu_enable(scu_base_addr);
39 56
 	return 0;
40 57
 }
41 58
 
23  arch/arm/mach-highbank/sysregs.h
@@ -44,28 +44,43 @@ static inline void highbank_set_core_pwr(void)
44 44
 		writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
45 45
 }
46 46
 
47  
-static inline void hignbank_set_pwr_suspend(void)
  47
+static inline void highbank_clear_core_pwr(void)
  48
+{
  49
+	int cpu = cpu_logical_map(smp_processor_id());
  50
+	if (scu_base_addr)
  51
+		scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
  52
+	else
  53
+		writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
  54
+}
  55
+
  56
+static inline void highbank_set_pwr_suspend(void)
48 57
 {
49 58
 	writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
50 59
 	highbank_set_core_pwr();
51 60
 }
52 61
 
53  
-static inline void hignbank_set_pwr_shutdown(void)
  62
+static inline void highbank_set_pwr_shutdown(void)
54 63
 {
55 64
 	writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
56 65
 	highbank_set_core_pwr();
57 66
 }
58 67
 
59  
-static inline void hignbank_set_pwr_soft_reset(void)
  68
+static inline void highbank_set_pwr_soft_reset(void)
60 69
 {
61 70
 	writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
62 71
 	highbank_set_core_pwr();
63 72
 }
64 73
 
65  
-static inline void hignbank_set_pwr_hard_reset(void)
  74
+static inline void highbank_set_pwr_hard_reset(void)
66 75
 {
67 76
 	writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
68 77
 	highbank_set_core_pwr();
69 78
 }
70 79
 
  80
+static inline void highbank_clear_pwr_request(void)
  81
+{
  82
+	writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);
  83
+	highbank_clear_core_pwr();
  84
+}
  85
+
71 86
 #endif
4  arch/arm/mach-highbank/system.c
@@ -22,9 +22,9 @@
22 22
 void highbank_restart(char mode, const char *cmd)
23 23
 {
24 24
 	if (mode == 'h')
25  
-		hignbank_set_pwr_hard_reset();
  25
+		highbank_set_pwr_hard_reset();
26 26
 	else
27  
-		hignbank_set_pwr_soft_reset();
  27
+		highbank_set_pwr_soft_reset();
28 28
 
29 29
 	while (1)
30 30
 		cpu_do_idle();
4  arch/arm/mach-kirkwood/board-dt.c
@@ -67,6 +67,10 @@ static void __init kirkwood_legacy_clk_init(void)
67 67
 	orion_clkdev_add(NULL, "mv643xx_eth_port.1",
68 68
 			 of_clk_get_from_provider(&clkspec));
69 69
 
  70
+	clkspec.args[0] = CGC_BIT_SDIO;
  71
+	orion_clkdev_add(NULL, "mvsdio",
  72
+			 of_clk_get_from_provider(&clkspec));
  73
+
70 74
 }
71 75
 
72 76
 static void __init kirkwood_of_clk_init(void)
4  arch/arm/mach-kirkwood/board-usi_topkick.c
@@ -64,8 +64,6 @@ static unsigned int topkick_mpp_config[] __initdata = {
64 64
 	0
65 65
 };
66 66
 
67  
-#define TOPKICK_SATA0_PWR_ENABLE 36
68  
-
69 67
 void __init usi_topkick_init(void)
70 68
 {
71 69
 	/*
@@ -73,8 +71,6 @@ void __init usi_topkick_init(void)
73 71
 	 */
74 72
 	kirkwood_mpp_conf(topkick_mpp_config);
75 73
 
76  
-	/* SATA0 power enable */
77  
-	gpio_set_value(TOPKICK_SATA0_PWR_ENABLE, 1);
78 74
 
79 75
 	kirkwood_ge00_init(&topkick_ge00_data);
80 76
 	kirkwood_sdio_init(&topkick_mvsdio_data);
1  arch/arm/mach-nomadik/board-nhk8815.c
@@ -27,7 +27,6 @@
27 27
 #include <linux/pinctrl/machine.h>
28 28
 #include <linux/platform_data/pinctrl-nomadik.h>
29 29
 #include <linux/platform_data/clocksource-nomadik-mtu.h>
30  
-#include <linux/platform_data/mtd-nomadik-nand.h>
31 30
 #include <asm/hardware/vic.h>
32 31
 #include <asm/sizes.h>
33 32
 #include <asm/mach-types.h>
78  arch/arm/mach-nomadik/include/mach/irqs.h
@@ -22,49 +22,49 @@
22 22
 
23 23
 #include <mach/hardware.h>
24 24
 
25  
-#define IRQ_VIC_START		1	/* first VIC interrupt is 1 */
  25
+#define IRQ_VIC_START		32	/* first VIC interrupt is 1 */
26 26
 
27 27
 /*
28 28
  * Interrupt numbers generic for all Nomadik Chip cuts
29 29
  */
30  
-#define IRQ_WATCHDOG			1
31  
-#define IRQ_SOFTINT			2
32  
-#define IRQ_CRYPTO			3
33  
-#define IRQ_OWM				4
34  
-#define IRQ_MTU0			5
35  
-#define IRQ_MTU1			6
36  
-#define IRQ_GPIO0			7
37  
-#define IRQ_GPIO1			8
38  
-#define IRQ_GPIO2			9
39  
-#define IRQ_GPIO3			10
40  
-#define IRQ_RTC_RTT			11
41  
-#define IRQ_SSP				12
42  
-#define IRQ_UART0			13
43  
-#define IRQ_DMA1			14
44  
-#define IRQ_CLCD_MDIF			15
45  
-#define IRQ_DMA0			16
46  
-#define IRQ_PWRFAIL			17
47  
-#define IRQ_UART1			18
48  
-#define IRQ_FIRDA			19
49  
-#define IRQ_MSP0			20
50  
-#define IRQ_I2C0			21
51  
-#define IRQ_I2C1			22
52  
-#define IRQ_SDMMC			23
53  
-#define IRQ_USBOTG			24
54  
-#define IRQ_SVA_IT0			25
55  
-#define IRQ_SVA_IT1			26
56  
-#define IRQ_SAA_IT0			27
57  
-#define IRQ_SAA_IT1			28
58  
-#define IRQ_UART2			29
59  
-#define IRQ_MSP2			30
60  
-#define IRQ_L2CC			49
61  
-#define IRQ_HPI				50
62  
-#define IRQ_SKE				51
63  
-#define IRQ_KP				52
64  
-#define IRQ_MEMST			55
65  
-#define IRQ_SGA_IT			59
66  
-#define IRQ_USBM			61
67  
-#define IRQ_MSP1			63
  30
+#define IRQ_WATCHDOG			(IRQ_VIC_START+0)
  31
+#define IRQ_SOFTINT			(IRQ_VIC_START+1)
  32
+#define IRQ_CRYPTO			(IRQ_VIC_START+2)
  33
+#define IRQ_OWM				(IRQ_VIC_START+3)
  34
+#define IRQ_MTU0			(IRQ_VIC_START+4)
  35
+#define IRQ_MTU1			(IRQ_VIC_START+5)
  36
+#define IRQ_GPIO0			(IRQ_VIC_START+6)
  37
+#define IRQ_GPIO1			(IRQ_VIC_START+7)
  38
+#define IRQ_GPIO2			(IRQ_VIC_START+8)
  39
+#define IRQ_GPIO3			(IRQ_VIC_START+9)
  40
+#define IRQ_RTC_RTT			(IRQ_VIC_START+10)
  41
+#define IRQ_SSP				(IRQ_VIC_START+11)
  42
+#define IRQ_UART0			(IRQ_VIC_START+12)
  43
+#define IRQ_DMA1			(IRQ_VIC_START+13)
  44
+#define IRQ_CLCD_MDIF			(IRQ_VIC_START+14)
  45
+#define IRQ_DMA0			(IRQ_VIC_START+15)
  46
+#define IRQ_PWRFAIL			(IRQ_VIC_START+16)
  47
+#define IRQ_UART1			(IRQ_VIC_START+17)
  48
+#define IRQ_FIRDA			(IRQ_VIC_START+18)
  49
+#define IRQ_MSP0			(IRQ_VIC_START+19)
  50
+#define IRQ_I2C0			(IRQ_VIC_START+20)
  51
+#define IRQ_I2C1			(IRQ_VIC_START+21)
  52
+#define IRQ_SDMMC			(IRQ_VIC_START+22)
  53
+#define IRQ_USBOTG			(IRQ_VIC_START+23)
  54
+#define IRQ_SVA_IT0			(IRQ_VIC_START+24)
  55
+#define IRQ_SVA_IT1			(IRQ_VIC_START+25)
  56
+#define IRQ_SAA_IT0			(IRQ_VIC_START+26)
  57
+#define IRQ_SAA_IT1			(IRQ_VIC_START+27)
  58
+#define IRQ_UART2			(IRQ_VIC_START+28)
  59
+#define IRQ_MSP2			(IRQ_VIC_START+29)
  60
+#define IRQ_L2CC			(IRQ_VIC_START+30)
  61
+#define IRQ_HPI				(IRQ_VIC_START+31)
  62
+#define IRQ_SKE				(IRQ_VIC_START+32)
  63
+#define IRQ_KP				(IRQ_VIC_START+33)
  64
+#define IRQ_MEMST			(IRQ_VIC_START+34)
  65
+#define IRQ_SGA_IT			(IRQ_VIC_START+35)
  66
+#define IRQ_USBM			(IRQ_VIC_START+36)
  67
+#define IRQ_MSP1			(IRQ_VIC_START+37)
68 68
 
69 69
 #define NOMADIK_GPIO_OFFSET		(IRQ_VIC_START+64)
70 70
 
2  arch/arm/mach-omap1/board-ams-delta.c
@@ -160,7 +160,7 @@ static struct omap_lcd_config ams_delta_lcd_config __initdata = {
160 160
 	.ctrl_name	= "internal",
161 161
 };
162 162
 
163  
-static struct omap_usb_config ams_delta_usb_config = {
  163
+static struct omap_usb_config ams_delta_usb_config __initdata = {
164 164
 	.register_host	= 1,
165 165
 	.hmc_mode	= 16,
166 166
 	.pins[0]	= 2,
8  arch/arm/mach-omap1/usb.c
@@ -629,8 +629,14 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
629 629
 static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
630 630
 #endif
631 631
 
632  
-void __init omap1_usb_init(struct omap_usb_config *pdata)
  632
+void __init omap1_usb_init(struct omap_usb_config *_pdata)
633 633
 {
  634
+	struct omap_usb_config *pdata;
  635
+
  636
+	pdata = kmemdup(_pdata, sizeof(*pdata), GFP_KERNEL);
  637
+	if (!pdata)
  638
+		return;
  639
+
634 640
 	pdata->usb0_init = omap1_usb0_init;
635 641
 	pdata->usb1_init = omap1_usb1_init;
636 642
 	pdata->usb2_init = omap1_usb2_init;
2  arch/arm/mach-omap2/cclock3xxx_data.c
@@ -1167,6 +1167,8 @@ static const struct clk_ops emu_src_ck_ops = {
1167 1167
 	.recalc_rate	= &omap2_clksel_recalc,
1168 1168
 	.get_parent	= &omap2_clksel_find_parent_index,
1169 1169
 	.set_parent	= &omap2_clksel_set_parent,
  1170
+	.enable		= &omap2_clkops_enable_clkdm,
  1171
+	.disable	= &omap2_clkops_disable_clkdm,
1170 1172
 };
1171 1173
 
1172 1174
 static struct clk emu_src_ck;
6  arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -2070,7 +2070,7 @@ static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2070 2070
 	{ .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2071 2071
 	{ .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2072 2072
 	{ .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2073  
-	{ .irq = -1 + OMAP_INTC_START, },
  2073
+	{ .irq = -1, },
2074 2074
 };
2075 2075
 
2076 2076
 static struct omap_hwmod am33xx_usbss_hwmod = {
@@ -2515,7 +2515,7 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2515 2515
 	.user		= OCP_USER_MPU,
2516 2516
 };
2517 2517
 
2518  
-struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
  2518
+static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2519 2519
 	{
2520 2520
 		.pa_start	= 0x4A101000,
2521 2521
 		.pa_end		= 0x4A101000 + SZ_256 - 1,
@@ -2523,7 +2523,7 @@ struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2523 2523
 	{ }
2524 2524
 };
2525 2525
 
2526  
-struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
  2526
+static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2527 2527
 	.master		= &am33xx_cpgmac0_hwmod,
2528 2528
 	.slave		= &am33xx_mdio_hwmod,
2529 2529
 	.addr		= am33xx_mdio_addr_space,
88  arch/arm/mach-omap2/prm2xxx.c
@@ -28,6 +28,14 @@
28 28
 #include "prm-regbits-24xx.h"
29 29
 
30 30
 /*
  31
+ * OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
  32
+ * these are reversed from the bits used on OMAP3+
  33
+ */
  34
+#define OMAP24XX_PWRDM_POWER_ON			0x0
  35
+#define OMAP24XX_PWRDM_POWER_RET		0x1
  36
+#define OMAP24XX_PWRDM_POWER_OFF		0x3
  37
+
  38
+/*
31 39
  * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
32 40
  *   hardware register (which are specific to the OMAP2xxx SoCs) to
33 41
  *   reset source ID bit shifts (which is an OMAP SoC-independent
@@ -68,6 +76,34 @@ static u32 omap2xxx_prm_read_reset_sources(void)
68 76
 }
69 77
 
70 78
 /**
  79
+ * omap2xxx_pwrst_to_common_pwrst - convert OMAP2xxx pwrst to common pwrst
  80
+ * @omap2xxx_pwrst: OMAP2xxx hardware power state to convert
  81
+ *
  82
+ * Return the common power state bits corresponding to the OMAP2xxx
  83
+ * hardware power state bits @omap2xxx_pwrst, or -EINVAL upon error.
  84
+ */
  85
+static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst)
  86
+{
  87
+	u8 pwrst;
  88
+
  89
+	switch (omap2xxx_pwrst) {
  90
+	case OMAP24XX_PWRDM_POWER_OFF:
  91
+		pwrst = PWRDM_POWER_OFF;
  92
+		break;
  93
+	case OMAP24XX_PWRDM_POWER_RET:
  94
+		pwrst = PWRDM_POWER_RET;
  95
+		break;
  96
+	case OMAP24XX_PWRDM_POWER_ON:
  97
+		pwrst = PWRDM_POWER_ON;
  98
+		break;
  99
+	default:
  100
+		return -EINVAL;
  101
+	}
  102
+
  103
+	return pwrst;
  104
+}
  105
+
  106
+/**
71 107
  * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
72 108
  *
73 109
  * Set the DPLL reset bit, which should reboot the SoC.  This is the
@@ -97,10 +133,56 @@ int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
97 133
 	return 0;
98 134
 }
99 135
 
  136
+static int omap2xxx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
  137
+{
  138
+	u8 omap24xx_pwrst;
  139
+
  140
+	switch (pwrst) {
  141
+	case PWRDM_POWER_OFF:
  142
+		omap24xx_pwrst = OMAP24XX_PWRDM_POWER_OFF;
  143
+		break;
  144
+	case PWRDM_POWER_RET:
  145
+		omap24xx_pwrst = OMAP24XX_PWRDM_POWER_RET;
  146
+		break;
  147
+	case PWRDM_POWER_ON:
  148
+		omap24xx_pwrst = OMAP24XX_PWRDM_POWER_ON;
  149
+		break;
  150
+	default:
  151
+		return -EINVAL;
  152
+	}
  153
+
  154
+	omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
  155
+				   (omap24xx_pwrst << OMAP_POWERSTATE_SHIFT),
  156
+				   pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
  157
+	return 0;
  158
+}
  159
+
  160
+static int omap2xxx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
  161
+{
  162
+	u8 omap2xxx_pwrst;
  163
+
  164
+	omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
  165
+						       OMAP2_PM_PWSTCTRL,
  166
+						       OMAP_POWERSTATE_MASK);
  167
+
  168
+	return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
  169
+}
  170
+
  171
+static int omap2xxx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
  172
+{
  173
+	u8 omap2xxx_pwrst;
  174
+
  175
+	omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
  176
+						       OMAP2_PM_PWSTST,
  177
+						       OMAP_POWERSTATEST_MASK);
  178
+
  179
+	return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
  180
+}
  181
+
100 182
 struct pwrdm_ops omap2_pwrdm_operations = {
101  
-	.pwrdm_set_next_pwrst	= omap2_pwrdm_set_next_pwrst,
102  
-	.pwrdm_read_next_pwrst	= omap2_pwrdm_read_next_pwrst,
103  
-	.pwrdm_read_pwrst	= omap2_pwrdm_read_pwrst,
  183
+	.pwrdm_set_next_pwrst	= omap2xxx_pwrdm_set_next_pwrst,
  184
+	.pwrdm_read_next_pwrst	= omap2xxx_pwrdm_read_next_pwrst,
  185
+	.pwrdm_read_pwrst	= omap2xxx_pwrdm_read_pwrst,
104 186
 	.pwrdm_set_logic_retst	= omap2_pwrdm_set_logic_retst,
105 187
 	.pwrdm_set_mem_onst	= omap2_pwrdm_set_mem_onst,
106 188
 	.pwrdm_set_mem_retst	= omap2_pwrdm_set_mem_retst,
22  arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -103,28 +103,6 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
103 103
 /* Powerdomain low-level functions */
104 104
 
105 105
 /* Common functions across OMAP2 and OMAP3 */
106  
-int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
107  
-{
108  
-	omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
109  
-				   (pwrst << OMAP_POWERSTATE_SHIFT),
110  
-				   pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
111  
-	return 0;
112  
-}
113  
-
114  
-int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
115  
-{
116  
-	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
117  
-					     OMAP2_PM_PWSTCTRL,
118  
-					     OMAP_POWERSTATE_MASK);
119  
-}
120  
-
121  
-int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
122  
-{
123  
-	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
124  
-					     OMAP2_PM_PWSTST,
125  
-					     OMAP_POWERSTATEST_MASK);
126  
-}
127  
-
128 106
 int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
129 107
 								u8 pwrst)
130 108
 {
28  arch/arm/mach-omap2/prm3xxx.c
@@ -277,6 +277,28 @@ static u32 omap3xxx_prm_read_reset_sources(void)
277 277
 
278 278
 /* Powerdomain low-level functions */
279 279
 
  280
+static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
  281
+{
  282
+	omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
  283
+				   (pwrst << OMAP_POWERSTATE_SHIFT),
  284
+				   pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
  285
+	return 0;
  286
+}
  287
+
  288
+static int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
  289
+{
  290
+	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
  291
+					     OMAP2_PM_PWSTCTRL,
  292
+					     OMAP_POWERSTATE_MASK);
  293
+}
  294
+
  295
+static int omap3_pwrdm_read_pwrst(struct powerdomain *pwrdm)
  296
+{
  297
+	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
  298
+					     OMAP2_PM_PWSTST,
  299
+					     OMAP_POWERSTATEST_MASK);
  300
+}
  301
+
280 302
 /* Applicable only for OMAP3. Not supported on OMAP2 */
281 303
 static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
282 304
 {
@@ -355,9 +377,9 @@ static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
355 377
 }
356 378
 
357 379
 struct pwrdm_ops omap3_pwrdm_operations = {
358  
-	.pwrdm_set_next_pwrst	= omap2_pwrdm_set_next_pwrst,
359  
-	.pwrdm_read_next_pwrst	= omap2_pwrdm_read_next_pwrst,
360  
-	.pwrdm_read_pwrst	= omap2_pwrdm_read_pwrst,
  380
+	.pwrdm_set_next_pwrst	= omap3_pwrdm_set_next_pwrst,
  381
+	.pwrdm_read_next_pwrst	= omap3_pwrdm_read_next_pwrst,
  382
+	.pwrdm_read_pwrst	= omap3_pwrdm_read_pwrst,
361 383
 	.pwrdm_read_prev_pwrst	= omap3_pwrdm_read_prev_pwrst,
362 384
 	.pwrdm_set_logic_retst	= omap2_pwrdm_set_logic_retst,
363 385
 	.pwrdm_read_logic_pwrst	= omap3_pwrdm_read_logic_pwrst,
6  arch/arm/mach-omap2/prm44xx.c
@@ -56,9 +56,9 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
56 56
  *   enumeration)
57 57
  */
58 58
 static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
59  
-	{ OMAP4430_RST_GLOBAL_WARM_SW_SHIFT,
  59
+	{ OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
60 60
 	  OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
61  
-	{ OMAP4430_RST_GLOBAL_COLD_SW_SHIFT,
  61
+	{ OMAP4430_GLOBAL_COLD_RST_SHIFT,
62 62
 	  OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
63 63
 	{ OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
64 64
 	  OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
@@ -333,7 +333,7 @@ static u32 omap44xx_prm_read_reset_sources(void)
333 333
 	u32 r = 0;
334 334
 	u32 v;
335 335
 
336  
-	v = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
  336
+	v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
337 337
 				    OMAP4_RM_RSTST);
338 338
 
339 339
 	p = omap44xx_prm_reset_src_map;
4  arch/arm/mach-omap2/prm44xx.h
@@ -62,8 +62,8 @@
62 62
 
63 63
 /* OMAP4 specific register offsets */
64 64
 #define OMAP4_RM_RSTCTRL				0x0000
65  
-#define OMAP4_RM_RSTTIME				0x0004
66  
-#define OMAP4_RM_RSTST					0x0008
  65
+#define OMAP4_RM_RSTST					0x0004
  66
+#define OMAP4_RM_RSTTIME				0x0008
67 67
 #define OMAP4_PM_PWSTCTRL				0x0000
68 68
 #define OMAP4_PM_PWSTST					0x0004
69 69
 
2  arch/arm/plat-omap/counter_32k.c
@@ -22,6 +22,8 @@
22 22
 #include <asm/mach/time.h>
23 23
 #include <asm/sched_clock.h>
24 24
 
  25
+#include <plat/counter-32k.h>
  26
+