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  1. Various projects for the Nexys4DDR board from Digilent

    VHDL 106 13

  2. A very simple chess engine

    C++ 44 17

  3. A fully functioning chess engine

    C++ 15 5

  4. Implementation of the 65C02 CPU suitable for FPGA.

    Assembly 13

  5. 8-bit computer

    VHDL 9 1

  6. 8-bit computer

    VHDL 5

477 contributions in the last year

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Contribution activity

October 1, 2020

MJoergen has no activity yet for this period.

September 2020

Created an issue in sy2002/QNICE-FPGA that received 26 comments

The M-L monitor command drops part of large files over UART on Nexys4DDR

Steps to reproduce: Connect to the Nexys4DDR via the UART using a serial terminal program. Issue the Memory (M) Load (L) command. Paste a large pr…


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