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Branch: jailhouse
Commits on Dec 18, 2019
  1. WIP: Initial Cortex-A53 support for i.MX8MM SoC and board

    Mani-Sadhasivam committed Dec 13, 2019
    Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Commits on Dec 13, 2019
  1. gic-v3: Modify the driver to use similar interface as of GIC-V2

    Mani-Sadhasivam committed Dec 13, 2019
    Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
  2. drivers: add GIC V3 driver

    sandeepbrcm authored and Mani-Sadhasivam committed Nov 6, 2019
    Add driver for GIC V3 interrupt controller.
    This implementation supports
     - SGI PPI and SPI handling.
     - Provides basic configuration of interrupts
       on distributor and re-distributor.
     - Assumes no legacy mode support and hence uses
       cpu system interface.
       ICC_SRE_EL3 initialization must be done by previous
       stage firmware eg: trusted-firmware-a
    
    The driver registers to irq manamenent framework 'gicv3'
    chip specific ops and first level interrupt handler. It
    uses the framework generic handler to process the interrupt.
    
    Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Commits on Nov 30, 2019
  1. arch: arm64: Enable config option to switch from EL3 to EL1

    carlocaione authored and Mani-Sadhasivam committed Nov 20, 2019
    ARMv8-A SoCs enter EL3 after reset. Add a new config option
    (CONFIG_SWITCH_TO_EL1) to switch from EL3 to EL1 at boot and default it
    to 'y'.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  2. arch: arm64: Fix logging test

    carlocaione authored and Mani-Sadhasivam committed Nov 18, 2019
    We need a slightly bigger stack to be able to successfully pass the
    logging test. Fix the stack size and enable back the test.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  3. arch: arm64: Enable tracing

    carlocaione authored and Mani-Sadhasivam committed Nov 18, 2019
    Enable the tracing hooks on the ARM64 platform and white-list the
    tracing tests.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  4. arch: arm64: Support all the ELn

    carlocaione authored and Mani-Sadhasivam committed Nov 14, 2019
    While QEMU's Cortex-A53 emulation by default only emulates a CPU in EL1,
    other QEMU forks (for example the QEMU released by Xilinx) and real
    hardware starts in EL3.
    
    To support all the ELn we introduce a macro to identify at run-time the
    Exception Level and take the correct actions.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  5. arch: arm64: Support zephyr toolchain

    carlocaione authored and Mani-Sadhasivam committed Nov 13, 2019
    ARM64 is a valid target for the zephyr toolchain. Add support for it.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  6. arch: arm64: Add support for qemu_cortex_a53 board

    carlocaione authored and Mani-Sadhasivam committed Nov 10, 2019
    This patch introduces support for the qemu_cortex_a53 board emulated
    using QEMU (virt platform) adding SoC, board and DTS files.
    
    | ./scripts/sanitycheck -p qemu_cortex_a53
    |
    | ...
    | 110 of 145 tests passed (100.00%), 0 failed,
    |	35 skipped with 0 warnings in 256.09 seconds
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  7. tests: benchmarks: Add ARM64 case

    carlocaione authored and Mani-Sadhasivam committed Nov 11, 2019
    To be able to pass the unit test we need to add a set of defines for the
    ARM64 architecture. Fix this.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  8. tests: testsuite: Add Cortex-A case

    carlocaione authored and Mani-Sadhasivam committed Nov 11, 2019
    The test requires a new define to be able to support Cortex-A. Add the
    missing define.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  9. interrupt_controller: gic: Enable GIC-400 for Cortex-A

    carlocaione authored and Mani-Sadhasivam committed Nov 4, 2019
    The GIC is supported also by Cortex-A. Change its Kconfig dependencies
    to reflect this.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  10. arch: arm64: Support aarch64-gcc compiler

    carlocaione authored and Mani-Sadhasivam committed Nov 10, 2019
    To be able to successfully compile the kernel for the ARM64 architecture
    we have to tweak the compiler-related files to be able to use the
    AArch64 GCC compiler.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  11. arch: arm64: Introduce ARM64 (AArch64) architecture

    carlocaione authored and Mani-Sadhasivam committed Nov 10, 2019
    Introduce the basic ARM64 architecture support.
    
    A new CONFIG_ARM64 symbol is introduced for the new architecture and new
    cmake / Kconfig files are added to switch between ARM and ARM64.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  12. drivers: timer: Add per-core ARM architected timer

    carlocaione authored and Mani-Sadhasivam committed Oct 27, 2019
    ARM cores may have a per-core architected timer, which provides per-cpu
    timers, attached to a GIC to deliver its per-processor interrupts via
    PPIs. This is the most common case supported by QEMU in the virt
    platform.
    
    This patch introduces support for this timer abstracting the way the
    timer registers are actually accessed. This is needed because different
    architectures (for example ARMv7-R vs ARMv8-A) use different registers
    and even the same architecture (ARMv8-A) can actually use different
    timers (ELx physical timers vs ELx virtual timers).
    
    So we introduce the common driver here but the actual SoC / architecture
    / board must provide the three helpers (arm_arch_timer_set_compare(),
    arm_arch_timer_toggle(), arm_arch_timer_count()) using an header file
    imported through the arch/cpu.h header file.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  13. arch: arm: Fix header guards

    carlocaione authored and Mani-Sadhasivam committed Nov 9, 2019
    Fix the header guards for the ARM header files to reflect the new code
    location.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  14. arch: arm: Move ARM code to AArch32 sub-directory

    carlocaione authored and Mani-Sadhasivam committed Nov 9, 2019
    Before introducing the code for ARM64 (AArch64) we need to relocate the
    current ARM code to a new AArch32 sub-directory. For now we can assume
    that no code is shared between ARM and ARM64.
    
    There are no functional changes. The code is moved to the new location
    and the file paths are fixed to reflect this change.
    
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
  15. scripts: dts: Support GIC interrupt type-specific IRQ number fix up.

    stephanosio authored and Mani-Sadhasivam committed Nov 8, 2019
    The ARM Generic Interrupt Controller (GIC) supports multiple interrupt
    types whose linear IRQ numbers are offset by a type-specific base
    number.
    
    This commit adds a function to automatically fix up ARM GIC interrupts
    in order to output a linear IRQ number that is offset by the interrupt
    type-specific base number.
    
    For more details, refer to the issue zephyrproject-rtos#19860.
    
    Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
  16. interrupt_controller: gic: Support PPIs

    carlocaione authored and Mani-Sadhasivam committed Oct 18, 2019
    The GIC-400 driver currently only supports SPIs because the (32) offset
    for the INTIDs is hard-coded in the driver. At the driver level there is
    no really difference between PPIs and SPIs so we can easily extend the
    driver to support PPIs as well.
    
    This is useful if we want to add support for the ARM Generic Timers that
    use INTIDs in the PPI range.
    
    SPI interrupts are in the range [0-987]. PPI interrupts are in the range
    [0-15].
    
    This commit adds interrupt 'type' cell to the GIC device tree binding
    and changes the 'irq' cell to use interrupt type-specific index, rather
    than a linear IRQ number.
    
    The 'type'+'irq (index)' combo is automatically fixed up into a linear
    IRQ number by the scripts/dts/gen_defines.py script.
    
    Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
    Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Commits on Nov 29, 2019
  1. Bluetooth: L2CAP: Fix unrefing buffers that are queued

    Vudentz authored and jhedberg committed Nov 28, 2019
    Processing of data received on dynamic channels is still done via syswq
    so the buffer shall not be unrefed when they are queued.
    
    Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
  2. Bluetooth: L2CAP: Fix not unrefing tx_buf

    Vudentz authored and jhedberg committed Nov 19, 2019
    If the channel has a tx_buf it must be unrefed when destroying the
    channel.
    
    Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
  3. usb: usb_dc_native_posix: Refactor similar code to function

    finikorg authored and nashif committed Nov 22, 2019
    Use skip_setup() function helper in a place we need to skip setup
    data.
    
    Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
  4. usb: usb_dc_native_posix: Use return code for skip_setup()

    finikorg authored and nashif committed Nov 21, 2019
    Use return code for usbip_skip_setup()
    
    Fixes zephyrproject-rtos#20840
    
    Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
  5. usb: usb_dc_native_posix: Check return code in handle_usb_data()

    finikorg authored and nashif committed Nov 21, 2019
    Fixes coverity complaints dealing with send()
    
    Fixes zephyrproject-rtos#20839
    Fixes zephyrproject-rtos#20841
    
    Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
  6. usb: usb_dc_native_posix: Fix buffer and max data 0 case

    finikorg authored and nashif committed Nov 21, 2019
    When both buffer and max data to read are zero return
    the available data in buffer.
    
    Fixes zephyrproject-rtos#20838
    
    Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
  7. usb: usb_dc_native_posix: Check return values in dc_write()

    finikorg authored and nashif committed Nov 21, 2019
    Fixes coverity issue:
    
    Fixes zephyrproject-rtos#20836
    Fixes zephyrproject-rtos#20837
    
    Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
  8. usb: usb_dc_native_posix_adapt: Check correct size

    finikorg authored and nashif committed Nov 21, 2019
    Fixes Coverity issues
    
    Fixes zephyrproject-rtos#20842
    
    Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
  9. kernel: init: simplify boot banner printing

    nashif committed Nov 28, 2019
    Just use printk directly instead of going over defines.
    
    For some reason, this change lets us pass on master when running
    tests/kernel/timer/timer_monotonic test. This test started failing after
    rc2 was tagged, just because the changing git version string passing to
    BUILD_VERSION. This is still under investigation.
    
    Signed-off-by: Anas Nashif <anas.nashif@intel.com>
  10. drivers: nrf: Add CTS and RTS pins to UART and UARTE PM

    Mierunski authored and ioannisg committed Nov 26, 2019
    Add gpio management for CTS and RTS pins in UART and UARTE drivers
    
    Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Commits on Nov 28, 2019
  1. test: pwm_api: fix test for nRF based boards

    jfischer-phytec-iot authored and nashif committed Nov 28, 2019
    Fix pwm_api test for nRF based boards.
    
    Fixes: zephyrproject-rtos#20176
    
    Signed-off-by: Johann Fischer <j.fischer@phytec.de>
  2. drivers: nrf_clock_calibration: wait for sensor initialization

    Peter Bigot authored and nashif committed Nov 12, 2019
    When using the RC clock source a periodic calibration is invoked that
    involves reading from the die temperature sensor.  The code did not
    protect against execution order that caused the periodic calibration
    to be invoked before the temperature sensor was initialized.
    
    Update the temperature sensor to detect that it has not been
    initialized and so should reject attempts to fetch a reading.
    
    Update the calibration code to do nothing when temperature reading
    fails.
    
    Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
  3. usb: hid core: fix call by reference

    jfischer-phytec-iot authored and nashif committed Nov 27, 2019
    Fix call by reference.
    
    Fixes: zephyrproject-rtos#20872
    Coverity CID :205779
    
    Signed-off-by: Johann Fischer <j.fischer@phytec.de>
  4. drivers: flash_handlers fixes stray semicolon

    agansari authored and nashif committed Nov 12, 2019
    z_vrfy_flash_get_page_count defined as a function prototype in place of
    a real function due to a stray semicolon.
    
    Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
  5. Bluetooth: host: Fix ordering of TX sent callbacks

    jhedberg committed Nov 28, 2019
    Now that the TX callbacks happen from the system workqueue but fixed
    channels get processed from the RX thread there's a risk that the
    ordering of these gets messed up. This is particularly bad for ATT
    when it's trying to enforce flow control.
    
    To fix the issue store the completed TX packet information in a
    per-connection list and process this list before processing any new
    packets for the same connection. We still also schedule a workqueue
    callback, which will simply do nothing for this list if bt_recv()
    already took care of it.
    
    Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
  6. counter: mchp_xec: fix logical/bit-wise AND

    dcpleung authored and nashif committed Nov 27, 2019
    Coverity discovered that a logical AND was used in place of
    a bit-wise AND. So fix it.
    
    Fixes zephyrproject-rtos#20489
    
    Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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