{"payload":{"header_redesign_enabled":false,"results":[{"id":"308259391","archived":false,"color":"#b2b7f8","followers":10,"has_funding_file":false,"hl_name":"Matrixpecker/VE370-Pipelined-Processor","hl_trunc_description":"An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) of UM-SJTU JI.","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":308259391,"name":"VE370-Pipelined-Processor","owner_id":43488501,"owner_login":"Matrixpecker","updated_at":"2020-12-28T18:07:57.023Z","has_issues":true}},"sponsorable":false,"topics":["cpu","pipeline","hazard-detection","computer-organisation-architechure","pipelined-processors"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":74,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AMatrixpecker%252FVE370-Pipelined-Processor%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/Matrixpecker/VE370-Pipelined-Processor/star":{"post":"n5_qLx4TBraHNoGfL1KcMQKNRaYNfKPNIlzoqL5F4sdDvvpwuq4hUi3Rnt6-FchUiZ8xvzfFD61pPjkwjTZNQw"},"/Matrixpecker/VE370-Pipelined-Processor/unstar":{"post":"MotR89iAETsqfvFY36OrAljJHvpHvrdxIN-xfVi-GkD_eYvUNcfiVnACV0qjfyhjdQJp4CcS2F4UshYuo_RT_w"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"rxFc7wWJD4aE5rYIP-122YBAiX5jOcfMcNrWmvNcpg3dZ8javP2uD0Udsix7qmgbyKSAyq77e6ASgCq4EBaSqg"}}},"title":"Repository search results"}