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db | ||
greybox_tmp | ||
incremental_db | ||
output_files | ||
simulation | ||
hc_output | ||
scaler | ||
hps_isw_handoff | ||
vip | ||
*_sim | ||
.qsys_edit | ||
PLLJ_PLLSPE_INFO.txt | ||
*.bak | ||
*.orig | ||
*.rej | ||
*.qdf | ||
*.rpt | ||
*.smsg | ||
*.summary | ||
*.done | ||
*.jdi | ||
*.pin | ||
*.sof | ||
*.qws | ||
*.ppf | ||
*.ddb | ||
build_id.v | ||
c5_pin_model_dump.txt | ||
*.sopcinfo | ||
*.csv | ||
*.f | ||
*.cmp | ||
*.sip | ||
*.spd | ||
*.bsf | ||
*~ | ||
*.xml | ||
*.cdf | ||
*.qarlog | ||
qar_info.json |
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# -------------------------------------------------------------------------- # | ||
# | ||
# Copyright (C) 2017 Intel Corporation. All rights reserved. | ||
# Your use of Intel Corporation's design tools, logic functions | ||
# and other software and tools, and its AMPP partner logic | ||
# functions, and any output files from any of the foregoing | ||
# (including device programming or simulation files), and any | ||
# associated documentation or information are expressly subject | ||
# to the terms and conditions of the Intel Program License | ||
# Subscription Agreement, the Intel Quartus Prime License Agreement, | ||
# the Intel FPGA IP License Agreement, or other applicable license | ||
# agreement, including, without limitation, that your use is for | ||
# the sole purpose of programming logic devices manufactured by | ||
# Intel and sold by Intel or its authorized distributors. Please | ||
# refer to the applicable agreement for further details. | ||
# | ||
# -------------------------------------------------------------------------- # | ||
# | ||
# Quartus Prime | ||
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition | ||
# Date created = 15:16:46 March 14, 2019 | ||
# | ||
# -------------------------------------------------------------------------- # | ||
|
||
QUARTUS_VERSION = "17.1" | ||
DATE = "15:16:46 March 14, 2019" | ||
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# Revisions | ||
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PROJECT_REVISION = "Arcade-Sprint1" |
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