diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..57b5f1a
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,40 @@
+db
+greybox_tmp
+incremental_db
+output_files
+simulation
+hc_output
+scaler
+hps_isw_handoff
+vip
+*_sim
+.qsys_edit
+PLLJ_PLLSPE_INFO.txt
+*.bak
+*.orig
+*.rej
+*.qdf
+*.rpt
+*.smsg
+*.summary
+*.done
+*.jdi
+*.pin
+*.sof
+*.qws
+*.ppf
+*.ddb
+build_id.v
+c5_pin_model_dump.txt
+*.sopcinfo
+*.csv
+*.f
+*.cmp
+*.sip
+*.spd
+*.bsf
+*~
+*.xml
+*.cdf
+*.qarlog
+qar_info.json
\ No newline at end of file
diff --git a/Arcade-Sprint1.qpf b/Arcade-Sprint1.qpf
new file mode 100644
index 0000000..fa3ce46
--- /dev/null
+++ b/Arcade-Sprint1.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+# Date created = 15:16:46  March 14, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "17.1"
+DATE = "15:16:46  March 14, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "Arcade-Sprint1"
diff --git a/Arcade-Sprint1.qsf b/Arcade-Sprint1.qsf
new file mode 100644
index 0000000..00cd1e5
--- /dev/null
+++ b/Arcade-Sprint1.qsf
@@ -0,0 +1,419 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 20:32:26  January 30, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Arcade-Sprint1_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Intel and sold by Intel or its
+# authorized distributors.  Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
+# Date created = 01:53:32  April 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name VERILOG_MACRO "LITE=1"
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEBA6U23I7
+set_global_assignment -name TOP_LEVEL_ENTITY sys_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:16:32  MARCH 14, 2019"
+set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
+set_global_assignment -name ECO_OPTIMIZE_TIMING ON
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION AUTO
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
+
+#============================================================
+# ADC
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+set_location_assignment PIN_U9 -to ADC_CONVST
+set_location_assignment PIN_V10 -to ADC_SCK
+set_location_assignment PIN_AC4 -to ADC_SDI
+set_location_assignment PIN_AD4 -to ADC_SDO
+
+#============================================================
+# ARDUINO
+#============================================================
+set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
+set_location_assignment PIN_U14 -to ARDUINO_IO[4]
+set_location_assignment PIN_U13 -to ARDUINO_IO[5]
+set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
+set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
+set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
+set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
+
+#============================================================
+# USER PORT
+#============================================================
+set_location_assignment PIN_AF15 -to USER_IO[5]
+set_location_assignment PIN_AG16 -to USER_IO[4]
+set_location_assignment PIN_AH11 -to USER_IO[3]
+set_location_assignment PIN_AH12 -to USER_IO[2]
+set_location_assignment PIN_AH9 -to USER_IO[1]
+set_location_assignment PIN_AG11 -to USER_IO[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*]
+
+#============================================================
+# SDIO
+#============================================================
+set_location_assignment PIN_AF25 -to SDIO_DAT[0]
+set_location_assignment PIN_AF23 -to SDIO_DAT[1]
+set_location_assignment PIN_AD26 -to SDIO_DAT[2]
+set_location_assignment PIN_AF28 -to SDIO_DAT[3]
+set_location_assignment PIN_AF27 -to SDIO_CMD
+set_location_assignment PIN_AH26 -to SDIO_CLK
+set_location_assignment PIN_AH7 -to SDIO_CD
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
+
+#============================================================
+# VGA
+#============================================================
+set_location_assignment PIN_AE17 -to VGA_R[0]
+set_location_assignment PIN_AE20 -to VGA_R[1]
+set_location_assignment PIN_AF20 -to VGA_R[2]
+set_location_assignment PIN_AH18 -to VGA_R[3]
+set_location_assignment PIN_AH19 -to VGA_R[4]
+set_location_assignment PIN_AF21 -to VGA_R[5]
+
+set_location_assignment PIN_AE19 -to VGA_G[0]
+set_location_assignment PIN_AG15 -to VGA_G[1]
+set_location_assignment PIN_AF18 -to VGA_G[2]
+set_location_assignment PIN_AG18 -to VGA_G[3]
+set_location_assignment PIN_AG19 -to VGA_G[4]
+set_location_assignment PIN_AG20 -to VGA_G[5]
+
+set_location_assignment PIN_AG21 -to VGA_B[0]
+set_location_assignment PIN_AA20 -to VGA_B[1]
+set_location_assignment PIN_AE22 -to VGA_B[2]
+set_location_assignment PIN_AF22 -to VGA_B[3]
+set_location_assignment PIN_AH23 -to VGA_B[4]
+set_location_assignment PIN_AH21 -to VGA_B[5]
+
+set_location_assignment PIN_AH22 -to VGA_HS
+set_location_assignment PIN_AG24 -to VGA_VS
+
+set_location_assignment PIN_AH27 -to VGA_EN
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
+
+#============================================================
+# AUDIO
+#============================================================
+set_location_assignment PIN_AC24 -to AUDIO_L
+set_location_assignment PIN_AE25 -to AUDIO_R
+set_location_assignment PIN_AG26 -to AUDIO_SPDIF
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
+
+#============================================================
+# SDRAM
+#============================================================
+set_location_assignment PIN_Y11 -to SDRAM_A[0]
+set_location_assignment PIN_AA26 -to SDRAM_A[1]
+set_location_assignment PIN_AA13 -to SDRAM_A[2]
+set_location_assignment PIN_AA11 -to SDRAM_A[3]
+set_location_assignment PIN_W11 -to SDRAM_A[4]
+set_location_assignment PIN_Y19 -to SDRAM_A[5]
+set_location_assignment PIN_AB23 -to SDRAM_A[6]
+set_location_assignment PIN_AC23 -to SDRAM_A[7]
+set_location_assignment PIN_AC22 -to SDRAM_A[8]
+set_location_assignment PIN_C12 -to SDRAM_A[9]
+set_location_assignment PIN_AB26 -to SDRAM_A[10]
+set_location_assignment PIN_AD17 -to SDRAM_A[11]
+set_location_assignment PIN_D12 -to SDRAM_A[12]
+set_location_assignment PIN_Y17 -to SDRAM_BA[0]
+set_location_assignment PIN_AB25 -to SDRAM_BA[1]
+
+set_location_assignment PIN_E8 -to SDRAM_DQ[0]
+set_location_assignment PIN_V12 -to SDRAM_DQ[1]
+set_location_assignment PIN_D11 -to SDRAM_DQ[2]
+set_location_assignment PIN_W12 -to SDRAM_DQ[3]
+set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
+set_location_assignment PIN_D8 -to SDRAM_DQ[5]
+set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
+set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
+set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
+set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
+set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
+set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
+set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
+set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
+set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
+set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
+set_location_assignment PIN_AG13 -to SDRAM_DQML
+set_location_assignment PIN_AF13 -to SDRAM_DQMH
+
+set_location_assignment PIN_AD20 -to SDRAM_CLK
+set_location_assignment PIN_AG10 -to SDRAM_CKE
+
+set_location_assignment PIN_AA19 -to SDRAM_nWE
+set_location_assignment PIN_AA18 -to SDRAM_nCAS
+set_location_assignment PIN_Y18 -to SDRAM_nCS
+set_location_assignment PIN_W14 -to SDRAM_nRAS
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
+
+#============================================================
+# I/O
+#============================================================
+set_location_assignment PIN_Y15 -to LED_USER
+set_location_assignment PIN_AA15 -to LED_HDD
+set_location_assignment PIN_AG28 -to LED_POWER
+
+set_location_assignment PIN_AH24 -to BTN_USER
+set_location_assignment PIN_AG25 -to BTN_OSD
+set_location_assignment PIN_AG23 -to BTN_RESET
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
+
+#============================================================
+# CLOCK
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
+set_location_assignment PIN_V11 -to FPGA_CLK1_50
+set_location_assignment PIN_Y13 -to FPGA_CLK2_50
+set_location_assignment PIN_E11 -to FPGA_CLK3_50
+
+#============================================================
+# HDMI
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
+set_location_assignment PIN_U10 -to HDMI_I2C_SCL
+set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
+set_location_assignment PIN_T13 -to HDMI_I2S
+set_location_assignment PIN_T11 -to HDMI_LRCLK
+set_location_assignment PIN_U11 -to HDMI_MCLK
+set_location_assignment PIN_T12 -to HDMI_SCLK
+set_location_assignment PIN_AG5 -to HDMI_TX_CLK
+set_location_assignment PIN_AD19 -to HDMI_TX_DE
+set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
+set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
+set_location_assignment PIN_W8 -to HDMI_TX_D[2]
+set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
+set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
+set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
+set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
+set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
+set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
+set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
+set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
+set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
+set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
+set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
+set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
+set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
+set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
+set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
+set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
+set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
+set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
+set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
+set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
+set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
+set_location_assignment PIN_T8 -to HDMI_TX_HS
+set_location_assignment PIN_AF11 -to HDMI_TX_INT
+set_location_assignment PIN_V13 -to HDMI_TX_VS
+
+#============================================================
+# KEY
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_location_assignment PIN_AH17 -to KEY[0]
+set_location_assignment PIN_AH16 -to KEY[1]
+
+#============================================================
+# LED
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
+set_location_assignment PIN_W15 -to LED[0]
+set_location_assignment PIN_AA24 -to LED[1]
+set_location_assignment PIN_V16 -to LED[2]
+set_location_assignment PIN_V15 -to LED[3]
+set_location_assignment PIN_AF26 -to LED[4]
+set_location_assignment PIN_AE26 -to LED[5]
+set_location_assignment PIN_Y16 -to LED[6]
+set_location_assignment PIN_AA23 -to LED[7]
+
+#============================================================
+# SW
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_location_assignment PIN_Y24 -to SW[0]
+set_location_assignment PIN_W24 -to SW[1]
+set_location_assignment PIN_W21 -to SW[2]
+set_location_assignment PIN_W20 -to SW[3]
+
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
+
+
+set_global_assignment -name SYSTEMVERILOG_FILE "Arcade-Sprint1.sv"
+set_global_assignment -name VHDL_FILE dpram.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE src/gearshift.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/joy2quad.sv
+set_global_assignment -name VHDL_FILE src/T65/T65_Pack.vhd
+set_global_assignment -name VHDL_FILE src/T65/T65_MCode.vhd
+set_global_assignment -name VHDL_FILE src/T65/T65_ALU.vhd
+set_global_assignment -name VHDL_FILE src/T65/T65.vhd
+set_global_assignment -name VHDL_FILE src/sync.vhd
+set_global_assignment -name VHDL_FILE src/sprint1_sound.vhd
+set_global_assignment -name VHDL_FILE src/sprint1.vhd
+set_global_assignment -name VHDL_FILE src/screech.vhd
+set_global_assignment -name VHDL_FILE src/playfield.vhd
+set_global_assignment -name VHDL_FILE src/motion.vhd
+set_global_assignment -name VHDL_FILE src/Inputs.vhd
+set_global_assignment -name VHDL_FILE src/EngineSound.vhd
+set_global_assignment -name VHDL_FILE src/deltasigma.vhd
+set_global_assignment -name VHDL_FILE src/cpu_mem.vhd
+set_global_assignment -name VHDL_FILE src/collision.vhd
+set_global_assignment -name CDF_FILE jtag.cdf
+set_global_assignment -name QIP_FILE sys/sys.qip
+set_global_assignment -name QIP_FILE src/Altera/ram1k_dp.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade-Sprint1.sv b/Arcade-Sprint1.sv
new file mode 100644
index 0000000..03bdf42
--- /dev/null
+++ b/Arcade-Sprint1.sv
@@ -0,0 +1,338 @@
+//============================================================================
+//  Sprint1 port to MiSTer
+//  Copyright (c) 2019 Alan Steremberg - alanswx
+//
+//   
+//============================================================================
+
+module emu
+(
+	//Master input clock
+	input         CLK_50M,
+
+	//Async reset from top-level module.
+	//Can be used as initial reset.
+	input         RESET,
+
+	//Must be passed to hps_io module
+	inout  [44:0] HPS_BUS,
+
+	//Base video clock. Usually equals to CLK_SYS.
+	output        VGA_CLK,
+
+	//Multiple resolutions are supported using different VGA_CE rates.
+	//Must be based on CLK_VIDEO
+	output        VGA_CE,
+
+	output  [7:0] VGA_R,
+	output  [7:0] VGA_G,
+	output  [7:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        VGA_DE,    // = ~(VBlank | HBlank)
+
+	//Base video clock. Usually equals to CLK_SYS.
+	output        HDMI_CLK,
+
+	//Multiple resolutions are supported using different HDMI_CE rates.
+	//Must be based on CLK_VIDEO
+	output        HDMI_CE,
+
+	output  [7:0] HDMI_R,
+	output  [7:0] HDMI_G,
+	output  [7:0] HDMI_B,
+	output        HDMI_HS,
+	output        HDMI_VS,
+	output        HDMI_DE,   // = ~(VBlank | HBlank)
+	output  [1:0] HDMI_SL,   // scanlines fx
+
+	//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
+	output  [7:0] HDMI_ARX,
+	output  [7:0] HDMI_ARY,
+
+	output        LED_USER,  // 1 - ON, 0 - OFF.
+
+	// b[1]: 0 - LED status is system status OR'd with b[0]
+	//       1 - LED status is controled solely by b[0]
+	// hint: supply 2'b00 to let the system control the LED.
+	output  [1:0] LED_POWER,
+	output  [1:0] LED_DISK,
+
+	output [15:0] AUDIO_L,
+	output [15:0] AUDIO_R,
+	output        AUDIO_S    // 1 - signed audio samples, 0 - unsigned
+);
+
+assign LED_USER  = ioctl_download;
+assign LED_DISK  = 0;
+assign LED_POWER = lamp;
+
+assign HDMI_ARX = status[1] ? 8'd16 : 8'd4;
+assign HDMI_ARY = status[1] ? 8'd9  : 8'd3;
+
+`include "build_id.v"
+localparam CONF_STR = {
+	"A.SPRINT1;;",
+	"-;",
+	"O1,Aspect Ratio,Original,Wide;",
+	"O35,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",  
+	"-;",
+	"O8,Oil Slicks,On,Off;",
+	"O9,Cycle tracks,every lap,every two laps;",
+	"OA,Extended Play,extended,normal;",
+	"OBC,Game time,150 Sec,120 Sec,90 Sec,60 Sec;",
+	"OD,Test,Off,On;",
+	"-;",
+	"R0,Reset;",
+	"J1,Gas,GearUp,GearDown,Start 1P,Start 2P;",
+	"V,v",`BUILD_DATE
+};
+
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire        forced_scandoubler;
+
+wire        ioctl_download;
+wire        ioctl_wr;
+wire [24:0] ioctl_addr;
+wire [7:0] ioctl_data;
+
+wire [10:0] ps2_key;
+
+wire [15:0] joystick_0, joystick_1;
+wire [15:0] joy = joystick_0 | joystick_1;
+
+hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
+(
+	.clk_sys(clk_sys),
+	.HPS_BUS(HPS_BUS),
+
+	.conf_str(CONF_STR),
+
+	.buttons(buttons),
+	.status(status),
+	.forced_scandoubler(forced_scandoubler),
+
+	.ioctl_download(ioctl_download),
+	.ioctl_wr(ioctl_wr),
+	.ioctl_addr(ioctl_addr),
+	.ioctl_dout(ioctl_data),
+
+	.joystick_0(joystick_0),
+	.joystick_1(joystick_1),
+	.ps2_key(ps2_key)
+);
+
+
+
+wire       pressed = ps2_key[9];
+wire [8:0] code    = ps2_key[8:0];
+always @(posedge clk_sys) begin
+	reg old_state;
+	old_state <= ps2_key[10];
+	
+	if(old_state != ps2_key[10]) begin
+		casex(code)
+//			'hX75: btn_up          <= pressed; // up
+//			'hX72: btn_down        <= pressed; // down
+			'hX6B: btn_left        <= pressed; // left
+			'hX74: btn_right       <= pressed; // right
+			'h014: btn_gas         <= pressed; // ctrl
+			'h011: btn_gearup      <= pressed; // Lalt
+			'h029: btn_geardown    <= pressed; // space
+
+			'h005: btn_one_player  <= pressed; // F1
+			'h006: btn_two_players <= pressed; // F2
+			// JPAC/IPAC/MAME Style Codes
+			'h016: btn_start_1     <= pressed; // 1
+			'h02E: btn_coin_1      <= pressed; // 5
+			'h036: btn_coin_2      <= pressed; // 6
+		endcase
+	end
+end
+
+//reg btn_up    = 0;
+//reg btn_down  = 0;
+reg btn_right = 0;
+reg btn_left  = 0;
+reg btn_gas  = 0;
+reg btn_gearup  = 0;
+reg btn_geardown  = 0;
+
+reg btn_one_player  = 0;
+reg btn_two_players = 0;
+
+reg btn_start_1=0;
+reg btn_coin_1=0;
+reg btn_coin_2=0;
+
+
+//wire m_up     =  btn_up    | joy[3];
+//wire m_down   =  btn_down  | joy[2];
+wire m_left     =  btn_left   | joy[1];
+wire m_right    =  btn_right  | joy[0];
+wire m_gas      =  btn_gas    | joy[4];
+wire m_gearup   =  btn_gearup |joy[5];
+wire m_geardown =  btn_geardown | joy[6];
+
+wire m_start1 = btn_one_player  | joy[7];
+wire m_start2 = btn_two_players | joy[8];
+wire m_coin   = m_start1 | m_start2;
+
+
+
+/*
+-- Configuration DIP switches, these can be brought out to external switches if desired
+-- See Sprint 2 manual page 11 for complete information. Active low (0 = On, 1 = Off)
+--    1 								Oil slicks			(0 - Oil slicks enabled)
+--			2							Cycle tracks      (0/1 - Cycle every lap/every two laps)
+--   			3	4					Coins per play		(00 - 1 Coin per player) 
+--						5				Extended Play		(0 - Extended Play enabled)
+--							6			Not used				(X - Don't care)
+--								7	8	Game time			(01 - 120 Seconds)
+--SW1 <= "01000101"; -- Config dip switches
+
+Game Time:
+0 0 - 150 seconds
+0 1 - 120 seconds
+1 0 -  90 seconds
+1 1 - 60 seconds
+
+*/
+wire [7:0] SW1 = {status[8],status[9],1'b0,1'b0,status[10],1'b1,status[12:11]};
+
+
+wire [1:0] steer;
+
+joy2quad steer1
+(
+	.CLK(CLK_VIDEO_2),
+	.clkdiv('d22500),
+	
+	.right(m_right),
+	.left(m_left),
+	
+	.steer(steer)
+);
+
+wire gear1,gear2,gear3;
+
+gearshift gearshift1
+(
+	.CLK(CLK_VIDEO_2),
+	.reset(m_start1|m_start2),
+	
+	.gearup(m_gearup),
+	.geardown(m_geardown),
+	
+	.gear1(gear1),
+	.gear2(gear2),
+	.gear3(gear3)
+
+);
+
+
+
+wire videowht,videoblk,compositesync,lamp;
+
+sprint1 sprint1(
+	.Clk_50_I(CLK_50M),
+	.Reset_n(~(RESET | status[0] | buttons[1] | ioctl_download)),
+
+	.dn_addr(ioctl_addr[16:0]),
+	.dn_data(ioctl_data),
+	.dn_wr(ioctl_wr),
+
+	.VideoW_O(videowht),
+	.VideoB_O(videoblk),
+
+	.Sync_O(compositesync),
+	.Audio1_O(audio),
+	.Coin1_I(~(m_coin|btn_coin_1)),
+	.Coin2_I(~(m_coin|btn_coin_2)),
+	.Start_I(~(m_start1|btn_start_1)),
+	.Gas_I(~m_gas),
+	.Gear1_I(gear1),
+	.Gear2_I(gear2),
+	.Gear3_I(gear3),
+	.Test_I	(~status[13]),
+	.SteerA_I(steer[1]),
+	.SteerB_I(steer[0]),
+	.StartLamp_O(lamp),
+	.hs_O(hs),
+	.vs_O(vs),
+	.hblank_O(hblank),
+	.vblank_O(vblank),
+	.clk_12(clk_12),
+	.clk_6_O(CLK_VIDEO_2),
+	.SW1_I(SW1)
+	);
+			
+wire [6:0] audio;
+wire [1:0] video;
+
+///////////////////////////////////////////////////
+wire clk_24,clk_12,CLK_VIDEO_2;
+wire clk_sys,locked;
+reg [7:0] vid_mono;
+wire[1:0] sprint_vid;
+
+always @(posedge clk_sys) begin
+		casex({videowht,videoblk})
+			//2'b01: vid_mono<=8'b01010000;
+			2'b01: vid_mono<=8'b01110000;
+			2'b10: vid_mono<=8'b10000110;
+			2'b11: vid_mono<=8'b11111111;
+			2'b00: vid_mono<=8'b00000000;
+		endcase
+end
+
+assign r=vid_mono[7:5];
+assign g=vid_mono[7:5];
+assign b=vid_mono[7:5];
+
+assign AUDIO_L={audio,1'b0,8'b00000000};
+assign AUDIO_R=AUDIO_L;
+assign AUDIO_S = 0;
+
+wire hblank, vblank;
+wire hs, vs;
+wire [2:0] r,g;
+wire [2:0] b;
+
+reg ce_pix;
+always @(posedge clk_24) begin
+        reg old_clk;
+
+        old_clk <= CLK_VIDEO_2;
+        ce_pix <= old_clk & ~CLK_VIDEO_2;
+end
+
+arcade_fx #(320,9) arcade_video
+(
+        .*,
+
+        .clk_video(clk_24),
+
+        .RGB_in({r,g,b}),
+        .HBlank(hblank),
+        .VBlank(vblank),
+        .HSync(hs),
+        .VSync(vs),
+
+        .fx(status[5:3])
+);
+
+
+pll pll (
+	.refclk ( CLK_50M   ),
+	.rst(0),
+	.locked 		( locked    ),        // PLL is running stable
+	.outclk_0	( clk_24	),        // 24 MHz
+	.outclk_1	( clk_12	)        // 12 MHz
+	 );
+
+assign clk_sys=clk_12;
+
+endmodule
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..94a9ed0
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
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+software and other kinds of works.
+
+  The licenses for most software and other practical works are designed
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+
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+The hypothetical commands `show w' and `show c' should show the appropriate
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+  The GNU General Public License does not permit incorporating your program
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diff --git a/README.md b/README.md
new file mode 100644
index 0000000..d445416
--- /dev/null
+++ b/README.md
@@ -0,0 +1,52 @@
+# Sprint1
+
+FPGA implementation by james10952001 of Sprint One arcade game released by Kee Games in 1978
+Port to MiSTer by Alan Steremberg
+
+The original Sprint game had a steering wheel with a quadrature encoder. This version implements a converter from the digital joystick inputs.
+
+# Keyboard inputs :
+```
+   F1          : Coin + Start 1P
+   F2          : Coin + Start 2P
+   LEFT,RIGHT arrows : Steering
+
+   MAME/IPAC/JPAC Style Keyboard inputs:
+     5           : Coin 1
+     6           : Coin 2
+     1           : Start 1 Player
+     2           : Start 2 Players
+     D,G         : Player 2 Movements
+   
+
+ Joystick support. (Converts the digital joystick to a simulated quadrature encoding)
+```
+ 
+# ROMs
+```
+                                *** Attention ***
+
+ROM is not included. In order to use this arcade, you need to provide a correct ROM file.
+
+Find this zip file somewhere. You need to find the file exactly as required.
+Do not rename other zip files even if they also represent the same game - they are not compatible!
+The name of zip is taken from M.A.M.E. project, so you can get more info about
+hashes and contained files there.
+
+To generate the ROM using Windows:
+1) Copy the zip into "releases" directory
+2) Execute bat file - it will show the name of zip file containing required files.
+3) Put required zip into the same directory and execute the bat again.
+4) If everything will go without errors or warnings, then you will get the a.*.rom file.
+5) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
+
+To generate the ROM using Linux/MacOS:
+1) Copy the zip into "releases" directory
+2) Execute build_rom.sh
+3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
+
+To generate the ROM using MiSTer:
+1) scp "releases" directory along with the zip file onto MiSTer:/media/fat/
+2) Using OSD execute build_rom.sh
+3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
+```
diff --git a/dpram.vhd b/dpram.vhd
new file mode 100644
index 0000000..9774848
--- /dev/null
+++ b/dpram.vhd
@@ -0,0 +1,75 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+entity dpram is
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0');
+		enable_a		: IN STD_LOGIC  := '1';
+		enable_b		: IN STD_LOGIC  := '1';
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END dpram;
+
+
+ARCHITECTURE SYN OF dpram IS
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "NORMAL",
+		clock_enable_input_b => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone V",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		numwords_b => 2**addr_width_g,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		widthad_b => addr_width_g,
+		width_a => data_width_g,
+		width_b => data_width_g,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		address_a => address_a,
+		address_b => address_b,
+		clock0 => clock_a,
+		clock1 => clock_b,
+		clocken0 => enable_a,
+		clocken1 => enable_b,
+		data_a => data_a,
+		data_b => data_b,
+		wren_a => wren_a,
+		wren_b => wren_b,
+		q_a => q_a,
+		q_b => q_b
+	);
+
+END SYN;
diff --git a/releases/build_rom.ini b/releases/build_rom.ini
new file mode 100644
index 0000000..6ac97aa
--- /dev/null
+++ b/releases/build_rom.ini
@@ -0,0 +1,4 @@
+zip=sprint1.zip
+ifiles=(6290-01.b1 6291-01.c1 6442-01.d1 6443-01.e1 6396-01.p4 6397-01.r4 6398-01.k6 6399-01.j6 6400-01.m2 6401-01.e2 )
+ofile=a.sprint1.rom
+ofileMd5sumValid=2a63b6ee5a63fdae0b71be6da31c27aa
diff --git a/releases/build_rom.sh b/releases/build_rom.sh
new file mode 100755
index 0000000..2b1f85f
--- /dev/null
+++ b/releases/build_rom.sh
@@ -0,0 +1,100 @@
+#!/bin/bash
+
+exit_with_error() {
+  echo -e "\nERROR:\n${1}\n"
+  exit 1
+}
+
+check_dependencies() {
+  if [[ $OSTYPE == darwin* ]]; then
+    for j in unzip md5 cat cut; do
+      command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}"
+    done
+  else
+    for j in unzip md5sum cat cut; do
+      command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}"
+    done
+  fi
+}
+
+check_permissions () {
+  if [ ! -w ${BASEDIR} ]; then
+    exit_with_error "Cannot write to\n${BASEDIR}"
+  fi
+}
+
+read_ini () {
+  if [ ! -f ${BASEDIR}/build_rom.ini ]; then
+    exit_with_error "Missing build_rom.ini"
+  else
+    source ${BASEDIR}/build_rom.ini
+  fi
+}
+
+uncompress_zip() {
+  if [ -f ${BASEDIR}/${zip} ]; then
+    tmpdir=tmp.`date +%Y%m%d%H%M%S%s`
+    unzip -qq -d ${BASEDIR}/${tmpdir}/ ${BASEDIR}/${zip}
+    if [ $? != 0 ] ; then
+      rm -rf ${BASEDIR}/$tmpdir
+      exit_with_error "Something went wrong\nwhen extracting\n${zip}"
+    fi
+  else
+    exit_with_error "Cannot find ${zip}"
+  fi
+}
+
+generate_rom() {
+  for i in "${ifiles[@]}"; do
+      # ensure provided zip contains required files
+      if [ ! -f "${BASEDIR}/${tmpdir}/${i}" ]; then
+        rm -rf ${BASEDIR}/$tmpdir
+        exit_with_error "Provided ${zip}\nis missing required file:\n\n${i}"
+      else
+        cat ${BASEDIR}/${tmpdir}/${i} >> ${BASEDIR}/${tmpdir}/${ofile}
+     fi
+  done
+}
+
+validate_rom() {
+
+  if [[ $OSTYPE == darwin* ]]; then
+    ofileMd5sumCurrent=$(md5 -r ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ")
+  else
+    ofileMd5sumCurrent=$(md5sum ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ")
+  fi
+
+  if [[ "${ofileMd5sumValid}" != "${ofileMd5sumCurrent}" ]]; then
+    echo -e "\nExpected checksum:\n${ofileMd5sumValid}"
+    echo -e "Actual checksum:\n${ofileMd5sumCurrent}"
+    mv ${BASEDIR}/${tmpdir}/${ofile} .
+    rm -rf ${BASEDIR}/$tmpdir
+    exit_with_error "Generated ${ofile}\nis invalid.\nThis is more likely\ndue to incorrect\n${zip} content."
+  else
+    mv ${BASEDIR}/${tmpdir}/${ofile} ${BASEDIR}/.
+    rm -rf ${BASEDIR}/$tmpdir
+    echo -e "\nChecksum verification passed\n\nCopy the ${ofile}\ninto root of SD card\nalong with the rbf file.\n"
+  fi
+}
+
+BASEDIR=$(dirname "$0")
+
+echo "Generating ROM ..."
+
+## verify dependencies
+check_dependencies
+
+## verify write permissions
+check_permissions
+
+## load ini
+read_ini
+
+## extract package
+uncompress_zip
+
+## build rom
+generate_rom
+
+## verify rom
+validate_rom
diff --git a/releases/build_rom_sprint1.bat b/releases/build_rom_sprint1.bat
new file mode 100644
index 0000000..1df5e8e
--- /dev/null
+++ b/releases/build_rom_sprint1.bat
@@ -0,0 +1,40 @@
+@echo off
+
+set    zip=sprint1.zip
+set ifiles=6290-01.b1+6291-01.c1+6442-01.d1+6443-01.e1+6396-01.p4+6397-01.r4+6398-01.k6+6399-01.j6+6400-01.m2+6401-01.e2
+set  ofile=a.sprint1.rom
+
+rem =====================================
+setlocal ENABLEDELAYEDEXPANSION
+
+set pwd=%~dp0
+echo.
+echo.
+
+if EXIST %zip% (
+
+	!pwd!7za x -otmp %zip%
+	if !ERRORLEVEL! EQU 0 ( 
+		cd tmp
+
+		copy /b/y %ifiles% !pwd!%ofile%
+		if !ERRORLEVEL! EQU 0 ( 
+			echo.
+			echo ** done **
+			echo.
+			echo Copy "%ofile%" into root of SD card
+		)
+		cd !pwd!
+		rmdir /s /q tmp
+	)
+
+) else (
+
+	echo Error: Cannot find "%zip%" file
+	echo.
+	echo Put "%zip%", "7za.exe" and "%~nx0" into the same directory
+)
+
+echo.
+echo.
+pause
diff --git a/src/Altera/clk_pll.BAK.vhd b/src/Altera/clk_pll.BAK.vhd
new file mode 100644
index 0000000..3d8a5a9
--- /dev/null
+++ b/src/Altera/clk_pll.BAK.vhd
@@ -0,0 +1,344 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: clk_pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY clk_pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC 
+	);
+END clk_pll;
+
+
+ARCHITECTURE SYN OF clk_pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire4_bv(0 DOWNTO 0) <= "0";
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	sub_wire2    <= inclk0;
+	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		clk0_divide_by => 3125,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 756,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone II",
+		lpm_hint => "CBX_MODULE_PREFIX=clk_pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED"
+	)
+	PORT MAP (
+		inclk => sub_wire3,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "12.096000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "12.09600000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3125"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "756"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/src/Altera/clk_pll.qip b/src/Altera/clk_pll.qip
new file mode 100644
index 0000000..137ee9d
--- /dev/null
+++ b/src/Altera/clk_pll.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "clk_pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_pll.ppf"]
diff --git a/src/Altera/clk_pll.vhd b/src/Altera/clk_pll.vhd
new file mode 100644
index 0000000..7dbf923
--- /dev/null
+++ b/src/Altera/clk_pll.vhd
@@ -0,0 +1,344 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: clk_pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY clk_pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC 
+	);
+END clk_pll;
+
+
+ARCHITECTURE SYN OF clk_pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire4_bv(0 DOWNTO 0) <= "0";
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	sub_wire2    <= inclk0;
+	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		clk0_divide_by => 3125,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 756,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone II",
+		lpm_hint => "CBX_MODULE_PREFIX=clk_pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED"
+	)
+	PORT MAP (
+		inclk => sub_wire3,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "12.096000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "12.09600000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3125"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "756"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/src/Altera/ram1k_dp.qip b/src/Altera/ram1k_dp.qip
new file mode 100644
index 0000000..67ae1ae
--- /dev/null
+++ b/src/Altera/ram1k_dp.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ram1k_dp.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram1k_dp.cmp"]
diff --git a/src/Altera/ram1k_dp.vhd b/src/Altera/ram1k_dp.vhd
new file mode 100644
index 0000000..b2f77f6
--- /dev/null
+++ b/src/Altera/ram1k_dp.vhd
@@ -0,0 +1,224 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: ram1k_dp.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+-- ************************************************************
+
+
+--Copyright (C) 2017  Intel Corporation. All rights reserved.
+--Your use of Intel Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Intel Program License 
+--Subscription Agreement, the Intel Quartus Prime License Agreement,
+--the Intel FPGA IP License Agreement, or other applicable license
+--agreement, including, without limitation, that your use is for
+--the sole purpose of programming logic devices manufactured by
+--Intel and sold by Intel or its authorized distributors.  Please
+--refer to the applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY ram1k_dp IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END ram1k_dp;
+
+
+ARCHITECTURE SYN OF ram1k_dp IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	q_a    <= sub_wire0(7 DOWNTO 0);
+	q_b    <= sub_wire1(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK0",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK0",
+		intended_device_family => "Cyclone V",
+		lpm_type => "altsyncram",
+		numwords_a => 1024,
+		numwords_b => 1024,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "CLOCK0",
+		outdata_reg_b => "CLOCK0",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_mixed_ports => "DONT_CARE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => 10,
+		widthad_b => 10,
+		width_a => 8,
+		width_b => 8,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK0"
+	)
+	PORT MAP (
+		address_a => address_a,
+		address_b => address_b,
+		clock0 => clock,
+		data_a => data_a,
+		data_b => data_b,
+		wren_a => wren_a,
+		wren_b => wren_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
+-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
+-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
+-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
+-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
+-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/src/EngineSound.vhd b/src/EngineSound.vhd
new file mode 100644
index 0000000..7a9521c
--- /dev/null
+++ b/src/EngineSound.vhd
@@ -0,0 +1,159 @@
+-- Motor sound generator for Kee Games Sprint 1
+-- Identical circuits are used in a number of other related games
+-- (c) 2017 James Sweet
+--
+-- Original circuit used a 555 configured as an astable oscillator with the frequency controlled by
+-- a four bit binary value. The output of this oscillator drives a counter configured to produce an
+-- irregular thumping simulating the sound of an engine.
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity EngineSound is 
+generic(
+			constant Freq_tune : integer := 50 -- Value from 0-100 used to tune the overall engine sound frequency
+			);
+port(		
+			Clk_6			: in  std_logic; 
+			Ena_3k		: in  std_logic;
+			EngineData	: in	std_logic_vector(3 downto 0);
+			Motor			: out std_logic_vector(5 downto 0)
+			);
+end EngineSound;
+
+architecture rtl of EngineSound is
+
+signal RPM_val 				: integer range 1 to 350;
+signal Ramp_term_unfilt		: integer range 1 to 80000;
+signal Ramp_Count 			: integer range 0 to 80000;
+signal Ramp_term				: integer range 1 to 80000;
+signal Freq_mod				: integer range 0 to 400;
+signal Motor_Clk				: std_logic;
+
+signal Counter_A				: std_logic;
+signal Counter_B 				: unsigned(2 downto 0);
+signal Counter_A_clk			: std_logic;
+
+signal Motor_prefilter 		: unsigned(1 downto 0);
+signal Motor_filter_t1 		: unsigned(3 downto 0);
+signal Motor_filter_t2 		: unsigned(3 downto 0);
+signal Motor_filter_t3 		: unsigned(3 downto 0);
+signal Motor_filtered		: unsigned(5 downto 0);
+
+
+begin
+
+-- The frequency of the oscillator is set by a 4 bit binary value controlled by the game CPU
+-- in the real hardware this is a 555 coupled to a 4 bit resistor DAC used to pull the frequency.
+-- The output of this DAC has a capacitor to smooth out the frequency variation.
+-- The constants assigned to RPM_val can be tweaked to adjust the frequency curve
+
+Speed_select: process(Clk_6)
+begin
+	if rising_edge(Clk_6) then
+		case EngineData is
+			when "0000" => RPM_val <= 280;
+			when "0001" => RPM_val <= 245;
+			when "0010" => RPM_val <= 230;
+			when "0011" => RPM_val <= 205;
+			when "0100" => RPM_val <= 190;
+			when "0101" => RPM_val <= 175;
+			when "0110" => RPM_val <= 160;
+			when "0111" => RPM_val <= 145;
+		   when "1000" => RPM_val <= 130;
+			when "1001" => RPM_val <= 115;
+			when "1010" => RPM_val <= 100;
+			when "1011" => RPM_val <= 85;
+			when "1100" => RPM_val <= 70;
+			when "1101" => RPM_val <= 55;
+			when "1110" => RPM_val <= 40;
+			when "1111" => RPM_val <= 25; 
+		end case;
+	end if;
+end process;
+
+
+-- There is a RC filter between the frequency control DAC and the 555 to smooth out the transitions between the
+-- 16 possible states. We can simulate a reasonable approximation of that behavior using a linear slope which is
+-- not truly accurate but should be close enough.
+RC_filt: process(clk_6, ena_3k, ramp_term_unfilt)
+begin
+	if rising_edge(clk_6) then
+		if ena_3k = '1' then
+			if ramp_term_unfilt > ramp_term then
+				ramp_term <= ramp_term + 5;
+			elsif ramp_term_unfilt = ramp_term then
+				ramp_term <= ramp_term;
+			else
+				ramp_term <= ramp_term - 3;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+-- Ramp_term terminates the ramp count, the higher this value, the longer the ramp will count up and the lower
+-- the frequency. RPM_val is multiplied by a constant which can be adjusted by changing the value of freq_tune
+-- to simulate the function of the frequency adjustment pot in the original hardware.
+ramp_term_unfilt <= ((200 - freq_tune) * RPM_val);
+
+-- Variable frequency oscillator roughly approximating the function of a 555 astable oscillator
+Ramp_osc: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		motor_clk <= '1';
+		ramp_count <= ramp_count + 1;
+		if ramp_count > ramp_term then
+			ramp_count <= 0;
+			motor_clk <= '0';
+		end if;
+	end if;
+end process;
+		
+
+-- 7492 counter with XOR on two of the outputs creates lumpy engine sound from smooth pulse train
+-- 7492 has two sections, one div-by-2 and one div-by-6.
+Engine_counter: process(motor_clk, Counter_A_clk, Counter_B)
+begin
+	if rising_edge(motor_clk) then
+		Counter_B <= Counter_B + '1';
+	end if;
+	Counter_A_clk <= Counter_B(0) xor Counter_B(2);
+	if rising_edge(counter_A_clk) then 
+		Counter_A <= (not Counter_A);
+	end if;
+end process;
+motor_prefilter <= ('0' & Counter_B(2)) + ('0' & Counter_B(1)) + ('0' & Counter_A);
+
+-- Very simple low pass filter, borrowed from MikeJ's Asteroids code
+Engine_filter: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		if (ena_3k = '1') then
+			motor_filter_t1 <= ("00" & motor_prefilter) + ("00" & motor_prefilter);
+			motor_filter_t2 <= motor_filter_t1;
+			motor_filter_t3 <= motor_filter_t2;
+		end if;
+		motor_filtered <= ("00" & motor_filter_t1) +
+								('0'  & motor_filter_t2 & '0') +
+								("00" & motor_filter_t3);
+	end if;
+end process;	
+
+motor <= std_logic_vector(motor_filtered);
+
+end rtl;
\ No newline at end of file
diff --git a/src/Inputs.vhd b/src/Inputs.vhd
new file mode 100644
index 0000000..6979617
--- /dev/null
+++ b/src/Inputs.vhd
@@ -0,0 +1,137 @@
+-- Input block for Kee Games Sprint 1
+-- 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+entity control_inputs is 
+port(		
+			Clk6				: in  std_logic; 
+			SW1				: in  std_logic_vector(7 downto 0); -- DIP switches
+			Coin1_n			: in  std_logic; -- Coin switches
+			Coin2_n			: in 	std_logic;
+			Start				: in	std_logic; -- player start switch
+			Gas				: in  std_logic; -- Gas pedal, simple on/off switche
+			Gear1				: in  std_logic; -- Gear select lever
+			Gear2				: in  std_logic;
+			Gear3				: in  std_logic;
+			Self_Test		: in	std_logic; -- Self test switch
+			Steering1A_n	: in  std_logic; -- Steering wheel signals
+			Steering1B_n	: in  std_logic;
+			SteerRst1_n		: in  std_logic;
+			Adr				: in  std_logic_vector(9 downto 0); -- Adress bus, only the lower 9 bits used by IO circuitry
+			Inputs			: out std_logic_vector(1 downto 0)  -- Out to data bus, only upper two bits used
+			);
+end control_inputs;
+
+architecture rtl of control_inputs is
+
+signal A8_8					: std_logic;
+signal H9_Q_n				: std_logic;
+signal H8_en				: std_logic;
+signal Coin1				: std_logic;
+signal Coin2				: std_logic;
+signal SW1_bank1			: std_logic;
+signal SW1_bank2			: std_logic;
+signal DipSW				: std_logic_vector(7 downto 0);
+signal E8_in				: std_logic_vector(3 downto 0);
+signal J9_out				: std_logic_vector(7 downto 0);
+signal E8_out				: std_logic_vector(9 downto 0);
+
+signal Steering1B_Q_n		        : std_logic;
+signal Steering1A_Q		        : std_logic;
+
+
+begin
+
+-- Inputs
+M8: process(Adr, A8_8, SW1_bank2, Coin2_n, Coin1_n, Steering1B_Q_n, Steering1A_Q)
+begin
+	case Adr(7 downto 6) is
+		when "00" => Inputs <= A8_8 & SW1_bank2; -- There is actually an inverter N9 fed by A8_8 so we will just account for that
+		when "01" => Inputs <= Coin2_n & Coin1_n;
+		when "10" => Inputs <= Steering1B_Q_n & Steering1A_Q;
+		when others => Inputs <= "11";
+		end case;
+end process;
+
+H9: process(Adr, Gear1, Gear2, Gear3, Gas, Self_Test, Start)
+begin
+	if Adr(4) = '0' then -- Adr(4) is connected to enable
+		case Adr(2 downto 0) is
+			when "000" => H9_Q_n <= (not Gear1);
+			when "001" => H9_Q_n <= (not Gear2);
+			when "010" => H9_Q_n <= (not Gear3);
+			when "011" => H9_Q_n <= (not Gas);
+			when "100" => H9_Q_n <= (not Self_Test);
+			when "101" => H9_Q_n <= (not Start);
+			when "110" => H9_Q_n <= '1';
+			when others => H9_Q_n <= '1';
+			end case;
+	else
+		H9_Q_n <= '1';
+	end if;
+end process;
+
+-- Steering
+M9: process(Steering1A_n, Steering1B_n, SteerRst1_n)
+begin
+	if SteerRst1_n = '0' then -- Asynchronous clear
+		Steering1B_Q_n <= '1';
+	elsif rising_edge(Steering1B_n) then -- Steering encoders are active low but inverted on board
+		Steering1A_Q <= Steering1A_n;
+		Steering1B_Q_n <= '0';
+	end if;
+end process;		
+		
+-- The way the dip switches are wired in the real hardware requires OR logic 
+-- to achieve the same result while using standard active-low switch inputs.
+-- Switches are split into two banks, each bank fed from half of selector J9.
+J9: process(Adr)
+begin
+	if Adr(3) = '1' then
+		J9_out <= "11111111";
+	else
+		case Adr(1 downto 0) is
+			when "00" => J9_out <= "11101110";
+			when "01" => J9_out <= "11011101";
+			when "10" => J9_out <= "10111011";
+			when "11" => J9_out <= "01110111";
+			end case;
+	end if;
+end process;
+
+-- Re-order the dip switch signals to match the physical order of the switches
+-- Bank 1
+DipSW(7) <= J9_out(7) or SW1(1);
+DipSW(6) <= J9_out(6) or SW1(3);
+DipSW(5) <= J9_out(5) or SW1(5);
+DipSW(4) <= J9_out(4) or SW1(7);
+
+--Bank 2
+DipSW(3) <= J9_out(3) or SW1(0);
+DipSW(2) <= J9_out(2) or SW1(2);
+DipSW(1) <= J9_out(1) or SW1(4);
+DipSW(0) <= J9_out(0) or SW1(6);
+
+-- Outputs from each switch bank are tied together, logical AND since they are active low
+SW1_bank1 <= DipSW(7) and DipSW(6) and DipSW(5) and DipSW(4);
+SW1_bank2 <= DipSW(3) and DipSW(2) and DipSW(1) and DipSW(0);
+
+-- Bank 1 of dip switches is multiplexed with player inputs connected to selectors F9 and H9
+A8_8 <= SW1_bank1 and H9_Q_n;
+
+end rtl;
diff --git a/src/T65/T65.vhd b/src/T65/T65.vhd
new file mode 100644
index 0000000..f02a5b6
--- /dev/null
+++ b/src/T65/T65.vhd
@@ -0,0 +1,551 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 more merging
+-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- 65C02 and 65C816 modes are incomplete
+-- Undocumented instructions are not supported
+-- Some interface signals behaves incorrect
+--
+-- File history :
+--
+--      0246 : First release
+--
+
+library IEEE;
+  use IEEE.std_logic_1164.all;
+  use IEEE.numeric_std.all;
+  use work.T65_Pack.all;
+
+-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
+-- the ready signal to limit the CPU.
+entity T65 is
+	port(
+		Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
+		Res_n   : in  std_logic;
+		Enable  : in  std_logic;
+		Clk     : in  std_logic;
+		Rdy     : in  std_logic;
+		Abort_n : in  std_logic;
+		IRQ_n   : in  std_logic;
+		NMI_n   : in  std_logic;
+		SO_n    : in  std_logic;
+		R_W_n   : out std_logic;
+		Sync    : out std_logic;
+		EF      : out std_logic;
+		MF      : out std_logic;
+		XF      : out std_logic;
+		ML_n    : out std_logic;
+		VP_n    : out std_logic;
+		VDA     : out std_logic;
+		VPA     : out std_logic;
+		A       : out std_logic_vector(23 downto 0);
+		DI      : in  std_logic_vector(7 downto 0);
+		DO      : out std_logic_vector(7 downto 0)
+	);
+end T65;
+
+architecture rtl of T65 is
+
+	-- Registers
+	signal ABC, X, Y, D       : std_logic_vector(15 downto 0);
+	signal P, AD, DL          : std_logic_vector(7 downto 0) :=  x"00";
+	signal BAH                : std_logic_vector(7 downto 0);
+	signal BAL                : std_logic_vector(8 downto 0);
+	signal PBR                : std_logic_vector(7 downto 0);
+	signal DBR                : std_logic_vector(7 downto 0);
+	signal PC                 : unsigned(15 downto 0);
+	signal S                  : unsigned(15 downto 0);
+	signal EF_i               : std_logic;
+	signal MF_i               : std_logic;
+	signal XF_i               : std_logic;
+
+	signal IR                 : std_logic_vector(7 downto 0);
+	signal MCycle             : std_logic_vector(2 downto 0);
+
+	signal Mode_r             : std_logic_vector(1 downto 0);
+	signal ALU_Op_r           : std_logic_vector(3 downto 0);
+	signal Write_Data_r       : std_logic_vector(2 downto 0);
+	signal Set_Addr_To_r      : std_logic_vector(1 downto 0);
+	signal PCAdder            : unsigned(8 downto 0);
+
+	signal RstCycle           : std_logic;
+	signal IRQCycle           : std_logic;
+	signal NMICycle           : std_logic;
+
+	signal B_o                : std_logic;
+	signal SO_n_o             : std_logic;
+	signal IRQ_n_o            : std_logic;
+	signal NMI_n_o            : std_logic;
+	signal NMIAct             : std_logic;
+
+	signal Break              : std_logic;
+
+	-- ALU signals
+	signal BusA               : std_logic_vector(7 downto 0);
+	signal BusA_r             : std_logic_vector(7 downto 0);
+	signal BusB               : std_logic_vector(7 downto 0);
+	signal ALU_Q              : std_logic_vector(7 downto 0);
+	signal P_Out              : std_logic_vector(7 downto 0);
+
+	-- Micro code outputs
+	signal LCycle             : std_logic_vector(2 downto 0);
+	signal ALU_Op             : std_logic_vector(3 downto 0);
+	signal Set_BusA_To        : std_logic_vector(2 downto 0);
+	signal Set_Addr_To        : std_logic_vector(1 downto 0);
+	signal Write_Data         : std_logic_vector(2 downto 0);
+	signal Jump               : std_logic_vector(1 downto 0);
+	signal BAAdd              : std_logic_vector(1 downto 0);
+	signal BreakAtNA          : std_logic;
+	signal ADAdd              : std_logic;
+	signal AddY               : std_logic;
+	signal PCAdd              : std_logic;
+	signal Inc_S              : std_logic;
+	signal Dec_S              : std_logic;
+	signal LDA                : std_logic;
+	signal LDP                : std_logic;
+	signal LDX                : std_logic;
+	signal LDY                : std_logic;
+	signal LDS                : std_logic;
+	signal LDDI               : std_logic;
+	signal LDALU              : std_logic;
+	signal LDAD               : std_logic;
+	signal LDBAL              : std_logic;
+	signal LDBAH              : std_logic;
+	signal SaveP              : std_logic;
+	signal Write              : std_logic;
+
+	signal really_rdy         : std_logic;
+	signal R_W_n_i            : std_logic;
+
+begin
+	-- ehenciak : gate Rdy with read/write to make an "OK, it's
+	--            really OK to stop the processor now if Rdy is
+	--            deasserted" signal
+	really_rdy <= Rdy or not(R_W_n_i);
+
+	-- ehenciak : Drive R_W_n_i off chip.
+	R_W_n      <= R_W_n_i;
+
+	Sync <= '1' when MCycle = "000" else '0';
+	EF <= EF_i;
+	MF <= MF_i;
+	XF <= XF_i;
+	ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
+	VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
+	VDA <= '1' when Set_Addr_To_r /= "000" else '0';            -- Incorrect !!!!!!!!!!!!
+	VPA <= '1' when Jump(1) = '0' else '0';                     -- Incorrect !!!!!!!!!!!!
+
+	mcode : T65_MCode
+		port map(
+			Mode        => Mode_r,
+			IR          => IR,
+			MCycle      => MCycle,
+			P           => P,
+			LCycle      => LCycle,
+			ALU_Op      => ALU_Op,
+			Set_BusA_To => Set_BusA_To,
+			Set_Addr_To => Set_Addr_To,
+			Write_Data  => Write_Data,
+			Jump        => Jump,
+			BAAdd       => BAAdd,
+			BreakAtNA   => BreakAtNA,
+			ADAdd       => ADAdd,
+			AddY        => AddY,
+			PCAdd       => PCAdd,
+			Inc_S       => Inc_S,
+			Dec_S       => Dec_S,
+			LDA         => LDA,
+			LDP         => LDP,
+			LDX         => LDX,
+			LDY         => LDY,
+			LDS         => LDS,
+			LDDI        => LDDI,
+			LDALU       => LDALU,
+			LDAD        => LDAD,
+			LDBAL       => LDBAL,
+			LDBAH       => LDBAH,
+			SaveP       => SaveP,
+			Write       => Write
+			);
+
+	alu : T65_ALU
+		port map(
+			Mode => Mode_r,
+			Op => ALU_Op_r,
+			BusA => BusA_r,
+			BusB => BusB,
+			P_In => P,
+			P_Out => P_Out,
+			Q => ALU_Q
+			);
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			IR <= "00000000";
+			S <= (others => '0');       -- Dummy !!!!!!!!!!!!!!!!!!!!!
+			D <= (others => '0');
+			PBR <= (others => '0');
+			DBR <= (others => '0');
+
+			Mode_r <= (others => '0');
+			ALU_Op_r <= "1100";
+			Write_Data_r <= "000";
+			Set_Addr_To_r <= "00";
+
+			R_W_n_i <= '1';
+			EF_i <= '1';
+			MF_i <= '1';
+			XF_i <= '1';
+
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				R_W_n_i <= not Write or RstCycle;
+
+				D <= (others => '1');   -- Dummy
+				PBR <= (others => '1'); -- Dummy
+				DBR <= (others => '1'); -- Dummy
+				EF_i <= '0';    -- Dummy
+				MF_i <= '0';    -- Dummy
+				XF_i <= '0';    -- Dummy
+
+				if MCycle  = "000" then
+					Mode_r <= Mode;
+
+					if IRQCycle = '0' and NMICycle = '0' then
+						PC <= PC + 1;
+					end if;
+
+					if IRQCycle = '1' or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DI;
+					end if;
+				end if;
+
+				ALU_Op_r <= ALU_Op;
+				Write_Data_r <= Write_Data;
+				if Break = '1' then
+					Set_Addr_To_r <= "00";
+				else
+					Set_Addr_To_r <= Set_Addr_To;
+				end if;
+
+				if Inc_S = '1' then
+					S <= S + 1;
+				end if;
+				if Dec_S = '1' and RstCycle = '0' then
+					S <= S - 1;
+				end if;
+				if LDS = '1' then
+					S(7 downto 0) <= unsigned(ALU_Q);
+				end if;
+
+				if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
+					PC <= PC + 1;
+				end if;
+				--
+				-- jump control logic
+				--
+				case Jump is
+				  when "01" =>
+					  PC <= PC + 1;
+
+				  when "10" =>
+					  PC <= unsigned(DI & DL);
+
+				  when "11" =>
+					  if PCAdder(8) = '1' then
+						  if DL(7) = '0' then
+							  PC(15 downto 8) <= PC(15 downto 8) + 1;
+						  else
+							  PC(15 downto 8) <= PC(15 downto 8) - 1;
+						  end if;
+					  end if;
+					  PC(7 downto 0) <= PCAdder(7 downto 0);
+
+				  when others => null;
+				end case;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+	PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
+			   else "0" & PC(7 downto 0);
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				if MCycle = "000" then
+					if LDA = '1' then
+						ABC(7 downto 0) <= ALU_Q;
+					end if;
+					if LDX = '1' then
+						X(7 downto 0) <= ALU_Q;
+					end if;
+					if LDY = '1' then
+						Y(7 downto 0) <= ALU_Q;
+					end if;
+					if (LDA or LDX or LDY) = '1' then
+						P <= P_Out;
+					end if;
+				end if;
+				if SaveP = '1' then
+					P <= P_Out;
+				end if;
+				if LDP = '1' then
+					P <= ALU_Q;
+				end if;
+				if IR(4 downto 0) = "11000" then
+					case IR(7 downto 5) is
+					when "000" =>
+						P(Flag_C) <= '0';
+					when "001" =>
+						P(Flag_C) <= '1';
+					when "010" =>
+						P(Flag_I) <= '0';
+					when "011" =>
+						P(Flag_I) <= '1';
+					when "101" =>
+						P(Flag_V) <= '0';
+					when "110" =>
+						P(Flag_D) <= '0';
+					when "111" =>
+						P(Flag_D) <= '1';
+					when others =>
+					end case;
+				end if;
+				if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
+					P(Flag_B) <= '1';
+				end if;
+				if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1')  then
+					P(Flag_I) <= '1';
+					P(Flag_B) <= B_o;
+				end if;
+				if SO_n_o = '1' and SO_n = '0' then
+					P(Flag_V) <= '1';
+				end if;
+				if RstCycle = '1' and Mode_r /= "00" then
+					P(Flag_1) <= '1';
+					P(Flag_D) <= '0';
+					P(Flag_I) <= '1';
+				end if;
+				P(Flag_1) <= '1';
+
+				B_o     <= P(Flag_B);
+				SO_n_o <= SO_n;
+				IRQ_n_o <= IRQ_n;
+				NMI_n_o <= NMI_n;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			BusA_r <= (others => '0');
+			BusB <= (others => '0');
+			AD <= (others => '0');
+			BAL <= (others => '0');
+			BAH <= (others => '0');
+			DL <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (Rdy = '1') then
+				BusA_r <= BusA;
+				BusB <= DI;
+
+				case BAAdd is
+				when "01" =>
+					-- BA Inc
+					AD <= std_logic_vector(unsigned(AD) + 1);
+					BAL <= std_logic_vector(unsigned(BAL) + 1);
+				when "10" =>
+					-- BA Add
+					BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
+				when "11" =>
+					-- BA Adj
+					if BAL(8) = '1' then
+						BAH <= std_logic_vector(unsigned(BAH) + 1);
+					end if;
+				when others =>
+				end case;
+
+				-- ehenciak : modified to use Y register as well (bugfix)
+				if ADAdd = '1' then
+				  if (AddY = '1') then
+					AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
+				  else
+					AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
+				  end if;
+				end if;
+
+				if IR = "00000000" then
+					BAL <= (others => '1');
+					BAH <= (others => '1');
+					if RstCycle = '1' then
+						BAL(2 downto 0) <= "100";
+					elsif NMICycle = '1' then
+						BAL(2 downto 0) <= "010";
+					else
+						BAL(2 downto 0) <= "110";
+					end if;
+					if Set_addr_To_r = "11" then
+						BAL(0) <= '1';
+					end if;
+				end if;
+
+
+				if LDDI = '1' then
+					DL <= DI;
+				end if;
+				if LDALU = '1' then
+					DL <= ALU_Q;
+				end if;
+				if LDAD = '1' then
+					AD <= DI;
+				end if;
+				if LDBAL = '1' then
+					BAL(7 downto 0) <= DI;
+				end if;
+				if LDBAH = '1' then
+					BAH <= DI;
+				end if;
+			end if;
+		end if;
+	  end if;
+	end process;
+
+	Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
+
+
+	with Set_BusA_To select
+		BusA <= DI when "000",
+			ABC(7 downto 0) when "001",
+			X(7 downto 0) when "010",
+			Y(7 downto 0) when "011",
+			std_logic_vector(S(7 downto 0)) when "100",
+			P when "101",
+			(others => '-') when others;
+
+	with Set_Addr_To_r select
+		A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
+			DBR & "00000000" & AD when "10",
+			"00000000" & BAH & BAL(7 downto 0) when "11",
+			PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
+
+	with Write_Data_r select
+		DO <= DL when "000",
+			ABC(7 downto 0) when "001",
+			X(7 downto 0) when "010",
+			Y(7 downto 0) when "011",
+			std_logic_vector(S(7 downto 0)) when "100",
+			P when "101",
+			std_logic_vector(PC(7 downto 0)) when "110",
+			std_logic_vector(PC(15 downto 8)) when others;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			MCycle <= "001";
+			RstCycle <= '1';
+			IRQCycle <= '0';
+			NMICycle <= '0';
+			NMIAct <= '0';
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				if MCycle = LCycle or Break = '1' then
+					MCycle <= "000";
+					RstCycle <= '0';
+					IRQCycle <= '0';
+					NMICycle <= '0';
+					if NMIAct = '1' then
+						NMICycle <= '1';
+					elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
+						IRQCycle <= '1';
+					end if;
+				else
+					MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+				end if;
+
+				if NMICycle = '1' then
+					NMIAct <= '0';
+				end if;
+				if NMI_n_o = '1' and NMI_n = '0' then
+					NMIAct <= '1';
+				end if;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+end;
diff --git a/src/T65/T65_ALU.vhd b/src/T65/T65_ALU.vhd
new file mode 100644
index 0000000..d9d25e1
--- /dev/null
+++ b/src/T65/T65_ALU.vhd
@@ -0,0 +1,260 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 6502 compatible microprocessor core
+--
+-- Version : 0245
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0245 : First version
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T65_Pack.all;
+
+entity T65_ALU is
+	port(
+		Mode    : in std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		Op      : in std_logic_vector(3 downto 0);
+		BusA    : in std_logic_vector(7 downto 0);
+		BusB    : in std_logic_vector(7 downto 0);
+		P_In    : in std_logic_vector(7 downto 0);
+		P_Out   : out std_logic_vector(7 downto 0);
+		Q       : out std_logic_vector(7 downto 0)
+	);
+end T65_ALU;
+
+architecture rtl of T65_ALU is
+
+	-- AddSub variables (temporary signals)
+	signal      ADC_Z           : std_logic;
+	signal      ADC_C           : std_logic;
+	signal      ADC_V           : std_logic;
+	signal      ADC_N           : std_logic;
+	signal      ADC_Q           : std_logic_vector(7 downto 0);
+	signal      SBC_Z           : std_logic;
+	signal      SBC_C           : std_logic;
+	signal      SBC_V           : std_logic;
+	signal      SBC_N           : std_logic;
+	signal      SBC_Q           : std_logic_vector(7 downto 0);
+
+begin
+
+	process (P_In, BusA, BusB)
+		variable AL : unsigned(6 downto 0);
+		variable AH : unsigned(6 downto 0);
+		variable C : std_logic;
+	begin
+		AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
+		AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
+			if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
+-- pragma translate_on
+
+		if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
+			ADC_Z <= '1';
+		else
+			ADC_Z <= '0';
+		end if;
+
+		if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+			AL(6 downto 1) := AL(6 downto 1) + 6;
+		end if;
+
+		C := AL(6) or AL(5);
+		AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
+
+		ADC_N <= AH(4);
+		ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
+-- pragma translate_on
+
+		if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+			AH(6 downto 1) := AH(6 downto 1) + 6;
+		end if;
+
+		ADC_C <= AH(6) or AH(5);
+
+		ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+	end process;
+
+	process (Op, P_In, BusA, BusB)
+		variable AL : unsigned(6 downto 0);
+		variable AH : unsigned(5 downto 0);
+		variable C : std_logic;
+	begin
+		C := P_In(Flag_C) or not Op(0);
+		AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
+		AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
+			if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
+-- pragma translate_on
+
+		if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
+			SBC_Z <= '1';
+		else
+			SBC_Z <= '0';
+		end if;
+
+		SBC_C <= not AH(5);
+		SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
+		SBC_N <= AH(4);
+
+		if P_In(Flag_D) = '1' then
+			if AL(5) = '1' then
+				AL(5 downto 1) := AL(5 downto 1) - 6;
+			end if;
+			AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
+			if AH(5) = '1' then
+				AH(5 downto 1) := AH(5 downto 1) - 6;
+			end if;
+		end if;
+
+		SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+	end process;
+
+	process (Op, P_In, BusA, BusB,
+			ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
+			SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
+		variable Q_t : std_logic_vector(7 downto 0);
+	begin
+		-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
+		-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
+		P_Out <= P_In;
+		Q_t := BusA;
+		case Op(3 downto 0) is
+		when "0000" =>
+			-- ORA
+			Q_t := BusA or BusB;
+		when "0001" =>
+			-- AND
+			Q_t := BusA and BusB;
+		when "0010" =>
+			-- EOR
+			Q_t := BusA xor BusB;
+		when "0011" =>
+			-- ADC
+			P_Out(Flag_V) <= ADC_V;
+			P_Out(Flag_C) <= ADC_C;
+			Q_t := ADC_Q;
+		when "0101" | "1101" =>
+			-- LDA
+		when "0110" =>
+			-- CMP
+			P_Out(Flag_C) <= SBC_C;
+		when "0111" =>
+			-- SBC
+			P_Out(Flag_V) <= SBC_V;
+			P_Out(Flag_C) <= SBC_C;
+			Q_t := SBC_Q;
+		when "1000" =>
+			-- ASL
+			Q_t := BusA(6 downto 0) & "0";
+			P_Out(Flag_C) <= BusA(7);
+		when "1001" =>
+			-- ROL
+			Q_t := BusA(6 downto 0) & P_In(Flag_C);
+			P_Out(Flag_C) <= BusA(7);
+		when "1010" =>
+			-- LSR
+			Q_t := "0" & BusA(7 downto 1);
+			P_Out(Flag_C) <= BusA(0);
+		when "1011" =>
+			-- ROR
+			Q_t := P_In(Flag_C) & BusA(7 downto 1);
+			P_Out(Flag_C) <= BusA(0);
+		when "1100" =>
+			-- BIT
+			P_Out(Flag_V) <= BusB(6);
+		when "1110" =>
+			-- DEC
+			Q_t := std_logic_vector(unsigned(BusA) - 1);
+		when "1111" =>
+			-- INC
+			Q_t := std_logic_vector(unsigned(BusA) + 1);
+		when others =>
+		end case;
+
+		case Op(3 downto 0) is
+		when "0011" =>
+			P_Out(Flag_N) <= ADC_N;
+			P_Out(Flag_Z) <= ADC_Z;
+		when "0110" | "0111" =>
+			P_Out(Flag_N) <= SBC_N;
+			P_Out(Flag_Z) <= SBC_Z;
+		when "0100" =>
+		when "1100" =>
+			P_Out(Flag_N) <= BusB(7);
+			if (BusA and BusB) = "00000000" then
+				P_Out(Flag_Z) <= '1';
+			else
+				P_Out(Flag_Z) <= '0';
+			end if;
+		when others =>
+			P_Out(Flag_N) <= Q_t(7);
+			if Q_t = "00000000" then
+				P_Out(Flag_Z) <= '1';
+			else
+				P_Out(Flag_Z) <= '0';
+			end if;
+		end case;
+
+		Q <= Q_t;
+	end process;
+
+end;
diff --git a/src/T65/T65_MCode.vhd b/src/T65/T65_MCode.vhd
new file mode 100644
index 0000000..fa62d86
--- /dev/null
+++ b/src/T65/T65_MCode.vhd
@@ -0,0 +1,1050 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 Jump timing fixed
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246 + fix
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- 65C02
+-- supported : inc, dec, phx, plx, phy, ply
+-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
+--
+-- File history :
+--
+--      0246 : First release
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T65_Pack.all;
+
+entity T65_MCode is
+	port(
+		Mode                    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		IR                      : in  std_logic_vector(7 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		P                       : in  std_logic_vector(7 downto 0);
+		LCycle                  : out std_logic_vector(2 downto 0);
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+		Set_BusA_To             : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
+		Set_Addr_To             : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
+		Write_Data              : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
+		Jump                    : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
+		BAAdd                   : out std_logic_vector(1 downto 0);     -- None,DB Inc,BA Add,BA Adj
+		BreakAtNA               : out std_logic;
+		ADAdd                   : out std_logic;
+		AddY                    : out std_logic;
+		PCAdd                   : out std_logic;
+		Inc_S                   : out std_logic;
+		Dec_S                   : out std_logic;
+		LDA                     : out std_logic;
+		LDP                     : out std_logic;
+		LDX                     : out std_logic;
+		LDY                     : out std_logic;
+		LDS                     : out std_logic;
+		LDDI                    : out std_logic;
+		LDALU                   : out std_logic;
+		LDAD                    : out std_logic;
+		LDBAL                   : out std_logic;
+		LDBAH                   : out std_logic;
+		SaveP                   : out std_logic;
+		Write                   : out std_logic
+	);
+end T65_MCode;
+
+architecture rtl of T65_MCode is
+
+	signal Branch : std_logic;
+
+begin
+
+	with IR(7 downto 5) select
+		Branch <= not P(Flag_N) when "000",
+					  P(Flag_N) when "001",
+				  not P(Flag_V) when "010",
+					  P(Flag_V) when "011",
+				  not P(Flag_C) when "100",
+					  P(Flag_C) when "101",
+				  not P(Flag_Z) when "110",
+					  P(Flag_Z) when others;
+
+	process (IR, MCycle, P, Branch, Mode)
+	begin
+		LCycle      <= "001";
+		Set_BusA_To <= "001"; -- A
+		Set_Addr_To <= (others => '0');
+		Write_Data  <= (others => '0');
+		Jump        <= (others => '0');
+		BAAdd       <= "00";
+		BreakAtNA   <= '0';
+		ADAdd       <= '0';
+		PCAdd       <= '0';
+		Inc_S       <= '0';
+		Dec_S       <= '0';
+		LDA         <= '0';
+		LDP         <= '0';
+		LDX         <= '0';
+		LDY         <= '0';
+		LDS         <= '0';
+		LDDI        <= '0';
+		LDALU       <= '0';
+		LDAD        <= '0';
+		LDBAL       <= '0';
+		LDBAH       <= '0';
+		SaveP       <= '0';
+		Write       <= '0';
+		AddY        <= '0';
+
+		case IR(7 downto 5) is
+		when "100" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				Set_BusA_To <= "011"; -- Y
+				Write_Data <= "011"; -- Y
+			when "10" =>
+				Set_BusA_To <= "010"; -- X
+				Write_Data <= "010"; -- X
+			when others =>
+				Write_Data <= "001"; -- A
+			end case;
+		--}}}
+		when "101" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) /= '1' or IR(2) /= '0' then
+					LDY <= '1';
+				end if;
+			when "10" =>
+				LDX <= '1';
+			when others =>
+				LDA <= '1';
+			end case;
+			Set_BusA_To <= "000"; -- DI
+		--}}}
+		when "110" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) = '0' then
+					LDY <= '1';
+				end if;
+				Set_BusA_To <= "011"; -- Y
+			when others =>
+				Set_BusA_To <= "001"; -- A
+			end case;
+		--}}}
+		when "111" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) = '0' then
+					LDX <= '1';
+				end if;
+				Set_BusA_To <= "010"; -- X
+			when others =>
+				Set_BusA_To <= "001"; -- A
+			end case;
+		--}}}
+		when others =>
+		end case;
+
+		if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+			Set_BusA_To <= "000"; -- DI
+		end if;
+
+		case IR(4 downto 0) is
+		when "00000" | "01000" | "01010" | "11000" | "11010" =>
+		--{{{
+			-- Implied
+			case IR is
+			when "00000000" =>
+				-- BRK
+				LCycle <= "110";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "111"; -- PCH
+					Write <= '1';
+				when 2 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "110"; -- PCL
+					Write <= '1';
+				when 3 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "101"; -- P
+					Write <= '1';
+				when 4 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					LDDI <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 6 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "00100000" =>
+				-- JSR
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "111"; -- PCH
+					Write <= '1';
+				when 3 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "110"; -- PCL
+					Write <= '1';
+				when 4 =>
+					Dec_S <= '1';
+				when 5 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "01000000" =>
+				-- RTI
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Set_BusA_To <= "000"; -- DI
+				when 4 =>
+					LDP <= '1';
+					Inc_S <= '1';
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 5 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "01100000" =>
+				-- RTS
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Inc_S <= '1';
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 4 =>
+					Jump <= "10"; -- DIDL
+				when 5 =>
+					Jump <= "01";
+				when others =>
+				end case;
+			when "00001000" | "01001000" | "01011010" | "11011010" =>
+				-- PHP, PHA, PHY*, PHX*
+				LCycle <= "010";
+				if Mode = "00" and IR(1) = '1' then
+					LCycle <= "001";
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					case IR(7 downto 4) is
+					when "0000" =>
+						Write_Data <= "101"; -- P
+					when "0100" =>
+						Write_Data <= "001"; -- A
+					when "0101" =>
+						Write_Data <= "011"; -- Y
+					when "1101" =>
+						Write_Data <= "010"; -- X
+					when others =>
+					end case;
+					Write <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Dec_S <= '1';
+				when others =>
+				end case;
+			when "00101000" | "01101000" | "01111010" | "11111010" =>
+				-- PLP, PLA, PLY*, PLX*
+				LCycle <= "011";
+				if Mode = "00" and IR(1) = '1' then
+					LCycle <= "001";
+				end if;
+				case IR(7 downto 4) is
+				when "0010" =>
+					LDP <= '1';
+				when "0110" =>
+					LDA <= '1';
+				when "0111" =>
+					if Mode /= "00" then
+						LDY <= '1';
+					end if;
+				when "1111" =>
+					if Mode /= "00" then
+						LDX <= '1';
+					end if;
+				when others =>
+				end case;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					SaveP <= '1';
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Set_BusA_To <= "000"; -- DI
+				when others =>
+				end case;
+			when "10100000" | "11000000" | "11100000" =>
+				-- LDY, CPY, CPX
+				-- Immediate
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+				when others =>
+				end case;
+			when "10001000" =>
+				-- DEY
+				LDY <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "011"; -- Y
+				when others =>
+				end case;
+			when "11001010" =>
+				-- DEX
+				LDX <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "010"; -- X
+				when others =>
+				end case;
+			when "00011010" | "00111010" =>
+				-- INC*, DEC*
+				if Mode /= "00" then
+					LDA <= '1'; -- A
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "100"; -- S
+				when others =>
+				end case;
+			when "00001010" | "00101010" | "01001010" | "01101010" =>
+				-- ASL, ROL, LSR, ROR
+				LDA <= '1'; -- A
+				Set_BusA_To <= "001"; -- A
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+				when others =>
+				end case;
+			when "10001010" | "10011000" =>
+				-- TYA, TXA
+				LDA <= '1'; -- A
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+				when others =>
+				end case;
+			when "10101010" | "10101000" =>
+				-- TAX, TAY
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "001"; -- A
+				when others =>
+				end case;
+			when "10011010" =>
+				-- TXS
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					LDS <= '1';
+				when 1 =>
+				when others =>
+				end case;
+			when "10111010" =>
+				-- TSX
+				LDX <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "100"; -- S
+				when others =>
+				end case;
+
+		--                      when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" =>
+		--                              -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX
+		--                              case to_integer(unsigned(MCycle)) is
+		--                              when 1 =>
+		--                              when others =>
+		--                              end case;
+			when others =>
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when others =>
+				end case;
+			end case;
+		--}}}
+
+		when "00001" | "00011" =>
+		--{{{
+			-- Zero Page Indexed Indirect (d,x)
+			LCycle <= "101";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+				ADAdd <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 3 =>
+				BAAdd <= "01";  -- DB Inc
+				LDBAL <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 4 =>
+				LDBAH <= '1';
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 5 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "01001" | "01011" =>
+		--{{{
+			-- Immediate
+			LDA <= '1';
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+			when others =>
+			end case;
+
+		--}}}
+
+		when "00010" | "10010" =>
+		--{{{
+			-- Immediate, KIL
+			LDX <= '1';
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				if IR = "10100010" then
+					-- LDX
+					Jump <= "01";
+				else
+					-- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+				end if;
+			when others =>
+			end case;
+		--}}}
+
+		when "00100" =>
+		--{{{
+			-- Zero Page
+			LCycle <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+				if IR(7 downto 5) = "001" then
+					SaveP <= '1';
+				end if;
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				end if;
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "00101" | "00110" | "00111" =>
+		--{{{
+			-- Zero Page
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 3 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 4 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "010";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "01100" =>
+		--{{{
+			-- Absolute
+			if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then
+				-- JMP
+				if IR(5) = '0' then
+					--LCycle <= "011";
+					LCycle <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Jump <= "01";
+						LDDI <= '1';
+					when 2 =>
+						Jump <= "10"; -- DIDL
+					when others =>
+					end case;
+				else
+					LCycle <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Jump <= "01";
+						LDDI <= '1';
+						LDBAL <= '1';
+					when 3 =>
+						LDBAH <= '1';
+						if Mode /= "00" then
+							Jump <= "10"; -- DIDL
+						end if;
+						if Mode = "00" then
+							Set_Addr_To <= "11"; -- BA
+						end if;
+					when 4 =>
+						LDDI <= '1';
+						if Mode = "00" then
+							Set_Addr_To <= "11"; -- BA
+							BAAdd <= "01";      -- DB Inc
+						else
+							Jump <= "01";
+						end if;
+					when 5 =>
+						Jump <= "10"; -- DIDL
+					when others =>
+					end case;
+				end if;
+			else
+				LCycle <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					if IR(7 downto 5) = "001" then
+						SaveP <= '1';
+					end if;
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "01101" | "01110" | "01111" =>
+		--{{{
+			-- Absolute
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+					Write <= '1';
+					LDALU <= '1';
+					SaveP <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					SaveP <= '0'; -- MIKEJ was 1
+				when others =>
+				end case;
+			else
+				LCycle <= "011";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "10000" =>
+		--{{{
+			-- Relative
+
+						-- This circuit dictates when the last
+						-- microcycle occurs for the branch depending on
+						-- whether or not the branch is taken and if a page
+						-- is crossed...
+			if (Branch = '1') then
+
+							 LCycle <= "011"; -- We're done @ T3 if branching...upper
+											  -- level logic will stop at T2 if no page cross
+											  -- (See the Break signal)
+			else
+
+							 LCycle <= "001";
+
+			end if;
+
+						-- This decodes the current microcycle and takes the
+						-- proper course of action...
+			case to_integer(unsigned(MCycle)) is
+
+							-- On the T1 microcycle, increment the program counter
+							-- and instruct the upper level logic to fetch the offset
+							-- from the Din bus and store it in the data latches. This
+							-- will be the last microcycle if the branch isn't taken.
+				when 1 =>
+
+					Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
+											  -- from microcycle T0.
+
+				LDDI <= '1';  -- Tells logic in top level (T65.vhd) to route
+											  -- the Din bus to the memory data latch (DL)
+											  -- so that the branch offset is fetched.
+
+							-- In microcycle T2, tell the logic in the top level to
+							-- add the offset.  If the most significant byte of the
+							-- program counter (i.e. the current "page") does not need
+							-- updating, we are done here...the Break signal at the
+							-- T65.vhd level takes care of that...
+				when 2 =>
+
+				Jump    <= "11"; -- Tell the PC Jump logic to use relative mode.
+
+				PCAdd   <= '1';  -- This tells the PC adder to update itself with
+												 -- the current offset recently fetched from
+												 -- memory.
+
+							-- The following is microcycle T3 :
+							-- The program counter should be completely updated
+							-- on this cycle after the page cross is detected.
+							-- We don't need to do anything here...
+				when 3 =>
+
+
+				when others => null; -- Do nothing.
+
+			end case;
+		--}}}
+
+		when "10001" | "10011" =>
+		--{{{
+			-- Zero Page Indirect Indexed (d),y
+			LCycle <= "101";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+				LDBAL <= '1';
+				BAAdd <= "01";  -- DB Inc
+				Set_Addr_To <= "10"; -- AD
+			when 3 =>
+				Set_BusA_To <= "011"; -- Y
+				BAAdd <= "10";  -- BA Add
+				LDBAH <= '1';
+				Set_Addr_To <= "11"; -- BA
+			when 4 =>
+				BAAdd <= "11";  -- BA Adj
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				else
+					BreakAtNA <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 5 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "10100" | "10101" | "10110" | "10111" =>
+		--{{{
+			-- Zero Page, X
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					ADAdd <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 3 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 4 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 5 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "011";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					ADAdd <= '1';
+					-- Added this check for Y reg. use...
+					if (IR(3 downto 0) = "0110") then
+					  AddY <= '1';
+					end if;
+
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "10"; -- AD
+				when 3 => null;
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "11001" | "11011" =>
+		--{{{
+			-- Absolute Y
+			LCycle <= "100";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDBAL <= '1';
+			when 2 =>
+				Jump <= "01";
+				Set_BusA_To <= "011"; -- Y
+				BAAdd <= "10";  -- BA Add
+				LDBAH <= '1';
+				Set_Addr_To <= "11"; -- BA
+			when 3 =>
+				BAAdd <= "11";  -- BA adj
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				else
+					BreakAtNA <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 4 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "11100" | "11101" | "11110" | "11111" =>
+		--{{{
+			-- Absolute X
+
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "110";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					Set_BusA_To <= "010"; -- X
+					BAAdd <= "10";      -- BA Add
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					BAAdd <= "11";      -- BA adj
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 6 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "100";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					-- mikej
+					-- special case 0xBE which uses Y reg as index!!
+					if (IR = "10111110") then
+					  Set_BusA_To <= "011"; -- Y
+					else
+					  Set_BusA_To <= "010"; -- X
+					end if;
+					BAAdd <= "10";      -- BA Add
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					BAAdd <= "11";      -- BA adj
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					else
+						BreakAtNA <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+		when others =>
+		end case;
+	end process;
+
+	process (IR, MCycle)
+	begin
+		-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
+		-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
+		case IR(1 downto 0) is
+		when "00" =>
+		--{{{
+			case IR(4 downto 2) is
+			when "000" | "001" | "011" =>
+				case IR(7 downto 5) is
+				when "110" | "111" =>
+					-- CP
+					ALU_Op <= "0110";
+				when "101" =>
+					-- LD
+					ALU_Op <= "0101";
+				when "001" =>
+					-- BIT
+					ALU_Op <= "1100";
+				when others =>
+					-- NOP/ST
+					ALU_Op <= "0100";
+				end case;
+			when "010" =>
+				case IR(7 downto 5) is
+				when "111" | "110" =>
+					-- IN
+					ALU_Op <= "1111";
+				when "100" =>
+					-- DEY
+					ALU_Op <= "1110";
+				when others =>
+					-- LD
+					ALU_Op <= "1101";
+				end case;
+			when "110" =>
+				case IR(7 downto 5) is
+				when "100" =>
+					-- TYA
+					ALU_Op <= "1101";
+				when others =>
+					ALU_Op <= "----";
+				end case;
+			when others =>
+				case IR(7 downto 5) is
+				when "101" =>
+					-- LD
+					ALU_Op <= "1101";
+				when others =>
+					ALU_Op <= "0100";
+				end case;
+			end case;
+		--}}}
+		when "01" => -- OR
+		--{{{
+			ALU_Op(3) <= '0';
+			ALU_Op(2 downto 0) <= IR(7 downto 5);
+		--}}}
+		when "10" =>
+		--{{{
+			ALU_Op(3) <= '1';
+			ALU_Op(2 downto 0) <= IR(7 downto 5);
+			case IR(7 downto 5) is
+			when "000" =>
+				if IR(4 downto 2) = "110" then
+					-- INC
+					ALU_Op <= "1111";
+				end if;
+			when "001" =>
+				if IR(4 downto 2) = "110" then
+					-- DEC
+					ALU_Op <= "1110";
+				end if;
+			when "100" =>
+				if IR(4 downto 2) = "010" then
+					-- TXA
+					ALU_Op <= "0101";
+				else
+					ALU_Op <= "0100";
+				end if;
+			when others =>
+			end case;
+		--}}}
+		when others =>
+		--{{{
+			case IR(7 downto 5) is
+			when "100" =>
+				ALU_Op <= "0100";
+			when others =>
+				if MCycle = "000" then
+					ALU_Op(3) <= '0';
+					ALU_Op(2 downto 0) <= IR(7 downto 5);
+				else
+					ALU_Op(3) <= '1';
+					ALU_Op(2 downto 0) <= IR(7 downto 5);
+				end if;
+			end case;
+		--}}}
+		end case;
+	end process;
+
+end;
diff --git a/src/T65/T65_Pack.vhd b/src/T65/T65_Pack.vhd
new file mode 100644
index 0000000..f8d603c
--- /dev/null
+++ b/src/T65/T65_Pack.vhd
@@ -0,0 +1,117 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T65_Pack is
+
+	constant Flag_C : integer := 0;
+	constant Flag_Z : integer := 1;
+	constant Flag_I : integer := 2;
+	constant Flag_D : integer := 3;
+	constant Flag_B : integer := 4;
+	constant Flag_1 : integer := 5;
+	constant Flag_V : integer := 6;
+	constant Flag_N : integer := 7;
+
+	component T65_MCode
+	port(
+		Mode                    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		IR                      : in  std_logic_vector(7 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		P                       : in  std_logic_vector(7 downto 0);
+		LCycle                  : out std_logic_vector(2 downto 0);
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+		Set_BusA_To             : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
+		Set_Addr_To             : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
+		Write_Data              : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
+		Jump                    : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
+		BAAdd                   : out std_logic_vector(1 downto 0);     -- None,DB Inc,BA Add,BA Adj
+		BreakAtNA               : out std_logic;
+		ADAdd                   : out std_logic;
+		AddY                    : out std_logic;
+		PCAdd                   : out std_logic;
+		Inc_S                   : out std_logic;
+		Dec_S                   : out std_logic;
+		LDA                     : out std_logic;
+		LDP                     : out std_logic;
+		LDX                     : out std_logic;
+		LDY                     : out std_logic;
+		LDS                     : out std_logic;
+		LDDI                    : out std_logic;
+		LDALU                   : out std_logic;
+		LDAD                    : out std_logic;
+		LDBAL                   : out std_logic;
+		LDBAH                   : out std_logic;
+		SaveP                   : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T65_ALU
+	port(
+		Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
+		Op      : in  std_logic_vector(3 downto 0);
+		BusA    : in  std_logic_vector(7 downto 0);
+		BusB    : in  std_logic_vector(7 downto 0);
+		P_In    : in  std_logic_vector(7 downto 0);
+		P_Out   : out std_logic_vector(7 downto 0);
+		Q       : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/src/collision.vhd b/src/collision.vhd
new file mode 100644
index 0000000..ce1d2a5
--- /dev/null
+++ b/src/collision.vhd
@@ -0,0 +1,95 @@
+-- Collision detection logic for for Kee Games Sprint 1
+-- This is called the "Car/Playfield Comparator" in the manual and works by comparing the
+-- video signals representing player and computer cars, track boundaries and oil slicks generating 
+-- collision signals when multiple objects appear at the same time (location) in the video. 
+-- Car 1 is the human player, Cars 2, 3 and Car 4 are computer controlled. 
+--
+-- NOTE: There is an error in the original schematic, F8 pin 5 should go to CAR1 (not inverted) and 
+-- F8 pin 9 to CAR2 (not inverted) while the schematic shows them connecting to the inverted signals
+-- 
+-- Tests for the following conditions:
+-- Car 1 equals Car 2
+-- Car 1 equals Car 3 or 4
+-- Car 1 equals Black Playfield (Oil slick)
+-- Car 1 equals White Playfield (Track boundary)
+--
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity collision_detect is 
+port(		
+			Clk6					: in  std_logic;
+			Car1					: in  std_logic;
+			Car1_n				: in  std_logic;
+			Car2					: in	std_logic;
+			Car2_n				: in	std_logic;
+			Car3_4_n				: in	std_logic;
+			WhitePF_n			: in  std_logic;
+			BlackPF_n			: in	std_logic;
+			CollRst1_n			: in  std_logic;
+			Collisions1			: out std_logic_vector(1 downto 0)
+			);
+end collision_detect;
+
+architecture rtl of collision_detect is
+
+signal Col_latch_Q		: std_logic_vector(2 downto 1) := (others => '0');
+signal S1_n					: std_logic_vector(2 downto 1);
+signal S2_n					: std_logic_vector(2 downto 1);
+signal R_n					: std_logic_vector(2 downto 1);
+
+
+begin
+
+-- Tristate buffer at E5 route collision signals to data bus 7-6
+Collisions1 <= Col_latch_Q(2 downto 1);
+	
+-- 74LS279 quad SR latch at H6, all inputs are active low
+-- Made synchronous here
+H6: process(Clk6, S1_n, S2_n, R_n, Col_latch_Q)
+begin
+	if rising_edge(Clk6) then
+-- Units 1 and 3 each have an extra Set element, only half of IC is used in Sprint 1
+-- Ordered from top to bottom as drawn in the schematic
+		if R_n(1) = '0' then
+			Col_latch_Q(1) <= '0';
+		elsif (S1_n(1) and S2_n(1)) = '0' then 
+			Col_latch_Q(1) <= '1';
+		else
+			Col_latch_Q(1) <= Col_latch_Q(1);
+		end if;
+		if R_n(2) = '0' then
+			Col_latch_Q(2) <= '0';
+		elsif S1_n(2) = '0' then 
+			Col_latch_Q(2) <= '1';
+		else
+			Col_latch_Q(2) <= Col_latch_Q(2);
+		end if;
+	end if;
+end process;	
+
+-- Glue logic	
+S2_n(1) <= BlackPF_n or Car1_n;
+S1_n(1) <= Car1 nand (Car2_n nand Car3_4_n);
+R_n(1) <= CollRst1_n; 
+
+R_n(2) <= CollRst1_n; 
+S1_n(2) <= Car1_n or WhitePF_n;
+
+end rtl;
\ No newline at end of file
diff --git a/src/cpu_mem.vhd b/src/cpu_mem.vhd
new file mode 100644
index 0000000..b2a71a2
--- /dev/null
+++ b/src/cpu_mem.vhd
@@ -0,0 +1,475 @@
+-- CPU, RAM, ROM and address decoder for Kee Games Sprint 1
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity CPU_mem is 
+port(		
+			CLK12					: in  std_logic;
+			CLK6					: in  std_logic; -- 6MHz on schematic
+			Reset_n				: in  std_logic;
+			VCount				: in 	std_logic_vector(7 downto 0);
+			HCount				: in  std_logic_vector(8 downto 0);
+			Vblank_s				: in  std_logic; -- Vblank* on schematic
+			Vreset				: in 	std_logic;
+			Hsync_n				: in  std_logic;
+			Test_n				: in  std_logic;
+			Attract				: out std_logic;
+			Skid1					: out std_logic;
+			Skid2					: out std_logic;
+			NoiseReset_n		: out std_logic;
+			CollRst1_n			: out std_logic;
+			CollRst2_n			: out std_logic;
+			Lamp1					: out std_logic;
+			SteerRst1_n			: out std_logic;
+			PHI1_O				: out std_logic;
+			PHI2_O				: out std_logic;
+			DISPLAY				: out	std_logic_vector(7 downto 0);
+			IO_Adr				: out std_logic_vector(9 downto 0);
+			Collisions1			: in  std_logic_vector(1 downto 0);
+			Collisions2			: in  std_logic_vector(1 downto 0);
+			Inputs				: in  std_logic_vector(1 downto 0);
+			
+			
+			-- signals that carry the ROM data from the MiSTer disk
+			dn_addr        	: in  std_logic_vector(15 downto 0);
+			dn_data        	: in  std_logic_vector(7 downto 0);
+			dn_wr          	: in  std_logic;
+			
+			rom1_cs				: in  std_logic;
+			rom2_cs				: in  std_logic;
+			rom3_cs				: in  std_logic;
+			rom4_cs				: in  std_logic;
+			rom_32_cs			: in	std_logic
+			);
+end CPU_mem;
+
+architecture rtl of CPU_mem is
+
+signal cpu_clk			: std_logic;
+signal PHI1				: std_logic;
+signal PHI2				: std_logic;
+signal Q5				: std_logic;
+signal Q6				: std_logic;
+signal A7_2				: std_logic;
+signal A7_5				: std_logic;
+signal A7_7				: std_logic;
+
+signal A8_6				: std_logic;
+
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H4				: std_logic;
+
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+
+signal IRQ_n			: std_logic;
+signal NMI_n			: std_logic;
+signal RW_n				: std_logic;
+signal RnW 				: std_logic;
+signal A					: std_logic_vector(15 downto 0);
+signal ADR				: std_logic_vector(9 downto 0);
+signal cpuDin			: std_logic_vector(7 downto 0);
+signal cpuDout			: std_logic_vector(7 downto 0);
+signal DBUS_n			: std_logic_vector(7 downto 0);
+signal DBUS				: std_logic_vector(7 downto 0);
+
+signal ROM1_dout		: std_logic_vector(7 downto 0);
+signal ROM2_dout		: std_logic_vector(7 downto 0);
+signal ROM3_dout		: std_logic_vector(7 downto 0);
+signal ROM4_dout		: std_logic_vector(7 downto 0);
+signal ROM_dout		: std_logic_vector(7 downto 0);
+
+signal ROM1				: std_logic;
+signal ROM2				: std_logic;
+signal ROM3				: std_logic;
+signal ROM4				: std_logic;
+signal ROM_ce			: std_logic;
+signal ROM_mux_in		: std_logic_vector(3 downto 0);
+
+signal cpuRAM_dout	: std_logic_vector(7 downto 0);
+signal Vram_dout		: std_logic_vector(7 downto 0);
+signal RAM_addr		: std_logic_vector(9 downto 0) := (others => '0');
+signal Vram_addr		: std_logic_vector(9 downto 0) := (others => '0');
+signal scanbus			: std_logic_vector(9 downto 0) := (others => '0');
+signal RAM_dout		: std_logic_vector(7 downto 0);
+signal RAM_we			: std_logic;
+signal RAM_RW_n 		: std_logic;
+signal RAM_ce_n		: std_logic;
+signal RAM_n			: std_logic; 
+signal WRAM				: std_logic;
+signal WRITE_n			: std_logic;
+
+signal F2_in			: std_logic_vector(3 downto 0);
+signal F2_out			: std_logic_vector(9 downto 0);
+signal D2_in			: std_logic_vector(3 downto 0);
+signal D2_out			: std_logic_vector(9 downto 0);
+signal E8_in			: std_logic_vector(3 downto 0);
+signal E8_out			: std_logic_vector(9 downto 0);
+signal P3_8				: std_logic;
+
+signal Sync			   : std_logic;
+signal Sync_n			: std_logic;
+signal Switch_n		: std_logic;
+signal Display_n		: std_logic;
+signal Addec_bus		: std_logic_vector(7 downto 0);
+
+signal Timer_Reset_n	: std_logic := '1';
+signal Collision1_n	: std_logic := '1';
+signal Collision2_n	: std_logic := '1';
+signal Attract_int	: std_logic := '1';
+
+signal J6_5				: std_logic;
+signal J6_9				: std_logic;
+
+signal Coin1			: std_logic;
+signal Coin2			: std_logic;
+signal Input_mux 		: std_logic;
+signal A8_8				: std_logic;
+signal H9_Q_n			: std_logic;
+signal J9_out			: std_logic_vector(7 downto 0);
+
+signal H8_en			: std_logic;
+
+begin
+
+H8 <= HCount(3);
+H16 <=  HCount(4);
+H32 <= HCount(5);
+H64 <= HCount(6);
+H128 <= HCount(7);
+H256 <= HCount(8);
+H256_n <= (not HCount(8));
+
+V8 <= VCount(3);
+V16 <= VCount(4);
+V32 <= VCount(5);
+V64 <= VCount(6);
+V128 <= VCount(7);
+
+
+CPU: entity work.T65
+port map(
+		Enable => '1',
+		Mode => "00",
+		Res_n => reset_n,
+		Clk => phi1,
+		Rdy => '1',
+		Abort_n => '1',
+		IRQ_n => '1',
+		NMI_n => NMI_n,
+		SO_n => '1',
+		R_W_n => RW_n,
+		A(15 downto 0) => A,
+		DI => cpuDin,
+		DO => cpuDout
+		);
+		
+DBUS_n <= (not cpuDout); -- Data bus to video RAM is inverted
+ADR(9 downto 7) <= (A(9) or WRAM) & (A(8) or WRAM) & (A(7) or WRAM);
+ADR(6 downto 0) <= A(6 downto 0);
+RnW <= (not RW_n);
+IO_Adr <= Adr;
+NMI_n <= not (Vblank_s and Test_n);
+
+		
+-- CPU clock
+H4 <= Hcount(2);
+CPU_clock: process(clk12, H4, Q5, Q6)
+begin
+	if rising_edge(clk12) then
+		Q5 <= H4;
+		Q6 <= Q5;
+	end if;
+	phi1 <= not (Q5 or Q6); --?
+end process;
+
+PHI2 <= (not PHI1);
+PHI1_O <= PHI1;
+PHI2_O <= PHI2;
+
+
+A8_6 <= not(RnW and PHI2 and H4 and WRITE_n);
+A7: process(clk12, A8_6) -- Shift register chain of 4 DFF's clocked by clk12, creates a delayed WRITE_n
+begin
+	if rising_edge(clk12) then
+		A7_2 <= A8_6;
+		A7_5 <= A7_2;
+		A7_7 <= A7_5;
+		WRITE_n <= A7_7;
+	end if;
+end process;
+		
+-- Program ROMs
+-- A1 ROM
+A1 : work.dpram generic map (11,8)
+port map
+(
+	clock_a   => CLK12,
+	wren_a    => dn_wr and rom1_cs,
+	address_a => dn_addr(10 downto 0),
+	data_a    => dn_data,
+
+	clock_b   => clk6,
+	address_b => A(10) & ADR(9 downto 0),
+	q_b       => rom1_dout
+);
+
+C1 : work.dpram generic map (11,8)
+port map
+(
+	clock_a   => CLK12,
+	wren_a    => dn_wr and rom2_cs,
+	address_a => dn_addr(10 downto 0),
+	data_a    => dn_data,
+
+	clock_b   => clk6,
+	address_b => A(10) & ADR(9 downto 0),
+	q_b       => rom2_dout
+);
+
+D1 : work.dpram generic map (11,8)
+port map
+(
+	clock_a   => CLK12,
+	wren_a    => dn_wr and rom3_cs,
+	address_a => dn_addr(10 downto 0),
+	data_a    => dn_data,
+
+	clock_b   => clk6,
+	address_b => A(10) & ADR(9 downto 0),
+	q_b       => rom3_dout
+);
+
+E1 : work.dpram generic map (11,8)
+port map
+(
+	clock_a   => CLK12,
+	wren_a    => dn_wr and rom4_cs,
+	address_a => dn_addr(10 downto 0),
+	data_a    => dn_data,
+
+	clock_b   => clk6,
+	address_b => A(10) & ADR(9 downto 0),
+	q_b       => rom4_dout
+);
+
+
+-- ROM data mux
+ROM_mux_in <= (ROM1 & ROM2 & ROM3 & ROM4);
+ROM_mux: process(ROM_mux_in, rom1_dout, rom2_dout, rom3_dout, rom4_dout)
+begin
+	ROM_dout <= (others => '0');
+ case ROM_mux_in is
+ 	when "1000" => rom_dout <= rom1_dout;
+	when "0100" => rom_dout <= rom2_dout;
+	when "0010" => rom_dout <= rom3_dout;
+	when "0001" => rom_dout <= rom4_dout;
+	when others => null;
+ end case;
+end process;
+
+-- RAM 
+-- The original hardware multiplexes access to the RAM between the CPU and video hardware. In the FPGA it's
+-- easier to use dual-ported RAM
+RAM: entity work.ram1k_dp
+port map(
+	clock => clk6,
+-- CPU side	
+	address_a => adr(9 downto 0),
+	wren_a => ram_we,
+	data_a => DBUS_n,
+	q_a=> CPUram_dout,
+
+-- Video side
+	address_b => Vram_addr,
+	wren_b => '0',
+	data_b => x"FF",
+	q_b => Vram_dout
+	);
+
+Vram_addr <= (V128 or H256_n) & (V64 or H256_n) & (V32 or H256_n) & (V16 and H256) & 	(V8 and H256) & H128 & H64 & H32 & H16 & H8;
+
+-- Real hardware has both WE and CE which are selected by K2 according to the state of the phase 2 clock
+-- Altera block RAM has active high WE, original RAM had active low WE
+ram_we <= (not Write_n) and (not Display_n) and Phi2;
+	
+-- Rising edge of phi2 clock latches inverted output of VRAM data bus 	
+F5: process(phi2)
+begin
+	if rising_edge(phi2) then
+		display <= not Vram_dout;
+	end if;
+end process;
+
+	
+-- Address decoder
+-- A15 and A14 are not used
+-- Original circuit uses a bipolar PROM in the address decoder, this could be replaced with combinational logic
+
+
+E2 : work.dpram generic map (5,8)
+port map
+(
+	clock_a   => CLK12,
+	wren_a    => dn_wr and rom_32_cs,
+	address_a => dn_addr(4 downto 0),
+	data_a    => dn_data,
+
+	clock_b   => clk12,
+	address_b => A(13 downto 9),
+	q_b       => addec_bus
+);	
+	
+	
+F2_in <= addec_bus(0) & addec_bus(1) & addec_bus(2) & addec_bus(3);	
+WRAM <= addec_bus(4);
+D2_in <= RnW & addec_bus(5) & addec_bus(6) & addec_bus(7);
+	
+-- Decoder code could be cleaned up a bit, unused decoder states are not explicitly implemented
+F2: process(F2_in)
+begin
+	case F2_in is
+      when "0000" =>
+         F2_out <= "1111111110";
+      when "0001" =>
+         F2_out <= "1111111101";
+      when "0010" =>
+         F2_out <= "1111111011";
+      when "0011" =>
+         F2_out <= "1111110111";
+      when "0100" =>
+         F2_out <= "1111101111";
+      when "0101" =>
+         F2_out <= "1111011111";
+      when "0110" =>
+         F2_out <= "1110111111";
+      when "0111" =>
+         F2_out <= "1101111111";
+      when others =>
+         F2_out <= "1111111111";
+      end case;
+end process;
+
+ROM1 <= (F2_out(0) nand F2_out(1));
+ROM2 <= (F2_out(2) nand F2_out(3));
+ROM3 <= (F2_out(4) nand F2_out(5));
+ROM4 <= (F2_out(6) nand F2_out(7));
+ROM_ce <= (ROM1 or ROM2 or ROM3 or ROM4);
+
+D2: process(D2_in)
+begin
+	case D2_in is
+		when "0000" =>
+         D2_out <= "1111111110";
+		when "0001" =>
+         D2_out <= "1111111101";
+      when "0010" =>
+         D2_out <= "1111111011";
+      when "0011" =>
+         D2_out <= "1111110111";
+      when "0100" =>
+         D2_out <= "1111101111";
+      when "1000" =>
+         D2_out <= "1011111111";
+      when "1001" =>
+         D2_out <= "0111111111";
+      when others =>
+         D2_out <= "1111111111";
+      end case;
+end process;	
+
+RAM_n <= D2_out(0);
+SYNC_n <= D2_out(1);
+SYNC <= (not SYNC_n);
+SWITCH_n <= D2_out(2);
+COLLISION1_n <= D2_out(3);
+COLLISION2_n <= D2_out(4);
+DISPLAY_n <= (D2_out(0) and D2_out(8));
+P3_8 <= (D2_out(9) or WRITE_n);
+
+E8_in <= P3_8 & ADR(9 downto 7);
+
+E8: process(E8_in)
+begin
+	case E8_in is
+		when "0000" =>
+         E8_out <= "1111111110";
+		when "0001" =>
+         E8_out <= "1111111101";
+		when "0010" =>
+         E8_out <= "1111111011";
+		when "0011" =>
+         E8_out <= "1111110111";
+      when "0100" =>
+         E8_out <= "1111101111";
+      when "0101" =>
+         E8_out <= "1111011111";
+      when "0110" =>
+         E8_out <= "1110111111";
+      when others =>
+         E8_out <= "1111111111";
+      end case;
+end process;
+
+H8_en <= E8_out(0);
+Timer_Reset_n <= E8_out(1);
+CollRst1_n <= E8_out(2);
+CollRst2_n <= E8_out(3);
+SteerRst1_n <= E8_out(4);
+NoiseReset_n <= E8_out(6);
+
+-- H8 9334 
+H8_dec: process(clk6, Adr)
+begin
+if rising_edge(clk6) then
+	if (H8_en = '0') then
+	  case Adr(6 downto 4) is
+		 when "000" => Attract_int <= Adr(0);
+		 when "001" => Skid1 <= Adr(0);
+		 when "010" => null;
+		 when "011" => LAMP1 <= Adr(0);
+		 when "100" => null;
+		 when "101" => null; -- "Spare" on schematic
+		 when "110" => null;
+		 when "111" => null;
+		 when others => null;
+	  end case;
+	end if;
+ end if;
+end process;		
+Attract <= Attract_Int;
+
+-- CPU Din mux
+cpuDin <= 	ROM_dout when rom_ce = '1' else 
+				(not CPUram_dout) when Display_n = '0' else -- Remember RAM data is inverted
+				VCount(7) & VBlank_s & Vreset & Attract_int & "1111" when Sync_n = '0' else -- Using V128 (VCount(7)) in place of 60Hz mains reference
+				Collisions1 & "111111" when Collision1_n = '0' else
+				Inputs & "111111" when SWITCH_n = '0' else
+				x"FF";
+				
+end rtl;
diff --git a/src/deltasigma.vhd b/src/deltasigma.vhd
new file mode 100644
index 0000000..1f2969f
--- /dev/null
+++ b/src/deltasigma.vhd
@@ -0,0 +1,61 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    20:12:02 06/27/2011 
+-- Design Name: 
+-- Module Name:    deltasigma - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+entity deltasigma is
+	generic (
+		width: integer :=8
+   );
+	Port ( inval : in  STD_LOGIC_VECTOR (width-1 downto 0);
+           output : out  STD_LOGIC;
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC);
+end deltasigma;
+
+architecture Behavioral of deltasigma is
+signal reg: STD_LOGIC_VECTOR(width+1 downto 0);
+signal reg_d: STD_LOGIC_VECTOR(width+1 downto 0);
+signal ddcout: STD_LOGIC_VECTOR(width+1 downto 0);
+
+begin
+ds: process(clk, reset)
+begin
+	if reset='1' then
+		reg<=(others => '0');
+		output<='0';
+	elsif rising_edge(clk) then
+		reg<=reg_d;
+		output<=reg(width);
+	end if;
+end process;
+ddcout(width+1 downto width)<="00";
+ddcout(width-1 downto 0)<=(others=>'1') when reg(width)='1' else (others => '0');
+reg_d<=(("00"&inval)-ddcout)+reg;
+end Behavioral;
+
diff --git a/src/gearshift.sv b/src/gearshift.sv
new file mode 100644
index 0000000..adb50e1
--- /dev/null
+++ b/src/gearshift.sv
@@ -0,0 +1,99 @@
+//============================================================================
+//  gearshift
+//
+//  Turn gearup and geardown buttons into state that can flip the correct switches
+//  for sprint
+//
+//
+//  Copyright (c) 2019 Alan Steremberg - alanswx
+//
+//   
+//============================================================================
+
+module gearshift
+(
+	input CLK,
+	input reset,
+	
+	input gearup,
+	input geardown,
+	
+	
+	output gear1,
+	output gear2,
+	output gear3
+);
+
+reg [2:0] gear=3'b0;
+
+always @(posedge CLK) begin
+  	reg old_gear_up;
+	reg old_gear_down;
+	
+	if (reset)
+		gear=0;
+		
+	if (gearup==1)
+	begin
+	   if (old_gear_up==0)
+		begin
+			old_gear_up=1;
+			if (gear<4)
+			begin
+				gear=gear+1;
+			end
+		end
+	end
+	else
+	begin
+		old_gear_up=0;
+	end
+	if (geardown==1)
+	begin
+	   if (old_gear_down==0)
+		begin
+			old_gear_down=1;
+			if (gear>0)
+			begin
+			gear=gear-1;
+			end
+		end
+	end
+	else
+	begin
+		old_gear_up=0;
+	end
+
+	
+	casex(gear)
+	3'b000: 
+	begin
+		gear1=0;
+		gear2=1;
+		gear3=1;
+	end
+	3'b001:
+	begin
+		gear1=1;
+		gear2=0;
+		gear3=1;
+
+	end
+	3'b010: 
+	begin
+		gear1=1;
+		gear2=1;
+		gear3=0;
+	end
+	3'b011:
+	begin
+		gear1=1;
+		gear2=1;
+		gear3=1;
+	end
+		endcase
+
+end
+
+
+endmodule
\ No newline at end of file
diff --git a/src/joy2quad.sv b/src/joy2quad.sv
new file mode 100644
index 0000000..dae1fa5
--- /dev/null
+++ b/src/joy2quad.sv
@@ -0,0 +1,100 @@
+//============================================================================
+//  joy2quad
+//
+//  Take in digital joystick buttons, and try to estimate a quadrature encoder
+//
+// 
+//  This makes an offset wave pattern for each keyboard stroke.  It might
+//  be a good extension to change the size of the wave based on how long the joystick
+//  is held down. 
+//
+//  Copyright (c) 2019 Alan Steremberg - alanswx
+//
+//   
+//============================================================================
+// digital joystick button to quadrature encoder
+
+module joy2quad
+(
+	input CLK,
+	input [31:0] clkdiv,
+	
+	input right,
+	input left,
+	
+	output reg [1:0] steer
+);
+
+
+reg [3:0] state = 0;
+
+always @(posedge CLK) begin
+ reg [31:0] count = 0;
+ if (count >0)
+  begin 
+	count=count-1;
+ end
+ else
+ begin
+ count=clkdiv;
+ casex(state)
+	4'b0000: 
+	  begin
+	    steer=2'b00;
+		 if (left==1)
+		 begin
+			state=4'b0001;
+		 end
+		 if (right==1)
+		 begin
+			state=4'b0101;
+		 end
+
+		 end
+	4'b0001: 
+	  begin
+	    steer=2'b00;
+		 state=4'b0010;
+	  end
+	4'b0010: 
+	  begin
+	    steer=2'b01;
+		 state=3'b0011;
+	  end
+	4'b0011: 
+	  begin
+	    steer=2'b11;
+		 state=4'b0100;
+	  end
+	4'b0100: 
+	  begin
+	    steer=2'b10;
+		 state=4'b000;
+	  end
+	4'b0101: 
+	  begin
+	    steer=2'b00;
+		 state=4'b0110;
+	  end
+	4'b0110: 
+	  begin
+	    steer=2'b10;
+		 state=4'b0111;
+	  end
+	4'b0111: 
+	  begin
+	    steer=2'b11;
+		 state=4'b1000;
+	  end
+	4'b1000: 
+	  begin
+	    steer=2'b01;
+		 state=4'b0000;
+		 
+	  end
+
+ endcase
+ end
+end
+
+endmodule
\ No newline at end of file
diff --git a/src/motion.vhd b/src/motion.vhd
new file mode 100644
index 0000000..95cb2b5
--- /dev/null
+++ b/src/motion.vhd
@@ -0,0 +1,378 @@
+-- Motion object generation circuitry for Kee Games Sprint 1
+-- This generates the four cars which are the only moving objects in the game
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity motion is 
+port(		
+			CLK6			: in  std_logic; -- 6MHz* on schematic
+			CLK12			: in  std_logic;
+			PHI2			: in  std_logic;
+			DISPLAY		: in  std_logic_vector(7 downto 0);
+			H256_s		: in  std_logic; -- 256H* on schematic
+			VCount		: in  std_logic_vector(7 downto 0);
+			HCount		: in  std_logic_vector(8 downto 0);
+			Crash_n		: out std_logic;
+			Motor1_n		: out std_logic;
+			Car1  		: out std_logic;
+			Car1_n  		: out std_logic;
+			Car2  		: out std_logic;
+			Car2_n  		: out std_logic;
+			Car3_4_n  	: out std_logic;
+			
+			-- signals that carry the ROM data from the MiSTer disk
+			dn_addr     : in  std_logic_vector(15 downto 0);
+			dn_data     : in  std_logic_vector(7 downto 0);
+			dn_wr       : in  std_logic;
+			rom_car_j6_cs  : in std_logic;
+			rom_car_k6_cs  : in std_logic
+			);
+end motion;
+
+architecture rtl of motion is
+
+signal phi0			: std_logic;
+
+signal LDH1_n		: std_logic;
+signal LDH2_n		: std_logic;
+signal LDH3_n		: std_logic;
+signal LDH4_n		: std_logic;
+
+signal LDV1A_n		: std_logic;
+signal LDV2A_n		: std_logic;
+signal LDV3A_n		: std_logic;
+signal LDV4A_n		: std_logic;
+
+signal LDV1B_n		: std_logic;
+signal LDV2B_n		: std_logic;
+signal LDV3B_n		: std_logic;
+signal LDV4B_n		: std_logic;
+
+signal Car1_Inh	: std_logic;
+signal Car2_Inh	: std_logic;
+signal Car3_Inh	: std_logic;
+signal Car4_Inh	: std_logic;
+
+signal VPos_sum		: std_logic_vector(7 downto 0) := x"00";
+signal N4_8			: std_logic;
+
+signal H256_n		: std_logic;
+signal H256			: std_logic;
+signal H64 			: std_logic;
+signal H32			: std_logic;
+signal H16			: std_logic;
+signal H8			: std_logic;
+signal H4			: std_logic;
+
+signal L5_reg		: std_logic_vector(3 downto 0);
+
+signal J8_3			: std_logic;
+signal J8_6			: std_logic;
+
+signal K8_in		: std_logic_vector(3 downto 0);
+signal K8_out		: std_logic_vector(9 downto 0);
+signal P7_in		: std_logic_vector(3 downto 0);
+signal P7_out		: std_logic_vector(9 downto 0);
+
+signal Car1_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+signal Car2_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+signal Car3_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+signal Car4_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+
+signal Car1_reg	: std_logic_vector(15 downto 0) := x"0000";
+signal Car2_reg	: std_logic_vector(15 downto 0) := x"0000";
+signal Car3_reg 	: std_logic_vector(15 downto 0) := x"0000";
+signal Car4_reg 	: std_logic_vector(15 downto 0) := x"0000";
+
+signal Vid			: std_logic_vector(7 downto 0);
+
+
+begin
+phi0 <= phi2;
+
+H4 <= Hcount(2);
+H8 <= Hcount(3);
+H16 <= Hcount(4);
+H32 <= Hcount(5);
+H64 <= Hcount(6);
+H256 <= Hcount(8);
+H256_n <= not(Hcount(8));
+
+-- Vertical line comparator
+VPos_sum <= Display + VCount; 
+N4_8 <= not(VPos_sum(7) and VPos_sum(6) and VPos_sum(5) and VPos_sum(4) and VPos_sum(3) and H256_n and H64 and H8);
+
+
+-- D type flip-flops in L5
+L5: process(phi2, N4_8, VPos_sum(2 downto 0))
+begin
+	if rising_edge(phi2) then
+		L5_reg <= N4_8 & VPos_sum(2 downto 0);
+	end if;
+end process;
+
+
+J6 : work.dpram generic map (9,8)
+port map
+(
+	clock_a   => clk12,
+	wren_a    => dn_wr and rom_car_j6_cs,
+	address_a => dn_addr(8 downto 0),
+	data_a    => dn_data,
+
+	clock_b   => clk6,
+	address_b => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+	q_b(3 downto 0)       => Vid(7 downto 4) 
+);
+
+K6 : work.dpram generic map (9,8)
+port map
+(
+	clock_a   => clk12,
+	wren_a    => dn_wr and rom_car_k6_cs,
+	address_a => dn_addr(8 downto 0),
+	data_a    => dn_data,
+
+	clock_b   => clk6,
+	address_b => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+	q_b(3 downto 0)       => Vid(3 downto 0) 
+);
+
+
+	
+-- Some glue logic
+J8_3 <= (H4 or L5_reg(3));
+J8_6 <= (H256 or H64 or H4);
+
+
+-- Decoders
+-- Making K8 synchronous fixes weird problem with ghost artifacts of motion objects
+K8_in <= J8_3 & H32 & H16 & phi0;
+K8: process(clk6, K8_in)
+begin
+	if rising_edge(clk6) then
+		case K8_in is
+			when "0000" =>
+				K8_out <= "1111111110";
+			when "0001" =>
+				K8_out <= "1111111101"; 
+			when "0010" =>
+				K8_out <= "1111111011"; 
+			when "0011" =>
+				K8_out <= "1111110111";
+			when "0100" =>
+				K8_out <= "1111101111"; 
+			when "0101" =>
+				K8_out <= "1111011111";
+			when "0110" =>
+				K8_out <= "1110111111"; 
+			when "0111" =>
+				K8_out <= "1101111111";
+			when "1000" =>
+				K8_out <= "1011111111";
+			when "1001" =>
+				K8_out <= "0111111111";
+			when others =>
+				K8_out <= "1111111111";
+			end case;
+		end if;
+end process;
+LDV3B_n <= K8_out(7);
+LDV3A_n <= K8_out(6);
+LDV2B_n <= K8_out(5);
+LDV2A_n <= K8_out(4);
+LDV1B_n <= K8_out(3);
+LDV1A_n <= K8_out(2);
+LDV4B_n <= K8_out(1);
+LDV4A_n <= K8_out(0);
+
+P7_in <= J8_6 & H32 & H16 & H8;
+P7: process(P7_in)
+begin
+	case P7_in is
+		when "0000" =>
+         P7_out <= "1111111110";
+		when "0001" =>
+         P7_out <= "1111111101";
+      when "0010" =>
+         P7_out <= "1111111011";
+      when "0011" =>
+         P7_out <= "1111110111";
+      when "0100" =>
+         P7_out <= "1111101111";
+      when "0101" =>
+         P7_out <= "1111011111";
+      when "0110" =>
+         P7_out <= "1110111111";
+      when "0111" =>
+         P7_out <= "1101111111";
+      when "1000" =>
+         P7_out <= "1011111111";
+      when "1001" =>
+         P7_out <= "0111111111";
+      when others =>
+         P7_out <= "1111111111";
+      end case;
+end process;
+Crash_n <= P7_out(7);
+Motor1_n <= P7_out(5);	
+LDH4_n <= P7_out(4);
+LDH3_n <= P7_out(3); 
+LDH2_n <= P7_out(2);
+LDH1_n <= P7_out(1);
+
+
+-- Car 1 Horizontal position counter
+-- This combines two 74163s at locations R5 and R6 on the PCB 
+R5_6: process(clk6, H256_s, LDH1_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH1_n = '0' then -- preload the counter
+			Car1_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car1_Hpos <= Car1_Hpos + '1';		
+		end if;
+		if Car1_Hpos(7 downto 3) = "11111" then
+			Car1_Inh <= '0';
+		else
+			Car1_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 1 video shift register
+-- This combines two 74165s at locations M7 and N7 on the PCB
+M_N7: process(clk12, Car1_Inh, LDV1A_n, LDV1B_n, Vid)
+begin
+	if LDV1A_n = '0' then
+			Car1_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV1B_n = '0' then
+			Car1_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car1_Inh = '0' then
+			Car1_reg <= '0' & Car1_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car1 <= Car1_reg(0);
+Car1_n <= not Car1_reg(0);
+
+
+-- Car 2 Horizontal position counter
+-- This combines two 74LS163s at locations P5 and P6 on the PCB 
+P5_6: process(clk6, H256_s, LDH2_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH2_n = '0' then -- preload the counter
+			Car2_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car2_Hpos <= Car2_Hpos + '1';
+		end if;
+		if Car2_Hpos(7 downto 3) = "11111" then
+			Car2_Inh <= '0';
+		else
+			Car2_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 2 video shift register
+K_L7: process(clk12, Car2_Inh, LDV2A_n, LDV2B_n, Vid)
+begin
+	if LDV2A_n = '0' then
+			Car2_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV2B_n = '0' then
+			Car2_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car2_Inh = '0' then
+			Car2_reg <= '0' & Car2_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car2 <= Car2_reg(0);
+Car2_n <= not Car2_reg(0);
+
+
+-- Car 3 Horizontal position counter
+-- This combines two 74LS163s at locations N5 and N6 on the PCB 
+N5_6: process(clk6, H256_s, LDH3_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH3_n = '0' then -- preload the counter
+			Car3_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car3_Hpos <= Car3_Hpos + '1';
+		end if;
+		if Car3_Hpos(7 downto 3) = "11111" then
+			Car3_Inh <= '0';
+		else
+			Car3_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 3 video shift register
+H_J7: process(clk12, Car3_Inh, LDV3A_n, LDV3B_n, Vid)
+begin
+	if LDV3A_n = '0' then
+			Car3_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV3B_n = '0' then
+			Car3_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car3_Inh = '0' then
+			Car3_reg <= '0' & Car3_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+
+
+-- Car 4 Horizontal position counter
+-- This combines two 74LS163s at locations M5 and M6 on the PCB 
+M5_6: process(clk6, H256_s, LDH4_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH4_n = '0' then -- preload the counter
+			Car4_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car4_Hpos <= Car4_Hpos + '1';
+		end if;
+		if Car4_Hpos(7 downto 3) = "11111" then
+			Car4_Inh <= '0';
+		else
+			Car4_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 4 video shift register
+E_F7: process(clk12, Car4_Inh, LDV4A_n, LDV4B_n, Vid)
+begin
+	if LDV4A_n = '0' then
+			Car4_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV4B_n = '0' then
+			Car4_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car4_Inh = '0' then
+			Car4_reg <= '0' & Car4_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car3_4_n <= not (Car3_reg(0) or Car4_reg(0));
+
+end rtl;
diff --git a/src/playfield.vhd b/src/playfield.vhd
new file mode 100644
index 0000000..53b1388
--- /dev/null
+++ b/src/playfield.vhd
@@ -0,0 +1,184 @@
+-- Playfield generation circuitry for Sprint 1 by Kee Games
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity playfield is 
+port(   
+			Clk6				: in	std_logic;
+			Clk12				: in	std_logic;
+			Display			: in	std_logic_vector(7 downto 0);
+			HCount			: in  std_logic_vector(8 downto 0);
+			VCount			: in  std_logic_vector(7 downto 0);
+			H256_s			: out std_logic;
+			HBlank			: in	std_logic;
+			VBlank			: in	std_logic;
+			VBlank_n_s		: in  std_logic; -- VBLANK* on the schematic	
+			HSync				: in	std_logic;
+			VSync				: in	std_logic;
+			CompSync_n_s	: out std_logic; -- COMP SYNC* on schematic
+			CompBlank_s		: out std_logic; -- COMP BLANK* on schematic
+			WhitePF_n		: out	std_logic; 
+			BlackPF_n		: out	std_logic;
+			
+			-- signals that carry the ROM data from the MiSTer disk
+			dn_addr        	: in  std_logic_vector(15 downto 0);
+			dn_data        	: in  std_logic_vector(7 downto 0);
+			dn_wr          	: in  std_logic;
+			rom_LSB_cs   		: in std_logic;
+			rom_MSB_cs   		: in std_logic
+			
+			);
+end playfield;
+
+architecture rtl of playfield is
+
+signal H1				: std_logic;
+signal H2				: std_logic;
+signal H4				: std_logic;
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+
+signal V1				: std_logic;
+signal V2				: std_logic;
+signal V4				: std_logic;
+
+signal char_addr		: std_logic_vector(8 downto 0) := (others => '0');
+signal char_data		: std_logic_vector(7 downto 0) := (others => '0');
+
+signal shift_data		: std_logic_vector(7 downto 0) := (others => '0');
+signal QH				: std_logic;
+
+signal R2_reg		: std_logic_vector(3 downto 0) := (others => '0');
+
+
+-- These signals are based off the schematic and are formatted as Designator_PinNumber
+signal R7_12			: std_logic;
+signal P3_3				: std_logic;
+signal P2_13			: std_logic;
+signal P3_6				: std_logic;
+signal A6_6				: std_logic;
+signal A6_3				: std_logic;
+
+begin
+
+-- Video synchronization 			s
+H1 <= Hcount(0);
+H2 <= Hcount(1);
+H4 <= Hcount(2);
+H256 <= Hcount(8);
+H256_n <= not(Hcount(8));
+
+V1 <= Vcount(0);
+V2 <= Vcount(1);
+V4 <= Vcount(2);
+
+-- Some glue logic, may be re-written later to be cleaner and easier to follow without referring to schematic
+R7_12 <= not(H1 and H2 and H4);
+
+P3_3 <= (H256_n or R7_12);
+
+P2_13 <= (HSync nor VSync);
+
+P3_6 <= (HBlank or VBlank);
+
+
+
+char_addr <= display(5 downto 0) & V4 & V2 & V1;
+
+-- Background character ROMs
+--R4: entity work.Char_MSB
+--port map(
+--	clock => clk6,
+--	Address => char_addr,
+--	q => char_data(3 downto 0) 
+--	);
+
+
+R4 : work.dpram generic map (9,8)
+port map
+(
+	clock_a   => clk12,
+	wren_a    => dn_wr and rom_MSB_cs,
+	address_a => dn_addr(8 downto 0),
+	data_a    => dn_data,
+
+	clock_b   => clk6,
+	address_b => char_addr,
+	q_b(3 downto 0)       => char_data(3 downto 0) 
+);
+
+
+--P4: entity work.Char_LSB
+--port map(
+--	clock => clk6,
+--	Address => char_addr,
+--	q => char_data(7 downto 4) 
+--	);
+P4 : work.dpram generic map (9,8)
+port map
+(
+	clock_a   => clk12,
+	wren_a    => dn_wr and rom_LSB_cs,
+	address_a => dn_addr(8 downto 0),
+	data_a    => dn_data,
+
+	clock_b   => clk6,
+	address_b => char_addr,
+	q_b(3 downto 0)       => char_data(7 downto 4) 
+);
+
+
+-- 74LS166 video shift register	
+R3: process(clk6, P3_3, VBlank_n_s, char_data, shift_data)
+begin
+	if VBlank_n_s = '0' then -- Connected Clear input
+		shift_data <= (others => '0');
+	elsif rising_edge(clk6) then 
+		if P3_3 = '0' then -- Parallel load
+			shift_data <= char_data(7 downto 0);
+		else
+			shift_data <= shift_data(6 downto 0) & '0';
+		end if;
+	end if;
+	QH <= shift_data(7);
+end process;
+
+
+-- 9316 counter at R2
+-- CEP and CET tied to ground, counter is used only as a synchronous latch
+R2: process(clk6, R7_12, display, H256, P2_13, P3_6)
+begin
+	if rising_edge(clk6) then
+		if R7_12 = '0' then
+			R2_reg <= (H256 & display(7) & P3_6 & P2_13);
+		end if;
+	end if;
+end process;
+
+
+H256_s <= R2_reg(3);
+CompBlank_s <= R2_reg(1);
+CompSync_n_s <= R2_reg(0);
+A6_6 <= (R2_reg(2) and QH);
+A6_3 <= ((not R2_reg(2)) and QH);
+
+WhitePF_n <= (not A6_6);
+BlackPF_n <= (not A6_3);
+
+end rtl;
\ No newline at end of file
diff --git a/src/screech.vhd b/src/screech.vhd
new file mode 100644
index 0000000..8eec581
--- /dev/null
+++ b/src/screech.vhd
@@ -0,0 +1,73 @@
+-- Tire screech sound generator for Kee Games Sprint 1
+-- Identical circuit is used in a number of related Kee/Atari games 
+-- (c) 2017 James Sweet
+--
+-- Original circuit used a 7414 Schmitt trigger oscillator operating at approximately
+-- 1.2kHz producing a sawtooth with the frequency modulated slightly by the pseudo-random 
+-- noise generator. This is an extension of work initially done in Verilog by Jonas Elofsson.
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity tire_screech is 
+generic(
+			constant Inc1 : integer := 24; -- These constants can be adjusted to tune the frequency and modulation
+			constant Inc2 : integer := 34;
+			constant Dec1 : integer := 23;
+			constant Dec2 : integer := 12
+			);
+port(		
+			Clk			: in  std_logic;  -- 750kHz from the horizontal line counter chain works well here
+			Noise			: in	std_logic;  -- Output from LFSR pseudo-random noise generator
+			Screech_out	: out std_logic	-- Screech output - single bit
+			);
+end tire_screech;
+
+architecture rtl of tire_screech is
+
+signal Screech_count	: integer range 1000 to 11000;
+signal Screech_state	: std_logic;
+
+begin
+
+Screech: process(Clk, Screech_state)
+begin
+	if rising_edge(Clk) then
+		if screech_state = '1' then -- screech_state is 1, counter is rising
+			if noise = '1' then 	-- Noise signal from LFSR, when high increases the slope of the rising ramp
+				screech_count <= screech_count + inc2;
+			else 						-- When Noise is low, decreas the slope of the ramp
+				screech_count <= screech_count + inc1; 
+			end if;
+			if screech_count > 10000 then -- Reverse the ramp direction when boundary value of 10,000 is reached
+				screech_state <= '0';
+			end if;
+		elsif screech_state = '0' then -- screech_state is now low, decrement the counter (ramp down)
+			if noise = '1' then 
+				screech_count <= screech_count - dec2; -- Slope is influenced by the Noise signal
+			else
+				screech_count <= screech_count - dec1;
+			end if;
+			if screech_count < 1000 then -- Reverse the ramp direction again when the lower boundary of 1,000 is crossed
+				screech_state <= '1';
+			end if;
+		end if;
+	end if;
+screech_out <= screech_state;
+end process;
+
+end rtl;
\ No newline at end of file
diff --git a/src/sprint1.vhd b/src/sprint1.vhd
new file mode 100644
index 0000000..42c61b9
--- /dev/null
+++ b/src/sprint1.vhd
@@ -0,0 +1,417 @@
+-- Top level file for Kee Games Sprint 1 
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- Targeted to EP2C5T144C8 mini board but porting to nearly any FPGA should be fairly simple
+-- See Sprint 1 manual for video output details. Resistor values listed here have been scaled 
+-- for 3.3V logic. 
+-- R48 1k Ohm
+-- R49 1k Ohm
+-- R50 680R
+-- R51 330R
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+
+entity sprint1 is 
+port(		
+			Clk_50_I		: in	std_logic;	-- 50MHz input clock
+			Reset_n		: in	std_logic;	-- Reset button (Active low)
+			Audio1_O			: out std_logic_vector(6 downto 0);
+
+			VideoW_O		: out std_logic;  -- White video output (680 Ohm)
+			VideoB_O		: out std_logic;	-- Black video output (1.2k)
+			Sync_O		: out std_logic;  -- Composite sync output (1.2k)
+			--Audio1_O		: out std_logic;  -- Ideally this should have a simple low pass filter
+			Coin1_I		: in  std_logic;  -- Coin switches (Active low)
+			Coin2_I		: in  std_logic;
+			Start_I		: in  std_logic;  -- Start button
+			Gas_I			: in  std_logic;	-- Gas pedal
+			Gear1_I		: in  std_logic;  -- Gear shifter, 4th gear = no other gear selected
+			Gear2_I		: in  std_logic;
+			Gear3_I		: in  std_logic;
+			Test_I		: in  std_logic;  -- Self-test switch
+			SteerA_I		: in  std_logic;	-- Steering wheel inputs, these are quadrature encoders
+			SteerB_I		: in	std_logic;
+			StartLamp_O	: out std_logic;	-- Start button lamp
+			hs_O: out std_logic;
+			vs_O: out std_logic;
+			hblank_O: out std_logic;
+			vblank_O: out std_logic;
+			clk_12: in std_logic;
+			clk_6_O: out std_logic;
+			SW1_I	: in std_logic_vector(7 downto 0);
+			
+			-- signals that carry the ROM data from the MiSTer disk
+			dn_addr        : in  std_logic_vector(15 downto 0);
+			dn_data        : in  std_logic_vector(7 downto 0);
+			dn_wr          : in  std_logic
+
+			);
+			
+end sprint1;
+
+architecture rtl of sprint1 is
+
+--signal clk_12			: std_logic;
+signal clk_6			: std_logic;
+signal phi1 			: std_logic;
+signal phi2				: std_logic;
+
+signal Hcount		   : std_logic_vector(8 downto 0) := (others => '0');
+signal H256				: std_logic;
+signal H256_s			: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H8_n				: std_logic;
+signal H4				: std_logic;
+signal H4_n				: std_logic;
+signal H2				: std_logic;
+signal H1				: std_logic;
+
+signal Hsync			: std_logic;
+signal Vsync			: std_logic;
+
+signal Vcount  		: std_logic_vector(7 downto 0) := (others => '0');
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+signal V4				: std_logic;
+signal V2				: std_logic;
+signal V1				: std_logic;
+
+signal Vblank			: std_logic;
+signal Vreset			: std_logic;
+signal Vblank_s		: std_logic;
+signal Vblank_n_s		: std_logic;
+signal HBlank			: std_logic;
+
+signal CompBlank_s	: std_logic;
+signal CompSync_n_s	: std_logic;
+
+signal WhitePF_n		: std_logic;
+signal BlackPF_n		: std_logic;
+
+signal Display			: std_logic_vector(7 downto 0);
+
+
+-- Address decoder
+signal addec_bus		: std_logic_vector(7 downto 0);
+signal RnW				: std_logic;
+signal Write_n			: std_logic;
+signal ROM1				: std_logic;
+signal ROM2				: std_logic;
+signal ROM3				: std_logic;
+signal WRAM				: std_logic;
+signal RAM_n			: std_logic;
+signal Sync_n			: std_logic;
+signal Switch_n		: std_logic;
+signal Collision1_n	: std_logic;
+signal Collision2_n	: std_logic;
+signal Display_n		: std_logic;
+signal TimerReset_n	: std_logic;
+signal CollRst1_n		: std_logic;
+signal CollRst2_n		: std_logic;
+signal SteerRst1_n	: std_logic;
+signal SteerRst2_n	: std_logic;
+signal NoiseRst_n		: std_logic;
+signal Attract			: std_logic;	
+signal Skid1			: std_logic;
+signal Skid2			: std_logic;
+
+signal Crash_n			: std_logic;
+signal Motor1_n 		: std_logic;
+signal Motor2_n		: std_logic;
+signal Car1				: std_logic;
+signal Car1_n			: std_logic;
+signal Car2				: std_logic;
+signal Car2_n			: std_logic;
+signal Car3_4_n		: std_logic;	
+
+signal NMI_n			: std_logic;
+
+signal Adr				: std_logic_vector(9 downto 0);
+
+
+signal Inputs			: std_logic_vector(1 downto 0);
+signal Collisions1	: std_logic_vector(1 downto 0);
+signal Collisions2	: std_logic_vector(1 downto 0);
+
+signal Vid_mono 		: std_logic_vector(3 downto 0);
+
+-- logic to load roms from disk
+signal rom1_cs   			: std_logic;
+signal rom2_cs   			: std_logic;
+signal rom3_cs   			: std_logic;
+signal rom4_cs   			: std_logic;
+signal rom_LSB_cs   		: std_logic;
+signal rom_MSB_cs   		: std_logic;
+signal rom_car_k6_cs   	: std_logic;
+signal rom_car_j6_cs   	: std_logic;
+signal rom_sync_prom_cs : std_logic;
+signal rom_32_cs   		: std_logic;
+
+begin
+-- Configuration DIP switches, these can be brought out to external switches if desired
+-- See Sprint 2 manual page 11 for complete information. Active low (0 = On, 1 = Off)
+--    1 								Oil slicks			(0 - Oil slicks enabled)
+--			2							Cycle tracks      (0/1 - Cycle every lap/every two laps)
+--   			3	4					Coins per play		(00 - 1 Coin per player) 
+--						5				Extended Play		(0 - Extended Play enabled)
+--							6			Not used				(X - Don't care)
+--								7	8	Game time			(01 - 120 Seconds)
+--SW1 <= "01000101"; -- Config dip switches
+
+-- PLL to generate 12.096 MHz clock
+--PLL: entity work.clk_pll
+--port map(-
+--		inclk0 => Clk_50_I,
+--		c0 => clk_12
+--		);
+		
+--                          13
+-- 
+--     2048     6290-01.b1  00 0000 0000 0000   prog_rom1	8 bit wide
+--     2048     6291-01.c1  00 1000 0000 0000   prog_rom2	8 bit wide
+--     2048     6442-01.d1  01 0000 0000 0000   prog_rom3	8 bit wide
+--     2048     6443-01.e1  01 1000 0000 0000   prog_rom4	8 bit wide
+--      512     6396-01.p4  10 0000 0000 0000  - LSB	4 bit wide
+--      512     6397-01.r4  10 0010 0000 0000  - MSB	4 bit wide
+--      512     6398-01.k6  10 0100 0000 0000  - cars k6	4 bit wide
+--      512     6399-01.j6  10 0110 0000 0000  - cars j6	4 bit wide
+--      256     6400-01.m2  10 1000 0000 0000  - sync_prom	4 bit wide
+--       32     6401-01.e2  10 1001 0000 0000					8 bit wide
+
+rom1_cs <= '1' when dn_addr(13 downto 11) = "000"     else '0';
+rom2_cs <= '1' when dn_addr(13 downto 11) = "001"     else '0';
+rom3_cs <= '1' when dn_addr(13 downto 11) = "010"     else '0';
+rom4_cs <= '1' when dn_addr(13 downto 11) = "011"     else '0';
+rom_LSB_cs <= '1' when dn_addr(13 downto 9) =  "10000"   else '0';
+rom_MSB_cs <= '1' when dn_addr(13 downto 9) =  "10001"   else '0';
+rom_car_k6_cs <= '1' when dn_addr(13 downto 9) =  "10010"   else '0';
+rom_car_j6_cs <= '1' when dn_addr(13 downto 9) =  "10011"   else '0';
+rom_sync_prom_cs <= '1' when dn_addr(13 downto 8) =  "101000"   else '0';
+rom_32_cs <= '1' when dn_addr(13 downto 8) =  "101001"   else '0';
+
+		
+-- add sync prom		
+Vid_sync: entity work.synchronizer
+port map(
+		clk_12 => clk_12,
+		clk_6 => clk_6,
+		hcount => hcount,
+		vcount => vcount,
+		hsync => hsync,
+		hblank => hblank,
+		vblank_s => vblank_s,
+		vblank_n_s => vblank_n_s,
+		vblank => vblank,
+		vsync => vsync,
+		vreset => vreset,
+		dn_wr => dn_wr,
+		dn_addr=>dn_addr,
+		dn_data=>dn_data,
+		
+		rom_sync_prom_cs=>rom_sync_prom_cs
+		);
+
+-- add playfield rom
+-- ./roms/6397-01r4.hex - MSB
+-- 6396-01.p4 -- LSB
+Background: entity work.playfield
+port map( 
+		clk6 => clk_6,
+		clk12=>clk_12,
+		display => display,
+		HCount => HCount,
+		VCount => VCount,
+		HBlank => HBlank,		
+		H256_s => H256_s,
+		VBlank => VBlank,
+		VBlank_n_s => Vblank_n_s,
+		HSync => Hsync,
+		VSync => VSync,
+		CompSync_n_s => CompSync_n_s,
+		CompBlank_s => CompBlank_s,
+		WhitePF_n => WhitePF_n,
+		BlackPF_n => BlackPF_n,
+		
+		dn_wr => dn_wr,
+		dn_addr=>dn_addr,
+		dn_data=>dn_data,
+		
+		rom_LSB_cs=>rom_LSB_cs,
+		rom_MSB_cs=>rom_MSB_cs
+		
+		);
+
+		
+Cars: entity work.motion
+port map(
+		CLK6 => clk_6,
+		CLK12 => clk_12,
+		PHI2 => phi2,
+		DISPLAY => Display,
+		H256_s => H256_s,
+		VCount => VCount,
+		HCount => HCount,
+		Crash_n => Crash_n,
+		Motor1_n => Motor1_n,
+		Car1 => Car1,
+		Car1_n => Car1_n,
+		Car2 => Car2,
+		Car2_n => Car2_n,
+		Car3_4_n => Car3_4_n,
+		
+		dn_wr => dn_wr,
+		dn_addr=>dn_addr,
+		dn_data=>dn_data,
+		
+		rom_car_j6_cs=>rom_car_j6_cs,
+		rom_car_k6_cs=>rom_car_k6_cs
+		);
+		
+		
+PF_Comparator: entity work.collision_detect
+port map(
+		Clk6 => Clk_6,
+		Car1 => Car1,
+		Car1_n => Car1_n,
+		Car2 => Car2,
+		Car2_n => Car2_n,
+		Car3_4_n	=> Car3_4_n,
+		WhitePF_n => WhitePF_n,
+		BlackPF_n => BlackPF_n,
+		CollRst1_n => CollRst1_n,
+		Collisions1 => Collisions1
+		);
+	
+	
+CPU: entity work.cpu_mem
+port map(
+		Clk12 => clk_12,
+		Clk6 => clk_6,
+		Reset_n => reset_n,
+		VCount => VCount,
+		HCount => HCount,
+		Hsync_n => not Hsync,
+		Vblank_s => Vblank_s,
+		Vreset => Vreset,
+		Test_n => not Test_I,
+		Attract => Attract,
+		Skid1 => Skid1,
+		Skid2 => Skid2,
+		NoiseReset_n => NoiseRst_n,
+		CollRst1_n => CollRst1_n,
+		CollRst2_n => CollRst2_n,
+		SteerRst1_n => SteerRst1_n,
+		Lamp1 => StartLamp_O,
+		Phi1_o => Phi1,
+		Phi2_o => Phi2,
+		Display => Display,
+		IO_Adr => Adr,
+		Collisions1 => Collisions1,
+		Collisions2 => Collisions2,
+		Inputs => Inputs,
+		
+		dn_wr => dn_wr,
+		dn_addr=>dn_addr,
+		dn_data=>dn_data,
+		
+		rom1_cs=>rom1_cs,
+		rom2_cs=>rom2_cs,
+		rom3_cs=>rom3_cs,
+		rom4_cs=>rom4_cs,
+		rom_32_cs=>rom_32_cs
+		);
+
+
+Input: entity work.Control_Inputs
+port map(
+		clk6 => clk_6,
+		SW1 => SW1_I, -- DIP switches
+		Coin1_n => Coin1_I,
+		Coin2_n => Coin2_I,
+		Start => not Start_I, -- Active high in real hardware, inverting these makes more sense with the FPGA
+		Gas => not Gas_I,
+		Gear1 => not Gear1_I,
+		Gear2 => not Gear2_I,
+		Gear3 => not Gear3_I,
+		Self_Test => not Test_I,
+		Steering1A_n => SteerA_I,
+		Steering1B_n => SteerB_I,
+		SteerRst1_n => SteerRst1_n,
+		Adr => Adr,
+		Inputs => Inputs
+	);	
+
+	
+Sound: entity work.audio
+port map( 
+		Clk_50 => Clk_50_I,
+		Clk_6 => Clk_6,
+		Reset_n => Reset_n,
+		Motor1_n => Motor1_n,
+		Skid1 => Skid1,
+		Crash_n => Crash_n,
+		NoiseReset_n => NoiseRst_n,
+		Attract => Attract,
+		Display => Display,
+		HCount => HCount,
+		VCount => VCount,
+		Audio1 => Audio1_O
+		);
+
+		
+		
+-- Video mixing	
+VideoB_O <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s;	
+VideoW_O <= not(WhitePF_n and Car1_n);
+
+
+
+--Video:process(SprintVid)
+--begin
+ -- case SprintVid_in is
+--     when "01" =>
+--	    Vid_mono<="0000";
+--    when "10" =>
+--	    Vid_mono<="1000";
+--    when "11" =>
+--	    Vid_mono<="1111";
+--    when others =>
+--	    Vid_mono<="0000";
+--  end case;
+--end process;
+
+
+
+Sync_O <= CompSync_n_s;
+
+hs_O<= hsync;
+hblank_O <= HBlank;
+vblank_O <= VBlank;
+vs_O <=vsync;
+clk_6_O<=clk_6;
+		
+end rtl;
\ No newline at end of file
diff --git a/src/sprint1_sound.vhd b/src/sprint1_sound.vhd
new file mode 100644
index 0000000..427f19d
--- /dev/null
+++ b/src/sprint1_sound.vhd
@@ -0,0 +1,208 @@
+-- Audio for Sprint 1
+-- First attempt at modeling the analog sound circuits used in Sprint 1, may be room for improvement as
+-- I do not have a real board to compare.
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity audio is 
+port(		
+			Clk_50			: in	std_logic;
+			Clk_6				: in  std_logic;
+			Reset_n			: in	std_logic;
+			Motor1_n			: in	std_logic;
+			Skid1				: in  std_logic;
+			Crash_n			: in  std_logic;
+			NoiseReset_n	: in  std_logic;
+			Attract			: in  std_logic;
+			Display			: in	std_logic_vector(7 downto 0);
+			HCount			: in  std_logic_vector(8 downto 0);
+			VCount			: in  std_logic_vector(7 downto 0);
+			Audio1			: out std_logic_vector(6 downto 0)
+			);
+end audio;
+
+architecture rtl of audio is
+
+signal reset			: std_logic;
+
+signal H4				: std_logic;
+signal V2				: std_logic;
+
+signal Noise			: std_logic;
+signal Noise_Shift	: std_logic_vector(15 downto 0);
+signal Shift_in  		: std_logic;
+
+signal Screech_count	: integer range 1000 to 11000;
+signal Screech_state	: std_logic;
+signal Screech_snd1	: std_logic;
+signal Screech1		: std_logic_vector(3 downto 0);
+
+signal Crash			: std_logic_vector(3 downto 0);
+signal Bang				: std_logic_vector(3 downto 0);
+
+signal Mtr1_Freq		: std_logic_vector(3 downto 0);
+signal Motor1_speed	: std_logic_vector(3 downto 0);
+signal Motor1_snd		: std_logic_vector(5 downto 0);
+signal P1_audio		: std_logic_vector(6 downto 0);
+
+signal ena_count		: std_logic_vector(10 downto 0);
+signal ena_3k			: std_logic;
+
+signal bang_prefilter     : std_logic_vector(3 downto 0);
+signal bang_filter_t1     : std_logic_vector(3 downto 0);
+signal bang_filter_t2     : std_logic_vector(3 downto 0);
+signal bang_filter_t3     : std_logic_vector(3 downto 0);
+signal bang_filtered      : std_logic_vector(5 downto 0);
+
+
+begin
+
+-- HCount
+-- (0) 1H 	3 MHz
+-- (1) 2H   1.5MHz
+-- (2) 4H	750 kHz
+-- (3) 8H	375 kHz
+-- (4) 16H	187 kHz
+-- (5) 32H	93 kHz
+-- (6) 64H	46 kHz
+-- (7) 128H 23 kHz
+-- (8) 256H 12 kHz
+
+reset <= (not reset_n);
+
+H4 <= HCount(2);
+V2 <= VCount(1);
+
+-- Generate the 3kHz clock enable used by the filter
+Enable: process(clk_6)
+begin
+	if rising_edge(CLK_6) then
+		ena_count <= ena_count + "1";
+		ena_3k <= '0';
+		if (ena_count(10 downto 0) = "00000000000") then
+			ena_3k <= '1';
+		end if;
+	end if;
+end process;
+
+
+-- LFSR that generates pseudo-random noise
+Noise_gen: process(NoiseReset_n, V2)
+begin
+	if (noisereset_n = '0') then
+		noise_shift <= (others => '0');
+		noise <= '0';
+	elsif rising_edge(V2) then
+		shift_in <= not(noise_shift(6) xor noise_shift(8));
+		noise_shift <= shift_in & noise_shift(15 downto 1);
+		noise <= noise_shift(0); 
+	end if;
+end process;
+
+
+-- Tire screech sound
+Screech_gen1: entity work.tire_screech
+generic map( -- These values can be tweaked to tune the screech sound
+		Inc1 => 24, -- Ramp increase rate when noise = 0
+		Inc2 => 33, -- Ramp increase rate when noise = 1
+		Dec1 => 29, -- Ramp decrease rate when noise = 0
+		Dec2 => 16  -- Ramp decrease rate when noise = 1
+		)
+port map(
+		Clk => H4,
+		Noise => noise,
+		Screech_out => screech_snd1
+		);
+		
+	
+-- Convert screech from 1 bit to 4 bits wide and enable via skid1  signal
+Screech_ctrl: process(screech_snd1, skid1)
+begin
+	if (skid1 and screech_snd1) = '1' then
+		screech1 <= "1111";
+	else
+		screech1 <= "0000";
+	end if;
+end process;
+		
+	
+Crash_sound: process(crash_n, display, noise)		
+begin
+	if crash_n = '0' then
+		crash <= display(3 downto 0);
+	end if;
+	if noise = '1' then
+		bang_prefilter <= crash;
+	else
+		bang_prefilter <= "0000";
+	end if;
+end process;
+
+
+---- Very simple low pass filter, borrowed from MikeJ's Asteroids code
+Crash_filter: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		if (ena_3k = '1') then
+			bang_filter_t1 <= bang_prefilter;
+			bang_filter_t2 <= bang_filter_t1;
+			bang_filter_t3 <= bang_filter_t2;
+		end if;
+		bang_filtered <=  ("00" & bang_filter_t1) +
+								('0'  & bang_filter_t2 & '0') +
+								("00" & bang_filter_t3);
+	end if;
+end process;	
+
+
+Motor1_latch: process(Motor1_n, Display)
+begin
+	if Motor1_n = '0' then
+		Motor1_speed <= Display(3 downto 0);
+	end if;
+end process;
+
+Motor1: entity work.EngineSound 
+generic map( 
+		Freq_tune => 50 -- Tuning pot for engine sound frequency
+		)
+port map(		
+		Clk_6 => clk_6, 
+		Ena_3k => ena_3k,
+		EngineData => motor1_speed,
+		Motor => motor1_snd
+		);
+	
+	
+-- Audio mixer, also mutes sound in attract mode
+audio1 <= ('0' & motor1_snd) + ("00" & screech1) + ('0' & bang_filtered) when attract = '0'
+				else "0000000";
+		
+
+--DAC1: entity work.deltasigma
+--generic map(
+--width => 7
+--)
+--port map(
+--	inval => P1_audio,
+--	output => audio1,
+--	clk => clk_50,
+--	reset => reset
+--	);
+	
+end rtl;
\ No newline at end of file
diff --git a/src/sync.vhd b/src/sync.vhd
new file mode 100644
index 0000000..1ced2e6
--- /dev/null
+++ b/src/sync.vhd
@@ -0,0 +1,199 @@
+-- Video synchronizer circuit for Sprint 1
+-- Similar circuit used in many other Atari and Kee Games arcade games
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity synchronizer is 
+port(		
+			clk_12		: in	std_logic;
+			clk_6			: out	std_logic;
+			hcount		: out	std_logic_vector(8 downto 0);
+			vcount		: out	std_logic_vector(7 downto 0);
+		   hsync			: out	std_logic;
+			hblank		: out std_logic;
+			vblank_s		: out std_logic;
+			vblank_n_s	: out std_logic;
+			vblank		: out	std_logic;
+			vsync			: out std_logic;
+			vreset		: out	std_logic;
+			
+			--signals that carry the ROM data from the MiSTer disk
+			dn_addr        	: in  std_logic_vector(15 downto 0);
+			dn_data        	: in  std_logic_vector(7 downto 0);
+			dn_wr          	: in  std_logic;
+			rom_sync_prom_cs  : in std_logic
+
+			
+			);
+end synchronizer;
+
+architecture rtl of synchronizer is
+
+signal h_counter		: std_logic_vector(9 downto 0) := (others => '0');
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H8_n				: std_logic;
+signal H4				: std_logic;
+signal H4_n				: std_logic;
+signal H2				: std_logic;
+signal H1				: std_logic;
+
+signal v_counter		: std_logic_vector(7 downto 0) := (others => '0');
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+signal V4				: std_logic;
+signal V2				: std_logic;
+signal V1				: std_logic;
+
+signal sync_bus		: std_logic_vector(3 downto 0) := (others => '0');
+signal sync_reg		: std_logic_vector(3 downto 0) := (others => '0');
+signal vblank_int		: std_logic := '0';
+signal vreset_n		: std_logic := '0';
+
+signal hblank_int		: std_logic := '0';
+signal hsync_int		: std_logic := '0';
+signal hsync_reset 	: std_logic := '0';
+
+
+begin
+
+-- Horizontal counter is 9 bits long plus additional flip flop. The last 4 bit IC in the chain resets to 0010 so total count resets to 128 
+-- using only the last three count states
+H_count: process(clk_12)
+begin
+	if rising_edge(clk_12) then
+		if h_counter = "1111111111" then
+			h_counter <= "0100000000";
+		else
+			h_counter <= h_counter + 1;
+		end if;
+	end if;
+end process;
+
+-- Vertical counter is 8 bits, clocked by the rising edge of H256 at the end of each horizontal line
+V_count: process(hsync_int)
+begin
+	if rising_edge(Hsync_int) then
+		if vreset_n = '0' then
+			v_counter <= (others => '0');
+		else
+			v_counter <= v_counter + '1';
+		end if;
+	end if;
+end process;
+
+-- Many Atari raster games use a 256 x 4 bit prom to decode vertical sync signals
+-- This could be replaced by combinatorial logic
+--M2: entity work.sync_prom
+--port map(
+--		clock => clk_12, 
+--		address => sync_reg(3) & V128 & V64 & V16 & V8 & V4 & V2 & V1,
+--		q => sync_bus
+--		);
+M2 : work.dpram generic map (8,8)
+port map
+(
+	clock_a   => clk_12,
+	wren_a    => dn_wr and rom_sync_prom_cs,
+	address_a => dn_addr(7 downto 0),
+	data_a    => dn_data,
+
+	clock_b   => clk_12,
+	address_b => sync_reg(3) & V128 & V64 & V16 & V8 & V4 & V2 & V1,
+	q_b(3 downto 0)       => sync_bus 
+);
+
+
+-- Register fed by the sync PROM, in the original hardware this also creates the complements of these signals
+sync_register: process(hsync_int)
+begin
+	if rising_edge(hsync_int) then
+		sync_reg <= sync_bus;
+	end if;
+end process;
+
+-- Outputs of sync PROM
+vblank_s <= sync_reg(3);
+vblank_n_s <= not sync_reg(3);
+vreset <= sync_reg(2);
+vreset_n <= not sync_reg(2);
+vblank <= sync_reg(1);
+vsync <= sync_reg(0);
+
+-- A pair of D type flip-flops that generate the Hsync signal
+Hsync_1: process(H256_n, H32)
+begin	
+	if H256_n = '0' then	
+		hblank_int <= '0';
+	else
+		if rising_edge(H32) then
+			hblank_int <= not H64;
+		end if;
+	end if;
+end process;
+
+Hsync_2: process(hblank_int, H8) 
+begin
+	if hblank_int = '0' then
+		hsync_int <= '0';
+	else
+		if rising_edge(H8) then
+			hsync_int <= H32;
+		end if;
+	end if;
+end process;
+
+-- Assign various signals
+clk_6 <= h_counter(0);
+H1 <= h_counter(1);
+H2 <= h_counter(2);
+H4 <= h_counter(3);
+H8 <= h_counter(4);
+H16 <=  h_counter(5);
+H32 <= h_counter(6);
+H64 <= h_counter(7);
+H128 <= h_counter(8);
+H256 <= h_counter(9);
+H4_n <= not H4;
+H8_n <= not H8;
+H256_n <= not H256;
+
+V1 <= v_counter(0);
+V2 <= v_counter(1);
+V4 <= v_counter(2);
+V8 <= v_counter(3);
+V16 <= v_counter(4);
+V32 <= v_counter(5);
+V64 <= v_counter(6);
+V128 <= v_counter(7);
+
+hcount <= h_counter(9 downto 1);
+vcount <= v_counter;
+hsync <= hsync_int;
+hblank <= hblank_int;
+
+end rtl;
\ No newline at end of file
diff --git a/sys/alsa.sv b/sys/alsa.sv
new file mode 100644
index 0000000..9ed448e
--- /dev/null
+++ b/sys/alsa.sv
@@ -0,0 +1,128 @@
+//============================================================================
+//
+//  ALSA sound support for MiSTer
+//  (c)2019 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//
+//============================================================================
+
+module alsa
+(
+	input             reset,
+
+	input             ram_clk,
+	output reg [28:0] ram_address,
+	output reg  [7:0] ram_burstcount,
+	input             ram_waitrequest,
+	input      [63:0] ram_readdata,
+	input             ram_readdatavalid,
+	output reg        ram_read,
+	
+	input             spi_ss,
+	input             spi_sck,
+	input             spi_mosi,
+	
+	output reg [15:0] pcm_l,
+	output reg [15:0] pcm_r
+);
+
+reg         spi_new = 0;
+reg [127:0] spi_data;
+always @(posedge spi_sck, posedge spi_ss) begin
+	reg [7:0] mosi;
+	reg [6:0] spicnt = 0;
+	
+	if(spi_ss) spicnt <= 0;
+	else begin
+		mosi <= {mosi[6:0],spi_mosi};
+
+		spicnt <= spicnt + 1'd1;
+		if(&spicnt[2:0]) begin
+			spi_data[{spicnt[6:3],3'b000} +:8] <= {mosi[6:0],spi_mosi};
+			spi_new <= &spicnt;
+		end
+	end
+end
+
+reg [31:0] buf_addr;
+reg [31:0] buf_len;
+reg [31:0] buf_wptr = 0;
+
+always @(posedge ram_clk) begin
+	reg n1,n2,n3;
+	reg [127:0] data1,data2;
+
+	n1 <= spi_new;
+	n2 <= n1;
+	n3 <= n2;
+	
+	data1 <= spi_data;
+	data2 <= data1;
+	
+	if(~n3 & n2) {buf_wptr,buf_len,buf_addr} <= data2[95:0];
+end
+
+reg [31:0] buf_rptr = 0;
+always @(posedge ram_clk) begin
+	reg got_first = 0;
+	reg ready = 0;
+	reg ud;
+	reg [31:0] readdata;
+
+	if(~ram_waitrequest) ram_read <= 0;
+	if(ram_readdatavalid && ram_burstcount) begin
+		ram_burstcount <= 0;
+		ready <= 1;
+		readdata <= ud ? ram_readdata[63:32] : ram_readdata[31:0];
+		if(buf_rptr[31:2] >= buf_len[31:2]) buf_rptr <= 0;
+	end
+
+	if(reset) {ready, got_first} <= 0;
+	else
+	if(buf_rptr[31:2] != buf_wptr[31:2]) begin
+		if(~got_first) begin
+			buf_rptr <= buf_wptr;
+			got_first <= 1;
+		end
+		else
+		if(!ram_burstcount && ~ram_waitrequest && ~ready) begin
+			ram_address <= buf_addr[31:3] + buf_rptr[31:3];
+			ud <= buf_rptr[2];
+			ram_burstcount <= 1;
+			ram_read <= 1;
+			buf_rptr <= buf_rptr + 4;
+		end
+	end
+
+	if(ready & ce_48k) begin
+		{pcm_r,pcm_l} <= readdata;
+		ready <= 0;
+	end
+end
+
+reg ce_48k;
+always @(posedge ram_clk) begin
+	reg [15:0] acc = 0;
+
+	ce_48k <= 0;
+	acc <= acc + 16'd48;
+	if(acc >= 50000) begin
+		acc <= acc - 16'd50000;
+		ce_48k <= 1;
+	end
+end
+
+endmodule
diff --git a/sys/arcade_video.v b/sys/arcade_video.v
new file mode 100644
index 0000000..93b4fbe
--- /dev/null
+++ b/sys/arcade_video.v
@@ -0,0 +1,478 @@
+//============================================================================
+//
+//  Screen +90/-90 deg. rotation
+//  Copyright (C) 2017-2019 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
+
+//
+// Output timings are incompatible with any TV/VGA mode.
+// The output is supposed to be send to scaler input.
+//
+module screen_rotate #(parameter WIDTH=320, HEIGHT=240, DEPTH=8, MARGIN=4, CCW=0)
+(
+	input              clk,
+	input              ce,
+
+	input  [DEPTH-1:0] video_in,
+	input              hblank,
+	input              vblank,
+
+	input              ce_out,
+	output [DEPTH-1:0] video_out,
+	output reg         hsync,
+	output reg         vsync,
+	output reg         hblank_out,
+	output reg         vblank_out
+);
+
+localparam bufsize = WIDTH*HEIGHT;
+localparam memsize = bufsize*2;
+localparam aw = memsize > 131072 ? 18 : memsize > 65536 ? 17 : 16; // resolutions up to ~ 512x256
+
+reg [aw-1:0] addr_in, addr_out;
+reg we_in;
+reg buff = 0;
+
+rram #(aw, DEPTH, memsize) ram
+(
+	.wrclock(clk),
+	.wraddress(addr_in),
+	.data(video_in),
+	.wren(en_we),
+	
+	.rdclock(clk),
+	.rdaddress(addr_out),
+	.q(out)
+);
+
+wire [DEPTH-1:0] out; 
+reg  [DEPTH-1:0] vout;
+
+assign video_out = vout;
+
+wire en_we = ce & ~blank & en_x & en_y;
+wire en_x = (xpos<WIDTH);
+wire en_y = (ypos<HEIGHT);
+integer xpos, ypos;
+
+wire blank = hblank | vblank;
+always @(posedge clk) begin
+	reg old_blank, old_vblank;
+	reg [aw-1:0] addr_row;
+
+	if(en_we) begin
+		addr_in <= CCW ? addr_in-HEIGHT[aw-1:0] : addr_in+HEIGHT[aw-1:0];
+		xpos <= xpos + 1;
+	end
+
+	old_blank <= blank;
+	old_vblank <= vblank;
+	if(~old_blank & blank) begin
+		xpos <= 0;
+		ypos <= ypos + 1;
+		addr_in  <= CCW ? addr_row + 1'd1 : addr_row - 1'd1;
+		addr_row <= CCW ? addr_row + 1'd1 : addr_row - 1'd1;
+	end
+
+	if(~old_vblank & vblank) begin
+		if(buff) begin
+			addr_in  <= CCW ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
+			addr_row <= CCW ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
+		end else begin
+			addr_in  <= CCW ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
+			addr_row <= CCW ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
+		end
+		buff <= ~buff;
+		ypos <= 0;
+		xpos <= 0;
+	end
+end
+
+always @(posedge clk) begin
+	reg old_buff;
+	reg hs;
+	reg ced;
+
+	integer vbcnt;
+	integer xposo, yposo, xposd, yposd;
+	
+	ced <= 0;
+	if(ce_out) begin
+		ced <= 1;
+
+		xposd <= xposo;
+		yposd <= yposo;
+
+		if(xposo == (HEIGHT + 8))  hsync <= 1;
+		if(xposo == (HEIGHT + 10)) hsync <= 0;
+
+		if((yposo>=MARGIN) && (yposo<WIDTH+MARGIN)) begin
+			if(xposo < HEIGHT) addr_out <= addr_out + 1'd1;
+		end
+
+		xposo <= xposo + 1;
+		if(xposo > (HEIGHT + 16)) begin
+			xposo  <= 0;
+			
+			if(yposo >= (WIDTH+MARGIN+MARGIN)) begin
+				vblank_out <= 1;
+				vbcnt <= vbcnt + 1;
+				if(vbcnt == 10	) vsync <= 1;
+				if(vbcnt == 12) vsync <= 0;
+			end
+			else yposo <= yposo + 1;
+			
+			old_buff <= buff;
+			if(old_buff != buff) begin
+				addr_out <= buff ? {aw{1'b0}} : bufsize[aw-1:0];
+				yposo <= 0;
+				vsync <= 0;
+				vbcnt <= 0;
+				vblank_out <= 0;
+			end
+		end
+	end
+	
+	if(ced) begin
+		if((yposd<MARGIN) || (yposd>=WIDTH+MARGIN)) begin
+			vout <= 0;
+		end else begin
+			vout <= out;
+		end
+		if(xposd == 0)       hblank_out <= 0;
+		if(xposd == HEIGHT)  hblank_out <= 1;
+	end
+end
+
+endmodule
+
+//////////////////////////////////////////////////////////
+
+// DW:
+//  6 : 2R 2G 2B
+//  8 : 3R 3G 2B
+//  9 : 3R 3G 3B
+// 12 : 4R 4G 4B
+
+module arcade_rotate_fx #(parameter WIDTH=320, HEIGHT=240, DW=8, CCW=0)
+(
+	input         clk_video,
+	input         ce_pix,
+
+	input[DW-1:0] RGB_in,
+	input         HBlank,
+	input         VBlank,
+	input         HSync,
+	input         VSync,
+
+	output        VGA_CLK,
+	output        VGA_CE,
+	output  [7:0] VGA_R,
+	output  [7:0] VGA_G,
+	output  [7:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        VGA_DE,
+
+	output        HDMI_CLK,
+	output        HDMI_CE,
+	output  [7:0] HDMI_R,
+	output  [7:0] HDMI_G,
+	output  [7:0] HDMI_B,
+	output        HDMI_HS,
+	output        HDMI_VS,
+	output        HDMI_DE,
+	output  [1:0] HDMI_SL,
+	
+	input   [2:0] fx,
+	input         forced_scandoubler,
+	input         no_rotate
+);
+
+assign VGA_CLK = clk_video;
+assign VGA_CE = ce_pix;
+assign VGA_HS = HSync;
+assign VGA_VS = VSync;
+assign VGA_DE = ~(HBlank | VBlank);
+
+generate
+	if(DW == 6) begin
+		assign VGA_R = {RGB_in[5:4],RGB_in[5:4],RGB_in[5:4],RGB_in[5:4]};
+		assign VGA_G = {RGB_in[3:2],RGB_in[3:2],RGB_in[3:2],RGB_in[3:2]};
+		assign VGA_B = {RGB_in[1:0],RGB_in[1:0],RGB_in[1:0],RGB_in[1:0]};
+	end
+	else if(DW == 8) begin
+		assign VGA_R = {RGB_in[7:5],RGB_in[7:5],RGB_in[7:6]};
+		assign VGA_G = {RGB_in[4:2],RGB_in[4:2],RGB_in[4:3]};
+		assign VGA_B = {RGB_in[1:0],RGB_in[1:0],RGB_in[1:0],RGB_in[1:0]};
+	end
+	else if(DW == 9) begin
+		assign VGA_R = {RGB_in[8:6],RGB_in[8:6],RGB_in[8:7]};
+		assign VGA_G = {RGB_in[5:3],RGB_in[5:3],RGB_in[5:4]};
+		assign VGA_B = {RGB_in[2:0],RGB_in[2:0],RGB_in[2:1]};
+	end
+	else begin
+		assign VGA_R = {RGB_in[11:8],RGB_in[11:8]};
+		assign VGA_G = {RGB_in[7:4],RGB_in[7:4]};
+		assign VGA_B = {RGB_in[3:0],RGB_in[3:0]};
+	end
+endgenerate
+
+wire [DW-1:0] RGB_out;
+wire rhs,rvs,rhblank,rvblank;
+
+screen_rotate #(WIDTH,HEIGHT,DW,4,CCW) rotator
+(
+	.clk(VGA_CLK),
+	.ce(VGA_CE),
+
+	.video_in(RGB_in),
+	.hblank(HBlank),
+	.vblank(VBlank),
+
+	.ce_out(VGA_CE | ~scandoubler),
+	.video_out(RGB_out),
+	.hsync(rhs),
+	.vsync(rvs),
+	.hblank_out(rhblank),
+	.vblank_out(rvblank)
+);
+
+wire [3:0] Rr,Gr,Br;
+
+generate
+	if(DW == 6) begin
+		assign Rr = {RGB_out[5:4],RGB_out[5:4]};
+		assign Gr = {RGB_out[3:2],RGB_out[3:2]};
+		assign Br = {RGB_out[1:0],RGB_out[1:0]};
+	end
+	else if(DW == 8) begin
+		assign Rr = {RGB_out[7:5],RGB_out[7]};
+		assign Gr = {RGB_out[4:2],RGB_out[4]};
+		assign Br = {RGB_out[1:0],RGB_out[1:0]};
+	end
+	else if(DW == 9) begin
+		assign Rr = {RGB_out[8:6],RGB_out[8]};
+		assign Gr = {RGB_out[5:3],RGB_out[5]};
+		assign Br = {RGB_out[2:0],RGB_out[2]};
+	end
+	else begin
+		assign Rr = RGB_out[11:8];
+		assign Gr = RGB_out[7:4];
+		assign Br = RGB_out[3:0];
+	end
+endgenerate
+
+assign HDMI_CLK = VGA_CLK;
+assign HDMI_SL  = no_rotate ? 2'd0 : sl[1:0];
+wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
+wire scandoubler = fx || forced_scandoubler;
+
+video_mixer #(WIDTH+4, 1) video_mixer
+(
+	.clk_sys(HDMI_CLK),
+	.ce_pix(VGA_CE | ~scandoubler),
+	.ce_pix_out(HDMI_CE),
+
+	.scandoubler(scandoubler),
+	.hq2x(fx==1),
+
+	.R(no_rotate ? VGA_R[7:4] : Rr),
+	.G(no_rotate ? VGA_G[7:4] : Gr),
+	.B(no_rotate ? VGA_B[7:4] : Br),
+
+	.HSync (no_rotate ? HSync  : rhs),
+	.VSync (no_rotate ? VSync  : rvs),
+	.HBlank(no_rotate ? HBlank : rhblank),
+	.VBlank(no_rotate ? VBlank : rvblank),
+
+	.VGA_R(HDMI_R),
+	.VGA_G(HDMI_G),
+	.VGA_B(HDMI_B),
+	.VGA_VS(HDMI_VS),
+	.VGA_HS(HDMI_HS),
+	.VGA_DE(HDMI_DE)
+);
+
+endmodule
+
+//////////////////////////////////////////////////////////
+
+// DW:
+//  6 : 2R 2G 2B
+//  8 : 3R 3G 2B
+//  9 : 3R 3G 3B
+// 12 : 4R 4G 4B
+
+module arcade_fx #(parameter WIDTH=320, DW=8)
+(
+	input         clk_video,
+	input         ce_pix,
+
+	input[DW-1:0] RGB_in,
+	input         HBlank,
+	input         VBlank,
+	input         HSync,
+	input         VSync,
+
+	output        VGA_CLK,
+	output        VGA_CE,
+	output  [7:0] VGA_R,
+	output  [7:0] VGA_G,
+	output  [7:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        VGA_DE,
+
+	output        HDMI_CLK,
+	output        HDMI_CE,
+	output  [7:0] HDMI_R,
+	output  [7:0] HDMI_G,
+	output  [7:0] HDMI_B,
+	output        HDMI_HS,
+	output        HDMI_VS,
+	output        HDMI_DE,
+	output  [1:0] HDMI_SL,
+	
+	input   [2:0] fx,
+	input         forced_scandoubler
+);
+
+assign VGA_CLK = clk_video;
+assign VGA_CE = ce_pix;
+assign VGA_HS = HSync;
+assign VGA_VS = VSync;
+assign VGA_DE = ~(HBlank | VBlank);
+
+generate
+	if(DW == 6) begin
+		assign VGA_R = {RGB_in[5:4],RGB_in[5:4],RGB_in[5:4],RGB_in[5:4]};
+		assign VGA_G = {RGB_in[3:2],RGB_in[3:2],RGB_in[3:2],RGB_in[3:2]};
+		assign VGA_B = {RGB_in[1:0],RGB_in[1:0],RGB_in[1:0],RGB_in[1:0]};
+	end
+	else if(DW == 8) begin
+		assign VGA_R = {RGB_in[7:5],RGB_in[7:5],RGB_in[7:6]};
+		assign VGA_G = {RGB_in[4:2],RGB_in[4:2],RGB_in[4:3]};
+		assign VGA_B = {RGB_in[1:0],RGB_in[1:0],RGB_in[1:0],RGB_in[1:0]};
+	end
+	else if(DW == 9) begin
+		assign VGA_R = {RGB_in[8:6],RGB_in[8:6],RGB_in[8:7]};
+		assign VGA_G = {RGB_in[5:3],RGB_in[5:3],RGB_in[5:4]};
+		assign VGA_B = {RGB_in[2:0],RGB_in[2:0],RGB_in[2:1]};
+	end
+	else begin
+		assign VGA_R = {RGB_in[11:8],RGB_in[11:8]};
+		assign VGA_G = {RGB_in[7:4],RGB_in[7:4]};
+		assign VGA_B = {RGB_in[3:0],RGB_in[3:0]};
+	end
+endgenerate
+
+assign HDMI_CLK = VGA_CLK;
+assign HDMI_SL  = sl[1:0];
+wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
+wire scandoubler = fx || forced_scandoubler;
+
+video_mixer #(WIDTH+4, 1) video_mixer
+(
+	.clk_sys(HDMI_CLK),
+	.ce_pix(VGA_CE),
+	.ce_pix_out(HDMI_CE),
+
+	.scandoubler(scandoubler),
+	.hq2x(fx==1),
+
+	.R(VGA_R[7:4]),
+	.G(VGA_G[7:4]),
+	.B(VGA_B[7:4]),
+
+	.HSync(HSync),
+	.VSync(VSync),
+	.HBlank(HBlank),
+	.VBlank(VBlank),
+
+	.VGA_R(HDMI_R),
+	.VGA_G(HDMI_G),
+	.VGA_B(HDMI_B),
+	.VGA_VS(HDMI_VS),
+	.VGA_HS(HDMI_HS),
+	.VGA_DE(HDMI_DE)
+);
+
+endmodule
+
+//////////////////////////////////////////////////////////
+
+module rram #(parameter AW=16, DW=8, NW=1<<AW)
+(
+	input           wrclock,
+	input  [AW-1:0] wraddress,
+	input  [DW-1:0] data,
+	input           wren,
+
+	input	          rdclock,
+	input	 [AW-1:0] rdaddress,
+	output [DW-1:0] q
+);
+
+altsyncram	altsyncram_component
+(
+	.address_a (wraddress),
+	.address_b (rdaddress),
+	.clock0 (wrclock),
+	.clock1 (rdclock),
+	.data_a (data),
+	.wren_a (wren),
+	.q_b (q),
+	.aclr0 (1'b0),
+	.aclr1 (1'b0),
+	.addressstall_a(1'b0),
+	.addressstall_b(1'b0),
+	.byteena_a(1'b1),
+	.byteena_b(1'b1),
+	.clocken0(1'b1),
+	.clocken1(1'b1),
+	.clocken2(1'b1),
+	.clocken3(1'b1),
+	.data_b({DW{1'b0}}),
+	.eccstatus (),
+	.q_a(),
+	.rden_a (1'b1),
+	.rden_b (1'b1),
+	.wren_b(1'b0)
+);
+
+defparam
+	altsyncram_component.address_aclr_b = "NONE",
+	altsyncram_component.address_reg_b = "CLOCK1",
+	altsyncram_component.clock_enable_input_a = "BYPASS",
+	altsyncram_component.clock_enable_input_b = "BYPASS",
+	altsyncram_component.clock_enable_output_b = "BYPASS",
+	altsyncram_component.intended_device_family = "Cyclone V",
+	altsyncram_component.lpm_type = "altsyncram",
+	altsyncram_component.numwords_a = NW,
+	altsyncram_component.numwords_b = NW,
+	altsyncram_component.operation_mode = "DUAL_PORT",
+	altsyncram_component.outdata_aclr_b = "NONE",
+	altsyncram_component.outdata_reg_b = "UNREGISTERED",
+	altsyncram_component.power_up_uninitialized = "FALSE",
+	altsyncram_component.widthad_a = AW,
+	altsyncram_component.widthad_b = AW,
+	altsyncram_component.width_a = DW,
+	altsyncram_component.width_b = DW,
+	altsyncram_component.width_byteena_a = 1;
+
+endmodule
diff --git a/sys/ascal.vhd b/sys/ascal.vhd
new file mode 100644
index 0000000..651ee6d
--- /dev/null
+++ b/sys/ascal.vhd
@@ -0,0 +1,2312 @@
+--------------------------------------------------------------------------------
+-- AVALON SCALER
+--------------------------------------------------------------------------------
+-- TEMLIB 10/2018
+--------------------------------------------------------------------------------
+-- This code can be freely distributed and used for any purpose, but, if you
+-- find any bug, or want to suggest an enhancement, you ought to send a mail
+-- to info@temlib.org.
+--------------------------------------------------------------------------------
+
+-- Features :
+--  - Arbitrary output video format
+--  - Autodetect input image size or fixed window
+--  - Progressive and interlaced input
+--  - Interpolation
+--    Upscaling   : Nearest, Bilinear, Sharp Bilinear, Bicubic, Polyphase
+--    Downscaling : Nearest, Bilinear
+--  - Avalon bus interface with 128 or 64 bits DATA
+--  - Optional triple buffering
+--  - Support for external low lag syntonization
+
+--------------------------------------------
+-- Downscaling
+-- - Horizontal and vertical up-/down-scaling are independant.
+-- - Downscaling, H and/or V, supports only nearest-neighbour and bilinear
+--   filtering.
+-- - For interlaced video, when the vertical size is lower than a deinterlaced
+--   frame size (2x half-frame), the scaler processes only half-frames
+--   and upscales (when the output size is between 1x an 2x) or downscales (size
+--   below 1x) them.
+
+--------------------------------------------
+-- 4 asynchronous clock domains :
+--  i_xxx    : Input video
+--  o_xxx    : Output video
+--  avl_xxx  : Avalon memory bus
+--  poly_xxx : Polyphase filters memory
+
+--------------------------------------------
+-- Mode 24bits
+
+--------------------------------------------
+-- Image header. When HEADER = TRUE
+-- Header Address = RAMBASE
+-- Image Address  = RAMBASE + HEADER_SIZE
+
+-- Header (Bytes. Big Endian.)
+--  0    : Type = 1
+--  1    : Pixel format
+--         1 : 24 bits/pixel, packed RGB. Big Endian
+
+--  3:2  : Header size : Offset to start of picture (= N_BURST). 12 bits
+--  5:4  : Attributes. TBD
+--         b0 ; Interlaced
+--         b1 : Field number
+--         b2 : Horizontal downscaled
+--         b3 : Vertical downscaled
+--         b4 : Triple buffered
+--       b7-5 : Frame counter
+--  7:6  : Image width. Pixels. 12 bits
+--  9:8  : Image height. Pixels. 12 bits
+-- 11:10 : Line length. Bytes.
+-- 13:12 : Output width. Pixels. 12 bits
+-- 15:14 : Output height. Pixels. 12 bits
+--------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+-- MODE[2:0]
+-- 000 : Nearest
+-- 001 : Bilinear
+-- 010 : Sharp Bilinear
+-- 011 : Bicubic
+-- 100 : Polyphase
+-- 101 : TBD
+-- 110 : TBD
+-- 111 : TEST
+
+-- MODE[3]
+-- 0 : Direct. Single framebuffer.
+-- 1 : Triple buffering
+
+-- MODE[4] : TBD
+
+-- MASK      : Enable / Disable selected interpoler
+--             0:Nearest 1:Bilinear 2:SharpBilinear 3:Bicubic 4:Polyphase
+-- RAMBASE   : RAM base address for framebuffer
+-- RAMSIZE   : RAM allocated for one framebuffer (needs x3 if triple-buffering)
+--             Must be a power of two
+-- INTER     : True=Autodetect interlaced video False=Force progressive scan
+-- HEADER    : True=Add image properties header
+-- DOWNSCALE : True=Support downscaling False=Downscaling disabled
+-- BYTESWAP  : Little/Big endian byte swap
+-- FRAC      : Fractional bits, subpixel resolution
+-- FORMAT    : TBD <TODO>
+-- OHRES     : Max. output horizontal resolution. Must be a power of two.
+--             (Used for sizing line buffers)
+-- IHRES     : Max. input horizontal resolution. Must be a power of two.
+--             (Used for sizing line buffers)
+-- N_DW      : Avalon data bus width. 64 or 128 bits
+-- N_AW      : Avalon address bus width
+-- N_BURST   : Burst size in bytes. Power of two.
+
+ENTITY ascal IS
+  GENERIC (
+    MASK      : unsigned(7 DOWNTO 0) :=x"FF";
+    RAMBASE   : unsigned(31 DOWNTO 0);
+    RAMSIZE   : unsigned(31 DOWNTO 0) := x"0080_0000"; -- =8MB
+    INTER     : boolean := true;
+    HEADER    : boolean := true;
+    DOWNSCALE : boolean := true;
+    BYTESWAP  : boolean := true;
+    FRAC      : natural RANGE 4 TO 6 :=4;
+    FORMAT    : natural RANGE 1 TO 8 :=1;
+    OHRES     : natural RANGE 1 TO 4096 :=2048;
+    IHRES     : natural RANGE 1 TO 2048 :=2048;
+    N_DW      : natural RANGE 64 TO 128 := 128;
+    N_AW      : natural RANGE 8 TO 32 := 32;
+    N_BURST   : natural := 256 -- 256 bytes per burst
+    );
+  PORT (
+    ------------------------------------
+    -- Input video
+    i_r   : IN  unsigned(7 DOWNTO 0);
+    i_g   : IN  unsigned(7 DOWNTO 0);
+    i_b   : IN  unsigned(7 DOWNTO 0);
+    i_hs  : IN  std_logic; -- H sync
+    i_vs  : IN  std_logic; -- V sync
+    i_fl  : IN  std_logic; -- Interlaced field
+    i_de  : IN  std_logic; -- Display Enable
+    i_ce  : IN  std_logic; -- Clock Enable
+    i_clk : IN  std_logic; -- Input clock
+    
+    ------------------------------------
+    -- Output video
+    o_r   : OUT unsigned(7 DOWNTO 0);
+    o_g   : OUT unsigned(7 DOWNTO 0);
+    o_b   : OUT unsigned(7 DOWNTO 0);
+    o_hs  : OUT std_logic; -- H sync
+    o_vs  : OUT std_logic; -- V sync
+    o_de  : OUT std_logic; -- Display Enable
+    o_ce  : IN  std_logic; -- Clock Enable
+    o_clk : IN  std_logic; -- Output clock
+
+    ------------------------------------
+    -- Low lag PLL tuning
+    o_lltune : OUT unsigned(15 DOWNTO 0);
+    
+    ------------------------------------
+    -- Input video parameters
+    iauto : IN std_logic; -- 1=Autodetect image size 0=Choose window
+    himin : IN natural RANGE 0 TO 4095; -- MIN < MAX, MIN >=0, MAX < DISP
+    himax : IN natural RANGE 0 TO 4095;
+    vimin : IN natural RANGE 0 TO 4095;
+    vimax : IN natural RANGE 0 TO 4095;
+    
+    -- Output video parameters
+    run    : IN std_logic; -- 1=Enable output image. 0=No image
+    freeze : IN std_logic; -- 1=Disable framebuffer writes
+    mode   : IN unsigned(4 DOWNTO 0);
+    -- SYNC  |________________________/"""""""""\______|
+    -- DE    |""""""""""""""""""\______________________|
+    -- RGB   |    <#IMAGE#>     ^HDISP                 |
+    --            ^HMIN   ^HMAX       ^HSSTART  ^HSEND ^HTOTAL
+    htotal  : IN natural RANGE 0 TO 4095;
+    hsstart : IN natural RANGE 0 TO 4095;
+    hsend   : IN natural RANGE 0 TO 4095;
+    hdisp   : IN natural RANGE 0 TO 4095;
+    hmin    : IN natural RANGE 0 TO 4095;
+    hmax    : IN natural RANGE 0 TO 4095; -- 0 <= hmin < hmax < hdisp
+    vtotal  : IN natural RANGE 0 TO 4095;
+    vsstart : IN natural RANGE 0 TO 4095;
+    vsend   : IN natural RANGE 0 TO 4095;
+    vdisp   : IN natural RANGE 0 TO 4095;
+    vmin    : IN natural RANGE 0 TO 4095;
+    vmax    : IN natural RANGE 0 TO 4095; -- 0 <= vmin < vmax < vdisp
+    
+    ------------------------------------
+    -- Polyphase filter coefficients
+    -- Order :
+    --   [Horizontal] [Vertical]
+    --   [0]...[2**FRAC-1]
+    --   [-1][0][1][2]
+    poly_clk : IN std_logic;
+    poly_dw  : IN unsigned(8 DOWNTO 0);
+    poly_a   : IN unsigned(FRAC+2 DOWNTO 0);
+    poly_wr  : IN std_logic;
+    
+    ------------------------------------
+    -- Avalon
+    avl_clk            : IN    std_logic; -- Avalon clock
+    avl_waitrequest    : IN    std_logic;
+    avl_readdata       : IN    std_logic_vector(N_DW-1 DOWNTO 0);
+    avl_readdatavalid  : IN    std_logic;
+    avl_burstcount     : OUT   std_logic_vector(7 DOWNTO 0);
+    avl_writedata      : OUT   std_logic_vector(N_DW-1 DOWNTO 0);
+    avl_address        : OUT   std_logic_vector(N_AW-1 DOWNTO 0);
+    avl_write          : OUT   std_logic;
+    avl_read           : OUT   std_logic;
+    avl_byteenable     : OUT   std_logic_vector(N_DW/8-1 DOWNTO 0);
+
+    ------------------------------------
+    reset_na           : IN    std_logic
+    );
+
+BEGIN
+  ASSERT N_DW=64 OR N_DW=128 REPORT "DW" SEVERITY failure;
+  
+END ENTITY ascal;
+
+--##############################################################################
+
+ARCHITECTURE rtl OF ascal IS
+  
+  CONSTANT MASK_NEAREST        : natural :=0;
+  CONSTANT MASK_BILINEAR       : natural :=1;
+  CONSTANT MASK_SHARP_BILINEAR : natural :=2;
+  CONSTANT MASK_BICUBIC        : natural :=3;
+  CONSTANT MASK_POLY           : natural :=4;
+  
+  ----------------------------------------------------------
+  FUNCTION ilog2 (CONSTANT v : natural) RETURN natural IS
+    VARIABLE r : natural := 1;
+    VARIABLE n : natural := 0;
+  BEGIN
+    WHILE v>r LOOP
+      n:=n+1;
+      r:=r*2;
+    END LOOP;
+    RETURN n;
+  END FUNCTION ilog2;
+  FUNCTION to_std_logic (a : boolean) RETURN std_logic IS
+  BEGIN
+    IF a THEN RETURN '1';
+         ELSE RETURN '0';
+    END IF;
+  END FUNCTION to_std_logic;
+  
+  ----------------------------------------------------------
+  CONSTANT NB_BURST : natural :=ilog2(N_BURST);
+  CONSTANT NB_LA : natural :=ilog2(N_DW/8); -- Low address bits
+  CONSTANT BLEN : natural :=N_BURST / N_DW * 8; -- Burst length
+  CONSTANT NP : natural :=24;
+
+  ----------------------------------------------------------
+  TYPE arr_dw IS  ARRAY (natural RANGE <>) OF unsigned(N_DW-1 DOWNTO 0);
+  
+  TYPE type_pix IS RECORD
+    r,g,b : unsigned(7 DOWNTO 0); -- 0.8
+  END RECORD;
+  TYPE arr_pix IS ARRAY (natural RANGE <>) OF type_pix;
+  ATTRIBUTE ramstyle : string;
+  
+  SUBTYPE uint12 IS natural RANGE 0 TO 4095;
+  SUBTYPE uint13 IS natural RANGE 0 TO 8191;
+  
+  ----------------------------------------------------------
+  -- Input image
+  SIGNAL i_pvs,i_pfl,i_pde,i_pce : std_logic;
+  SIGNAL i_ppix : type_pix;
+  SIGNAL i_freeze : std_logic;
+  SIGNAL i_count : unsigned(2 DOWNTO 0);
+  SIGNAL i_hsize,i_hmin,i_hmax,i_hcpt : uint12;
+  SIGNAL i_hrsize,i_vrsize : uint12;
+  SIGNAL i_himax,i_vimax : uint12;
+  SIGNAL i_vsize,i_vmaxmin,i_vmin,i_vmax,i_vcpt : uint12;
+  SIGNAL i_iauto : std_logic;
+  SIGNAL i_mode : unsigned(4 DOWNTO 0);
+  SIGNAL i_ven,i_sof : std_logic;
+  SIGNAL i_wr : std_logic;
+  SIGNAL i_divstart,i_divrun : std_logic;
+  SIGNAL i_de_pre,i_vs_pre,i_fl_pre : std_logic;
+  SIGNAL i_hs_delay : natural RANGE 0 TO 31;
+  SIGNAL i_intercnt : natural RANGE 0 TO 3;
+  SIGNAL i_inter,i_half,i_flm : std_logic;
+  SIGNAL i_write,i_walt,i_wline : std_logic;
+  SIGNAL i_push,i_pushend,i_pushend2,i_eol,i_eol2,i_eol3 : std_logic;
+  SIGNAL i_pushhead,i_pushhead2,i_pushhead3,i_hbfix : std_logic;
+  SIGNAL i_hburst,i_hbcpt : natural RANGE 0 TO 31;
+  SIGNAL i_shift : unsigned(0 TO 119) := (OTHERS =>'0');
+  SIGNAL i_head : unsigned(127 DOWNTO 0);
+  SIGNAL i_acpt : natural RANGE 0 TO 15;
+  SIGNAL i_dpram : arr_dw(0 TO BLEN*2-1);
+  ATTRIBUTE ramstyle OF i_dpram : SIGNAL IS "no_rw_check";
+  SIGNAL i_endframe0,i_endframe1,i_syncline : std_logic;
+  SIGNAL i_wad : natural RANGE  0 TO BLEN*2-1;
+  SIGNAL i_dw : unsigned(N_DW-1 DOWNTO 0);
+  SIGNAL i_adrs,i_adrsi : unsigned(31 DOWNTO 0); -- Avalon address
+  SIGNAL i_reset_na : std_logic;
+  SIGNAL i_hnp,i_vnp : std_logic;
+  SIGNAL i_line : arr_pix(0 TO IHRES-1); -- Downscale line buffer
+  ATTRIBUTE ramstyle OF i_line : SIGNAL IS "no_rw_check";
+  SIGNAL i_ohsize,i_ovsize : uint12;
+  SIGNAL i_vdivi   : unsigned(12 DOWNTO 0);
+  SIGNAL i_vdivr   : unsigned(24 DOWNTO 0);
+  SIGNAL i_div     : unsigned(16 DOWNTO 0);
+  SIGNAL i_dir     : unsigned(11 DOWNTO 0);
+  SIGNAL i_h_frac,i_v_frac : unsigned(11 DOWNTO 0);
+  SIGNAL i_hacc,i_vacc     : uint13;
+  SIGNAL i_hdown,i_vdown   : std_logic;
+  SIGNAL i_divcpt : natural RANGE 0 TO 36;
+  SIGNAL i_lwad,i_lrad : natural RANGE 0 TO OHRES-1;
+  SIGNAL i_lwr,i_bil : std_logic;
+  SIGNAL i_ldw,i_ldrm : type_pix;
+  SIGNAL i_hpixp,i_hpix0,i_hpix1,i_hpix2,i_hpix3,i_hpix4 : type_pix;
+  SIGNAL i_hpix,i_pix : type_pix;
+  SIGNAL i_hnp1,i_hnp2,i_hnp3,i_hnp4 : std_logic;
+  SIGNAL i_ven1,i_ven2,i_ven3,i_ven4,i_ven5,i_ven6,i_ven7 : std_logic;
+  
+  ----------------------------------------------------------
+  -- Avalon
+  TYPE type_avl_state IS (sIDLE,sWRITE,sREAD);
+  SIGNAL avl_state : type_avl_state;
+  SIGNAL avl_write_i,avl_write_sync,avl_write_sync2 : std_logic;
+  SIGNAL avl_read_i,avl_read_sync,avl_read_sync2 : std_logic;
+  SIGNAL avl_read_pulse,avl_write_pulse : std_logic;
+  SIGNAL avl_reading : std_logic;
+  SIGNAL avl_read_sr,avl_write_sr,avl_read_clr,avl_write_clr : std_logic;
+  SIGNAL avl_rad,avl_rad_c,avl_wad : natural RANGE 0 TO 2*BLEN-1;
+  SIGNAL avl_walt,avl_wline,avl_rline : std_logic;
+  SIGNAL avl_dw,avl_dr : unsigned(N_DW-1 DOWNTO 0);
+  SIGNAL avl_wr : std_logic;
+  SIGNAL avl_readack : std_logic;
+  SIGNAL avl_radrs,avl_wadrs : unsigned(31 DOWNTO 0);
+  SIGNAL avl_rbib : std_logic;
+  SIGNAL avl_i_offset0,avl_o_offset0 : unsigned(31 DOWNTO 0);
+  SIGNAL avl_i_offset1,avl_o_offset1 : unsigned(31 DOWNTO 0);
+  SIGNAL avl_reset_na : std_logic;
+  SIGNAL avl_o_vs_sync,avl_o_vs : std_logic;
+  
+  FUNCTION buf_next(a,b : natural RANGE 0 TO 2) RETURN natural IS
+  BEGIN
+    IF (a=0 AND b=1) OR (a=1 AND b=0) THEN RETURN 2; END IF;
+    IF (a=1 AND b=2) OR (a=2 AND b=1) THEN RETURN 0; END IF;
+    RETURN 1;                              
+  END FUNCTION;
+  FUNCTION buf_offset(b : natural RANGE 0 TO 2) RETURN unsigned IS
+  BEGIN
+    IF b=1 THEN RETURN RAMSIZE; END IF;
+    IF b=2 THEN RETURN RAMSIZE(30 DOWNTO 0) & '0'; END IF;
+    RETURN x"00000000"; 
+  END FUNCTION;
+  
+  ----------------------------------------------------------
+  -- Output
+  SIGNAL o_run : std_logic;
+  SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0);
+  SIGNAL o_htotal,o_hsstart,o_hsend : uint12;
+  SIGNAL o_hmin,o_hmax,o_hdisp : uint12;
+  SIGNAL o_hsize,o_vsize : uint12;
+  SIGNAL o_vtotal,o_vsstart,o_vsend : uint12;
+  SIGNAL o_vmin,o_vmax,o_vdisp : uint12;
+  SIGNAL o_divcpt : natural RANGE 0 TO 36;
+  SIGNAL o_iendframe0,o_iendframe02,o_iendframe1,o_iendframe12 : std_logic;
+  SIGNAL o_bufup0,o_bufup1,o_inter : std_logic;
+  SIGNAL o_ibuf0,o_ibuf1,o_obuf0,o_obuf1 : natural RANGE 0 TO 2;
+  TYPE type_o_state IS (sDISP,sHSYNC,sREAD,sWAITREAD);
+  SIGNAL o_state : type_o_state;
+  SIGNAL o_copy,o_readack,o_readack_sync,o_readack_sync2 : std_logic;
+  SIGNAL o_copyv : unsigned(0 TO 7);
+  SIGNAL o_adrs : unsigned(31 DOWNTO 0); -- Avalon address
+  SIGNAL o_adrs_pre : natural RANGE 0 TO 32*4096-1;
+  SIGNAL o_adrsa,o_rline : std_logic;
+  SIGNAL o_ad,o_ad1,o_ad2,o_ad3 : natural RANGE 0 TO 2*BLEN-1;
+  SIGNAL o_adturn : std_logic;
+  SIGNAL o_dr : unsigned(N_DW-1 DOWNTO 0);
+  SIGNAL o_shift : unsigned(0 TO N_DW+15);
+  SIGNAL o_sh,o_sh1,o_sh2,o_sh3 : std_logic;
+  SIGNAL o_reset_na : std_logic;
+  SIGNAL o_dpram : arr_dw(0 TO BLEN*2-1);
+  ATTRIBUTE ramstyle OF o_dpram : SIGNAL IS "no_rw_check";
+  SIGNAL o_line0,o_line1,o_line2,o_line3 : arr_pix(0 TO OHRES-1);
+  ATTRIBUTE ramstyle OF o_line0 : SIGNAL IS "no_rw_check";
+  ATTRIBUTE ramstyle OF o_line1 : SIGNAL IS "no_rw_check";
+  ATTRIBUTE ramstyle OF o_line2 : SIGNAL IS "no_rw_check";
+  ATTRIBUTE ramstyle OF o_line3 : SIGNAL IS "no_rw_check";
+  SIGNAL o_wadl,o_radl : natural RANGE 0 TO OHRES-1;
+  SIGNAL o_ldw,o_ldr0,o_ldr1,o_ldr2,o_ldr3 : type_pix;
+  SIGNAL o_wr : unsigned(3 DOWNTO 0);
+  SIGNAL o_hcpt,o_vcpt,o_vcpt_pre,o_vcpt_pre2,o_vcpt_pre3 : uint12;
+  SIGNAL o_ihsize,o_ivsize : uint12;
+  
+  SIGNAL o_vfrac,o_hfrac,o_hfrac1,o_hfrac2,o_hfrac3 : unsigned(11 DOWNTO 0);
+  SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1;
+  SIGNAL o_hsv,o_vsv,o_dev,o_pev : unsigned(0 TO 5);
+  SIGNAL o_hsp,o_vss : std_logic;
+  SIGNAL o_read,o_read_pre : std_logic;
+  SIGNAL o_readlev,o_copylev : natural RANGE 0 TO 2;
+  SIGNAL o_hburst,o_hbcpt : natural RANGE 0 TO 31;
+  SIGNAL o_fload : natural RANGE 0 TO 3;
+  SIGNAL o_acpt,o_acpt1,o_acpt2,o_acpt3,o_acpt4 : natural RANGE 0 TO 15; -- Alternance pixels FIFO
+  SIGNAL o_dshi : natural RANGE 0 TO 3;
+  SIGNAL o_first,o_last,o_last1,o_last2,o_last3 : std_logic;
+  SIGNAL o_lastt1,o_lastt2,o_lastt3 : std_logic;
+  SIGNAL o_alt : unsigned(3 DOWNTO 0);
+  SIGNAL o_hdown,o_vdown : std_logic;
+  SIGNAL o_primv,o_lastv,o_bibv : unsigned(0 TO 2);
+  SIGNAL o_bibu,o_bib : std_logic :='0';
+  SIGNAL o_dcpt,o_dcpt1,o_dcpt2,o_dcpt3,o_dcpt4,o_dcpt5,o_dcpt6,o_dcpt7 : uint12;
+  SIGNAL o_hpix0,o_hpix1,o_hpix2,o_hpix3 : type_pix;
+  SIGNAL o_hpixq,o_vpixq,o_vpixq1 : arr_pix(0 TO 3);
+  
+  SIGNAL o_vpe : std_logic;
+  SIGNAL o_div,o_div2 : unsigned(18 DOWNTO 0); --uint12;
+  SIGNAL o_dir,o_dir2 : unsigned(11 DOWNTO 0);
+  SIGNAL o_vdivi : unsigned(12 DOWNTO 0);
+  SIGNAL o_vdivr : unsigned(24 DOWNTO 0);
+  SIGNAL o_divstart : std_logic;
+  SIGNAL o_divrun : std_logic;
+  SIGNAL o_hacpt,o_vacpt : unsigned(11 DOWNTO 0);
+  
+  -----------------------------------------------------------------------------
+  -- ACPT 012345678901234---  128bits DATA
+  --  0   ...............RGB
+  --  1   ............RGBrgb
+  --  2   .........RGBrgbRGB
+  --  3   ......RGBrgbRGBrgb
+  --  4   ...RGBrgbRGBrgbRGB
+  --  5   RGBrgbRGBrgbRGBrgb => PUSH RGBrgbRGBrgbRGBr
+  --  6   .............gbRGB
+  --  7   ..........gbRGBrgb
+  --  8   .......gbRGBrgbRGB
+  --  9   ....gbRGBrgbRGBrgb
+  -- 10   .gbRGBrgbRGBrgbRGB => PUSH gbRGBrgbRGBrgbRG
+  -- 11   ..............Brgb
+  -- 12   ...........BrgbRGB
+  -- 13   ........BrgbRGBrgb
+  -- 14   .....BrgbRGBrgbRGB
+  -- 15   ..BrgbRGBrgbRGBrgb => PUSH BrgbRGBrgbRGBrgb
+  
+  -- ACPT 012345678901234---  64bits DATA
+  --  0   ...............RGB
+  --  1   ............RGBrgb
+  --  2   .........RGBrgbRGB => PUSH RGBrgbRG
+  --  3   ..............Brgb
+  --  4   ...........BrgbRGB
+  --  5   ........BrgbRGBrgb => PUSH BrgbRGBr
+  --  6   .............gbRGB
+  --- 7   ..........gbRGBrgb => PUSH gbRGBrgb
+  
+  FUNCTION shift24_ipack(i_dw : unsigned(N_DW-1 DOWNTO 0);
+                         acpt : natural RANGE 0 TO 15;
+                         shift : unsigned(0 TO 119);
+                         pix : type_pix) RETURN unsigned IS
+    VARIABLE dw : unsigned(N_DW-1 DOWNTO 0);
+  BEGIN
+    IF N_DW=128 THEN
+      IF    acpt=5 THEN   dw:=shift(0 TO 119) & pix.r;
+      ELSIF acpt=10 THEN  dw:=shift(8 TO 119) & pix.r & pix.g;
+      ELSIF acpt=15 THEN  dw:=shift(16 TO 119) & pix.r & pix.g & pix.b;
+      ELSE                dw:=i_dw;
+      END IF;
+    ELSE -- N_DW=64
+      IF    (acpt MOD 8)=2 THEN  dw:=shift(72 TO 119) & pix.r & pix.g;
+      ELSIF (acpt MOD 8)=5 THEN  dw:=shift(64 TO 119) & pix.r;
+      ELSIF (acpt MOD 8)=7 THEN  dw:=shift(80 TO 119) & pix.r & pix.g & pix.b;
+      ELSE                       dw:=i_dw;
+      END IF;
+    END IF;
+    RETURN dw;
+  END FUNCTION;
+  
+  FUNCTION shift24_inext (acpt : natural RANGE 0 TO 15) RETURN boolean IS
+  BEGIN
+    IF N_DW=128 THEN
+      RETURN (acpt=5 OR acpt=10 OR acpt=15);
+    ELSE -- N_DW=64
+      RETURN ((acpt MOD 8)=2 OR (acpt MOD 8)=5 OR (acpt MOD 8)=7);
+    END IF;
+  END FUNCTION;
+  
+  ----------------------
+  -- ACPT 0123456789012345   128bits DATA
+  --  0  >RGBrgbRGBrgbRGBr
+  --  1   rgbRGBrgbRGBr
+  --  2   RGBrgbRGBr
+  --  3   rgbRGBr
+  --  4   RGBr
+  --  5  >r gbRGBrgbRGBrgbRG
+  --  6   RGBrgbRGBrgbRG
+  --  7   rgbRGBrgbRG
+  --  8   RGBrgbRG
+  --  9   rgbRG
+  --  10 >RG BrgbRGBrgbRGBrgb
+  --  11  rgbRGBrgbRGBrgb
+  --  12  RGBrgbRGBrgb
+  --  13  rgbRGBrgb
+  --  14  RGBrgb
+  --  15  rgb
+
+  -- ACPT 01234567   64bits DATA
+  --  0  >RGBrgbRG
+  --  1   rgbRG
+  --  2  >RG BrgbRGBr
+  --  3   rgbRGBr
+  --  4   RGBr
+  --  5  >r gbRGBrgb
+  --  6   RGBrgb
+  --  7   rgb
+  
+  FUNCTION shift24_opack(acpt : natural RANGE 0 TO 15;
+                         shift : unsigned(0 TO N_DW+15);
+                         dr : unsigned(N_DW-1 DOWNTO 0)) RETURN unsigned IS
+    VARIABLE shift_v : unsigned(0 TO N_DW+15);
+  BEGIN
+    IF N_DW=128 THEN
+      IF acpt=0 THEN
+        shift_v:=dr & dr(15 DOWNTO 0);
+      ELSIF acpt=5 THEN
+        shift_v:=shift(24 TO 31) & dr & dr(7 DOWNTO 0);
+      ELSIF acpt=10 THEN
+        shift_v:=shift(24 TO 39) & dr;
+      ELSE
+        shift_v:=shift(24 TO N_DW+15) & dr(23 DOWNTO 0);
+      END IF;
+    ELSE -- N_DW=64
+      IF (acpt MOD 8)=0 THEN
+        shift_v:=dr & dr(15 DOWNTO 0);
+      ELSIF (acpt MOD 8)=2 THEN
+        shift_v:=shift(24 TO 39) & dr;
+      ELSIF (acpt MOD 8)=5 THEN
+        shift_v:=shift(24 TO 31) & dr & dr(7 DOWNTO 0);
+      ELSE
+        shift_v:=shift(24 TO N_DW+15) & dr(23 DOWNTO 0);
+      END IF;
+    END IF;
+    RETURN shift_v;
+  END FUNCTION;
+  
+  FUNCTION shift24_onext (acpt : natural RANGE 0 TO 15) RETURN boolean IS
+  BEGIN
+    IF N_DW=128 THEN
+      RETURN (acpt=0 OR acpt=5 OR acpt=10);
+    ELSE -- N_DW=64
+      RETURN ((acpt MOD 8)=0 OR (acpt MOD 8)=2 OR (acpt MOD 8)=5);
+    END IF;
+  END FUNCTION;
+
+  FUNCTION swap(d : unsigned(N_DW-1 DOWNTO 0)) RETURN unsigned IS
+    VARIABLE e : unsigned(N_DW-1 DOWNTO 0);
+  BEGIN
+    IF BYTESWAP THEN
+      FOR i IN 0 TO N_DW/8-1 LOOP
+        e(i*8+7 DOWNTO i*8):=d(N_DW-i*8-1 DOWNTO N_DW-i*8-8);
+      END LOOP;
+      RETURN e;
+    ELSE
+      RETURN d;
+    END IF;
+  END FUNCTION swap;
+  
+  -----------------------------------------------------------------------------
+  FUNCTION altx (a : unsigned(1 DOWNTO 0)) RETURN unsigned IS
+  BEGIN
+    CASE a IS
+      WHEN "00"   => RETURN "0001";
+      WHEN "01"   => RETURN "0010";
+      WHEN "10"   => RETURN "0100";
+      WHEN OTHERS => RETURN "1000";
+    END CASE;
+  END FUNCTION;
+  
+  -----------------------------------------------------------------------------
+  FUNCTION bound(a : unsigned;
+                 s : natural) RETURN unsigned IS
+  BEGIN
+    IF a(a'left)='1' THEN
+      RETURN x"00";
+    ELSIF a(a'left DOWNTO s)/=0 THEN
+      RETURN x"FF";
+    ELSE
+      RETURN a(s-1 DOWNTO s-8);
+    END IF;
+  END FUNCTION bound;
+  
+  -----------------------------------------------------------------------------
+  -- Nearest
+  FUNCTION near_frac(f : unsigned) RETURN unsigned IS
+    VARIABLE x : unsigned(FRAC-1 DOWNTO 0);
+  BEGIN
+    x:=(OTHERS =>f(f'left));
+    RETURN x;
+  END FUNCTION;
+  
+  SIGNAL o_h_frac2,o_v_frac : unsigned(FRAC-1 DOWNTO 0);
+  SIGNAL o_h_bil_pix,o_v_bil_pix : type_pix;
+  
+  -----------------------------------------------------------------------------
+  -- Nearest + Bilinear + Sharp Bilinear
+  FUNCTION bil_frac(f : unsigned) RETURN unsigned IS
+  BEGIN
+    RETURN f(f'left DOWNTO f'left+1-FRAC);
+  END FUNCTION;
+  
+  TYPE type_bil_t IS RECORD
+    r,g,b : unsigned(8+FRAC DOWNTO 0);
+  END RECORD;
+  FUNCTION bil_calc(f : unsigned(FRAC-1 DOWNTO 0);
+                    p : arr_pix(0 TO 3)) RETURN type_bil_t IS
+    VARIABLE fp,fn : unsigned(FRAC DOWNTO 0);
+    VARIABLE u : unsigned(8+FRAC DOWNTO 0);
+    VARIABLE x : type_bil_t;
+    CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0');
+  BEGIN
+    fp:='0' & f;
+    fn:=('1' & Z) - fp;
+    u:=p(2).r * fp + p(1).r * fn;
+    x.r:=u;
+    u:=p(2).g * fp + p(1).g * fn;
+    x.g:=u;
+    u:=p(2).b * fp + p(1).b * fn;
+    x.b:=u;
+    RETURN x;
+  END FUNCTION;
+  SIGNAL o_h_bil_t,o_v_bil_t : type_bil_t;
+  SIGNAL i_h_bil_t : type_bil_t;
+  
+  -----------------------------------------------------------------------------
+  -- Sharp Bilinear
+  --  <0.5 : x*x*x*4
+  --  >0.5 : 1 - (1-x)*(1-x)*(1-x)*4
+  
+  TYPE type_sbil_tt IS RECORD
+    f : unsigned(FRAC-1 DOWNTO 0);
+    s : unsigned(FRAC-1 DOWNTO 0);
+  END RECORD;
+  
+  SIGNAL o_h_sbil_t,o_v_sbil_t : type_sbil_tt;
+  
+  FUNCTION sbil_frac1(f : unsigned(11 DOWNTO 0)) RETURN type_sbil_tt IS
+    VARIABLE u : unsigned(FRAC-1 DOWNTO 0);
+    VARIABLE v : unsigned(2*FRAC-1 DOWNTO 0);
+    VARIABLE x : type_sbil_tt;
+  BEGIN
+    IF f(11)='0' THEN
+      u:=f(11 DOWNTO 12-FRAC);
+    ELSE
+      u:=NOT f(11 DOWNTO 12-FRAC);
+    END IF;
+    v:=u*u;
+    x.f:=u;
+    x.s:=v(2*FRAC-2 DOWNTO FRAC-1);
+    RETURN x;  
+  END FUNCTION;
+  
+  FUNCTION sbil_frac2(f : unsigned(11 DOWNTO 0);
+                      t : type_sbil_tt) RETURN unsigned IS
+    VARIABLE v : unsigned(2*FRAC-1 DOWNTO 0);
+  BEGIN
+    v:=t.f*t.s;
+    IF f(11)='0' THEN
+      RETURN v(2*FRAC-2 DOWNTO FRAC-1);
+    ELSE
+      RETURN NOT v(2*FRAC-2 DOWNTO FRAC-1);
+    END IF;
+  END FUNCTION;
+  
+  -----------------------------------------------------------------------------
+  -- Bicubic
+  TYPE type_bic_abcd IS RECORD
+    a  : unsigned(7 DOWNTO 0);  --  0.8
+    b  : signed(8 DOWNTO 0);  --  0.9
+    c  : signed(11 DOWNTO 0); -- 3.9
+    d  : signed(10 DOWNTO 0); -- 2.9
+    xx : signed(8 DOWNTO 0); -- X.X 1.8
+  END RECORD;
+  TYPE type_bic_pix_abcd IS RECORD
+    r,g,b : type_bic_abcd;
+  END RECORD;
+  TYPE type_bic_tt1 IS RECORD -- Intermediate result
+    r_bx,g_bx,b_bx    : signed(8 DOWNTO 0);  -- B.X 1.8
+    r_cxx,g_cxx,b_cxx : signed(11 DOWNTO 0); -- C.XX 3.9
+    r_dxx,g_dxx,b_dxx : signed(10 DOWNTO 0); -- D.XX 2.9
+  END RECORD;
+  TYPE type_bic_tt2 IS RECORD -- Intermediate result
+    r_abxcxx,g_abxcxx,b_abxcxx : signed(9 DOWNTO 0); --  A + B.X + C.XX 2.8
+    r_dxxx,g_dxxx,b_dxxx : signed(9 DOWNTO 0); -- D.X.X.X 2.8
+  END RECORD;
+  
+  ----------------------------------------------------------
+  -- Y = A + B.X + C.X.X + D.X.X.X = A + X.(B + X.(C + X.D))
+  -- A = Y(0)                                       0 .. 1    unsigned
+  -- B = Y(1)/2 - Y(-1)/2                        -1/2 .. +1/2 signed
+  -- C = Y(-1) - 5*Y(0)/2 + 2*Y(1) - Y(2)/2        -3 .. +3   signed
+  -- D = -Y(-1)/2 + 3*Y(0)/2 - 3*Y(1)/2 + Y(2)/2   -2 .. +2   signed
+  
+  FUNCTION bic_calc0(f : unsigned(11 DOWNTO 0);
+                    pm,p0,p1,p2 : unsigned(7 DOWNTO 0)) RETURN type_bic_abcd IS
+    VARIABLE xx : signed(2*FRAC+1 DOWNTO 0); -- 2.(2*FRAC)
+  BEGIN
+    xx := signed('0' & f(11 DOWNTO 12-FRAC)) *
+          signed('0' & f(11 DOWNTO 12-FRAC)); -- 2.(2*FRAC)
+    RETURN type_bic_abcd'(
+      a=>p0,-- 0.8
+      b=>signed(('0' & p1) - ('0' & pm)), -- 0.9
+      c=>signed(("000" & pm & '0') - ("00" & p0 & "00") - ("0000" & p0) +
+                ("00" & p1 & "00") - ("0000" & p2)), -- 3.9
+      d=>signed(("00" & p0 & '0') - ("00" & p1 & '0') - ("000" & p1) +
+                ("000" & p0) + ("000" & p2) - ("000" & pm)), -- 2.9
+      xx=>xx(2*FRAC DOWNTO 2*FRAC-8)); -- 1.8
+  END FUNCTION;
+  FUNCTION bic_calc0(f : unsigned(11 DOWNTO 0);
+                     p : arr_pix(0 TO 3)) RETURN type_bic_pix_abcd IS
+  BEGIN
+    RETURN type_bic_pix_abcd'(r=>bic_calc0(f,p(0).r,p(1).r,p(2).r,p(3).r),
+                              g=>bic_calc0(f,p(0).g,p(1).g,p(2).g,p(3).g),
+                              b=>bic_calc0(f,p(0).b,p(1).b,p(2).b,p(3).b));
+  END FUNCTION;
+  
+  ----------------------------------------------------------
+  -- Calc : B.X, C.XX, D.XX
+  FUNCTION bic_calc1(f    : unsigned(11 DOWNTO 0);
+                     abcd : type_bic_pix_abcd) RETURN type_bic_tt1 IS
+    VARIABLE t : type_bic_tt1;
+    VARIABLE bx : signed(9+FRAC DOWNTO 0); -- 1.(FRAC+9)
+    VARIABLE cxx : signed(20 DOWNTO 0); -- 4.17
+    VARIABLE dxx : signed(19 DOWNTO 0); -- 3.17
+  BEGIN
+    bx := abcd.r.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9)
+    t.r_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8
+    cxx:= abcd.r.c * abcd.r.xx; -- 3.9 * 1.8 = 4.17
+    t.r_cxx:=cxx(19 DOWNTO 8); -- 3.9
+    dxx:= abcd.r.d * abcd.r.xx; -- 2.9 * 1.8 = 3.17
+    t.r_dxx:=dxx(18 DOWNTO 8); -- 2.9
+    bx := abcd.g.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9)
+    t.g_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8
+    cxx:= abcd.g.c * abcd.g.xx; -- 3.9 * 1.8 = 4.17
+    t.g_cxx:=cxx(19 DOWNTO 8); -- 3.9
+    dxx:= abcd.g.d * abcd.g.xx; -- 2.9 * 1.8 = 3.17
+    t.g_dxx:=dxx(18 DOWNTO 8); -- 2.9
+    bx := abcd.b.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9)
+    t.b_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8
+    cxx:= abcd.b.c * abcd.b.xx; -- 3.9 * 1.8 = 4.17
+    t.b_cxx:=cxx(19 DOWNTO 8); -- 3.9
+    dxx:= abcd.b.d * abcd.b.xx; -- 2.9 * 1.8 = 3.17
+    t.b_dxx:=dxx(18 DOWNTO 8); -- 2.9
+    RETURN t;
+  END FUNCTION;
+  
+  ----------------------------------------------------------
+  -- Calc A + BX + CXX , X.DXX
+  FUNCTION bic_calc2(f    : unsigned(11 DOWNTO 0);
+                     t    : type_bic_tt1;
+                     abcd : type_bic_pix_abcd) RETURN type_bic_tt2 IS
+    VARIABLE u : type_bic_tt2;
+    VARIABLE x : signed(11+FRAC DOWNTO 0); -- 3.(9+FRAC)
+  BEGIN
+    u.r_abxcxx:=(t.r_bx(8) & t.r_bx) + ("00" & signed(abcd.r.a)) + t.r_cxx(10 DOWNTO 1); -- 2.8
+    u.g_abxcxx:=(t.g_bx(8) & t.g_bx) + ("00" & signed(abcd.g.a)) + t.g_cxx(10 DOWNTO 1); -- 2.8
+    u.b_abxcxx:=(t.b_bx(8) & t.b_bx) + ("00" & signed(abcd.b.a)) + t.b_cxx(10 DOWNTO 1); -- 2.8
+
+    x:=t.r_dxx *  signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC)
+    u.r_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8
+    x:=t.g_dxx *  signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC)
+    u.g_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8
+    x:=t.b_dxx *  signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC)
+    u.b_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8
+    RETURN u;
+  END FUNCTION;
+  
+  ----------------------------------------------------------
+  -- Calc  (A + BX + CXX) + (DXXX)
+  FUNCTION bic_calc3(f    : unsigned(11 DOWNTO 0);
+                     t    : type_bic_tt2;
+                     abcd : type_bic_pix_abcd) RETURN type_pix IS
+    VARIABLE x : type_pix;
+    VARIABLE v : signed(9 DOWNTO 0); -- 2.8
+  BEGIN
+    v:=t.r_abxcxx + t.r_dxxx;
+    x.r:=bound(unsigned(v),8);
+    v:=t.g_abxcxx + t.g_dxxx;
+    x.g:=bound(unsigned(v),8);
+    v:=t.b_abxcxx + t.b_dxxx;
+    x.b:=bound(unsigned(v),8);
+    RETURN x;
+  END FUNCTION;
+  
+  -----------------------------------------------------------------------------
+  SIGNAL o_h_bic_pix,o_v_bic_pix : type_pix;
+  SIGNAL o_h_bic_abcd1,o_h_bic_abcd2 : type_bic_pix_abcd;
+  SIGNAL o_v_bic_abcd1,o_v_bic_abcd2 : type_bic_pix_abcd;
+  SIGNAL o_h_bic_tt1,o_v_bic_tt1 : type_bic_tt1;
+  SIGNAL o_h_bic_tt2,o_v_bic_tt2 : type_bic_tt2;
+  
+  -----------------------------------------------------------------------------
+  -- Polyphase
+  
+  TYPE arr_uv36 IS ARRAY (natural RANGE <>) OF unsigned(35 DOWNTO 0);
+  TYPE arr_int9 IS ARRAY (natural RANGE <>) OF integer RANGE -256 TO 255;
+  
+  CONSTANT POLY16 : arr_int9 := (
+  -24,-21,-15,-9,-5,-1,4,8,6,8,5,4,3,1,0,0,
+  176,174,169,160,150,131,115,85,58,27,4,-6,-20,-24,-26,-25,
+  -24,-25,-26,-24,-20,-6,4,27,58,85,115,131,150,160,169,174,
+   0,0,0,1,3,4,5,8,6,8,4,-1,-5,-9,-15,-21);
+  
+  CONSTANT POLY32 : arr_int9 := (
+    -24,-22,-20,-18,-16,-13,-11,-8,-6,-3,-1,0,2,3,5,5,6,6,6,5,5,4,4,3,2,1,1,0,0,0,0,0,
+    176,175,174,172,169,164,160,153,147,138,129,119,109,96,84,71,58,40,22,12,3,-4,-12,-16,-20,-22,-25,-25,-26,-25,-25,-25,
+    -24,-25,-26,-26,-26,-24,-23,-19,-16,-10,-4,4,11,22,32,45,58,77,96,108,119,129,140,147,154,159,165,168,172,173,175,175,
+    0,0,0,0,1,1,2,2,3,3,4,5,6,7,7,7,6,5,4,3,1,-1,-4,-6,-8,-10,-13,-15,-18,-20,-22,-22);
+  
+  FUNCTION init_poly RETURN arr_uv36 IS
+    VARIABLE m : arr_uv36(0 TO 2**FRAC-1) :=(OTHERS =>x"000000000");
+  BEGIN
+    IF FRAC=4 THEN
+      FOR i IN 0 TO 15 LOOP
+        m(i):=unsigned(to_signed(POLY16(i),9)    & to_signed(POLY16(i+16),9) &
+                       to_signed(POLY16(i+32),9) & to_signed(POLY16(i+48),9));
+      END LOOP;
+    ELSIF FRAC=5 THEN
+      FOR i IN 0 TO 31 LOOP
+        m(i):=unsigned(to_signed(POLY32(i),9)    & to_signed(POLY32(i+32),9) &
+                       to_signed(POLY32(i+64),9) & to_signed(POLY32(i+96),9));
+      END LOOP;
+    END IF;
+    RETURN m;
+  END FUNCTION;
+  
+  SIGNAL o_h_poly : arr_uv36(0 TO 2**FRAC-1):=init_poly;
+  SIGNAL o_v_poly : arr_uv36(0 TO 2**FRAC-1):=init_poly;
+  ATTRIBUTE ramstyle OF o_h_poly : SIGNAL IS "no_rw_check";
+  ATTRIBUTE ramstyle OF o_v_poly : SIGNAL IS "no_rw_check";
+  SIGNAL o_h_poly_a,o_v_poly_a : integer RANGE 0 TO 2**FRAC-1;
+  SIGNAL o_h_poly_dr,o_h_poly_dr2,o_v_poly_dr,o_v_poly_dr2 : unsigned(35 DOWNTO 0);
+  SIGNAL o_h_poly_pix,o_v_poly_pix : type_pix;
+  SIGNAL poly_h_wr,poly_v_wr : std_logic;
+  SIGNAL poly_tdw : unsigned(35 DOWNTO 0);
+  SIGNAL poly_a2 : unsigned(FRAC-1 DOWNTO 0);
+  
+  TYPE type_poly_t IS RECORD
+    r0,r1,b0,b1,g0,g1 : signed(17 DOWNTO 0);
+  END RECORD;
+  
+  SIGNAL o_h_poly_t,o_v_poly_t   : type_poly_t;
+  
+  FUNCTION poly_calc1(fi : unsigned(35 DOWNTO 0);
+                      p  : arr_pix(0 TO 3)) RETURN type_poly_t IS
+    VARIABLE t : type_poly_t;
+  BEGIN
+    -- 2.7 * 1.8 = 3.15 
+    t.r0:=(signed(fi(35 DOWNTO 27)) * signed('0' & p(0).r) +
+           signed(fi(26 DOWNTO 18)) * signed('0' & p(1).r));
+    t.r1:=(signed(fi(17 DOWNTO  9)) * signed('0' & p(2).r) +
+           signed(fi( 8 DOWNTO  0)) * signed('0' & p(3).r));
+    t.g0:=(signed(fi(35 DOWNTO 27)) * signed('0' & p(0).g) +
+           signed(fi(26 DOWNTO 18)) * signed('0' & p(1).g));
+    t.g1:=(signed(fi(17 DOWNTO  9)) * signed('0' & p(2).g) +
+           signed(fi( 8 DOWNTO  0)) * signed('0' & p(3).g));
+    t.b0:=(signed(fi(35 DOWNTO 27)) * signed('0' & p(0).b) +
+           signed(fi(26 DOWNTO 18)) * signed('0' & p(1).b));
+    t.b1:=(signed(fi(17 DOWNTO  9)) * signed('0' & p(2).b) +
+           signed(fi( 8 DOWNTO  0)) * signed('0' & p(3).b));
+    RETURN t;
+  END FUNCTION;
+  
+  FUNCTION poly_calc2(t : type_poly_t) RETURN type_pix IS
+    VARIABLE p : type_pix;
+  BEGIN
+    p.r:=bound(unsigned(t.r0+t.r1),15);
+    p.g:=bound(unsigned(t.g0+t.g1),15);
+    p.b:=bound(unsigned(t.b0+t.b1),15);
+    RETURN p;
+  END FUNCTION;
+  
+BEGIN
+  
+  -----------------------------------------------------------------------------
+  i_reset_na<='0'   WHEN reset_na='0' ELSE '1' WHEN rising_edge(i_clk);
+  o_reset_na<='0'   WHEN reset_na='0' ELSE '1' WHEN rising_edge(o_clk);
+  avl_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(avl_clk);
+  
+  -----------------------------------------------------------------------------
+  -- Input pixels FIFO and shreg
+  InAT:PROCESS(i_clk,i_reset_na) IS
+    CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0');
+    VARIABLE frac_v : unsigned(FRAC-1 DOWNTO 0);
+    VARIABLE div_v : unsigned(16 DOWNTO 0);
+    VARIABLE dir_v : unsigned(11 DOWNTO 0);
+    VARIABLE bil_t_v : type_bil_t;
+  BEGIN
+    IF i_reset_na='0' THEN
+      i_write<='0';
+      
+    ELSIF rising_edge(i_clk) THEN
+      i_push<='0';
+      i_eol<='0'; -- End Of Line
+      i_freeze <=freeze; -- <ASYNC>
+      i_iauto<=iauto; -- <ASYNC>
+      
+      ------------------------------------------------------
+      i_head(127 DOWNTO 120)<=x"01"; -- Header type
+      i_head(119 DOWNTO 112)<=x"01"; -- 24bits/pixels, packed RGB, big endian
+      i_head(111 DOWNTO 96)<="0000" & to_unsigned(N_BURST,12); -- Header size
+      i_head(95 DOWNTO 80)<=x"0000"; -- Attributes. TBD
+      i_head(80)<=i_inter;
+      i_head(81)<=i_flm;
+      i_head(82)<=i_hdown;
+      i_head(83)<=i_vdown;
+      i_head(84)<=i_mode(3);
+      i_head(87 DOWNTO 85)<=i_count;
+      i_head(79 DOWNTO 64)<="0000" & to_unsigned(i_hrsize,12); -- Image width
+      i_head(63 DOWNTO 48)<="0000" & to_unsigned(i_vrsize,12); -- Image height
+      i_head(47 DOWNTO 32)<=
+        to_unsigned(N_BURST * i_hburst,16); -- Line Length. Bytes
+      i_head(31 DOWNTO 16)<="0000" & to_unsigned(i_ohsize,12);
+      i_head(15 DOWNTO 0) <="0000" & to_unsigned(i_ovsize,12);
+      
+      ------------------------------------------------------
+      i_ppix<=(i_r,i_g,i_b);
+      i_pvs<=i_vs;
+      i_pfl<=i_fl;
+      i_pde<=i_de;
+      i_pce<=i_ce;
+      
+      ------------------------------------------------------
+      IF i_pce='1' THEN
+        ----------------------------------------------------
+        i_vs_pre<=i_pvs;
+        i_de_pre<=i_pde;
+        i_fl_pre<=i_pfl;
+        
+        ----------------------------------------------------
+        -- Detect interlaced video
+        IF NOT INTER THEN
+          i_intercnt<=0;
+        ELSIF i_pfl/=i_fl_pre THEN
+          i_intercnt<=3;
+        ELSIF i_pvs='1' AND i_vs_pre='0' AND i_intercnt>0 THEN
+          i_intercnt<=i_intercnt-1;
+        END IF;
+        i_inter<=to_std_logic(i_intercnt>0);
+        
+        ----------------------------------------------------
+        IF i_pvs='1' AND i_vs_pre='0' THEN
+          i_sof<='1';
+        END IF;
+        
+        IF i_pde='1' AND i_sof='1' THEN
+          i_sof<='0';
+          i_vcpt<=0;
+          IF i_inter='1' AND i_flm='1' AND i_half='0' AND INTER THEN
+            i_wline<='1';
+            i_adrsi<=to_unsigned(N_BURST * i_hburst,32) +
+                     to_unsigned(N_BURST * to_integer(
+                       unsigned'("00") & to_std_logic(HEADER)),32);
+          ELSE
+            i_wline<='0';
+            i_adrsi<=to_unsigned(N_BURST * to_integer(
+                       unsigned'("00") & to_std_logic(HEADER)),32);
+          END IF;
+        END IF;
+        
+        IF i_pde='1' THEN
+          i_flm<=NOT i_pfl;
+        END IF;
+        
+        i_ven<=to_std_logic(i_hcpt>=i_hmin AND i_hcpt<=i_hmax AND
+                            i_vcpt>=i_vmin AND i_vcpt<=i_vmax);
+        
+        -- Detects end of frame for triple buffering.
+        i_endframe0<=to_std_logic(i_vcpt=i_vmax + 1 AND
+                     (i_inter='0' OR i_flm='0'));
+        i_endframe1<=to_std_logic(i_vcpt=i_vmax + 1 AND
+                     (i_inter='0' OR i_flm='1'));
+        
+        -- Detects third line for low lag mode
+        i_syncline<=to_std_logic(i_vcpt=i_vmin + 4);
+        
+        ----------------------------------------------------
+        IF i_pde='1' AND i_de_pre='0' THEN
+          i_vimax<=i_vcpt;
+          i_hcpt<=0;
+        ELSE
+          i_hcpt<=(i_hcpt+1) MOD 4096;
+        END IF;
+        
+        IF i_pde='0' AND i_de_pre='1' THEN
+          i_himax<=i_hcpt;
+        END IF;
+        
+        IF i_iauto='1' THEN
+          -- Auto-size
+          i_hmin<=0;
+          i_hmax<=i_himax;
+          i_vmin<=0;
+          IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN
+            i_vmax<=i_vimax;
+          END IF;
+        ELSE
+          -- Forced image
+          i_hmin<=himin; -- <ASYNC>
+          i_hmax<=himax; -- <ASYNC>
+          i_vmin<=vimin; -- <ASYNC>
+          i_vmax<=vimax; -- <ASYNC>
+        END IF;
+        
+        ----------------------------------------------------
+        i_mode<=mode; -- <ASYNC>
+        
+        -- Downscaling : Nearest or bilinear
+        i_bil<=to_std_logic(i_mode(2 DOWNTO 0)/="000" AND DOWNSCALE);
+        
+        i_hdown<=to_std_logic(i_hsize>i_ohsize AND DOWNSCALE); --H downscale
+        i_vdown<=to_std_logic(i_vsize>i_ovsize AND DOWNSCALE); --V downscale
+        
+        ----------------------------------------------------
+        i_hsize  <=(4096+i_hmax-i_hmin+1) MOD 4096;
+        i_vmaxmin<=(4096+i_vmax-i_vmin+1) MOD 4096;
+                            
+        IF i_inter='0' THEN
+          -- Non interlaced
+          i_vsize<=i_vmaxmin;
+          i_half<='0';
+        ELSIF i_ovsize<2*i_vmaxmin THEN
+          -- Interlaced, but downscaling, use only half frames
+          i_vsize<=i_vmaxmin;
+          i_half<='1';
+        ELSE
+          -- Interlaced : Double image height
+          i_vsize<=2*i_vmaxmin;
+          i_half<='0';
+        END IF;
+        
+        i_ohsize<=o_hsize; -- <ASYNC>
+        i_ovsize<=o_vsize; -- <ASYNC>
+        
+        ----------------------------------------------------
+        -- Downscaling vertical
+        i_divstart<='0';
+        IF i_hs_delay=7 THEN
+          IF (i_vacc + 2*i_ovsize) < 2*i_vsize THEN
+            i_vacc<=(i_vacc + 2*i_ovsize) MOD 8192;
+            i_vnp<='0';
+          ELSE
+            i_vacc<=(i_vacc + 2*i_ovsize - 2*i_vsize + 8192) MOD 8192;
+            i_vnp<='1';
+          END IF;
+          i_divstart<='1';
+          
+          IF i_vcpt=i_vmin THEN
+           i_vacc<=(i_vsize - i_ovsize + 8192) MOD 8192;
+           i_vnp<='1'; -- <AVOIR>
+          END IF;
+        END IF;
+        
+        --IF i_vdown='0' THEN
+        --  i_vnp<='1';
+        --END IF;
+        
+        -- Downscaling horizontal
+        IF i_ven='1' THEN
+          IF i_hacc + 2*i_ohsize < 2*i_hsize THEN
+            i_hacc<=(i_hacc + 2*i_ohsize) MOD 8192;
+            i_hnp<='0'; -- Skip. pix.
+          ELSE
+            i_hacc<=(i_hacc + 2*i_ohsize - 2*i_hsize + 8192) MOD 8192;
+            i_hnp<='1';
+          END IF;
+        END IF;
+        IF i_hdown='0' THEN
+          i_hnp<='1';
+        END IF;
+        
+        ----------------------------------------------------
+        -- Downscaling interpolation
+        i_hpixp<=i_ppix;
+        i_hpix0<=i_hpixp;
+        i_hpix1<=i_hpix0;
+        i_hpix2<=i_hpix1;
+        i_hpix3<=i_hpix2;
+        i_hpix4<=i_hpix3;
+        
+        i_hnp1<=i_hnp; i_hnp2<=i_hnp1; i_hnp3<=i_hnp2; i_hnp4<=i_hnp3; 
+        i_ven1<=i_ven; i_ven2<=i_ven1; i_ven3<=i_ven2; i_ven4<=i_ven3;
+        i_ven5<=i_ven4; i_ven6<=i_ven5; i_ven7<=i_ven6;
+        
+        -- C1 : DIV 1. Pipelined 4 bits non-restoring divider
+        dir_v:=x"000";
+        div_v:=to_unsigned(i_hacc * 16,17);
+        
+        div_v:=div_v-to_unsigned(i_hsize*16,17);
+        dir_v(11):=NOT div_v(16);
+        IF div_v(16)='0' THEN
+          div_v:=div_v-to_unsigned(i_hsize*8,17);
+        ELSE
+          div_v:=div_v+to_unsigned(i_hsize*8,17);
+        END IF;
+        dir_v(10):=NOT div_v(16);
+        i_div<=div_v;
+        i_dir<=dir_v;
+        
+        -- C2 : DIV 2.
+        div_v:=i_div;
+        dir_v:=i_dir;
+        IF div_v(16)='0' THEN
+          div_v:=div_v-to_unsigned(i_hsize*4,17);
+        ELSE
+          div_v:=div_v+to_unsigned(i_hsize*4,17);
+        END IF;
+        dir_v(9):=NOT div_v(16);
+
+        IF div_v(16)='0' THEN
+          div_v:=div_v-to_unsigned(i_hsize*2,17);
+        ELSE
+          div_v:=div_v+to_unsigned(i_hsize*2,17);
+        END IF;
+        dir_v(8):=NOT div_v(16);
+        i_h_frac<=dir_v;
+        
+        -- C4 : Horizontal Bilinear
+        IF i_bil='0' THEN
+          frac_v:=near_frac(i_h_frac);
+        ELSE
+          frac_v:=bil_frac(i_h_frac);
+        END IF;
+        
+        i_h_bil_t<=bil_calc(frac_v,(i_hpix2,i_hpix2,i_hpix3,i_hpix3));
+        i_hpix.r<=bound(i_h_bil_t.r,8+FRAC);
+        i_hpix.g<=bound(i_h_bil_t.g,8+FRAC);
+        i_hpix.b<=bound(i_h_bil_t.b,8+FRAC);
+        
+        IF i_hdown='0' THEN
+          i_hpix<=i_hpix4;
+        END IF;
+        
+        -- C5 : Vertical Bilinear
+        IF i_bil='0' THEN
+          frac_v:=near_frac(i_v_frac(11 DOWNTO 0));
+        ELSE
+          frac_v:=bil_frac(i_v_frac(11 DOWNTO 0));
+        END IF;
+        
+        bil_t_v:=bil_calc(frac_v,(i_hpix,i_hpix,i_ldrm,i_ldrm));
+        i_pix.r<=bound(bil_t_v.r,8+FRAC);
+        i_pix.g<=bound(bil_t_v.g,8+FRAC);
+        i_pix.b<=bound(bil_t_v.b,8+FRAC);
+        
+        IF i_vdown='0' THEN
+          i_pix<=i_hpix;
+        END IF;
+        
+        ----------------------------------------------------
+        -- VNP : Vert. downscaling line enable
+        -- HNP : Horiz. downscaling pix. enable
+        -- VEN : Enable pixel within displayed window
+        
+        IF (i_hnp4='1' AND i_ven6='1') OR i_pushend='1' THEN
+          i_shift<=i_shift(24 TO 119) & i_pix.r & i_pix.g & i_pix.b;
+          i_dw<=shift24_ipack(i_dw,i_acpt,i_shift,i_pix);
+          
+          IF shift24_inext(i_acpt) AND i_vnp='1' THEN
+            i_push<='1';
+            i_pushend<='0';
+          END IF;
+          i_acpt<=(i_acpt+1) MOD 16;
+        END IF;
+        
+        IF i_pushhead='1' THEN
+          i_dw<=i_head;
+          i_pushhead2<='1';
+          i_pushhead<='0';
+          i_count<=i_count+1;
+        END IF;
+        
+        IF i_ven6='1' AND i_ven5='0' AND i_vnp='1' THEN
+          i_pushend<='1';
+        END IF;
+        i_pushend2<=i_pushend;
+        
+        IF ((i_ven7='1' AND i_ven6='0') OR i_pushend2='1')
+          AND i_pushend='0' THEN
+          -- EOL après fin PUSHEND.
+          -- - Soit il n'y a pas eu de pushend (à cause de VNP)
+          -- - Soit front descendant pushend
+          i_eol<='1';
+        END IF;
+
+        IF i_pde='0' AND i_de_pre='1' THEN
+          i_hs_delay<=0;
+        ELSIF i_hs_delay<18 THEN
+          i_hs_delay<=i_hs_delay+1;
+        END IF;
+        
+        IF i_hs_delay=7 THEN
+          i_lwad<=0;
+          i_lrad<=0;
+          i_vcpt<=i_vcpt+1;
+          i_hacc<=(i_hsize - i_ohsize + 8192) MOD 8192;
+        END IF;
+        IF i_hs_delay=17 THEN
+          i_acpt<=0;
+          i_wad<=2*BLEN-1;
+          i_hbcpt<=0; -- Bursts per line counter
+          IF i_vnp='1' AND i_hbcpt>0 AND i_hbfix='0' THEN
+            i_hburst<=i_hbcpt;
+            i_hbfix<='1';
+          END IF;
+        END IF;
+        
+        IF i_pvs='0' AND i_vs_pre='1' THEN
+          -- Push header
+          i_pushhead<=to_std_logic(HEADER);
+          i_hbfix<='0';
+        END IF;
+        
+      END IF; -- IF i_pce='1'
+      
+      ------------------------------------------------------
+      -- Push pixels to downscaling line buffer
+      i_lwr<=i_hnp4 AND i_ven5 AND i_pce;
+      IF i_lwr='1' THEN
+        i_lwad<=(i_lwad+1) MOD OHRES;
+      END IF;
+      i_ldw<=i_hpix;
+      
+      IF i_hnp3='1' AND i_ven4='1' AND i_pce='1' THEN
+        i_lrad<=(i_lrad+1) MOD OHRES;
+      END IF;
+      
+      ------------------------------------------------------
+      -- Push pixels to DPRAM
+      i_wr<='0';
+      
+      IF i_push='1' AND i_freeze='0' THEN
+        i_wr<='1';
+        i_wad<=(i_wad+1) MOD (BLEN*2);
+        IF (i_wad+1) MOD BLEN=BLEN-1 THEN
+          i_hbcpt<=(i_hbcpt+1) MOD 32;
+          i_write<=i_write XOR NOT i_freeze;
+          i_walt<=to_std_logic((i_wad+1)/BLEN /= 0);
+          i_adrs<=i_adrsi;
+          i_adrsi<=i_adrsi+N_BURST;
+        END IF;
+      END IF;
+      
+      i_pushhead3<=i_pushhead2;
+      
+      IF i_pushhead2='1' AND i_freeze='0' THEN
+        i_wr<='1';
+        i_wad<=0;
+        i_write<=i_write XOR NOT i_freeze;
+        i_walt<='0';
+        i_adrs<=(OTHERS =>'0');
+        i_pushhead2<='0';
+      END IF;
+      IF i_pushhead3='1' THEN
+        i_wad<=BLEN-1;
+      END IF;
+      
+      -- Delay a bit EOL : Async. AVL/I clocks...
+      i_eol2<=i_eol; i_eol3<=i_eol2;
+      
+      -- End of line
+      IF i_eol3='1' AND i_freeze='0' THEN
+        IF (i_wad MOD BLEN)/=BLEN-1 THEN
+          -- Some pixels are in the partially filled buffer
+          i_hbcpt<=(i_hbcpt+1) MOD 32;
+          i_write<=i_write XOR NOT i_freeze;
+          i_walt <=to_std_logic(i_wad/BLEN /= 0);
+          i_adrs <=i_adrsi;
+          IF i_inter='1' AND i_half='0' THEN
+            -- Skip every other line for interlaced video
+            i_adrsi<=i_adrsi + N_BURST * (i_hburst + 1);
+          ELSE
+            i_adrsi<=i_adrsi + N_BURST;
+          END IF;
+        ELSE
+          IF i_inter='1' AND i_half='0' THEN
+            -- Skip every other line for interlaced video
+            i_adrsi<=i_adrsi + N_BURST * i_hburst;
+          END IF;
+        END IF;
+      END IF;
+    END IF;
+  END PROCESS;
+  
+  -- If downscaling, export to the output part the downscaled size
+  i_hrsize<=i_hsize WHEN i_hdown='0' ELSE i_ohsize;
+  i_vrsize<=i_vsize WHEN i_vdown='0' ELSE i_ovsize;                    
+  
+  -----------------------------------------------------------------------------
+  -- Input Divider. For downscaling.
+  -- Vfrac = IVacc / IVsize 12 / 12 --> 12
+  IDividers:PROCESS (i_clk,i_reset_na) IS
+  BEGIN
+    IF i_reset_na='0' THEN
+--pragma synthesis_off
+      i_v_frac<=x"000";
+--pragma synthesis_on
+      NULL;
+    ELSIF rising_edge(i_clk) THEN
+      i_vdivi<=to_unsigned(2*i_vsize,13);
+      i_vdivr<=to_unsigned(i_vacc*4096,25);
+      
+      ------------------------------------------------------
+      IF i_divstart='1' THEN
+        i_divcpt<=0;
+        i_divrun<='1';
+        
+      ELSIF i_divrun='1' THEN
+        ----------------------------------------------------
+        IF i_divcpt=6 THEN
+          i_divrun<='0';
+          i_v_frac<=i_vdivr(4 DOWNTO 0) & NOT i_vdivr(24) & "000000";
+        ELSE
+          i_divcpt<=i_divcpt+1;
+        END IF;
+        
+        IF i_vdivr(24)='0' THEN
+          i_vdivr(24 DOWNTO 12)<=i_vdivr(23 DOWNTO 11) - i_vdivi;
+        ELSE
+          i_vdivr(24 DOWNTO 12)<=i_vdivr(23 DOWNTO 11) + i_vdivi;
+        END IF;
+        i_vdivr(11 DOWNTO 0)<=i_vdivr(10 DOWNTO 0) & NOT i_vdivr(24);
+        
+        ----------------------------------------------------
+      END IF;
+    END IF;
+  END PROCESS IDividers;
+
+  -----------------------------------------------------------------------------
+  -- DPRAM Input. Double buffer for RAM bursts.
+  PROCESS (i_clk) IS
+  BEGIN
+    IF rising_edge(i_clk) THEN
+      IF i_wr='1' THEN
+        i_dpram(i_wad)<=i_dw;
+      END IF;
+    END IF;
+  END PROCESS;
+  
+  avl_dr<=i_dpram(avl_rad_c) WHEN rising_edge(avl_clk);
+  
+  -- Line buffer for downscaling with interpolation
+  DownLine:IF DOWNSCALE GENERATE
+    ILBUF:PROCESS(i_clk) IS
+    BEGIN
+      IF rising_edge(i_clk) THEN
+        IF i_lwr='1' THEN
+          i_line(i_lwad MOD IHRES)<=i_ldw;
+        END IF;
+        IF i_pce='1' THEN
+          i_ldrm<=i_line(i_lrad MOD IHRES);
+        END IF;
+      END IF;
+    END PROCESS ILBUF;
+  END GENERATE DownLine;
+  
+  -----------------------------------------------------------------------------
+  -- AVALON interface
+  Avaloir:PROCESS(avl_clk,avl_reset_na) IS
+  BEGIN
+    IF avl_reset_na='0' THEN
+      avl_reading<='0';
+      avl_state<=sIDLE;
+      avl_write_sr<='0';
+      avl_read_sr<='0';
+      avl_readack<='0';
+      
+    ELSIF rising_edge(avl_clk) THEN
+      ----------------------------------
+      avl_write_sync<=i_write; -- <ASYNC>
+      avl_write_sync2<=avl_write_sync;
+      avl_write_pulse<=avl_write_sync XOR avl_write_sync2;
+      avl_wadrs <=i_adrs AND (RAMSIZE - 1); -- <ASYNC>
+      avl_wline <=i_wline; -- <ASYNC>
+      avl_walt  <=i_walt; -- <ASYNC>
+      
+      ----------------------------------
+      avl_read_sync<=o_read; -- <ASYNC>
+      avl_read_sync2<=avl_read_sync;
+      avl_read_pulse<=avl_read_sync XOR avl_read_sync2;
+      avl_rbib  <=o_bib;
+      avl_radrs <=o_adrs AND (RAMSIZE - 1); -- <ASYNC>
+      avl_rline <=o_rline; -- <ASYNC>
+      
+      --------------------------------------------
+      avl_o_offset0<=buf_offset(o_obuf0);  -- <ASYNC>
+      avl_o_offset1<=buf_offset(o_obuf1);  -- <ASYNC>
+      avl_i_offset0<=buf_offset(o_ibuf0);  -- <ASYNC>
+      avl_i_offset1<=buf_offset(o_ibuf1);  -- <ASYNC>
+      
+      avl_o_vs_sync<=o_vsv(0); -- <SYNC>
+      avl_o_vs<=avl_o_vs_sync;
+      
+      --------------------------------------------
+      avl_dw<=swap(unsigned(avl_readdata));
+      avl_read_i<='0';
+      avl_write_i<='0';
+      
+      avl_write_sr<=(avl_write_sr OR avl_write_pulse) AND NOT avl_write_clr;
+      avl_read_sr <=(avl_read_sr OR avl_read_pulse) AND NOT avl_read_clr;
+      avl_write_clr<='0';
+      avl_read_clr <='0';
+      
+      avl_rad<=avl_rad_c;
+      
+      --------------------------------------------
+      CASE avl_state IS
+        WHEN sIDLE =>
+          IF avl_o_vs='0' AND avl_o_vs_sync='1' THEN
+            avl_wad<=0;
+          END IF;
+          IF avl_write_sr='1' THEN
+            avl_state<=sWRITE;
+            avl_write_clr<='1';
+            IF avl_walt='0' THEN
+              avl_rad<=0;
+            ELSE
+              avl_rad<=BLEN;
+            END IF;
+          ELSIF avl_read_sr='1' AND avl_reading='0' THEN
+            IF avl_rbib='0' THEN
+              avl_wad<=2*BLEN-1;
+            ELSE
+              avl_wad<=BLEN-1;
+            END IF;
+            avl_state<=sREAD;
+            avl_read_clr<='1';
+          END IF;
+          
+        WHEN sWRITE =>
+          IF avl_wline='0' THEN
+            avl_address<=std_logic_vector(RAMBASE(N_AW+NB_LA-1 DOWNTO NB_LA) +
+              avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) +
+              avl_i_offset0(N_AW+NB_LA-1 DOWNTO NB_LA));
+          ELSE
+            avl_address<=std_logic_vector(RAMBASE(N_AW+NB_LA-1 DOWNTO NB_LA) +
+              avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) +
+              avl_i_offset1(N_AW+NB_LA-1 DOWNTO NB_LA));
+          END IF;
+            
+          avl_write_i<='1';
+          IF avl_write_i='1' AND avl_waitrequest='0' THEN
+            IF (avl_rad MOD BLEN)=BLEN-1 THEN
+              avl_write_i<='0';
+              avl_state<=sIDLE;
+            END IF;
+          END IF;
+          
+        WHEN sREAD =>
+          IF avl_rline='0' THEN
+            avl_address<=std_logic_vector(RAMBASE(N_AW+NB_LA-1 DOWNTO NB_LA) +
+              avl_radrs(N_AW+NB_LA-1 DOWNTO NB_LA) +
+              avl_o_offset0(N_AW+NB_LA-1 DOWNTO NB_LA));
+          ELSE
+            avl_address<=std_logic_vector(RAMBASE(N_AW+NB_LA-1 DOWNTO NB_LA) +
+              avl_radrs(N_AW+NB_LA-1 DOWNTO NB_LA) +
+              avl_o_offset1(N_AW+NB_LA-1 DOWNTO NB_LA));
+          END IF;  
+          avl_read_i<='1';
+          avl_reading<='1';
+          IF avl_read_i='1' AND avl_waitrequest='0' THEN
+            avl_state<=sIDLE;
+            avl_read_i<='0';
+          END IF;
+      END CASE;
+      
+      --------------------------------------------
+      -- Pipelined data read
+      avl_wr<='0';
+      IF avl_readdatavalid='1' THEN
+        avl_wr<='1';
+        avl_wad<=(avl_wad+1) MOD (2*BLEN);
+        IF (avl_wad MOD BLEN)=BLEN-2 THEN
+          avl_reading<='0';
+          avl_readack<=NOT avl_readack;
+        END IF;
+      END IF;
+      
+      --------------------------------------------
+    END IF;
+  END PROCESS Avaloir;
+  
+  avl_read<=avl_read_i;
+  avl_write<=avl_write_i;
+  avl_writedata<=std_logic_vector(swap(avl_dr));
+  avl_burstcount<=std_logic_vector(to_unsigned(BLEN,8));
+  avl_byteenable<=(OTHERS =>'1');
+  
+  avl_rad_c<=(avl_rad+1) MOD (2*BLEN)
+              WHEN avl_write_i='1' AND avl_waitrequest='0' ELSE avl_rad;
+  
+  -----------------------------------------------------------------------------
+  -- DPRAM Output. Double buffer for RAM bursts.
+  PROCESS (avl_clk) IS
+  BEGIN
+    IF rising_edge(avl_clk) THEN
+      IF avl_wr='1' THEN
+        o_dpram(avl_wad)<=avl_dw;
+      END IF;
+    END IF;
+  END PROCESS;
+  
+  o_dr<=o_dpram(o_ad3) WHEN rising_edge(o_clk);
+  
+  -----------------------------------------------------------------------------
+  -- Output Vertical Divider
+  -- Vfrac = Vacc / Vsize
+  ODivider:PROCESS (o_clk,o_reset_na) IS
+  BEGIN
+    IF o_reset_na='0' THEN
+--pragma synthesis_off
+      o_vfrac<=x"000";
+--pragma synthesis_on
+    ELSIF rising_edge(o_clk) THEN
+      o_vdivi<=to_unsigned(2*o_vsize,13);
+      o_vdivr<=to_unsigned(o_vacc*4096,25);
+      ------------------------------------------------------
+      IF o_divstart='1' THEN
+        o_divcpt<=0;
+        o_divrun<='1';
+        
+      ELSIF o_divrun='1' THEN
+        ----------------------------------------------------
+        IF o_divcpt=12 THEN
+          o_divrun<='0';
+          o_vfrac<=o_vdivr(10 DOWNTO 0) & NOT o_vdivr(24);
+        ELSE
+          o_divcpt<=o_divcpt+1;
+        END IF;
+        
+        IF o_vdivr(24)='0' THEN
+          o_vdivr(24 DOWNTO 12)<=o_vdivr(23 DOWNTO 11) - o_vdivi;
+        ELSE
+          o_vdivr(24 DOWNTO 12)<=o_vdivr(23 DOWNTO 11) + o_vdivi;
+        END IF;
+        o_vdivr(11 DOWNTO 0)<=o_vdivr(10 DOWNTO 0) & NOT o_vdivr(24);
+        ----------------------------------------------------
+      END IF;
+    END IF;
+  END PROCESS ODivider;
+  
+  -----------------------------------------------------------------------------
+  Scalaire:PROCESS (o_clk,o_reset_na) IS
+    VARIABLE lev_inc_v,lev_dec_v : std_logic;
+    VARIABLE prim_v,last_v,bib_v : std_logic;
+    VARIABLE shift_v : unsigned(0 TO N_DW+15);
+    VARIABLE hcarry_v,vcarry_v : boolean;
+    VARIABLE dif_v : natural RANGE 0 TO 8*OHRES-1;
+ BEGIN
+    IF o_reset_na='0' THEN
+      o_copy<='0';
+      o_state<=sDISP;
+      o_read_pre<='0';
+      o_readlev<=0;
+      o_copylev<=0;
+      o_hsp<='0';
+      
+    ELSIF rising_edge(o_clk) THEN
+      ------------------------------------------------------
+      o_mode   <=mode; -- <ASYNC> ?
+      o_run    <=run; -- <ASYNC> ?
+      
+      o_htotal <=htotal; -- <ASYNC> ?
+      o_hsstart<=hsstart; -- <ASYNC> ?
+      o_hsend  <=hsend; -- <ASYNC> ?
+      o_hdisp  <=hdisp; -- <ASYNC> ?
+      o_hmin   <=hmin; -- <ASYNC> ?
+      o_hmax   <=hmax; -- <ASYNC> ?
+
+      o_vtotal <=vtotal; -- <ASYNC> ?
+      o_vsstart<=vsstart; -- <ASYNC> ?
+      o_vsend  <=vsend; -- <ASYNC> ?
+      o_vdisp  <=vdisp; -- <ASYNC> ?
+      o_vmin   <=vmin; -- <ASYNC> ?
+      o_vmax   <=vmax; -- <ASYNC> ?
+      
+      o_hsize  <=o_hmax - o_hmin + 1;
+      o_vsize  <=o_vmax - o_vmin + 1;
+      
+      --------------------------------------------
+      -- Triple buffering.
+      -- For intelaced video, half frames are updated independently
+      -- Input : Toggle buffer at end of input frame
+      o_inter  <=i_inter; -- <ASYNC>
+      o_iendframe0<=i_endframe0; -- <ASYNC>
+      o_iendframe02<=o_iendframe0;
+      IF o_iendframe0='1' AND o_iendframe02='0' THEN
+        o_ibuf0<=buf_next(o_ibuf0,o_obuf0);
+        o_bufup0<='1';
+      END IF;
+      o_iendframe1<=i_endframe1; -- <ASYNC>
+      o_iendframe12<=o_iendframe1;
+      IF o_iendframe1='1' AND o_iendframe12='0' THEN
+        o_ibuf1<=buf_next(o_ibuf1,o_obuf1);
+        o_bufup1<='1';
+      END IF;
+      -- Output : Change framebuffer, and image properties, at VS falling edge
+      IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup1='1' THEN
+        o_obuf1<=buf_next(o_obuf1,o_ibuf1);
+        o_bufup1<='0';
+        o_hburst <=i_hburst; -- <ASYNC> Bursts per line
+        o_ihsize<=i_hrsize; -- <ASYNC>
+        o_ivsize<=i_vrsize; -- <ASYNC>
+        o_hdown<=i_hdown; -- <ASYNC>
+        o_vdown<=i_vdown; -- <ASYNC>
+      END IF;
+      IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN
+        o_obuf0<=buf_next(o_obuf0,o_ibuf0);
+        o_bufup0<='0';
+      END IF;
+      
+      IF o_inter='0' THEN
+        o_ibuf1<=o_ibuf0;
+        o_obuf1<=o_obuf0;
+      END IF;
+      
+      -- Triple buffer disabled
+      IF o_mode(3)='0' THEN
+        o_obuf0<=0;
+        o_obuf1<=0;
+        o_ibuf0<=0;
+        o_ibuf1<=0;
+      END IF;
+      
+      ------------------------------------------------------
+      o_hmode<=o_mode; 
+      IF o_hdown='1' AND DOWNSCALE THEN
+        -- Force nearest if downscaling : Downscaled framebuffer
+        o_hmode(2 DOWNTO 0)<="000";
+      END IF;
+      
+      o_vmode<=o_mode;
+      IF o_vdown='1' AND DOWNSCALE THEN
+        -- Force nearest if downscaling : Downscaled framebuffer
+        o_vmode(2 DOWNTO 0)<="000";
+      END IF;
+      
+      ------------------------------------------------------
+      -- End DRAM READ
+      o_readack_sync<=avl_readack; -- <ASYNC>
+      o_readack_sync2<=o_readack_sync;
+      o_readack<=o_readack_sync XOR o_readack_sync2;
+      
+      ------------------------------------------------------
+      lev_inc_v:='0';
+      lev_dec_v:='0';
+      
+      -- acpt : Pixel position within current data word
+      -- dcpt : Destination image position
+      -- hpos : Source image position, fixed point 12.12
+      
+      -- Force preload 2 lines at top of screen
+      IF o_hsv(0)='1' AND o_hsv(1)='0' THEN
+        IF o_vcpt_pre3=o_vmin THEN
+          o_fload<=2;
+        END IF;
+        o_hsp<='1';
+      END IF;
+      
+      o_vpe<=to_std_logic(o_vcpt_pre<o_vmax AND o_vcpt_pre>=o_vmin);
+      o_divstart<='0';
+      o_adrsa<='0';
+
+      o_vacc_ini<=(o_vsize - o_ivsize + 8192) MOD 8192;
+      o_hacc_ini<=(o_hsize + o_ihsize + 8192) MOD 8192;
+      
+      CASE o_state IS
+          --------------------------------------------------
+        WHEN sDISP =>
+          IF o_hsp='1' THEN
+            o_state<=sHSYNC;
+            o_hsp<='0';
+          END IF;
+          
+          --------------------------------------------------
+        WHEN sHSYNC =>
+          dif_v:=(o_vacc_next - 2*o_vsize + 16384) MOD 16384;
+          IF dif_v>=8192 THEN
+            o_vacc     <=o_vacc_next;
+            o_vacc_next<=(o_vacc_next + 2*o_ivsize) MOD 8192;
+            vcarry_v:=false;
+          ELSE
+            o_vacc     <=dif_v;
+            o_vacc_next<=(dif_v + 2*o_ivsize + 8192) MOD 8192;
+            vcarry_v:=true;
+          END IF;
+          o_divstart<='1';
+          IF o_vcpt_pre2=o_vmin THEN --pe='0' THEN
+            o_vacc     <=o_vacc_ini;
+            o_vacc_next<=o_vacc_ini + 2*o_ivsize;
+            o_vacpt<=x"001";
+            vcarry_v:=false;
+          END IF;
+
+          IF vcarry_v THEN
+            o_vacpt<=o_vacpt+1;
+          END IF;
+          o_hbcpt<=0; -- Clear burst counter on line
+          IF (o_vpe='1' AND vcarry_v) OR o_fload>0 THEN
+            o_state<=sREAD;
+          ELSE
+            o_state<=sDISP;
+          END IF;
+          
+        WHEN sREAD =>
+          -- Read a block
+          IF o_readlev<2 THEN
+            lev_inc_v:='1';
+            o_read_pre<=NOT o_read_pre;
+            o_state <=sWAITREAD;
+            o_bibu<=NOT o_bibu;
+          END IF;
+          prim_v:=to_std_logic(o_hbcpt=0);
+          last_v:=to_std_logic(o_hbcpt=o_hburst-1);
+          bib_v :=o_bibu;
+          o_bib <=o_bibu;
+          o_adrsa<='1';
+          
+        WHEN sWAITREAD =>
+          IF o_readack='1' THEN
+            o_hbcpt<=o_hbcpt+1;
+            IF o_hbcpt<o_hburst-1 THEN
+              -- If not finshed line, read more
+              o_state<=sREAD;
+            ELSE
+              o_state<=sDISP;
+              IF o_fload>=1 THEN
+                o_fload<=o_fload-1;
+              END IF;
+            END IF;
+          END IF;
+          
+          --------------------------------------------------
+      END CASE;
+      
+      o_read<=o_read_pre AND o_run;
+      
+      o_adrs_pre<=to_integer(o_vacpt) * o_hburst;
+      o_rline<=o_vacpt(0); -- Even/Odd line for interlaced video
+      IF o_adrsa='1' THEN
+        IF HEADER THEN
+          IF o_fload=2 THEN
+            o_adrs<=to_unsigned((o_hbcpt + 1) * N_BURST,32);
+            o_alt<="1111";
+          ELSIF o_fload=1 THEN
+            o_adrs<=to_unsigned((o_hburst + o_hbcpt + 1) * N_BURST,32);
+            o_alt<="0100";
+          ELSE
+            o_adrs<=to_unsigned((o_adrs_pre + o_hbcpt + 1) * N_BURST,32);
+            o_alt<=altx(o_vacpt(1 DOWNTO 0) + 1);
+          END IF;
+        ELSE
+          IF o_fload=2 THEN
+            o_adrs<=to_unsigned(o_hbcpt * N_BURST,32);
+            o_alt<="1111";
+          ELSIF o_fload=1 THEN
+            o_adrs<=to_unsigned((o_hburst + o_hbcpt) * N_BURST,32);
+            o_alt<="0100";
+          ELSE
+            o_adrs<=to_unsigned((o_adrs_pre + o_hbcpt) * N_BURST,32);
+            o_alt<=altx(o_vacpt(1 DOWNTO 0) + 1);
+          END IF;
+        END IF;
+      END IF;
+      
+      ------------------------------------------------------
+      -- Copy from buffered memory to pixel lines
+      o_sh<='0';
+      IF o_copy='0' THEN
+        o_copyv(0)<='0';
+        IF o_copylev>0 AND o_copyv(0)='0' THEN
+          o_copy<='1';
+        END IF;
+        o_adturn<='0';
+        
+        IF o_primv(0)='1' THEN
+          -- First memcopy of a horizontal line, carriage return !
+          -- HPOS starts at 1 for the first input image pix,to keep it positive
+          o_hacc     <=o_hacc_ini;
+          o_hacc_next<=o_hacc_ini + 2*o_ihsize;
+          o_hacpt    <=x"000";
+          o_dcpt<=0;
+          o_dshi<=2;
+          o_acpt<=0;
+          o_first<='1';
+          o_last<='0';
+        END IF;
+        
+        IF o_bibv(0)='0' THEN
+          o_ad<=0;
+        ELSE
+          o_ad<=BLEN;
+        END IF;
+      ELSE
+        -- dshi : Force shift first two or three pixels of each line
+        IF o_dshi=0  THEN
+          dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRES)) MOD (8*OHRES);
+          IF dif_v>=4*OHRES THEN
+            o_hacc<=o_hacc_next;
+            o_hacc_next<=o_hacc_next + 2*o_ihsize;
+            hcarry_v:=false;
+          ELSE
+            o_hacc<=dif_v;
+            o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRES)) MOD (4*OHRES);
+            hcarry_v:=true;
+          END IF;
+          o_dcpt<=(o_dcpt+1) MOD 4096;
+        ELSE
+          o_dshi<=o_dshi-1;
+          hcarry_v:=false;
+        END IF;
+        IF o_dshi<=1 THEN
+          o_copyv(0)<='1';
+        END IF;
+        IF hcarry_v THEN
+          o_hacpt<=o_hacpt+1;
+          o_last<=to_std_logic(o_hacpt>=o_ihsize-2);
+        END IF;
+        
+        IF hcarry_v OR o_dshi>0 THEN
+          o_sh<='1';
+          o_acpt<=(o_acpt+1) MOD 16;
+          
+          -- Shift two more pixels to the right before ending line.
+          o_last1<=o_last;
+          o_last2<=o_last1;
+          
+          IF shift24_onext(o_acpt) THEN
+            o_ad<=(o_ad+1) MOD (2*BLEN);
+          END IF;
+          
+          IF o_adturn='1' AND (shift24_onext((o_acpt+1) MOD 16)) AND
+            (((o_ad MOD BLEN=0) AND o_lastv(0)='0') OR o_last2='1')  THEN
+            o_copy<='0';
+            lev_dec_v:='1';
+          END IF;
+          
+          IF o_ad MOD BLEN=4 THEN
+            o_adturn<='1';
+          END IF;
+        END IF;
+      END IF;
+      
+      o_acpt1<=o_acpt; o_acpt2<=o_acpt1; o_acpt3<=o_acpt2; o_acpt4<=o_acpt3;
+      o_ad1<=o_ad; o_ad2<=o_ad1; o_ad3<=o_ad2;
+      o_sh1<=o_sh; o_sh2<=o_sh1; o_sh3<=o_sh2;
+      o_lastt1<=o_last; o_lastt2<=o_lastt1; o_lastt3<=o_lastt2;
+      
+      ------------------------------------------------------
+      IF o_sh3='1' THEN
+        shift_v:=shift24_opack(o_acpt4,o_shift,o_dr);
+        o_shift<=shift_v;
+        
+        o_hpix0<=(r=>shift_v(0 TO 7),g=>shift_v(8 TO 15),b=>shift_v(16 TO 23));
+        o_hpix1<=o_hpix0;
+        o_hpix2<=o_hpix1;
+        o_hpix3<=o_hpix2;
+        
+        IF o_first='1' THEN
+          -- Left edge. Duplicate first pixel
+          o_hpix1<=(r=>shift_v(0 TO 7),g=>shift_v(8 TO 15),b=>shift_v(16 TO 23));
+          o_hpix2<=(r=>shift_v(0 TO 7),g=>shift_v(8 TO 15),b=>shift_v(16 TO 23));         
+          o_first<='0';
+        END IF;
+        IF o_lastt3='1' THEN
+          -- Right edge. Keep last pixel.
+          o_hpix0<=o_hpix0;
+        END IF;
+      END IF;
+      
+      ------------------------------------------------------
+      -- READLEV : Number of ongoing Avalon Reads
+      IF lev_dec_v='1' AND lev_inc_v='0' THEN
+        o_readlev<=o_readlev-1;
+      ELSIF lev_dec_v='0' AND lev_inc_v='1' THEN
+        o_readlev<=o_readlev+1;
+      END IF;
+      
+      -- COPYLEV : Number of ongoing copies to line buffers
+      IF lev_dec_v='1' AND o_readack='0' THEN
+        o_copylev<=o_copylev-1;
+      ELSIF lev_dec_v='0' AND o_readack='1' THEN
+        o_copylev<=o_copylev+1;
+      END IF;
+      
+      -- FIFOs
+      IF lev_dec_v='1' THEN
+        o_primv(0 TO 1)<=o_primv(1 TO 2); -- First buffer of line
+        o_lastv(0 TO 1)<=o_lastv(1 TO 2); -- Last buffer of line
+        o_bibv (0 TO 1)<=o_bibv (1 TO 2); -- Double buffer select
+      END IF;
+      
+      IF lev_inc_v='1' THEN
+        IF o_readlev=0 OR (o_readlev=1 AND lev_dec_v='1') THEN
+          o_primv(0)<=prim_v;
+          o_lastv(0)<=last_v;
+          o_bibv (0)<=bib_v;
+        ELSIF (o_readlev=1 AND lev_dec_v='0') OR
+              (o_readlev=2 AND lev_dec_v='1') THEN
+          o_primv(1)<=prim_v;
+          o_lastv(1)<=last_v;
+          o_bibv (1)<=bib_v;
+        END IF;
+        o_primv(2)<=prim_v;
+        o_lastv(2)<=last_v;
+        o_bibv (2)<=bib_v;
+      END IF;
+      
+      ------------------------------------------------------
+    END IF;
+  END PROCESS Scalaire;
+  
+  o_h_poly_a<=to_integer(o_hfrac(11 DOWNTO 12-FRAC));
+  o_v_poly_a<=to_integer(o_vfrac(11 DOWNTO 12-FRAC));
+  
+  o_h_poly_dr<=o_h_poly(o_h_poly_a) WHEN rising_edge(o_clk);
+  o_v_poly_dr<=o_v_poly(o_v_poly_a) WHEN rising_edge(o_clk);
+  
+  -----------------------------------------------------------------------------
+  -- Polyphase ROMs
+  Polikarpov:PROCESS(poly_clk) IS
+  BEGIN
+    IF rising_edge(poly_clk) THEN
+      IF poly_wr='1' THEN
+        poly_tdw(8+9*(3-to_integer(poly_a(1 DOWNTO 0))) DOWNTO
+                   9*(3-to_integer(poly_a(1 DOWNTO 0))))<=poly_dw;
+      END IF;
+      
+      poly_h_wr<=poly_wr AND NOT poly_a(FRAC+2);
+      poly_v_wr<=poly_wr AND poly_a(FRAC+2);
+      poly_a2<=poly_a(FRAC+1 DOWNTO 2);
+      
+      IF poly_h_wr='1' THEN
+        o_h_poly(to_integer(poly_a2))<=poly_tdw;
+      END IF;
+      IF poly_v_wr='1' THEN
+        o_v_poly(to_integer(poly_a2))<=poly_tdw;
+      END IF;
+    END IF;
+  END PROCESS Polikarpov;
+  
+  -----------------------------------------------------------------------------
+  -- Horizontal Scaler
+  HSCAL:PROCESS(o_clk) IS
+    VARIABLE div_v : unsigned(18 DOWNTO 0);
+    VARIABLE dir_v : unsigned(11 DOWNTO 0);
+  BEGIN
+    IF rising_edge(o_clk) THEN
+      -- Pipeline signals
+      -----------------------------------
+      -- Pipelined 6 bits non-restoring divider. Cycle 1
+      dir_v:=x"000";
+      div_v:=to_unsigned(o_hacc * 64,19);
+      
+      div_v:=div_v-to_unsigned(o_hsize*64,19);
+      dir_v(11):=NOT div_v(18);
+      IF div_v(18)='0' THEN
+        div_v:=div_v-to_unsigned(o_hsize*32,19);
+      ELSE
+        div_v:=div_v+to_unsigned(o_hsize*32,19);
+      END IF;
+      dir_v(10):=NOT div_v(18);
+      o_div<=div_v;
+      o_dir<=dir_v;
+      
+      -- Cycle 2
+      div_v:=o_div;
+      dir_v:=o_dir;
+      IF div_v(18)='0' THEN
+        div_v:=div_v-to_unsigned(o_hsize*16,19);
+      ELSE
+        div_v:=div_v+to_unsigned(o_hsize*16,19);
+      END IF;
+      dir_v( 9):=NOT div_v(18);
+
+      IF div_v(18)='0' THEN
+        div_v:=div_v-to_unsigned(o_hsize*8,19);
+      ELSE
+        div_v:=div_v+to_unsigned(o_hsize*8,19);
+      END IF;
+      dir_v(8):=NOT div_v(18);
+      o_div2<=div_v;
+      o_dir2<=dir_v;
+      
+      -- Cycle 3
+      div_v:=o_div2;
+      dir_v:=o_dir2;
+      IF FRAC>4 THEN
+        IF div_v(18)='0' THEN
+          div_v:=div_v-to_unsigned(o_hsize*4,19);
+        ELSE
+          div_v:=div_v+to_unsigned(o_hsize*4,19);
+        END IF;
+        dir_v(7):=NOT div_v(18);
+        IF div_v(18)='0' THEN
+          div_v:=div_v-to_unsigned(o_hsize*2,19);
+        ELSE
+          div_v:=div_v+to_unsigned(o_hsize*2,19);
+        END IF;
+        dir_v(6):=NOT div_v(18);
+      END IF;
+      
+      -----------------------------------
+      o_hfrac<=dir_v;
+      o_hfrac1<=o_hfrac; o_hfrac2<=o_hfrac1; o_hfrac3<=o_hfrac2;
+      
+      o_copyv(1 TO 7)<=o_copyv(0 TO 6);
+      
+      o_dcpt1<=o_dcpt;
+      IF o_dcpt1>o_hsize THEN
+        o_copyv(2)<='0';
+      END IF;
+      o_dcpt2<=o_dcpt1 MOD OHRES;
+      o_dcpt3<=o_dcpt2; o_dcpt4<=o_dcpt3; o_dcpt5<=o_dcpt4;
+      o_dcpt6<=o_dcpt5; o_dcpt7<=o_dcpt6;
+      
+      o_hpixq<=(o_hpix3,o_hpix2,o_hpix1,o_hpix0);
+      
+      -- NEAREST / BILINEAR / SHARP BILINEAR ---------------
+      -- C1 : Pre-calc Sharp Bilinear
+      o_h_sbil_t<=sbil_frac1(o_hfrac);
+      
+      -- C2 : Select
+      o_h_frac2<=(OTHERS =>'0');
+      CASE o_hmode(1 DOWNTO 0) IS
+        WHEN "00" => -- Nearest
+          IF MASK(MASK_NEAREST)='1' THEN
+            o_h_frac2<=near_frac(o_hfrac1);
+          END IF;
+        WHEN "01" => -- Bilinear
+          IF MASK(MASK_BILINEAR)='1' THEN
+            o_h_frac2<=bil_frac(o_hfrac1);
+          END IF;
+        WHEN "10" => -- Sharp Bilinear
+          IF MASK(MASK_SHARP_BILINEAR)='1' THEN
+            o_h_frac2<=sbil_frac2(o_hfrac1,o_h_sbil_t);
+          END IF;
+        WHEN OTHERS =>
+          NULL;
+      END CASE;
+      
+      -- C3 : Opposite frac
+      o_h_bil_t<=bil_calc(o_h_frac2,o_hpixq);
+      
+      -- C4 : Nearest / Bilinear / Sharp Bilinear
+      o_h_bil_pix.r<=bound(o_h_bil_t.r,8+FRAC);
+      o_h_bil_pix.g<=bound(o_h_bil_t.g,8+FRAC);
+      o_h_bil_pix.b<=bound(o_h_bil_t.b,8+FRAC);
+      
+      -- BICUBIC -------------------------------------------
+      -- C1 : Bicubic coefficients A,B,C,D
+      
+      -- C2 : Bicubic calc T1 = X.D + C
+      o_h_bic_abcd1<=bic_calc0(o_hfrac1,(o_hpix3,o_hpix2,o_hpix1,o_hpix0));
+      o_h_bic_tt1<=bic_calc1(o_hfrac1,
+                     bic_calc0(o_hfrac1,(o_hpix3,o_hpix2,o_hpix1,o_hpix0)));
+      
+      -- C3 : Bicubic calc T2 = X.T1 + B
+      o_h_bic_abcd2<=o_h_bic_abcd1;
+      o_h_bic_tt2<=bic_calc2(o_hfrac2,o_h_bic_tt1,o_h_bic_abcd1);
+      
+      -- C4 : Bicubic final Y = X.T2 + A
+      o_h_bic_pix<=bic_calc3(o_hfrac3,o_h_bic_tt2,o_h_bic_abcd2);
+      
+      -- POLYPHASE -----------------------------------------
+      -- C1 : Read memory
+      
+      -- C2 : Filter calc
+      o_h_poly_dr2<=o_h_poly_dr;
+      
+      -- C3 : Add
+      o_h_poly_t<=poly_calc1(o_h_poly_dr2,o_hpixq);
+      
+      -- C4 : Bounding
+      o_h_poly_pix<=poly_calc2(o_h_poly_t);
+      
+      -- C5 : Select interpoler ----------------------------
+      o_wadl<=o_dcpt7;
+      o_wr<=o_alt AND (o_copyv(7) & o_copyv(7) & o_copyv(7) & o_copyv(7));
+      o_ldw<=(x"00",x"00",x"00");
+      
+      CASE o_hmode(2 DOWNTO 0) IS
+        WHEN "000" | "001" | "010" => -- Nearest | Bilinear | Sharp Bilinear
+          IF MASK(MASK_NEAREST)='1' OR
+             MASK(MASK_BILINEAR)='1' OR
+             MASK(MASK_SHARP_BILINEAR)='1' THEN
+            o_ldw<=o_h_bil_pix;
+         END IF;
+        WHEN "011" => -- BiCubic
+          IF MASK(MASK_BICUBIC)='1' THEN
+            o_ldw<=o_h_bic_pix;
+          END IF;
+        WHEN OTHERS => -- PolyPhase
+          IF MASK(MASK_POLY)='1' THEN
+            o_ldw<=o_h_poly_pix;
+          END IF;
+      END CASE;
+      ------------------------------------------------------
+    END IF;
+  END PROCESS HSCAL;
+  
+  -----------------------------------------------------------------------------
+  -- Line buffers 4 x OHRES x (R+G+B)
+  OLBUF:PROCESS(o_clk) IS
+  BEGIN
+    IF rising_edge(o_clk) THEN
+      -- WRITES
+      IF o_wr(0)='1' THEN o_line0(o_wadl)<=o_ldw; END IF;
+      IF o_wr(1)='1' THEN o_line1(o_wadl)<=o_ldw; END IF;
+      IF o_wr(2)='1' THEN o_line2(o_wadl)<=o_ldw; END IF;
+      IF o_wr(3)='1' THEN o_line3(o_wadl)<=o_ldw; END IF;
+      
+      -- READS
+      o_ldr0<=o_line0(o_radl);
+      o_ldr1<=o_line1(o_radl);
+      o_ldr2<=o_line2(o_radl);
+      o_ldr3<=o_line3(o_radl);
+    END IF;
+  END PROCESS OLBUF;
+  
+  -----------------------------------------------------------------------------
+  -- Output video sweep
+  OSWEEP:PROCESS(o_clk) IS
+  BEGIN
+    IF rising_edge(o_clk) THEN
+      IF o_ce='1' THEN
+        -- Output pixels count
+        IF o_hcpt+1<o_htotal THEN
+          o_hcpt<=(o_hcpt+1) MOD 4096;
+        ELSE
+          o_hcpt<=0;
+          IF o_vcpt_pre3+1>=o_vtotal THEN
+            o_vcpt_pre3<=0;
+          ELSE
+            o_vcpt_pre3<=(o_vcpt_pre3+1) MOD 4096;
+          END IF;
+          o_vcpt_pre2<=o_vcpt_pre3;
+          o_vcpt_pre<=o_vcpt_pre2;
+          o_vcpt<=o_vcpt_pre;
+        END IF;
+        
+        o_dev(0)<=to_std_logic(o_hcpt<o_hdisp AND o_vcpt<o_vdisp);
+        o_pev(0)<=to_std_logic(o_hcpt>=o_hmin AND o_hcpt<=o_hmax AND
+                               o_vcpt>=o_vmin AND o_vcpt<=o_vmax);
+        o_hsv(0)<=to_std_logic(o_hcpt>=o_hsstart AND o_hcpt<o_hsend);
+        o_vsv(0)<=to_std_logic((o_vcpt=o_vsstart AND o_hcpt>=o_hsstart) OR
+                               (o_vcpt>o_vsstart AND o_vcpt<o_vsend) OR
+                               (o_vcpt=o_vsend   AND o_hcpt<o_hsstart));
+
+        o_vss<=to_std_logic(o_vcpt_pre2=o_vmin);
+        o_hsv(1 TO 5)<=o_hsv(0 TO 4);
+        o_vsv(1 TO 5)<=o_vsv(0 TO 4);
+        o_dev(1 TO 5)<=o_dev(0 TO 4);
+        o_pev(1 TO 5)<=o_pev(0 TO 4);
+
+        
+        IF o_run='0' THEN
+          o_hsv(2)<='0';
+          o_vsv(2)<='0';
+          o_dev(2)<='0';
+          o_pev(2)<='0';
+        END IF;
+        
+      END IF;
+    END IF;
+    
+  END PROCESS OSWEEP;
+  
+  -----------------------------------------------------------------------------
+  -- Vertical Scaler
+  VSCAL:PROCESS(o_clk) IS
+    VARIABLE pixq_v : arr_pix(0 TO 3);
+  BEGIN
+    IF rising_edge(o_clk) THEN
+      IF o_ce='1' THEN
+        -- CYCLE 1 -----------------------------------------
+        -- Read mem
+        o_radl<=(o_hcpt-o_hmin+OHRES) MOD OHRES;
+        
+        -- CYCLE 2 -----------------------------------------
+        -- Lines reordering
+        CASE o_vacpt(1 DOWNTO 0) IS
+          WHEN "10"   => pixq_v:=(o_ldr0,o_ldr1,o_ldr2,o_ldr3);
+          WHEN "11"   => pixq_v:=(o_ldr1,o_ldr2,o_ldr3,o_ldr0);
+          WHEN "00"   => pixq_v:=(o_ldr2,o_ldr3,o_ldr0,o_ldr1);
+          WHEN OTHERS => pixq_v:=(o_ldr3,o_ldr0,o_ldr1,o_ldr2);
+        END CASE;
+        
+        o_vpixq<=pixq_v;
+        
+        -- Bottom edge : replicate last line
+        IF to_integer(o_vacpt)=o_ivsize THEN
+          o_vpixq(2)<=pixq_v(2);
+        END IF;
+        IF to_integer(o_vacpt)>=o_ivsize+1 THEN
+          o_vpixq(2)<=pixq_v(1);
+          o_vpixq(1)<=pixq_v(1);
+        END IF;
+        
+        o_vpixq1<=o_vpixq;
+        
+        -- NEAREST / BILINEAR / SHARP BILINEAR -------------
+        -- C3 : Pre-calc Sharp Bilinear
+        o_v_sbil_t<=sbil_frac1(o_vfrac);
+        
+        -- C4 : Select
+        o_v_frac<=(OTHERS =>'0');
+        CASE o_vmode(1 DOWNTO 0) IS
+          WHEN "00" => -- Nearest
+            IF MASK(MASK_NEAREST)='1' THEN
+              o_v_frac<=near_frac(o_vfrac);
+            END IF;
+          WHEN "01" => -- Bilinear
+            IF MASK(MASK_BILINEAR)='1' THEN
+              o_v_frac<=bil_frac(o_vfrac);
+            END IF;
+          WHEN "10" => -- Sharp Bilinear
+            IF MASK(MASK_SHARP_BILINEAR)='1' THEN
+              o_v_frac<=sbil_frac2(o_vfrac,o_v_sbil_t);
+            END IF;
+          WHEN OTHERS => NULL;
+        END CASE;
+        
+        o_v_bil_t<=bil_calc(o_v_frac,o_vpixq1);
+        
+        -- C6 : Nearest / Bilinear / Sharp Bilinear
+        o_v_bil_pix.r<=bound(o_v_bil_t.r,8+FRAC);
+        o_v_bil_pix.g<=bound(o_v_bil_t.g,8+FRAC);
+        o_v_bil_pix.b<=bound(o_v_bil_t.b,8+FRAC);
+        
+        -- BICUBIC -----------------------------------------
+        -- C3 : Bicubic coefficients A,B,C,D
+        
+        -- C4 : Bicubic calc T1 = X.D + C
+        o_v_bic_abcd1<=bic_calc0(o_vfrac,o_vpixq);
+        o_v_bic_tt1<=bic_calc1(o_vfrac,bic_calc0(o_vfrac,o_vpixq));
+        
+        -- C5 : Bicubic calc T2 = X.T1 + B
+        o_v_bic_abcd2<=o_v_bic_abcd1;
+        o_v_bic_tt2<=bic_calc2(o_vfrac,o_v_bic_tt1,o_v_bic_abcd1);
+        
+        -- C6 : Bicubic final Y = X.T2 + A
+        o_v_bic_pix<=bic_calc3(o_vfrac,o_v_bic_tt2,o_v_bic_abcd2);
+        
+        -- POLYPHASE ---------------------------------------
+        -- C3 : Read memory
+        
+        -- C4 : Filter calc
+        o_v_poly_dr2<=o_v_poly_dr;
+        
+        -- C5 : Add
+        o_v_poly_t<=poly_calc1(o_v_poly_dr2,o_vpixq1);
+        
+        -- C6 : Bounding
+        o_v_poly_pix<=poly_calc2(o_v_poly_t);
+        
+        -- CYCLE 6 -----------------------------------------
+        o_hs<=o_hsv(5);
+        o_vs<=o_vsv(5);
+        o_de<=o_dev(5);
+        o_r<=x"00";
+        o_g<=x"00";
+        o_b<=x"00";
+            
+        CASE o_vmode(2 DOWNTO 0) IS
+          WHEN "000" | "001" | "010" => -- Nearest | Bilinear | Sharp Bilinear
+            IF MASK(MASK_NEAREST)='1' OR
+               MASK(MASK_BILINEAR)='1' OR
+               MASK(MASK_SHARP_BILINEAR)='1' THEN
+              o_r<=o_v_bil_pix.r;
+              o_g<=o_v_bil_pix.g;
+              o_b<=o_v_bil_pix.b;
+            END IF;
+          WHEN "011" => -- BiCubic
+            IF MASK(MASK_BICUBIC)='1' THEN
+              o_r<=o_v_bic_pix.r;
+              o_g<=o_v_bic_pix.g;
+              o_b<=o_v_bic_pix.b;
+            END IF;
+            
+          WHEN OTHERS => -- Polyphase
+            IF MASK(MASK_POLY)='1' THEN
+              o_r<=o_v_poly_pix.r;
+              o_g<=o_v_poly_pix.g;
+              o_b<=o_v_poly_pix.b;
+            END IF;
+        END CASE;
+        
+        IF o_pev(5)='0' THEN
+          o_r<=x"00"; -- Border colour
+          o_g<=x"00";
+          o_b<=x"00";
+        END IF;
+        
+        ----------------------------------------------------
+      END IF;
+    END IF;
+
+  END PROCESS VSCAL;
+  
+  -----------------------------------------------------------------------------
+  -- Low Lag syntoniser interface
+  -- i_syncline falling edge shall be aligned with o_vss raising edge.
+  
+  o_lltune<=(0 => NOT i_syncline,
+             1 => '0',
+             2 => i_inter,
+             3 => i_flm,
+             4 => o_vss,
+             5 => '0',
+             6 => i_clk,
+             7 => o_clk,
+             OTHERS =>'0');
+  
+  ----------------------------------------------------------------------------  
+END ARCHITECTURE rtl;
+
diff --git a/sys/build_id.tcl b/sys/build_id.tcl
new file mode 100644
index 0000000..3705e4c
--- /dev/null
+++ b/sys/build_id.tcl
@@ -0,0 +1,69 @@
+
+# Build TimeStamp Verilog Module
+# Jeff Wiencrot - 8/1/2011
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Build CDF file
+# Sorgelig - 17/2/2018
+proc generateCDF {revision device outpath} {
+
+	set outputFileName "jtag.cdf"
+	set outputFile [open $outputFileName "w"]
+
+	puts $outputFile "JedecChain;"
+	puts $outputFile "	FileRevision(JESD32A);"
+	puts $outputFile "	DefaultMfr(6E);"
+	puts $outputFile ""
+	puts $outputFile "	P ActionCode(Ign)"
+	puts $outputFile "		Device PartName(SOCVHPS) MfrSpec(OpMask(0));"
+	puts $outputFile "	P ActionCode(Cfg)"
+	puts $outputFile "		Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));"
+	puts $outputFile "ChainEnd;"
+	puts $outputFile ""
+	puts $outputFile "AlteraBegin;"
+	puts $outputFile "	ChainType(JTAG);"
+	puts $outputFile "AlteraEnd;"
+}
+
+set project_name [lindex $quartus(args) 1]
+set revision [lindex $quartus(args) 2]
+
+if {[project_exists $project_name]} {
+    if {[string equal "" $revision]} {
+        project_open $project_name -revision [get_current_revision $project_name]
+    } else {
+        project_open $project_name -revision $revision
+    }
+} else {
+    post_message -type error "Project $project_name does not exist"
+    exit
+}
+
+set device  [get_global_assignment -name DEVICE]
+set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY]
+
+if [is_project_open] {
+    project_close
+}
+
+generateBuildID_Verilog
+generateCDF $revision $device $outpath
diff --git a/sys/hdmi_config.sv b/sys/hdmi_config.sv
new file mode 100644
index 0000000..17662e4
--- /dev/null
+++ b/sys/hdmi_config.sv
@@ -0,0 +1,202 @@
+
+module hdmi_config
+(
+	//	Host Side
+	input			iCLK,
+	input			iRST_N,
+	
+	input       dvi_mode,
+	input       audio_96k,
+
+	//	I2C Side
+	output		I2C_SCL,
+	inout 		I2C_SDA
+);
+
+//	Internal Registers/Wires
+reg        mI2C_GO = 0;
+wire       mI2C_END;
+wire       mI2C_ACK;
+reg [15:0] LUT_DATA;
+reg  [7:0] LUT_INDEX = 0;
+
+i2c #(50_000_000, 20_000) i2c_av
+(
+	.CLK(iCLK),
+
+	.I2C_SCL(I2C_SCL),		//	I2C CLOCK
+	.I2C_SDA(I2C_SDA),		//	I2C DATA
+
+	.I2C_DATA({8'h72,init_data[LUT_INDEX]}),	//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]. 0x72 is the Slave Address of the ADV7513 chip!
+	.START(mI2C_GO),    		//	START transfer
+	.END(mI2C_END),			//	END transfer 
+	.ACK(mI2C_ACK) 			//	ACK
+);
+
+//////////////////////	Config Control	////////////////////////////
+always@(posedge iCLK or negedge iRST_N) begin
+	reg  [1:0] mSetup_ST = 0;
+
+	if(!iRST_N) begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+	end else begin
+		if(init_data[LUT_INDEX] != 16'hFFFF) begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1: if(~mI2C_END) mSetup_ST	<=	2;
+			2:	begin
+					mI2C_GO <= 0;
+					if(mI2C_END) begin
+						mSetup_ST <= 0;
+						if(!mI2C_ACK) LUT_INDEX <= LUT_INDEX + 8'd1;
+					end
+				end
+			endcase
+		end
+	end
+end
+
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT   //////////////////////////
+
+wire [15:0] init_data[58] = 
+'{
+	16'h9803,					// ADI required Write.
+
+	{8'hD6, 8'b1100_0000},	// [7:6] HPD Control...
+									// 00 = HPD is from both HPD pin or CDC HPD
+									// 01 = HPD is from CDC HPD
+									// 10 = HPD is from HPD pin
+									// 11 = HPD is always high
+
+	16'h4110,					// Power Down control
+	16'h9A70,					// ADI required Write.
+	16'h9C30,					// ADI required Write.
+	{8'h9D, 8'b0110_0001},	// [7:4] must be b0110!.
+									// [3:2] b00 = Input clock not divided. b01 = Clk divided by 2. b10 = Clk divided by 4. b11 = invalid!
+									//	[1:0] must be b01!
+	16'hA2A4,					// ADI required Write.
+	16'hA3A4,					// ADI required Write.
+	16'hE0D0,					// ADI required Write.
+
+
+	16'h35_40,
+	16'h36_D9,
+	16'h37_0A,
+	16'h38_00,
+	16'h39_2D,
+	16'h3A_00,
+
+	{8'h16, 8'b0011_1000},	// Output Format 444 [7]=0.
+									// [6] must be 0!
+									// Colour Depth for Input Video data [5:4] b11 = 8-bit.
+									// Input Style [3:2] b10 = Style 1 (ignored when using 444 input).
+									// DDR Input Edge falling [1]=0 (not using DDR atm).
+									// Output Colour Space RGB [0]=0.
+
+	{8'h17, 8'b01100010},   // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
+
+	{8'h18, 8'b0100_0110},	// CSC disabled [7]=0.
+									// CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380.
+									// CSC Equation 3 [4:0] b00110.
+
+
+	{8'h3B, 8'b0000_0000},	// Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
+
+	16'h4000,					// General Control Packet Enable
+
+	{8'h48, 8'b0000_1000},	// [6]=0 Normal bus order!
+									// [5] DDR Alignment.
+									// [4:3] b01 Data right justified (for YCbCr 422 input modes).
+
+	16'h49A8,					// ADI required Write.
+	16'h4C00,					// ADI required Write.
+
+	{8'h55, 8'b0001_0000},	// [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4].
+									// AVI InfoFrame Valid [4].
+									// Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both.
+									// Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None.
+
+	16'h7301,
+
+	{8'h94, 8'b1000_0000},	// [7]=1 HPD Interrupt ENabled.
+
+	16'h9902,					// ADI required Write.
+	16'h9B18,					// ADI required Write.
+
+	16'h9F00,					// ADI required Write.
+
+	{8'hA1, 8'b0000_0000},	// [6]=1 Monitor Sense Power Down DISabled.
+	
+	16'hA408,					// ADI required Write.
+	16'hA504,					// ADI required Write.
+	16'hA600,					// ADI required Write.
+	16'hA700,					// ADI required Write.
+	16'hA800,					// ADI required Write.
+	16'hA900,					// ADI required Write.
+	16'hAA00,					// ADI required Write.
+	16'hAB40,					// ADI required Write.
+	
+	{8'hAF, 6'b0000_01,~dvi_mode,1'b0},	// [7]=0 HDCP Disabled.
+									// [6:5] must be b00!
+									// [4]=0 Current frame is unencrypted
+									// [3:2] must be b01!
+									//	[1]=1 HDMI Mode.
+									// [0] must be b0!
+
+	16'hB900,					// ADI required Write.
+
+	{8'hBA, 8'b0110_0000},	// [7:5] Input Clock delay...
+									// b000 = -1.2ns.
+									// b001 = -0.8ns.
+									// b010 = -0.4ns.
+									// b011 = No delay.
+									// b100 = 0.4ns.
+									// b101 = 0.8ns.
+									// b110 = 1.2ns.
+									// b111 = 1.6ns.
+					
+	16'hBB00,					// ADI required Write.
+	
+	16'hDE9C,					// ADI required Write.
+	16'hE460,					// ADI required Write.
+	16'hFA7D,					// Nbr of times to search for good phase
+
+	
+									// (Audio stuff on Programming Guide, Page 66)...
+	
+	{8'h0A, 8'b0000_0000},	// [6:4] Audio Select. b000 = I2S.
+									// [3:2] Audio Mode. (HBR stuff, leave at 00!).
+
+	{8'h0B, 8'b0000_1110},	//
+									
+	{8'h0C, 8'b0000_0100},	// [7] 0 = Use sampling rate from I2S stream.   1 = Use samp rate from I2C Register.
+									// [6] 0 = Use Channel Status bits from stream. 1 = Use Channel Status bits from I2C register.
+									// [2] 1 = I2S0 Enable.
+									// [1:0] I2S Format: 00 = Standard. 01 = Right Justified. 10 = Left Justified. 11 = AES.
+									
+	{8'h0D, 8'b0001_0000},	// [4:0] I2S Bit (Word) Width for Right-Justified.
+	{8'h14, 8'b0000_0010},	// [3:0] Audio Word Length. b0010 = 16 bits.
+	{8'h15, audio_96k, 7'b010_0000},	// I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
+									// Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs.
+
+	// Audio Clock Config
+	16'h0100,					//  
+	audio_96k ? 16'h0230 : 16'h0218,	// Set N Value 12288/6144
+	16'h0300,					//
+
+	16'h0701,					//
+	16'h0822,					// Set CTS Value 74250
+	16'h090A,					//
+
+	16'hFFFF 				   // END
+};
+
+////////////////////////////////////////////////////////////////////
+
+endmodule
\ No newline at end of file
diff --git a/sys/hps_io.v b/sys/hps_io.v
new file mode 100644
index 0000000..1003bbd
--- /dev/null
+++ b/sys/hps_io.v
@@ -0,0 +1,734 @@
+//
+// hps_io.v
+//
+// mist_io-like module for MiSTer
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+// Copyright (c) 2017,2018 Sorgelig
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+///////////////////////////////////////////////////////////////////////
+
+//
+// Use buffer to access SD card. It's time-critical part.
+//
+// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
+// clk_ps2 = CLK_SYS/(PS2DIV*2)
+//
+
+// WIDE=1 for 16 bit file I/O
+// VDNUM 1-4
+module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
+(
+	input             clk_sys,
+	inout      [44:0] HPS_BUS,
+
+	// parameter STRLEN and the actual length of conf_str have to match
+	input [(8*STRLEN)-1:0] conf_str,
+
+	output reg [15:0] joystick_0,
+	output reg [15:0] joystick_1,
+	output reg [15:0] joystick_2,
+	output reg [15:0] joystick_3,
+	output reg [15:0] joystick_4,
+	output reg [15:0] joystick_5,
+	output reg [15:0] joystick_analog_0,
+	output reg [15:0] joystick_analog_1,
+	output reg [15:0] joystick_analog_2,
+	output reg [15:0] joystick_analog_3,
+	output reg [15:0] joystick_analog_4,
+	output reg [15:0] joystick_analog_5,
+
+	output      [1:0] buttons,
+	output            forced_scandoubler,
+
+	output reg [31:0] status,
+	input      [31:0] status_in,
+	input             status_set,
+
+	//toggle to force notify of video mode change
+	input             new_vmode,
+
+	// SD config
+	output reg [VD:0] img_mounted,  // signaling that new image has been mounted
+	output reg        img_readonly, // mounted as read only. valid only for active bit in img_mounted
+	output reg [63:0] img_size,     // size of image in bytes. valid only for active bit in img_mounted
+
+	// SD block level access
+	input      [31:0] sd_lba,
+	input      [VD:0] sd_rd,       // only single sd_rd can be active at any given time
+	input      [VD:0] sd_wr,       // only single sd_wr can be active at any given time
+	output reg        sd_ack,
+
+	// do not use in new projects.
+	// CID and CSD are fake except CSD image size field.
+	input             sd_conf,
+	output reg        sd_ack_conf,
+
+	// SD byte level access. Signals for 2-PORT altsyncram.
+	output reg [AW:0] sd_buff_addr,
+	output reg [DW:0] sd_buff_dout,
+	input      [DW:0] sd_buff_din,
+	output reg        sd_buff_wr,
+
+	// ARM -> FPGA download
+	output reg        ioctl_download = 0, // signal indicating an active download
+	output reg  [7:0] ioctl_index,        // menu index used to upload the file
+	output reg        ioctl_wr,
+	output reg [24:0] ioctl_addr,         // in WIDE mode address will be incremented by 2
+	output reg [DW:0] ioctl_dout,
+	output reg [31:0] ioctl_file_ext,
+	input             ioctl_wait,
+
+	// RTC MSM6242B layout
+	output reg [64:0] RTC,
+
+	// Seconds since 1970-01-01 00:00:00
+	output reg [32:0] TIMESTAMP,
+
+	// UART flags
+	input      [15:0] uart_mode,
+
+	// ps2 keyboard emulation
+	output            ps2_kbd_clk_out,
+	output            ps2_kbd_data_out,
+	input             ps2_kbd_clk_in,
+	input             ps2_kbd_data_in,
+
+	input       [2:0] ps2_kbd_led_status,
+	input       [2:0] ps2_kbd_led_use,
+
+	output            ps2_mouse_clk_out,
+	output            ps2_mouse_data_out,
+	input             ps2_mouse_clk_in,
+	input             ps2_mouse_data_in,
+
+	// ps2 alternative interface.
+
+	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
+	output reg [10:0] ps2_key = 0,
+
+	// [24] - toggles with every event
+	output reg [24:0] ps2_mouse = 0
+);
+
+localparam DW = (WIDE) ? 15 : 7;
+localparam AW = (WIDE) ?  7 : 8;
+localparam VD = VDNUM-1;
+
+wire        io_wait  = ioctl_wait;
+wire        io_enable= |HPS_BUS[35:34];
+wire        io_strobe= HPS_BUS[33];
+wire        io_wide  = (WIDE) ? 1'b1 : 1'b0;
+wire [15:0] io_din   = HPS_BUS[31:16];
+reg  [15:0] io_dout;
+
+assign HPS_BUS[37]   = io_wait;
+assign HPS_BUS[36]   = clk_sys;
+assign HPS_BUS[32]   = io_wide;
+assign HPS_BUS[15:0] = io_dout;
+
+reg [7:0] cfg;
+assign buttons = cfg[1:0];
+//cfg[2] - vga_scaler handled in sys_top
+//cfg[3] - csync handled in sys_top
+assign forced_scandoubler = cfg[4];
+//cfg[5] - ypbpr handled in sys_top
+
+// command byte read by the io controller
+wire [15:0] sd_cmd =
+{
+	2'b00,
+	(VDNUM>=4) ? sd_wr[3] : 1'b0,
+	(VDNUM>=3) ? sd_wr[2] : 1'b0,
+	(VDNUM>=2) ? sd_wr[1] : 1'b0,
+
+	(VDNUM>=4) ? sd_rd[3] : 1'b0,
+	(VDNUM>=3) ? sd_rd[2] : 1'b0,
+	(VDNUM>=2) ? sd_rd[1] : 1'b0,
+
+	4'h5, sd_conf, 1'b1,
+	sd_wr[0],
+	sd_rd[0]
+};
+
+///////////////// calc video parameters //////////////////
+
+wire clk_100 = HPS_BUS[43];
+wire clk_vid = HPS_BUS[42];
+wire ce_pix  = HPS_BUS[41];
+wire de      = HPS_BUS[40];
+wire hs      = HPS_BUS[39];
+wire vs      = HPS_BUS[38];
+wire vs_hdmi = HPS_BUS[44];
+
+reg [31:0] vid_hcnt = 0;
+reg [31:0] vid_vcnt = 0;
+reg  [7:0] vid_nres = 0;
+integer hcnt;
+
+always @(posedge clk_vid) begin
+	integer vcnt;
+	reg old_vs= 0, old_de = 0, old_vmode = 0;
+	reg calch = 0;
+
+	if(ce_pix) begin
+		old_vs <= vs;
+		old_de <= de;
+
+		if(~vs & ~old_de & de) vcnt <= vcnt + 1;
+		if(calch & de) hcnt <= hcnt + 1;
+		if(old_de & ~de) calch <= 0;
+
+		if(old_vs & ~vs) begin
+			if(hcnt && vcnt) begin
+				old_vmode <= new_vmode;
+				if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) vid_nres <= vid_nres + 1'd1;
+				vid_hcnt <= hcnt;
+				vid_vcnt <= vcnt;
+			end
+			vcnt <= 0;
+			hcnt <= 0;
+			calch <= 1;
+		end
+	end
+end
+
+reg [31:0] vid_htime = 0;
+reg [31:0] vid_vtime = 0;
+reg [31:0] vid_pix = 0;
+
+always @(posedge clk_100) begin
+	integer vtime, htime, hcnt;
+	reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2;
+	reg calch = 0;
+
+	old_vs <= vs;
+	old_hs <= hs;
+
+	old_vs2 <= old_vs;
+	old_hs2 <= old_hs;
+
+	vtime <= vtime + 1'd1;
+	htime <= htime + 1'd1;
+
+	if(~old_vs2 & old_vs) begin
+		vid_pix <= hcnt;
+		vid_vtime <= vtime;
+		vtime <= 0;
+		hcnt <= 0;
+	end
+
+	if(old_vs2 & ~old_vs) calch <= 1;
+
+	if(~old_hs2 & old_hs) begin
+		vid_htime <= htime;
+		htime <= 0;
+	end
+
+	old_de   <= de;
+	old_de2  <= old_de;
+
+	if(calch & old_de) hcnt <= hcnt + 1;
+	if(old_de2 & ~old_de) calch <= 0;
+end
+
+reg [31:0] vid_vtime_hdmi;
+always @(posedge clk_100) begin
+	integer vtime;
+	reg old_vs, old_vs2;
+
+	old_vs <= vs_hdmi;
+	old_vs2 <= old_vs;
+
+	vtime <= vtime + 1'd1;
+
+	if(~old_vs2 & old_vs) begin
+		vid_vtime_hdmi <= vtime;
+		vtime <= 0;
+	end
+end
+
+
+/////////////////////////////////////////////////////////
+
+reg [31:0] ps2_key_raw = 0;
+wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
+wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
+
+always@(posedge clk_sys) begin
+	reg [15:0] cmd;
+	reg  [9:0] byte_cnt;   // counts bytes
+	reg  [2:0] b_wr;
+	reg  [2:0] stick_idx;
+	reg        ps2skip = 0;
+	reg  [3:0] stflg = 0;
+	reg [31:0] status_req;
+	reg        old_status_set = 0;
+
+	old_status_set <= status_set;
+	if(~old_status_set & status_set) begin
+		stflg <= stflg + 1'd1;
+		status_req <= status_in;
+	end
+
+	sd_buff_wr <= b_wr[0];
+	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
+	b_wr <= (b_wr<<1);
+
+	{kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
+
+	if(~io_enable) begin
+		if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
+		if(cmd == 5 && !ps2skip) begin
+			ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
+			if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
+			if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
+			if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
+		end
+		if(cmd == 'h22) RTC[64] <= ~RTC[64];
+		if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
+		cmd <= 0;
+		byte_cnt <= 0;
+		sd_ack <= 0;
+		sd_ack_conf <= 0;
+		io_dout <= 0;
+		ps2skip <= 0;
+	end else begin
+		if(io_strobe) begin
+
+			io_dout <= 0;
+			if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
+
+			if(byte_cnt == 0) begin
+				cmd <= io_din;
+
+				case(io_din)
+					'h19: sd_ack_conf <= 1;
+					'h17,
+					'h18: sd_ack <= 1;
+					'h29: io_dout <= {4'hA, stflg};
+					'h2B: io_dout <= 1;
+				endcase
+
+				sd_buff_addr <= 0;
+				img_mounted <= 0;
+				if(io_din == 5) ps2_key_raw <= 0;
+			end else begin
+
+				case(cmd)
+					// buttons and switches
+					'h01: cfg        <= io_din[7:0];
+					'h02: joystick_0 <= io_din;
+					'h03: joystick_1 <= io_din;
+					'h10: joystick_2 <= io_din;
+					'h11: joystick_3 <= io_din;
+					'h12: joystick_4 <= io_din;
+					'h13: joystick_5 <= io_din;
+
+					// store incoming ps2 mouse bytes
+					'h04: begin
+							mouse_data <= io_din[7:0];
+							mouse_we   <= 1;
+							if(&io_din[15:8]) ps2skip <= 1;
+							if(~&io_din[15:8] & ~ps2skip) begin
+								case(byte_cnt)
+									1: ps2_mouse[7:0]   <= io_din[7:0];
+									2: ps2_mouse[15:8]  <= io_din[7:0];
+									3: ps2_mouse[23:16] <= io_din[7:0];
+								endcase
+							end
+						end
+
+					// store incoming ps2 keyboard bytes
+					'h05: begin
+							if(&io_din[15:8]) ps2skip <= 1;
+							if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
+							kbd_data <= io_din[7:0];
+							kbd_we <= 1;
+						end
+
+					// reading config string, returning a byte from string
+					'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
+
+					// reading sd card status
+					'h16: case(byte_cnt)
+								1: io_dout <= sd_cmd;
+								2: io_dout <= sd_lba[15:0];
+								3: io_dout <= sd_lba[31:16];
+							endcase
+
+					// send SD config IO -> FPGA
+					// flag that download begins
+					// sd card knows data is config if sd_dout_strobe is asserted
+					// with sd_ack still being inactive (low)
+					'h19,
+					// send sector IO -> FPGA
+					// flag that download begins
+					'h17: begin
+							sd_buff_dout <= io_din[DW:0];
+							b_wr <= 1;
+						end
+
+					// reading sd card write data
+					'h18: begin
+							if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
+							io_dout <= sd_buff_din;
+						end
+
+					// joystick analog
+					'h1a: case(byte_cnt)
+								1: stick_idx <= io_din[2:0]; // first byte is joystick index
+								2: case(stick_idx)
+										0: joystick_analog_0 <= io_din;
+										1: joystick_analog_1 <= io_din;
+										2: joystick_analog_2 <= io_din;
+										3: joystick_analog_3 <= io_din;
+										4: joystick_analog_4 <= io_din;
+										5: joystick_analog_5 <= io_din;
+									endcase
+							endcase
+
+					// notify image selection
+					'h1c: begin
+							img_mounted  <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
+							img_readonly <= io_din[7];
+						end
+
+					// send image info
+					'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
+
+					// status, 32bit version
+					'h1e: if(byte_cnt==1) status[15:0] <= io_din;
+								else if(byte_cnt==2) status[31:16] <= io_din;
+
+					// reading keyboard LED status
+					'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
+
+					// reading ps2 keyboard/mouse control
+					'h21: if(byte_cnt == 1) begin
+								io_dout <= kbd_data_host;
+								kbd_rd <= 1;
+							end
+							else
+							if(byte_cnt == 2) begin
+								io_dout <= mouse_data_host;
+								mouse_rd <= 1;
+							end
+					//RTC
+					'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
+
+					//Video res.
+					'h23: case(byte_cnt)
+								1: io_dout <= vid_nres;
+								2: io_dout <= vid_hcnt[15:0];
+								3: io_dout <= vid_hcnt[31:16];
+								4: io_dout <= vid_vcnt[15:0];
+								5: io_dout <= vid_vcnt[31:16];
+								6: io_dout <= vid_htime[15:0];
+								7: io_dout <= vid_htime[31:16];
+								8: io_dout <= vid_vtime[15:0];
+								9: io_dout <= vid_vtime[31:16];
+							  10: io_dout <= vid_pix[15:0];
+							  11: io_dout <= vid_pix[31:16];
+							  12: io_dout <= vid_vtime_hdmi[15:0];
+							  13: io_dout <= vid_vtime_hdmi[31:16];
+							endcase
+
+					//RTC
+					'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
+
+					//UART flags
+					'h28: io_dout <= uart_mode;
+
+					//status set
+					'h29: case(byte_cnt)
+								1: io_dout <= status_req[15:0];
+								2: io_dout <= status_req[31:16];
+							endcase
+				endcase
+			end
+		end
+	end
+end
+
+
+///////////////////////////////   PS2   ///////////////////////////////
+reg clk_ps2;
+always @(negedge clk_sys) begin
+	integer cnt;
+	cnt <= cnt + 1'd1;
+	if(cnt == PS2DIV) begin
+		clk_ps2 <= ~clk_ps2;
+		cnt <= 0;
+	end
+end
+
+reg  [7:0] kbd_data;
+reg        kbd_we;
+wire [8:0] kbd_data_host;
+reg        kbd_rd;
+
+ps2_device keyboard
+(
+	.clk_sys(clk_sys),
+
+	.wdata(kbd_data),
+	.we(kbd_we),
+
+	.ps2_clk(clk_ps2),
+	.ps2_clk_out(ps2_kbd_clk_out),
+	.ps2_dat_out(ps2_kbd_data_out),
+
+	.ps2_clk_in(ps2_kbd_clk_in  || !PS2WE),
+	.ps2_dat_in(ps2_kbd_data_in || !PS2WE),
+
+	.rdata(kbd_data_host),
+	.rd(kbd_rd)
+);
+
+reg  [7:0] mouse_data;
+reg        mouse_we;
+wire [8:0] mouse_data_host;
+reg        mouse_rd;
+
+ps2_device mouse
+(
+	.clk_sys(clk_sys),
+
+	.wdata(mouse_data),
+	.we(mouse_we),
+
+	.ps2_clk(clk_ps2),
+	.ps2_clk_out(ps2_mouse_clk_out),
+	.ps2_dat_out(ps2_mouse_data_out),
+
+	.ps2_clk_in(ps2_mouse_clk_in  || !PS2WE),
+	.ps2_dat_in(ps2_mouse_data_in || !PS2WE),
+
+	.rdata(mouse_data_host),
+	.rd(mouse_rd)
+);
+
+
+///////////////////////////////   DOWNLOADING   ///////////////////////////////
+
+localparam UIO_FILE_TX      = 8'h53;
+localparam UIO_FILE_TX_DAT  = 8'h54;
+localparam UIO_FILE_INDEX   = 8'h55;
+localparam UIO_FILE_INFO    = 8'h56;
+
+always@(posedge clk_sys) begin
+	reg [15:0] cmd;
+	reg  [2:0] cnt;
+	reg        has_cmd;
+	reg [24:0] addr;
+	reg        wr;
+
+	ioctl_wr <= wr;
+	wr <= 0;
+
+	if(~io_enable) has_cmd <= 0;
+	else begin
+		if(io_strobe) begin
+
+			if(!has_cmd) begin
+				cmd <= io_din;
+				has_cmd <= 1;
+				cnt <= 0;
+			end else begin
+
+				case(cmd)
+					UIO_FILE_INFO:
+						if(~cnt[1]) begin
+							case(cnt)
+								0: ioctl_file_ext[31:16] <= io_din;
+								1: ioctl_file_ext[15:00] <= io_din;
+							endcase
+							cnt <= cnt + 1'd1;
+						end
+
+					UIO_FILE_INDEX:
+						begin
+							ioctl_index <= io_din[7:0];
+						end
+
+					UIO_FILE_TX:
+						begin
+							if(io_din[7:0]) begin
+								addr <= 0;
+								ioctl_download <= 1;
+							end else begin
+								ioctl_addr <= addr;
+								ioctl_download <= 0;
+							end
+						end
+
+					UIO_FILE_TX_DAT:
+						begin
+							ioctl_addr <= addr;
+							ioctl_dout <= io_din[DW:0];
+							wr   <= 1;
+							addr <= addr + (WIDE ? 2'd2 : 2'd1);
+						end
+				endcase
+			end
+		end
+	end
+end
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ps2_device #(parameter PS2_FIFO_BITS=5)
+(
+	input        clk_sys,
+
+	input  [7:0] wdata,
+	input        we,
+
+	input        ps2_clk,
+	output reg   ps2_clk_out,
+	output reg   ps2_dat_out,
+	output reg   tx_empty,
+
+	input        ps2_clk_in,
+	input        ps2_dat_in,
+
+	output [8:0] rdata,
+	input        rd
+);
+
+
+(* ramstyle = "logic" *) reg [7:0] fifo[1<<PS2_FIFO_BITS];
+
+reg [PS2_FIFO_BITS-1:0] wptr;
+reg [PS2_FIFO_BITS-1:0] rptr;
+
+reg [2:0] rx_state = 0;
+reg [3:0] tx_state = 0;
+
+reg       has_data;
+reg [7:0] data;
+assign    rdata = {has_data, data};
+
+always@(posedge clk_sys) begin
+	reg [7:0] tx_byte;
+	reg parity;
+	reg r_inc;
+	reg old_clk;
+	reg [1:0] timeout;
+
+	reg [3:0] rx_cnt;
+
+	reg c1,c2,d1;
+
+	tx_empty <= ((wptr == rptr) && (tx_state == 0));
+
+	if(we) begin
+		fifo[wptr] <= wdata;
+		wptr <= wptr + 1'd1;
+	end
+
+	if(rd) has_data <= 0;
+
+	c1 <= ps2_clk_in;
+	c2 <= c1;
+	d1 <= ps2_dat_in;
+	if(!rx_state && !tx_state && ~c2 && c1 && ~d1) begin
+		rx_state <= rx_state + 1'b1;
+		ps2_dat_out <= 1;
+	end
+
+	old_clk <= ps2_clk;
+	if(~old_clk & ps2_clk) begin
+
+		if(rx_state) begin
+			case(rx_state)
+				1: begin
+						rx_state <= rx_state + 1'b1;
+						rx_cnt <= 0;
+					end
+
+				2: begin
+						if(rx_cnt <= 7) data <= {d1, data[7:1]};
+						else rx_state <= rx_state + 1'b1;
+						rx_cnt <= rx_cnt + 1'b1;
+					end
+
+				3: if(d1) begin
+						rx_state <= rx_state + 1'b1;
+						ps2_dat_out <= 0;
+					end
+
+				4: begin
+						ps2_dat_out <= 1;
+						has_data <= 1;
+						rx_state <= 0;
+					end
+			endcase
+		end else begin
+
+			// transmitter is idle?
+			if(tx_state == 0) begin
+				// data in fifo present?
+				if(c2 && c1 && d1 && wptr != rptr) begin
+
+					timeout <= timeout - 1'd1;
+					if(!timeout) begin
+						tx_byte <= fifo[rptr];
+						rptr <= rptr + 1'd1;
+
+						// reset parity
+						parity <= 1;
+
+						// start transmitter
+						tx_state <= 1;
+
+						// put start bit on data line
+						ps2_dat_out <= 0;			// start bit is 0
+					end
+				end
+			end else begin
+
+				// transmission of 8 data bits
+				if((tx_state >= 1)&&(tx_state < 9)) begin
+					ps2_dat_out <= tx_byte[0];	          // data bits
+					tx_byte[6:0] <= tx_byte[7:1]; // shift down
+					if(tx_byte[0])
+						parity <= !parity;
+				end
+
+				// transmission of parity
+				if(tx_state == 9) ps2_dat_out <= parity;
+
+				// transmission of stop bit
+				if(tx_state == 10) ps2_dat_out <= 1;    // stop bit is 1
+
+				// advance state machine
+				if(tx_state < 11) tx_state <= tx_state + 1'd1;
+					else tx_state <= 0;
+			end
+		end
+	end
+
+	if(~old_clk & ps2_clk) ps2_clk_out <= 1;
+	if(old_clk & ~ps2_clk) ps2_clk_out <= ((tx_state == 0) && (rx_state<2));
+
+end
+
+endmodule
diff --git a/sys/hq2x.sv b/sys/hq2x.sv
new file mode 100644
index 0000000..ece54f9
--- /dev/null
+++ b/sys/hq2x.sv
@@ -0,0 +1,385 @@
+//
+//
+// Copyright (c) 2012-2013 Ludvig Strigeus
+// Copyright (c) 2017,2018 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+
+module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	input             clk,
+	input             ce_x4,
+	input  [DWIDTH:0] inputpixel,
+	input             mono,
+	input             disable_hq2x,
+	input             reset_frame,
+	input             reset_line,
+	input       [1:0] read_y,
+	input             hblank,
+	output [DWIDTH:0] outpixel
+);
+
+
+localparam AWIDTH = $clog2(LENGTH)-1;
+localparam DWIDTH = HALF_DEPTH ? 11 : 23;
+localparam DWIDTH1 = DWIDTH+1;
+
+wire [5:0] hqTable[256] = '{
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
+};
+
+reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
+reg [23:0] A, B, D, F, G, H;
+reg  [7:0] pattern, nextpatt;
+reg  [1:0] cyc;
+
+reg  curbuf;
+reg  prevbuf = 0;
+wire iobuf = !curbuf;
+
+wire diff0, diff1;
+DiffCheck diffcheck0(Curr1, (cyc == 0) ? Prev0 : (cyc == 1) ? Curr0 : (cyc == 2) ? Prev2 : Next1, diff0);
+DiffCheck diffcheck1(Curr1, (cyc == 0) ? Prev1 : (cyc == 1) ? Next0 : (cyc == 2) ? Curr2 : Next2, diff1);
+
+wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
+
+wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
+wire [23:0] blend_result_pre;
+Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result_pre);
+
+wire [DWIDTH:0] Curr20tmp;
+wire     [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
+wire [DWIDTH:0] Curr21tmp;
+wire     [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp;
+
+reg  [AWIDTH:0] wrin_addr2;
+reg  [DWIDTH:0] wrpix;
+reg             wrin_en;
+
+function [23:0] h2rgb;
+	input [11:0] v;
+begin
+	h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]};
+end
+endfunction
+
+function [11:0] rgb2h;
+	input [23:0] v;
+begin
+	rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]};
+end
+endfunction
+
+hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
+(
+	.clk(clk),
+
+	.rdaddr(offs),
+	.rdbuf0(prevbuf),
+	.rdbuf1(curbuf),
+	.q0(Curr20tmp),
+	.q1(Curr21tmp),
+
+	.wraddr(wrin_addr2),
+	.wrbuf(iobuf),
+	.data(wrpix),
+	.wren(wrin_en)
+);
+
+reg     [AWIDTH+1:0] read_x;
+reg     [AWIDTH+1:0] wrout_addr; 
+reg                  wrout_en;
+reg  [DWIDTH1*4-1:0] wrdata, wrdata_pre;
+wire [DWIDTH1*4-1:0] outpixel_x4;
+reg  [DWIDTH1*2-1:0] outpixel_x2;
+
+assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0];
+
+hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out
+(
+	.clock(clk),
+
+	.rdaddress({read_x[AWIDTH+1:1],read_y[1]}),
+	.q(outpixel_x4),
+
+	.data(wrdata),
+	.wraddress(wrout_addr),
+	.wren(wrout_en)
+);
+
+wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
+
+reg [AWIDTH:0] offs;
+always @(posedge clk) begin
+	reg old_reset_line;
+	reg old_reset_frame;
+
+	wrout_en <= 0;
+	wrin_en  <= 0;
+
+	if(ce_x4) begin
+
+		pattern <= new_pattern;
+		if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
+
+		if(~&offs) begin
+			if (cyc == 1) begin
+				Prev2 <= Curr20;
+				Curr2 <= Curr21;
+				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
+				wrpix <= inputpixel;
+				wrin_addr2 <= offs;
+				wrin_en <= 1;
+			end
+
+			case({cyc[1],^cyc})
+				0: wrdata[DWIDTH:0]                   <= blend_result;
+				1: wrdata[DWIDTH1+DWIDTH:DWIDTH1]     <= blend_result;
+				2: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
+				3: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
+			endcase
+
+			if(cyc==3) begin
+				offs <= offs + 1'd1;
+				wrout_addr <= {offs, curbuf};
+				wrout_en <= 1;
+			end
+		end
+
+		if(cyc==3) begin
+			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
+			{A, G} <= {Prev0, Next0};
+			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
+			{Prev0, Prev1} <= {Prev1, Prev2};
+			{Curr0, Curr1} <= {Curr1, Curr2};
+			{Next0, Next1} <= {Next1, Next2};
+		end else begin
+			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
+			{B, F, H, D} <= {F, H, D, B};
+		end
+
+		cyc <= cyc + 1'b1;
+		if(old_reset_line && ~reset_line) begin
+			old_reset_frame <= reset_frame;
+			offs <= 0;
+			cyc <= 0;
+			curbuf <= ~curbuf;
+			prevbuf <= curbuf;
+			{Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0;
+			if(old_reset_frame & ~reset_frame) begin
+				curbuf <= 0;
+				prevbuf <= 0;
+			end
+		end
+		
+		if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
+		if(hblank) read_x <= 0;
+
+		old_reset_line  <= reset_line;
+	end
+end
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module hq2x_in #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input            rdbuf0, rdbuf1,
+	output[DWIDTH:0] q0,q1,
+
+	input [AWIDTH:0] wraddr,
+	input            wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = $clog2(LENGTH)-1;
+	wire  [DWIDTH:0] out[2];
+	assign q0 = out[rdbuf0];
+	assign q1 = out[rdbuf1];
+
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+endmodule
+
+module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
+(
+	input                   clock,
+	input        [DWIDTH:0] data,
+	input        [AWIDTH:0] rdaddress,
+	input        [AWIDTH:0] wraddress,
+	input                   wren,
+	output logic [DWIDTH:0] q
+);
+
+logic [DWIDTH:0] ram[0:NUMWORDS-1];
+
+always_ff@(posedge clock) begin
+	if(wren) ram[wraddress] <= data;
+	q <= ram[rdaddress];
+end
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module DiffCheck
+(
+	input [23:0] rgb1,
+	input [23:0] rgb2,
+	output result
+);
+
+	wire [7:0] r = rgb1[7:1]   - rgb2[7:1];
+	wire [7:0] g = rgb1[15:9]  - rgb2[15:9];
+	wire [7:0] b = rgb1[23:17] - rgb2[23:17];
+	wire [8:0] t = $signed(r) + $signed(b);
+	wire [8:0] gx = {g[7], g};
+	wire [9:0] y = $signed(t) + $signed(gx);
+	wire [8:0] u = $signed(r) - $signed(b);
+	wire [9:0] v = $signed({g, 1'b0}) - $signed(t);
+
+	// if y is inside (-96..96)
+	wire y_inside = (y < 10'h60 || y >= 10'h3a0);
+
+	// if u is inside (-16, 16)
+	wire u_inside = (u < 9'h10 || u >= 9'h1f0);
+
+	// if v is inside (-24, 24)
+	wire v_inside = (v < 10'h18 || v >= 10'h3e8);
+	assign result = !(y_inside && u_inside && v_inside);
+endmodule
+
+module InnerBlend
+(
+	input  [8:0] Op,
+	input  [7:0] A,
+	input  [7:0] B,
+	input  [7:0] C,
+	output [7:0] O
+);
+
+	function  [10:0] mul8x3;
+		input   [7:0] op1;
+		input   [2:0] op2;
+	begin
+		mul8x3 = 11'd0;
+		if(op2[0]) mul8x3 = mul8x3 + op1;
+		if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0};
+		if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00};
+	end
+	endfunction
+
+	wire OpOnes = Op[4];
+	wire [10:0] Amul = mul8x3(A, Op[7:5]);
+	wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0});
+	wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0});
+	wire [10:0] At =  Amul;
+	wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
+	wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
+	wire [11:0] Res = {At, 1'b0} + Bt + Ct;
+	assign O = Op[8] ? A : Res[11:4];
+endmodule
+
+module Blend
+(
+	input   [5:0] rule,
+	input         disable_hq2x,
+	input  [23:0] E,
+	input  [23:0] A,
+	input  [23:0] B,
+	input  [23:0] D,
+	input  [23:0] F,
+	input  [23:0] H,
+	output [23:0] Result
+);
+
+	reg [1:0] input_ctrl;
+	reg [8:0] op;
+	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
+	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
+	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
+	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
+	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
+	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
+	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
+	localparam AB = 2'b00;
+	localparam AD = 2'b01;
+	localparam DB = 2'b10;
+	localparam BD = 2'b11;
+	wire is_diff;
+	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
+
+	always @* begin
+		case({!is_diff, rule[5:2]})
+			1,17:  {op, input_ctrl} = {BLEND1, AB};
+			2,18:  {op, input_ctrl} = {BLEND1, DB};
+			3,19:  {op, input_ctrl} = {BLEND1, BD};
+			4,20:  {op, input_ctrl} = {BLEND2, DB};
+			5,21:  {op, input_ctrl} = {BLEND2, AB};
+			6,22:  {op, input_ctrl} = {BLEND2, AD};
+
+			 8: {op, input_ctrl} = {BLEND0, 2'bxx};
+			 9: {op, input_ctrl} = {BLEND0, 2'bxx};
+			10: {op, input_ctrl} = {BLEND0, 2'bxx};
+			11: {op, input_ctrl} = {BLEND1, AB};
+			12: {op, input_ctrl} = {BLEND1, AB};
+			13: {op, input_ctrl} = {BLEND1, AB};
+			14: {op, input_ctrl} = {BLEND1, DB};
+			15: {op, input_ctrl} = {BLEND1, BD};
+
+			24: {op, input_ctrl} = {BLEND2, DB};
+			25: {op, input_ctrl} = {BLEND5, DB};
+			26: {op, input_ctrl} = {BLEND6, DB};
+			27: {op, input_ctrl} = {BLEND2, DB};
+			28: {op, input_ctrl} = {BLEND4, DB};
+			29: {op, input_ctrl} = {BLEND5, DB};
+			30: {op, input_ctrl} = {BLEND3, BD};
+			31: {op, input_ctrl} = {BLEND3, DB};
+			default: {op, input_ctrl} = {11{1'bx}};
+		endcase
+
+		// Setting op[8] effectively disables HQ2X because blend will always return E.
+		if (disable_hq2x) op[8] = 1;
+	end
+
+	// Generate inputs to the inner blender. Valid combinations.
+	// 00: E A B
+	// 01: E A D 
+	// 10: E D B
+	// 11: E B D
+	wire [23:0] Input1 = E;
+	wire [23:0] Input2 = !input_ctrl[1] ? A :
+                        !input_ctrl[0] ? D : B;
+
+	wire [23:0] Input3 = !input_ctrl[0] ? B : D;
+	InnerBlend inner_blend1(op, Input1[7:0],   Input2[7:0],   Input3[7:0],   Result[7:0]);
+	InnerBlend inner_blend2(op, Input1[15:8],  Input2[15:8],  Input3[15:8],  Result[15:8]);
+	InnerBlend inner_blend3(op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]);
+endmodule
diff --git a/sys/i2c.v b/sys/i2c.v
new file mode 100644
index 0000000..ace6293
--- /dev/null
+++ b/sys/i2c.v
@@ -0,0 +1,69 @@
+
+module i2c
+(
+	input        CLK,
+
+	input        START,
+	input [23:0] I2C_DATA,
+	output reg   END = 1,
+	output reg   ACK = 0,
+
+	//I2C bus
+	output       I2C_SCL,
+ 	inout        I2C_SDA
+);
+
+
+//	Clock Setting
+parameter CLK_Freq = 50_000_000;	//	50 MHz
+parameter I2C_Freq = 400_000;		//	400 KHz
+
+reg I2C_CLOCK;
+always@(negedge CLK) begin
+	integer mI2C_CLK_DIV = 0;
+	if(mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)) begin
+		mI2C_CLK_DIV <= mI2C_CLK_DIV + 1;
+	end else	begin
+		mI2C_CLK_DIV <= 0;
+		I2C_CLOCK    <= ~I2C_CLOCK;
+	end
+end
+
+assign I2C_SCL = SCLK | I2C_CLOCK;
+assign I2C_SDA = SDO  ? 1'bz : 1'b0;
+
+reg SCLK = 1, SDO = 1;
+
+always @(posedge CLK) begin
+	reg old_clk;
+	reg old_st;
+
+	reg  [5:0] SD_COUNTER = 'b111111;
+	reg [0:31] SD;
+
+	old_clk <= I2C_CLOCK;
+	old_st  <= START;
+
+	if(~old_st && START) begin
+		SCLK <= 1;
+		SDO  <= 1;
+		ACK  <= 0;
+		END  <= 0;
+		SD   <= {2'b10, I2C_DATA[23:16], 1'b1, I2C_DATA[15:8], 1'b1, I2C_DATA[7:0], 4'b1011};
+		SD_COUNTER <= 0;
+	end else begin
+		if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin
+			SD_COUNTER <= SD_COUNTER + 6'd1;	
+			case(SD_COUNTER)
+				      01: SCLK <= 0;
+				10,19,28: ACK  <= ACK | I2C_SDA;
+				      29: SCLK <= 1;
+				      32: END  <= 1;
+			endcase
+		end
+
+		if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO <= SD[SD_COUNTER[4:0]];
+	end
+end
+
+endmodule
diff --git a/sys/i2s.v b/sys/i2s.v
new file mode 100644
index 0000000..b4c2d95
--- /dev/null
+++ b/sys/i2s.v
@@ -0,0 +1,136 @@
+
+module i2s
+#(
+	parameter CLK_RATE   = 50000000,
+	parameter AUDIO_DW   = 16,
+	parameter AUDIO_RATE = 96000
+)
+(
+	input      reset,
+	input      clk_sys,
+	input      half_rate,
+
+	output reg sclk,
+	output reg lrclk,
+	output reg sdata,
+
+	input [AUDIO_DW-1:0]	left_chan,
+	input [AUDIO_DW-1:0]	right_chan
+);
+
+localparam WHOLE_CYCLES          = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
+localparam ERROR_BASE            = 10000;
+localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
+
+reg lpf_ce;
+wire [AUDIO_DW-1:0] al, ar;
+
+lpf_i2s lpf_l
+(
+   .CLK(clk_sys),
+   .CE(lpf_ce),
+   .IDATA(left_chan),
+   .ODATA(al)
+);
+
+lpf_i2s lpf_r
+(
+   .CLK(clk_sys),
+   .CE(lpf_ce),
+
+   .IDATA(right_chan),
+   .ODATA(ar)
+);
+
+always @(posedge clk_sys) begin
+	reg [31:0] count_q;
+	reg [31:0] error_q;
+	reg  [7:0] bit_cnt;
+	reg        skip = 0;
+
+	reg [AUDIO_DW-1:0] left;
+	reg [AUDIO_DW-1:0] right;
+
+	reg msclk;
+	reg ce;
+	
+	lpf_ce <= 0;
+
+	if (reset) begin
+		count_q   <= 0;
+		error_q   <= 0;
+		ce        <= 0;
+		bit_cnt   <= 1;
+		lrclk     <= 1;
+		sclk      <= 1;
+		msclk     <= 1;
+	end
+	else
+	begin
+		if(count_q == WHOLE_CYCLES-1) begin
+			if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0];
+				count_q <= 0;
+			end else begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
+				count_q <= count_q + 1;
+			end
+		end else if(count_q == WHOLE_CYCLES) begin
+			count_q <= 0;
+		end else begin
+			count_q <= count_q + 1;
+		end
+
+		sclk <= msclk;
+		if(!count_q) begin
+			ce <= ~ce;
+			if(~half_rate || ce) begin
+				msclk <= ~msclk;
+				if(msclk) begin
+					skip <= ~skip;
+					if(skip) lpf_ce <= 1;
+					if(bit_cnt >= AUDIO_DW) begin
+						bit_cnt <= 1;
+						lrclk <= ~lrclk;
+						if(lrclk) begin
+							left  <= al;
+							right <= ar;
+						end
+					end
+					else begin
+						bit_cnt <= bit_cnt + 1'd1;
+					end
+					sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
+				end
+			end
+		end
+	end
+end
+
+endmodule
+
+module lpf_i2s
+(
+   input         CLK,
+   input         CE,
+   input  [15:0] IDATA,
+   output reg [15:0] ODATA
+);
+
+reg [511:0] acc;
+reg [20:0] sum;
+
+always @(*) begin
+	integer i;
+	sum = 0;
+	for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
+end
+
+always @(posedge CLK) begin
+	if(CE) begin
+		acc <= {acc[495:0], IDATA};
+		ODATA <= sum[20:5];
+	end
+end
+
+endmodule
diff --git a/sys/osd.v b/sys/osd.v
new file mode 100644
index 0000000..81939c6
--- /dev/null
+++ b/sys/osd.v
@@ -0,0 +1,195 @@
+// A simple OSD implementation. Can be hooked up between a cores
+// VGA output and the physical VGA pins
+
+module osd
+(
+	input         clk_sys,
+
+	input         io_osd,
+	input         io_strobe,
+	input  [15:0] io_din,
+
+	input         clk_video,
+	input  [23:0] din,
+	output [23:0] dout,
+	input         de_in,
+	output reg    de_out,
+	output reg    osd_status
+);
+
+parameter  OSD_COLOR    =  3'd4;
+parameter  OSD_X_OFFSET = 12'd0;
+parameter  OSD_Y_OFFSET = 12'd0;
+
+localparam OSD_WIDTH    = 12'd256;
+localparam OSD_HEIGHT   = 12'd64;
+
+reg        osd_enable;
+reg  [7:0] osd_buffer[4096];
+
+reg        info = 0;
+reg  [8:0] infoh;
+reg  [8:0] infow;
+reg [11:0] infox;
+reg [21:0] infoy;
+reg [21:0] hrheight;
+
+always@(posedge clk_sys) begin
+	reg [11:0] bcnt;
+	reg  [7:0] cmd;
+	reg        has_cmd;
+	reg        old_strobe;
+	reg        highres = 0;
+
+	hrheight <= info ? infoh : (OSD_HEIGHT<<highres);
+
+	old_strobe <= io_strobe;
+
+	if(~io_osd) begin
+		bcnt <= 0;
+		has_cmd <= 0;
+		cmd <= 0;
+		if(cmd[7:4] == 4) osd_enable <= cmd[0];
+	end else begin
+		if(~old_strobe & io_strobe) begin
+			if(!has_cmd) begin
+				has_cmd <= 1;
+				cmd <= io_din[7:0];
+				// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+				if(io_din[7:4] == 4) begin
+					if(!io_din[0]) {osd_status,highres} <= 0;
+					else {osd_status,info} <= {~io_din[2],io_din[2]};
+					bcnt <= 0;
+				end
+				// command 0x20: OSDCMDWRITE
+				if(io_din[7:4] == 2) begin
+					if(io_din[3]) highres <= 1;
+					bcnt <= {io_din[3:0], 8'h00};
+				end
+			end else begin
+				// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+				if(cmd[7:4] == 4) begin
+					if(bcnt == 0) infox <= io_din[11:0];
+					if(bcnt == 1) infoy <= io_din[11:0];
+					if(bcnt == 2) infow <= {io_din[5:0], 3'b000};
+					if(bcnt == 3) infoh <= {io_din[5:0], 3'b000};
+				end
+
+				// command 0x20: OSDCMDWRITE
+				if(cmd[7:4] == 2) osd_buffer[bcnt] <= io_din[7:0];
+
+				bcnt <= bcnt + 1'd1;
+			end
+		end
+	end
+end
+
+reg ce_pix;
+always @(negedge clk_video) begin
+	integer cnt = 0;
+	integer pixsz, pixcnt;
+	reg deD;
+
+	cnt <= cnt + 1;
+	deD <= de_in;
+
+	pixcnt <= pixcnt + 1;
+	if(pixcnt == pixsz) pixcnt <= 0;
+	ce_pix <= !pixcnt;
+
+	if(~deD && de_in) cnt <= 0;
+
+	if(deD && ~de_in) begin
+		pixsz  <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0;
+		pixcnt <= 0;
+	end
+end
+
+reg [2:0] osd_de;
+reg       osd_pixel;
+
+always @(posedge clk_video) begin
+	reg        deD;
+	reg  [1:0] osd_div;
+	reg  [1:0] multiscan;
+	reg  [7:0] osd_byte; 
+	reg [23:0] h_cnt;
+	reg [21:0] v_cnt;
+	reg [21:0] dsp_width;
+	reg [21:0] osd_vcnt;
+	reg [21:0] h_osd_start;
+	reg [21:0] v_osd_start;
+	reg [21:0] osd_hcnt;
+	reg        osd_de1,osd_de2;
+	reg  [1:0] osd_en;
+
+	if(ce_pix) begin
+
+		deD <= de_in;
+		if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
+
+		if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1;
+		if (h_cnt == h_osd_start) begin
+			osd_de[0] <= osd_en[1] && hrheight && (osd_vcnt < hrheight);
+			osd_hcnt <= 0;
+		end
+		if (osd_hcnt+1 == (info ? infow : OSD_WIDTH)) osd_de[0] <= 0;
+
+		// falling edge of de
+		if(!de_in && deD) dsp_width <= h_cnt[21:0];
+
+		// rising edge of de
+		if(de_in && !deD) begin
+			h_cnt <= 0;
+			v_cnt <= v_cnt + 1'd1;
+			h_osd_start <= info ? infox : (((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET - 2'd2);
+
+			if(h_cnt > {dsp_width, 2'b00}) begin
+				v_cnt <= 0;
+
+				osd_en <= (osd_en << 1) | osd_enable;
+				if(~osd_enable) osd_en <= 0;
+
+				if(v_cnt<320) begin
+					multiscan <= 0;
+					v_osd_start <= info ? infoy : (((v_cnt-hrheight)>>1) + OSD_Y_OFFSET);
+				end
+				else if(v_cnt<640) begin
+					multiscan <= 1;
+					v_osd_start <= info ? (infoy<<1) : (((v_cnt-(hrheight<<1))>>1) + OSD_Y_OFFSET);
+				end
+				else if(v_cnt<960) begin
+					multiscan <= 2;
+					v_osd_start <= info ? (infoy + (infoy << 1)) : (((v_cnt-(hrheight + (hrheight<<1)))>>1) + OSD_Y_OFFSET);
+				end
+				else begin
+					multiscan <= 3;
+					v_osd_start <= info ? (infoy<<2) : (((v_cnt-(hrheight<<2))>>1) + OSD_Y_OFFSET);
+				end
+			end
+
+			osd_div <= osd_div + 1'd1;
+			if(osd_div == multiscan) begin
+				osd_div <= 0;
+				if(~&osd_vcnt) osd_vcnt <= osd_vcnt + 1'd1;
+			end
+			if(v_osd_start == (v_cnt+1'b1)) {osd_div, osd_vcnt} <= 0;
+		end
+
+		osd_byte  <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}];
+		osd_pixel <= osd_byte[osd_vcnt[2:0]];
+		osd_de[2:1] <= osd_de[1:0];
+	end
+end
+
+reg [23:0] rdout;
+assign dout = rdout;
+
+always @(posedge clk_video) begin
+	rdout <= ~osd_de[2] ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
+	                             {osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
+	                             {osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
+	de_out <= de_in;
+end
+
+endmodule
diff --git a/sys/pll.qip b/sys/pll.qip
new file mode 100644
index 0000000..9305b9f
--- /dev/null
+++ b/sys/pll.qip
@@ -0,0 +1,337 @@
+set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjQuMTky::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MzE=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTIuMDk2::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NjI=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::Ni4wNDg=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MzA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MjQ4::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::My4wMjQ=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MzA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::NDk2::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::NDguMzg0::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MzA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MzE=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjQuMTkzNTQ4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTIuMDk2Nzc0IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::OCw3LDI1NiwyNTYsZmFsc2UsdHJ1ZSx0cnVlLGZhbHNlLDE2LDE1LDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsMzEsMzEsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMSwyMCw0MDAwLDc1MC4wIE1IeiwxLG5vbmUsZ2xiLG1fY250LHBoX211eF9jbGssZmFsc2U=::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+
+set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
+set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
+set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"]
+
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim"
diff --git a/sys/pll.v b/sys/pll.v
new file mode 100644
index 0000000..af8eed1
--- /dev/null
+++ b/sys/pll.v
@@ -0,0 +1,255 @@
+// megafunction wizard: %Altera PLL v17.1%
+// GENERATION: XML
+// pll.v
+
+// Generated using ACDS version 17.1 590
+
+`timescale 1 ps / 1 ps
+module pll (
+		input  wire  refclk,   //  refclk.clk
+		input  wire  rst,      //   reset.reset
+		output wire  outclk_0, // outclk0.clk
+		output wire  outclk_1, // outclk1.clk
+		output wire  locked    //  locked.export
+	);
+
+	pll_0002 pll_inst (
+		.refclk   (refclk),   //  refclk.clk
+		.rst      (rst),      //   reset.reset
+		.outclk_0 (outclk_0), // outclk0.clk
+		.outclk_1 (outclk_1), // outclk1.clk
+		.locked   (locked)    //  locked.export
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2019 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_pll" version="17.1" >
+// Retrieval info: 	<generic name="debug_print_output" value="false" />
+// Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
+// Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
+// Retrieval info: 	<generic name="gui_device_speed_grade" value="1" />
+// Retrieval info: 	<generic name="gui_pll_mode" value="Integer-N PLL" />
+// Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
+// Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
+// Retrieval info: 	<generic name="gui_operation_mode" value="direct" />
+// Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
+// Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
+// Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
+// Retrieval info: 	<generic name="gui_use_locked" value="true" />
+// Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
+// Retrieval info: 	<generic name="gui_number_of_clocks" value="2" />
+// Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
+// Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
+// Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
+// Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="24.192" />
+// Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="12.096" />
+// Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift1" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg1" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="6.048" />
+// Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency3" value="3.024" />
+// Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="48.384" />
+// Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency5" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units5" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency6" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units6" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units7" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units8" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units9" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units10" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units11" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units12" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units13" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units14" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units15" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units16" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units17" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
+// Retrieval info: 	<generic name="gui_pll_auto_reset" value="Off" />
+// Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
+// Retrieval info: 	<generic name="gui_en_reconf" value="false" />
+// Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
+// Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
+// Retrieval info: 	<generic name="gui_phout_division" value="1" />
+// Retrieval info: 	<generic name="gui_mif_generate" value="false" />
+// Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />
+// Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />
+// Retrieval info: 	<generic name="gui_dps_num" value="1" />
+// Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
+// Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
+// Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
+// Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
+// Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
+// Retrieval info: 	<generic name="gui_active_clk" value="false" />
+// Retrieval info: 	<generic name="gui_clk_bad" value="false" />
+// Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />
+// Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />
+// Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
+// Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
+// Retrieval info: </instance>
+// IPFS_FILES : pll.vo
+// RELATED_FILES: pll.v, pll_0002.v
diff --git a/sys/pll/pll_0002.qip b/sys/pll/pll_0002.qip
new file mode 100644
index 0000000..45157f8
--- /dev/null
+++ b/sys/pll/pll_0002.qip
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
+ 
+set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pll_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"
diff --git a/sys/pll/pll_0002.v b/sys/pll/pll_0002.v
new file mode 100644
index 0000000..f5135cc
--- /dev/null
+++ b/sys/pll/pll_0002.v
@@ -0,0 +1,90 @@
+`timescale 1ns/10ps
+module  pll_0002(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'outclk1'
+	output wire outclk_1,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("false"),
+		.reference_clock_frequency("50.0 MHz"),
+		.operation_mode("direct"),
+		.number_of_clocks(2),
+		.output_clock_frequency0("24.193548 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("12.096774 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("0 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("0 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_1, outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+
diff --git a/sys/pll_hdmi.qip b/sys/pll_hdmi.qip
new file mode 100644
index 0000000..be34aeb
--- /dev/null
+++ b/sys/pll_hdmi.qip
@@ -0,0 +1,483 @@
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWk="
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA=="
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWlfMDAwMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfY291dA==::MzI=::cGxsX2ZyYWN0aW9uYWxfY291dA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::cGxsX2RzbV9vdXRfc2Vs"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTQ4LjU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzkwODQyMDE1Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjcuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTQ4LjUwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::dHJ1ZQ==::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::Q3ljbG9uZSBW::UExMIFRZUEU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::UmVjb25maWd1cmFibGU=::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfaGlfZGl2::NA==::bV9jbnRfaGlfZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfbG9fZGl2::NA==::bV9jbnRfbG9fZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfaGlfZGl2::MjU2::bl9jbnRfaGlfZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfbG9fZGl2::MjU2::bl9jbnRfbG9fZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfYnlwYXNzX2Vu::ZmFsc2U=::bV9jbnRfYnlwYXNzX2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfYnlwYXNzX2Vu::dHJ1ZQ==::bl9jbnRfYnlwYXNzX2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MA==::Mg==::Y19jbnRfaGlfZGl2MA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MA==::MQ==::Y19jbnRfbG9fZGl2MA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDA=::MQ==::Y19jbnRfcHJzdDA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qw::MA==::Y19jbnRfcGhfbXV4X3Byc3Qw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMA==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==::dHJ1ZQ==::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MQ==::MQ==::Y19jbnRfaGlfZGl2MQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MQ==::MQ==::Y19jbnRfbG9fZGl2MQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE=::MQ==::Y19jbnRfcHJzdDE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qx::MA==::Y19jbnRfcGhfbXV4X3Byc3Qx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mg==::MQ==::Y19jbnRfaGlfZGl2Mg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mg==::MQ==::Y19jbnRfbG9fZGl2Mg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDI=::MQ==::Y19jbnRfcHJzdDI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qy::MA==::Y19jbnRfcGhfbXV4X3Byc3Qy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mw==::MQ==::Y19jbnRfaGlfZGl2Mw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mw==::MQ==::Y19jbnRfbG9fZGl2Mw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDM=::MQ==::Y19jbnRfcHJzdDM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qz::MA==::Y19jbnRfcGhfbXV4X3Byc3Qz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NA==::MQ==::Y19jbnRfaGlfZGl2NA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NA==::MQ==::Y19jbnRfbG9fZGl2NA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDQ=::MQ==::Y19jbnRfcHJzdDQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q0::MA==::Y19jbnRfcGhfbXV4X3Byc3Q0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NQ==::MQ==::Y19jbnRfaGlfZGl2NQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NQ==::MQ==::Y19jbnRfbG9fZGl2NQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDU=::MQ==::Y19jbnRfcHJzdDU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q1::MA==::Y19jbnRfcGhfbXV4X3Byc3Q1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Ng==::MQ==::Y19jbnRfaGlfZGl2Ng=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Ng==::MQ==::Y19jbnRfbG9fZGl2Ng=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDY=::MQ==::Y19jbnRfcHJzdDY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q2::MA==::Y19jbnRfcGhfbXV4X3Byc3Q2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Nw==::MQ==::Y19jbnRfaGlfZGl2Nw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Nw==::MQ==::Y19jbnRfbG9fZGl2Nw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDc=::MQ==::Y19jbnRfcHJzdDc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q3::MA==::Y19jbnRfcGhfbXV4X3Byc3Q3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OA==::MQ==::Y19jbnRfaGlfZGl2OA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OA==::MQ==::Y19jbnRfbG9fZGl2OA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDg=::MQ==::Y19jbnRfcHJzdDg="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q4::MA==::Y19jbnRfcGhfbXV4X3Byc3Q4"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OQ==::MQ==::Y19jbnRfaGlfZGl2OQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OQ==::MQ==::Y19jbnRfbG9fZGl2OQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDk=::MQ==::Y19jbnRfcHJzdDk="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q5::MA==::Y19jbnRfcGhfbXV4X3Byc3Q5"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTA=::MQ==::Y19jbnRfaGlfZGl2MTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTA=::MQ==::Y19jbnRfbG9fZGl2MTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEw::MQ==::Y19jbnRfcHJzdDEw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTA=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTA=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTE=::MQ==::Y19jbnRfaGlfZGl2MTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTE=::MQ==::Y19jbnRfbG9fZGl2MTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEx::MQ==::Y19jbnRfcHJzdDEx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTE=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTE=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTI=::MQ==::Y19jbnRfaGlfZGl2MTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTI=::MQ==::Y19jbnRfbG9fZGl2MTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEy::MQ==::Y19jbnRfcHJzdDEy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTI=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTI=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTM=::MQ==::Y19jbnRfaGlfZGl2MTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTM=::MQ==::Y19jbnRfbG9fZGl2MTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEz::MQ==::Y19jbnRfcHJzdDEz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTM=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTM=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTQ=::MQ==::Y19jbnRfaGlfZGl2MTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTQ=::MQ==::Y19jbnRfbG9fZGl2MTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE0::MQ==::Y19jbnRfcHJzdDE0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTQ=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTQ=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTU=::MQ==::Y19jbnRfaGlfZGl2MTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTU=::MQ==::Y19jbnRfbG9fZGl2MTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE1::MQ==::Y19jbnRfcHJzdDE1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTU=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTU=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTY=::MQ==::Y19jbnRfaGlfZGl2MTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTY=::MQ==::Y19jbnRfbG9fZGl2MTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE2::MQ==::Y19jbnRfcHJzdDE2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTY=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTY=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTc=::MQ==::Y19jbnRfaGlfZGl2MTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTc=::MQ==::Y19jbnRfbG9fZGl2MTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE3::MQ==::Y19jbnRfcHJzdDE3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTc=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTc=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3Zjb19kaXY=::Mg==::cGxsX3Zjb19kaXY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2NwX2N1cnJlbnQ=::MjA=::cGxsX2NwX2N1cnJlbnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2J3Y3RybA==::NDAwMA==::cGxsX2J3Y3RybA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5::NDQ1LjQ5OTk5OSBNSHo=::cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=::MzkwODQyMDE1Mw==::cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bWltaWNfZmJjbGtfdHlwZQ==::bm9uZQ==::bWltaWNfZmJjbGtfdHlwZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8x::Z2xi::cGxsX2ZiY2xrX211eF8x"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8y::bV9jbnQ=::cGxsX2ZiY2xrX211eF8y"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX21fY250X2luX3NyYw==::cGhfbXV4X2Nsaw==::cGxsX21fY250X2luX3NyYw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3NsZl9yc3Q=::dHJ1ZQ==::cGxsX3NsZl9yc3Q="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwyLDEsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDQ1LjQ5OTk5OSBNSHosMzkwODQyMDE1Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+
+set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
+set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
+set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.qip"]
+
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
diff --git a/sys/pll_hdmi.v b/sys/pll_hdmi.v
new file mode 100644
index 0000000..0cefd25
--- /dev/null
+++ b/sys/pll_hdmi.v
@@ -0,0 +1,256 @@
+// megafunction wizard: %Altera PLL v17.0%
+// GENERATION: XML
+// pll_hdmi.v
+
+// Generated using ACDS version 17.0 598
+
+`timescale 1 ps / 1 ps
+module pll_hdmi (
+		input  wire        refclk,            //            refclk.clk
+		input  wire        rst,               //             reset.reset
+		output wire        outclk_0,          //           outclk0.clk
+		input  wire [63:0] reconfig_to_pll,   //   reconfig_to_pll.reconfig_to_pll
+		output wire [63:0] reconfig_from_pll  // reconfig_from_pll.reconfig_from_pll
+	);
+
+	pll_hdmi_0002 pll_hdmi_inst (
+		.refclk            (refclk),            //            refclk.clk
+		.rst               (rst),               //             reset.reset
+		.outclk_0          (outclk_0),          //           outclk0.clk
+		.reconfig_to_pll   (reconfig_to_pll),   //   reconfig_to_pll.reconfig_to_pll
+		.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
+		.locked            ()                   //       (terminated)
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2018 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
+// Retrieval info: 	<generic name="debug_print_output" value="false" />
+// Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
+// Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
+// Retrieval info: 	<generic name="gui_device_speed_grade" value="2" />
+// Retrieval info: 	<generic name="gui_pll_mode" value="Fractional-N PLL" />
+// Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
+// Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
+// Retrieval info: 	<generic name="gui_operation_mode" value="direct" />
+// Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
+// Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
+// Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
+// Retrieval info: 	<generic name="gui_use_locked" value="false" />
+// Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
+// Retrieval info: 	<generic name="gui_number_of_clocks" value="1" />
+// Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
+// Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
+// Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
+// Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="148.5" />
+// Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="65.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift1" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg1" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="27.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency3" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency5" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units5" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency6" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units6" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units7" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units8" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units9" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units10" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units11" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units12" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units13" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units14" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units15" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units16" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units17" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
+// Retrieval info: 	<generic name="gui_pll_auto_reset" value="On" />
+// Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
+// Retrieval info: 	<generic name="gui_en_reconf" value="true" />
+// Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
+// Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
+// Retrieval info: 	<generic name="gui_phout_division" value="1" />
+// Retrieval info: 	<generic name="gui_mif_generate" value="false" />
+// Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />
+// Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />
+// Retrieval info: 	<generic name="gui_dps_num" value="1" />
+// Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
+// Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
+// Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
+// Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
+// Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
+// Retrieval info: 	<generic name="gui_active_clk" value="false" />
+// Retrieval info: 	<generic name="gui_clk_bad" value="false" />
+// Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />
+// Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />
+// Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
+// Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
+// Retrieval info: </instance>
+// IPFS_FILES : pll_hdmi.vo
+// RELATED_FILES: pll_hdmi.v, pll_hdmi_0002.v
diff --git a/sys/pll_hdmi/pll_hdmi_0002.qip b/sys/pll_hdmi/pll_hdmi_0002.qip
new file mode 100644
index 0000000..3cb7073
--- /dev/null
+++ b/sys/pll_hdmi/pll_hdmi_0002.qip
@@ -0,0 +1,2 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
diff --git a/sys/pll_hdmi/pll_hdmi_0002.v b/sys/pll_hdmi/pll_hdmi_0002.v
new file mode 100644
index 0000000..9347c76
--- /dev/null
+++ b/sys/pll_hdmi/pll_hdmi_0002.v
@@ -0,0 +1,241 @@
+`timescale 1ns/10ps
+module  pll_hdmi_0002(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'locked'
+	output wire locked,
+
+	// interface 'reconfig_to_pll'
+	input wire [63:0] reconfig_to_pll,
+
+	// interface 'reconfig_from_pll'
+	output wire [63:0] reconfig_from_pll
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("true"),
+		.reference_clock_frequency("50.0 MHz"),
+		.pll_fractional_cout(32),
+		.pll_dsm_out_sel("1st_order"),
+		.operation_mode("direct"),
+		.number_of_clocks(1),
+		.output_clock_frequency0("148.500000 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("0 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("0 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("0 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("Cyclone V"),
+		.pll_subtype("Reconfigurable"),
+		.m_cnt_hi_div(4),
+		.m_cnt_lo_div(4),
+		.n_cnt_hi_div(256),
+		.n_cnt_lo_div(256),
+		.m_cnt_bypass_en("false"),
+		.n_cnt_bypass_en("true"),
+		.m_cnt_odd_div_duty_en("false"),
+		.n_cnt_odd_div_duty_en("false"),
+		.c_cnt_hi_div0(2),
+		.c_cnt_lo_div0(1),
+		.c_cnt_prst0(1),
+		.c_cnt_ph_mux_prst0(0),
+		.c_cnt_in_src0("ph_mux_clk"),
+		.c_cnt_bypass_en0("false"),
+		.c_cnt_odd_div_duty_en0("true"),
+		.c_cnt_hi_div1(1),
+		.c_cnt_lo_div1(1),
+		.c_cnt_prst1(1),
+		.c_cnt_ph_mux_prst1(0),
+		.c_cnt_in_src1("ph_mux_clk"),
+		.c_cnt_bypass_en1("true"),
+		.c_cnt_odd_div_duty_en1("false"),
+		.c_cnt_hi_div2(1),
+		.c_cnt_lo_div2(1),
+		.c_cnt_prst2(1),
+		.c_cnt_ph_mux_prst2(0),
+		.c_cnt_in_src2("ph_mux_clk"),
+		.c_cnt_bypass_en2("true"),
+		.c_cnt_odd_div_duty_en2("false"),
+		.c_cnt_hi_div3(1),
+		.c_cnt_lo_div3(1),
+		.c_cnt_prst3(1),
+		.c_cnt_ph_mux_prst3(0),
+		.c_cnt_in_src3("ph_mux_clk"),
+		.c_cnt_bypass_en3("true"),
+		.c_cnt_odd_div_duty_en3("false"),
+		.c_cnt_hi_div4(1),
+		.c_cnt_lo_div4(1),
+		.c_cnt_prst4(1),
+		.c_cnt_ph_mux_prst4(0),
+		.c_cnt_in_src4("ph_mux_clk"),
+		.c_cnt_bypass_en4("true"),
+		.c_cnt_odd_div_duty_en4("false"),
+		.c_cnt_hi_div5(1),
+		.c_cnt_lo_div5(1),
+		.c_cnt_prst5(1),
+		.c_cnt_ph_mux_prst5(0),
+		.c_cnt_in_src5("ph_mux_clk"),
+		.c_cnt_bypass_en5("true"),
+		.c_cnt_odd_div_duty_en5("false"),
+		.c_cnt_hi_div6(1),
+		.c_cnt_lo_div6(1),
+		.c_cnt_prst6(1),
+		.c_cnt_ph_mux_prst6(0),
+		.c_cnt_in_src6("ph_mux_clk"),
+		.c_cnt_bypass_en6("true"),
+		.c_cnt_odd_div_duty_en6("false"),
+		.c_cnt_hi_div7(1),
+		.c_cnt_lo_div7(1),
+		.c_cnt_prst7(1),
+		.c_cnt_ph_mux_prst7(0),
+		.c_cnt_in_src7("ph_mux_clk"),
+		.c_cnt_bypass_en7("true"),
+		.c_cnt_odd_div_duty_en7("false"),
+		.c_cnt_hi_div8(1),
+		.c_cnt_lo_div8(1),
+		.c_cnt_prst8(1),
+		.c_cnt_ph_mux_prst8(0),
+		.c_cnt_in_src8("ph_mux_clk"),
+		.c_cnt_bypass_en8("true"),
+		.c_cnt_odd_div_duty_en8("false"),
+		.c_cnt_hi_div9(1),
+		.c_cnt_lo_div9(1),
+		.c_cnt_prst9(1),
+		.c_cnt_ph_mux_prst9(0),
+		.c_cnt_in_src9("ph_mux_clk"),
+		.c_cnt_bypass_en9("true"),
+		.c_cnt_odd_div_duty_en9("false"),
+		.c_cnt_hi_div10(1),
+		.c_cnt_lo_div10(1),
+		.c_cnt_prst10(1),
+		.c_cnt_ph_mux_prst10(0),
+		.c_cnt_in_src10("ph_mux_clk"),
+		.c_cnt_bypass_en10("true"),
+		.c_cnt_odd_div_duty_en10("false"),
+		.c_cnt_hi_div11(1),
+		.c_cnt_lo_div11(1),
+		.c_cnt_prst11(1),
+		.c_cnt_ph_mux_prst11(0),
+		.c_cnt_in_src11("ph_mux_clk"),
+		.c_cnt_bypass_en11("true"),
+		.c_cnt_odd_div_duty_en11("false"),
+		.c_cnt_hi_div12(1),
+		.c_cnt_lo_div12(1),
+		.c_cnt_prst12(1),
+		.c_cnt_ph_mux_prst12(0),
+		.c_cnt_in_src12("ph_mux_clk"),
+		.c_cnt_bypass_en12("true"),
+		.c_cnt_odd_div_duty_en12("false"),
+		.c_cnt_hi_div13(1),
+		.c_cnt_lo_div13(1),
+		.c_cnt_prst13(1),
+		.c_cnt_ph_mux_prst13(0),
+		.c_cnt_in_src13("ph_mux_clk"),
+		.c_cnt_bypass_en13("true"),
+		.c_cnt_odd_div_duty_en13("false"),
+		.c_cnt_hi_div14(1),
+		.c_cnt_lo_div14(1),
+		.c_cnt_prst14(1),
+		.c_cnt_ph_mux_prst14(0),
+		.c_cnt_in_src14("ph_mux_clk"),
+		.c_cnt_bypass_en14("true"),
+		.c_cnt_odd_div_duty_en14("false"),
+		.c_cnt_hi_div15(1),
+		.c_cnt_lo_div15(1),
+		.c_cnt_prst15(1),
+		.c_cnt_ph_mux_prst15(0),
+		.c_cnt_in_src15("ph_mux_clk"),
+		.c_cnt_bypass_en15("true"),
+		.c_cnt_odd_div_duty_en15("false"),
+		.c_cnt_hi_div16(1),
+		.c_cnt_lo_div16(1),
+		.c_cnt_prst16(1),
+		.c_cnt_ph_mux_prst16(0),
+		.c_cnt_in_src16("ph_mux_clk"),
+		.c_cnt_bypass_en16("true"),
+		.c_cnt_odd_div_duty_en16("false"),
+		.c_cnt_hi_div17(1),
+		.c_cnt_lo_div17(1),
+		.c_cnt_prst17(1),
+		.c_cnt_ph_mux_prst17(0),
+		.c_cnt_in_src17("ph_mux_clk"),
+		.c_cnt_bypass_en17("true"),
+		.c_cnt_odd_div_duty_en17("false"),
+		.pll_vco_div(2),
+		.pll_cp_current(20),
+		.pll_bwctrl(4000),
+		.pll_output_clk_frequency("445.499999 MHz"),
+		.pll_fractional_division("3908420153"),
+		.mimic_fbclk_type("none"),
+		.pll_fbclk_mux_1("glb"),
+		.pll_fbclk_mux_2("m_cnt"),
+		.pll_m_cnt_in_src("ph_mux_clk"),
+		.pll_slf_rst("true")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_0}),
+		.locked	(locked),
+		.reconfig_to_pll	(reconfig_to_pll),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk),
+		.reconfig_from_pll	(reconfig_from_pll)
+	);
+endmodule
+
diff --git a/sys/pll_hdmi/pll_hdmi_0002_q13.qip b/sys/pll_hdmi/pll_hdmi_0002_q13.qip
new file mode 100644
index 0000000..fb8053d
--- /dev/null
+++ b/sys/pll_hdmi/pll_hdmi_0002_q13.qip
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
diff --git a/sys/pll_hdmi_adj.vhd b/sys/pll_hdmi_adj.vhd
new file mode 100644
index 0000000..8c242af
--- /dev/null
+++ b/sys/pll_hdmi_adj.vhd
@@ -0,0 +1,360 @@
+--------------------------------------------------------------------------------
+-- HDMI PLL Adjust
+--------------------------------------------------------------------------------
+
+-- Changes the HDMI PLL frequency according to the scaler suggestions.
+--------------------------------------------
+-- LLTUNE :
+--  0   : Input Syncline
+--  1   : 
+--  2   : Input Interlaced mode
+--  3   : Input Interlaced field
+--  4   : Output Syncline
+--  5   : 
+--  6   : Input clock
+--  7   : Output clock
+  
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY pll_hdmi_adj IS
+  PORT (
+    -- Scaler
+    llena         : IN  std_logic; -- 0=Disabled 1=Enabled
+    lltune        : IN  unsigned(15 DOWNTO 0); -- Outputs from scaler
+    
+    locked        : OUT std_logic;
+    
+    -- Signals from reconfig commands
+    i_waitrequest : OUT std_logic;
+    i_write       : IN  std_logic;
+    i_address     : IN  unsigned(5 DOWNTO 0);
+    i_writedata   : IN  unsigned(31 DOWNTO 0);
+
+    -- Outputs to PLL_HDMI_CFG
+    o_waitrequest : IN  std_logic;
+    o_write       : OUT std_logic;
+    o_address     : OUT unsigned(5 DOWNTO 0);
+    o_writedata   : OUT unsigned(31 DOWNTO 0);
+    
+    ------------------------------------
+    clk           : IN  std_logic;
+    reset_na      : IN  std_logic
+    );
+
+BEGIN
+
+  
+END ENTITY pll_hdmi_adj;
+
+--##############################################################################
+
+ARCHITECTURE rtl OF pll_hdmi_adj IS
+  SIGNAL pwrite : std_logic;
+  SIGNAL paddress : unsigned(5 DOWNTO 0);
+  SIGNAL pdata    : unsigned(31 DOWNTO 0);
+  TYPE enum_state IS (sIDLE,sW1,sW2,sW3,sW4,sW5,sW6);
+  SIGNAL state : enum_state;
+  SIGNAL tune_freq,tune_phase : unsigned(5 DOWNTO 0);
+  SIGNAL lltune_sync,lltune_sync2,lltune_sync3 : unsigned(15 DOWNTO 0);
+  SIGNAL mfrac,mfrac_mem,mfrac_ref,diff : unsigned(40 DOWNTO 0);
+  SIGNAL mul : unsigned(15 DOWNTO 0);
+  SIGNAL sign,sign_pre : std_logic;
+  SIGNAL up,modo,phm,dir : std_logic;
+  SIGNAL cpt : natural RANGE 0 TO 3;
+  SIGNAL col : natural RANGE 0 TO 15;
+  
+  SIGNAL icpt,ocpt,ssh : natural RANGE 0 TO 2**24-1;
+  SIGNAL isync,isync2,itog,ipulse : std_logic;
+  SIGNAL osync,osync2,otog,opulse : std_logic;
+  SIGNAL sync,pulse,los,lop : std_logic;
+  SIGNAL osize,isize,offset,osizep : signed(23 DOWNTO 0);
+  SIGNAL logcpt : natural RANGE 0 TO 31;
+  SIGNAL udiff : integer RANGE -2**23 TO 2**23-1 :=0;
+  
+BEGIN
+  ----------------------------------------------------------------------------
+  -- Sample image sizes
+  Sampler:PROCESS(clk,reset_na) IS
+  BEGIN
+    IF reset_na='0' THEN
+--pragma synthesis_off
+      otog<='0';
+      itog<='0';
+      isync<='0';
+      isync2<='0';
+      osync<='0';
+      osync2<='0';
+--pragma synthesis_on
+      
+    ELSIF rising_edge(clk) THEN
+      -- Clock domain crossing
+      isync<=lltune(0); -- <ASYNC>
+      isync2<=isync;
+      osync<=lltune(4); -- <ASYNC>
+      osync2<=osync;
+      
+      itog<=itog XOR (isync AND NOT isync2);
+      otog<=otog XOR (osync AND NOT osync2);
+      
+      --ipulse<=isync AND NOT isync2 AND itog;
+      --opulse<=osync AND NOT osync2 AND otog;
+      
+      -- Measure output image size
+      IF osync='1' AND osync2='0' AND otog='1' THEN
+        ocpt<=0;
+        osizep<=to_signed(ocpt,24);
+      ELSE
+        ocpt<=ocpt+1;
+      END IF;
+      
+      -- Measure input image size
+      IF isync='1' AND isync2='0' AND itog='1' THEN
+        icpt<=0;
+        --isize<=to_signed(icpt,24);
+        osize<=osizep;
+        offset<=to_signed(ocpt,24);
+        udiff<=integer(to_integer(osizep)) - integer(icpt);
+        sync<='1';
+      ELSE
+        icpt<=icpt+1;
+        sync<='0';
+      END IF;
+
+      --------------------------------------------
+      pulse<='0';
+      IF sync='1' THEN
+        logcpt<=0;
+        ssh<=to_integer(osize);
+        los<='0';
+        lop<='0';
+        
+      ELSIF logcpt<24 THEN
+        -- Frequency difference
+        IF udiff>0 AND ssh<udiff AND los='0' THEN
+          tune_freq<='0' & to_unsigned(logcpt,5);
+          los<='1';
+        ELSIF udiff<=0 AND ssh<-udiff AND los='0' THEN
+          tune_freq<='1' & to_unsigned(logcpt,5);
+          los<='1';
+        END IF;
+        -- Phase difference
+        IF offset<osize/2 AND ssh<offset AND lop='0' THEN
+          tune_phase<='0' & to_unsigned(logcpt,5);
+          lop<='1';
+        ELSIF offset>=osize/2 AND ssh<(osize-offset) AND lop='0' THEN
+          tune_phase<='1' & to_unsigned(logcpt,5);
+          lop<='1';
+        END IF;
+        ssh<=ssh/2;
+        logcpt<=logcpt+1;
+        
+      ELSIF logcpt=24 THEN
+        pulse<='1';
+        ssh<=ssh/2;
+        logcpt<=logcpt+1;
+      END IF;
+
+    END IF;
+  END PROCESS Sampler;
+  
+    ----------------------------------------------------------------------------
+  -- 000010 : Start reg "Write either 0 or 1 to start fractional PLL reconf.
+  -- 000100 : M counter
+  -- 000111 : M counter Fractional Value K
+  
+  Comb:PROCESS(i_write,i_address,
+               i_writedata,pwrite,paddress,pdata) IS
+  BEGIN
+    IF i_write='1' THEN
+      o_write      <=i_write;
+      o_address    <=i_address;
+      o_writedata  <=i_writedata;
+    ELSE
+      o_write    <=pwrite;
+      o_address  <=paddress;
+      o_writedata<=pdata;
+    END IF;
+  END PROCESS Comb;
+  
+  i_waitrequest<=o_waitrequest WHEN state=sIDLE ELSE '0';
+    
+  ----------------------------------------------------------------------------
+  Schmurtz:PROCESS(clk,reset_na) IS
+    VARIABLE off_v,ofp_v : natural RANGE 0 TO 63;
+    VARIABLE diff_v : unsigned(40 DOWNTO 0);
+    VARIABLE mulco : unsigned(15 DOWNTO 0);
+    VARIABLE up_v,sign_v : std_logic;
+  BEGIN
+    IF reset_na='0' THEN
+      modo<='0';
+      state<=sIDLE;
+    ELSIF rising_edge(clk) THEN
+      ------------------------------------------------------
+      -- Snoop accesses to PLL reconfiguration
+      IF i_address="000100" AND i_write='1' THEN
+        mfrac    (40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
+                                 ('0' & i_writedata(7  DOWNTO 0));
+        mfrac_ref(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
+                                 ('0' & i_writedata(7  DOWNTO 0));
+        mfrac_mem(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
+                                 ('0' & i_writedata(7  DOWNTO 0));
+        mul<=i_writedata(15 DOWNTO 0);
+        modo<='1';
+      END IF;
+      
+      IF i_address="000111" AND i_write='1' THEN
+        mfrac    (31 DOWNTO 0)<=i_writedata;
+        mfrac_ref(31 DOWNTO 0)<=i_writedata;
+        mfrac_mem(31 DOWNTO 0)<=i_writedata;
+        modo<='1';
+      END IF;
+      
+      ------------------------------------------------------
+      -- Tuning
+      off_v:=to_integer('0' & tune_freq(4 DOWNTO 0));
+      ofp_v:=to_integer('0' & tune_phase(4 DOWNTO 0));
+      --IF off_v<8 THEN off_v:=8; END IF;
+      --IF ofp_v<7 THEN ofp_v:=7; END IF;
+      IF off_v<4 THEN off_v:=4; END IF;
+      IF ofp_v<4 THEN ofp_v:=4; END IF;
+      
+      IF off_v>=18 AND ofp_v>=18 THEN
+        locked<=llena;
+      ELSE
+        locked<='0';
+      END IF;
+      
+      up_v:='0';
+      IF pulse='1' THEN
+        cpt<=(cpt+1) MOD 4;
+        IF llena='0' THEN 
+          -- Recover original freq when disabling low lag mode
+          cpt<=0;
+          col<=0;
+          IF modo='1' THEN
+            mfrac<=mfrac_mem;
+            mfrac_ref<=mfrac_mem;
+            up<='1';
+            modo<='0';
+          END IF;
+          
+        ELSIF phm='0' AND cpt=0 THEN
+          -- Frequency adjust
+          sign_v:=tune_freq(5);
+          IF col<10 THEN col<=col+1; END IF;
+          IF off_v>=16 AND col>=10 THEN
+            phm<='1';
+            col<=0;
+          ELSE
+            off_v:=off_v+1;
+            IF off_v>17 THEN
+              off_v:=off_v + 3;
+            END IF;
+            up_v:='1';
+            up<='1';
+          END IF;
+          
+        ELSIF cpt=0 THEN
+          -- Phase adjust
+          sign_v:=NOT tune_phase(5);
+          col<=col+1;
+          IF col>=10 THEN
+            phm<='0';
+            up_v:='1';
+            off_v:=31;
+            col<=0;
+          ELSE
+            off_v:=ofp_v + 1;
+            IF ofp_v>7 THEN
+              off_v:=off_v + 1;
+            END IF;
+            IF ofp_v>14 THEN
+              off_v:=off_v + 2;
+            END IF;
+            IF ofp_v>17 THEN
+              off_v:=off_v + 3;
+            END IF;
+            up_v:='1';
+          END IF;
+          up<='1';
+        END IF;
+      END IF;
+      
+      diff_v:=shift_right(mfrac_ref,off_v);
+      IF sign_v='0' THEN
+        diff_v:=mfrac_ref + diff_v;
+      ELSE
+        diff_v:=mfrac_ref - diff_v;
+      END IF;
+      
+      IF up_v='1' THEN
+        mfrac<=diff_v;
+      END IF;
+      
+      IF up_v='1' AND phm='0' THEN
+        mfrac_ref<=diff_v;
+      END IF;
+      
+      ------------------------------------------------------
+      -- Update PLL registers
+      mulco:=mfrac(40 DOWNTO 33) & (mfrac(40 DOWNTO 33) + ('0' & mfrac(32)));
+      
+      CASE state IS
+        WHEN sIDLE =>
+          pwrite<='0';
+          IF up='1' THEN
+            up<='0';
+            IF mulco/=mul THEN
+              state<=sW1;
+            ELSE
+              state<=sW3;
+            END IF;
+          END IF;
+          
+        WHEN sW1 => -- Change M multiplier
+          mul<=mulco;
+          pdata<=x"0000" & mulco;
+          paddress<="000100";
+          pwrite<='1';
+          state<=sW2;
+          
+        WHEN sW2 =>
+          IF pwrite='1' AND o_waitrequest='0' THEN
+            state<=sW3;
+            pwrite<='0';
+          END IF;
+          
+        WHEN sW3 => -- Change M fractional value
+          pdata<=mfrac(31 DOWNTO 0);
+          paddress<="000111";
+          pwrite<='1';
+          state<=sW4;
+          
+        WHEN sW4 =>
+          IF pwrite='1' AND o_waitrequest='0' THEN
+            state<=sW5;
+            pwrite<='0';
+          END IF;
+          
+        WHEN sW5 =>
+          pdata<=x"0000_0001";
+          paddress<="000010";
+          pwrite<='1';
+          state<=sW6;
+          
+        WHEN sW6 =>
+          IF pwrite='1' AND o_waitrequest='0' THEN
+            pwrite<='0';
+            state<=sIDLE;
+          END IF;
+      END CASE;
+
+    END IF;
+  END PROCESS Schmurtz;
+  
+  ----------------------------------------------------------------------------
+  
+END ARCHITECTURE rtl;
+
diff --git a/sys/pll_hdmi_cfg.qip b/sys/pll_hdmi_cfg.qip
new file mode 100644
index 0000000..f6447f5
--- /dev/null
+++ b/sys/pll_hdmi_cfg.qip
@@ -0,0 +1,44 @@
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_VERSION "17.0"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_hdmi_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg.cmp"]
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
+
+set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg.v"]
+set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg/altera_pll_reconfig_top.v"]
+set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg/altera_pll_reconfig_core.v"]
+
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_VERSION "17.0"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_ENV "mwpim"
diff --git a/sys/pll_hdmi_cfg.v b/sys/pll_hdmi_cfg.v
new file mode 100644
index 0000000..1ebf6f0
--- /dev/null
+++ b/sys/pll_hdmi_cfg.v
@@ -0,0 +1,86 @@
+// megafunction wizard: %Altera PLL Reconfig v17.0%
+// GENERATION: XML
+// pll_hdmi_cfg.v
+
+// Generated using ACDS version 17.0 598
+
+`timescale 1 ps / 1 ps
+module pll_hdmi_cfg #(
+		parameter ENABLE_BYTEENABLE   = 0,
+		parameter BYTEENABLE_WIDTH    = 4,
+		parameter RECONFIG_ADDR_WIDTH = 6,
+		parameter RECONFIG_DATA_WIDTH = 32,
+		parameter reconf_width        = 64,
+		parameter WAIT_FOR_LOCK       = 1
+	) (
+		input  wire        mgmt_clk,          //          mgmt_clk.clk
+		input  wire        mgmt_reset,        //        mgmt_reset.reset
+		output wire        mgmt_waitrequest,  // mgmt_avalon_slave.waitrequest
+		input  wire        mgmt_read,         //                  .read
+		input  wire        mgmt_write,        //                  .write
+		output wire [31:0] mgmt_readdata,     //                  .readdata
+		input  wire [5:0]  mgmt_address,      //                  .address
+		input  wire [31:0] mgmt_writedata,    //                  .writedata
+		output wire [63:0] reconfig_to_pll,   //   reconfig_to_pll.reconfig_to_pll
+		input  wire [63:0] reconfig_from_pll  // reconfig_from_pll.reconfig_from_pll
+	);
+
+	altera_pll_reconfig_top #(
+		.device_family       ("Cyclone V"),
+		.ENABLE_MIF          (0),
+		.MIF_FILE_NAME       ("sys/pll_hdmi_cfg.mif"),
+		.ENABLE_BYTEENABLE   (ENABLE_BYTEENABLE),
+		.BYTEENABLE_WIDTH    (BYTEENABLE_WIDTH),
+		.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
+		.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
+		.reconf_width        (reconf_width),
+		.WAIT_FOR_LOCK       (WAIT_FOR_LOCK)
+	) pll_hdmi_cfg_inst (
+		.mgmt_clk          (mgmt_clk),          //          mgmt_clk.clk
+		.mgmt_reset        (mgmt_reset),        //        mgmt_reset.reset
+		.mgmt_waitrequest  (mgmt_waitrequest),  // mgmt_avalon_slave.waitrequest
+		.mgmt_read         (mgmt_read),         //                  .read
+		.mgmt_write        (mgmt_write),        //                  .write
+		.mgmt_readdata     (mgmt_readdata),     //                  .readdata
+		.mgmt_address      (mgmt_address),      //                  .address
+		.mgmt_writedata    (mgmt_writedata),    //                  .writedata
+		.reconfig_to_pll   (reconfig_to_pll),   //   reconfig_to_pll.reconfig_to_pll
+		.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
+		.mgmt_byteenable   (4'b0000)            //       (terminated)
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2018 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
+// Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="ENABLE_MIF" value="false" />
+// Retrieval info: 	<generic name="MIF_FILE_NAME" value="sys/pll_hdmi_cfg.mif" />
+// Retrieval info: 	<generic name="ENABLE_BYTEENABLE" value="false" />
+// Retrieval info: </instance>
+// IPFS_FILES : pll_hdmi_cfg.vo
+// RELATED_FILES: pll_hdmi_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
diff --git a/sys/pll_hdmi_cfg/altera_pll_reconfig_core.v b/sys/pll_hdmi_cfg/altera_pll_reconfig_core.v
new file mode 100644
index 0000000..4bc1fbb
--- /dev/null
+++ b/sys/pll_hdmi_cfg/altera_pll_reconfig_core.v
@@ -0,0 +1,2184 @@
+// (C) 2001-2017 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1ps/1ps
+
+module altera_pll_reconfig_core
+#(
+    parameter 	reconf_width       	= 64,
+    parameter 	device_family       	= "Stratix V",
+    // MIF Streaming parameters
+    parameter   RECONFIG_ADDR_WIDTH     = 6,
+    parameter   RECONFIG_DATA_WIDTH     = 32,
+    parameter   ROM_ADDR_WIDTH          = 9,
+    parameter   ROM_DATA_WIDTH          = 32,
+    parameter	ROM_NUM_WORDS           = 512
+) ( 
+
+    //input
+    input   wire    mgmt_clk,
+    input   wire    mgmt_reset,
+
+
+    //conduits
+    output  wire [reconf_width-1:0] reconfig_to_pll,
+    input  wire [reconf_width-1:0] reconfig_from_pll,
+
+    // user data (avalon-MM slave interface)
+    output  wire [31:0] mgmt_readdata,
+    output  wire        mgmt_waitrequest,
+    input   wire [5:0]  mgmt_address,
+    input   wire        mgmt_read,
+    input   wire        mgmt_write,
+    input   wire [31:0] mgmt_writedata,
+
+    //other
+    output  wire        mif_start_out,
+    output  reg [ROM_ADDR_WIDTH-1:0]    mif_base_addr
+);
+    localparam mode_WR            = 1'b0;
+    localparam mode_POLL          = 1'b1;
+    localparam MODE_REG           = 6'b000000;
+    localparam STATUS_REG         = 6'b000001;
+    localparam START_REG          = 6'b000010;
+    localparam N_REG              = 6'b000011;
+    localparam M_REG              = 6'b000100;
+    localparam C_COUNTERS_REG     = 6'b000101;
+    localparam DPS_REG            = 6'b000110;
+    localparam DSM_REG            = 6'b000111;
+    localparam BWCTRL_REG         = 6'b001000;
+    localparam CP_CURRENT_REG     = 6'b001001;
+    localparam ANY_DPRIO          = 6'b100000;
+    localparam CNT_BASE           = 5'b001010;
+    localparam VCO_REG              = 6'b011100;
+    localparam MIF_REG            = 6'b011111;
+    
+    //C Counters
+    localparam number_of_counters = 5'd18;
+    localparam  CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2,
+                CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5,
+                CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8,
+                CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11,
+                CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14,
+                CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17;
+    //C counter addresses
+    localparam C_CNT_0_DIV_ADDR = 5'h00;
+    localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11;
+    localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15;
+    localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17;
+    localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14;
+    localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16;
+    //N counter addresses
+    localparam N_CNT_DIV_ADDR = 5'h13;
+    localparam N_CNT_BYPASS_EN_ADDR = 5'h15;
+    localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17;
+    //M counter addresses
+    localparam M_CNT_DIV_ADDR = 5'h12;
+    localparam M_CNT_BYPASS_EN_ADDR = 5'h15;
+    localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17;
+    
+    //DSM address
+    localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18;
+    localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19;
+    localparam DSM_K_READY_ADDR = 5'h17;
+    localparam DSM_K_DITHER_ADDR = 5'h17;
+    localparam DSM_OUT_SEL_ADDR = 6'h30;
+    
+    //Other DSM params
+    localparam DSM_K_READY_BIT_INDEX = 4'd11;
+    //BWCTRL address
+    //Bit 0-3 of addr
+    localparam BWCTRL_ADDR = 6'h30;
+    //CP_CURRENT address
+    //Bit 0-2 of addr
+    localparam CP_CURRENT_ADDR = 6'h31;
+    
+    // VCODIV address
+    localparam VCO_ADDR = 5'h17;
+
+    localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4,
+               FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10,
+               ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15;
+    localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10;
+    
+    wire            clk;
+    wire            reset;
+    wire            gnd;
+
+    wire [5: 0]     slave_address;
+    wire            slave_read;
+    wire            slave_write;
+    wire [31: 0]    slave_writedata;
+
+    reg  [31: 0]     slave_readdata_d;
+    reg  [31: 0]     slave_readdata_q;
+    wire            slave_waitrequest;
+    reg             slave_mode;
+
+    assign          clk             = mgmt_clk;
+
+    assign          slave_address       = mgmt_address;
+    assign          slave_read      = mgmt_read;    
+    assign          slave_write     = mgmt_write;
+    assign          slave_writedata     = mgmt_writedata;
+    
+    reg read_waitrequest;
+    // Outputs
+    assign          mgmt_readdata       = slave_readdata_q;
+    assign          mgmt_waitrequest    = slave_waitrequest | read_waitrequest; //Read waitrequest asserted in polling mode
+
+    //internal signals
+    wire            locked_orig;
+    wire            locked;
+   
+    wire            pll_start;
+    wire            pll_start_valid;
+    reg             status_read;
+    wire            read_slave_mode_asserted;
+
+    wire            pll_start_asserted;
+
+    reg  [1:0]      current_state;
+    reg  [1:0]      next_state;
+
+    reg             status;//0=busy, 1=ready
+    //user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load);
+    //declaring the init wires. These will have 0 on them for 64 clk cycles
+    wire       [ 5:0]  init_dprio_address;
+    wire               init_dprio_read;
+    wire       [ 1:0]  init_dprio_byteen;
+    wire               init_dprio_write;
+    wire       [15:0]  init_dprio_writedata;
+
+    wire               init_atpgmode;
+    wire               init_mdio_dis;
+    wire               init_scanen;
+    wire               init_ser_shift_load;
+    wire               dprio_init_done;
+
+    //DPRIO output signals after initialization is done
+    wire            dprio_clk;
+    reg             avmm_dprio_write;
+    reg             avmm_dprio_read;
+    reg  [5:0]      avmm_dprio_address;
+    reg  [15:0]     avmm_dprio_writedata;
+    reg  [1:0]      avmm_dprio_byteen;
+    wire            avmm_atpgmode;
+    wire            avmm_mdio_dis;
+    wire            avmm_scanen;
+
+    //Final output wires that are muxed between the init and avmm wires.
+    wire            dprio_init_reset;
+    wire [5:0]      dprio_address /*synthesis keep*/;
+    wire            dprio_read/*synthesis keep*/;
+    wire [1:0]      dprio_byteen/*synthesis keep*/;
+    wire            dprio_write/*synthesis keep*/;
+    wire [15:0]     dprio_writedata/*synthesis keep*/;
+    wire            dprio_mdio_dis/*synthesis keep*/;
+    wire            dprio_ser_shift_load/*synthesis keep*/;
+    wire            dprio_atpgmode/*synthesis keep*/;
+    wire            dprio_scanen/*synthesis keep*/;
+
+
+    //other PLL signals for dyn ph shift
+    wire            phase_done/*synthesis keep*/;
+    wire            phase_en/*synthesis keep*/;
+    wire            up_dn/*synthesis keep*/;
+    wire  [4:0]     cnt_sel;
+    
+    //DPRIO input signals
+    wire  [15:0]     dprio_readdata;
+
+    //internal logic signals
+    //storage registers for user sent data
+    reg             dprio_temp_read_1;
+    reg             dprio_temp_read_2;
+    reg             dprio_start;
+    reg             mif_start_assert;
+    reg             dps_start_assert;
+    wire            usr_valid_changes;
+    reg  [3:0]      dprio_cur_state;
+    reg  [3:0]      dprio_next_state;
+    reg  [15:0]     dprio_temp_m_n_c_readdata_1_d;
+    reg  [15:0]     dprio_temp_m_n_c_readdata_2_d;
+    reg  [15:0]     dprio_temp_m_n_c_readdata_1_q;
+    reg  [15:0]     dprio_temp_m_n_c_readdata_2_q;
+	reg 			dprio_write_done;
+    //C counters signals
+    reg  [7:0]      usr_c_cnt_lo;
+    reg  [7:0]      usr_c_cnt_hi;
+    reg             usr_c_cnt_bypass_en;
+    reg             usr_c_cnt_odd_duty_div_en;
+    reg  [7:0]      temp_c_cnt_lo [0:17]; 
+    reg  [7:0]      temp_c_cnt_hi [0:17];
+    reg             temp_c_cnt_bypass_en [0:17];
+    reg      	    temp_c_cnt_odd_duty_div_en [0:17];
+    reg             any_c_cnt_changed;
+    reg             all_c_cnt_done_q;
+    reg             all_c_cnt_done_d;
+    reg  [17:0]     c_cnt_changed;
+    reg  [17:0]     c_cnt_done_d;
+    reg  [17:0]     c_cnt_done_q;
+    //N counter signals
+    reg  [7:0]      usr_n_cnt_lo; 
+    reg  [7:0]      usr_n_cnt_hi;
+    reg             usr_n_cnt_bypass_en;
+    reg             usr_n_cnt_odd_duty_div_en;
+    reg             n_cnt_changed;
+    reg             n_cnt_done_d;
+    reg             n_cnt_done_q;
+    //M counter signals
+    reg  [7:0]      usr_m_cnt_lo; 
+    reg  [7:0]      usr_m_cnt_hi;
+    reg             usr_m_cnt_bypass_en;
+    reg             usr_m_cnt_odd_duty_div_en;
+    reg             m_cnt_changed;
+    reg             m_cnt_done_d;
+    reg             m_cnt_done_q;
+    //dyn phase regs
+    reg  [15:0]     usr_num_shifts;
+    reg  [4:0]      usr_cnt_sel /*synthesis preserve*/;
+    reg             usr_up_dn;
+    reg             dps_changed;
+    wire            dps_changed_valid;
+    wire            dps_done;
+
+    //DSM Signals
+    reg  [31:0]     usr_k_value;
+    reg             dsm_k_changed;
+    reg             dsm_k_done_d;
+    reg             dsm_k_done_q;
+    reg             dsm_k_ready_false_done_d;
+    //BW signals 
+    reg [3:0]       usr_bwctrl_value;
+    reg             bwctrl_changed;
+    reg             bwctrl_done_d;
+    reg             bwctrl_done_q;
+    //CP signals 
+    reg [2:0]       usr_cp_current_value;
+    reg             cp_current_changed;
+    reg             cp_current_done_d;
+    reg             cp_current_done_q;
+    //VCO signals 
+    reg             usr_vco_value;
+    reg             vco_changed;
+    reg             vco_done_d;
+    reg             vco_done_q;
+    //Manual DPRIO signals
+    reg             manual_dprio_done_q;
+    reg             manual_dprio_done_d;
+    reg             manual_dprio_changed;
+    reg  [5:0]      usr_dprio_address;
+    reg  [15:0]     usr_dprio_writedata_0;
+    reg             usr_r_w;
+	 //keeping track of which operation happened last
+	 reg  [5:0]		  operation_address;
+    // Address wires for all C_counter DPRIO registers
+    // These are outputs of LUTS, changing depending
+    // on whether PLL_0 or PLL_1 being used
+
+
+    //Fitter will tell if FPLL1 is being used 
+    wire            fpll_1;
+
+    // other
+    reg             mif_reg_asserted;
+    // MAIN FSM                             
+
+    // Synchronize locked signal
+   altera_std_synchronizer #(
+        .depth(3)
+    ) altera_std_synchronizer_inst (
+        .clk(mgmt_clk),
+        .reset_n(~mgmt_reset), 
+        .din(locked_orig),
+        .dout(locked)
+    );
+   
+    always @(posedge clk)
+    begin
+        if (reset)
+        begin
+            dprio_cur_state <= DPRIO_IDLE;
+            current_state <= IDLE;
+        end
+        else
+        begin
+            current_state <= next_state;
+            dprio_cur_state <= dprio_next_state;
+        end
+    end
+
+    always @(*)
+     begin
+        case(current_state)
+          IDLE:
+            begin
+               if (pll_start & !slave_waitrequest & usr_valid_changes)
+                 next_state = WAIT_ON_LOCK;
+               else
+                 next_state = IDLE;
+            end
+          WAIT_ON_LOCK:
+            begin
+               if (locked & dps_done & dprio_write_done)  // received locked high from PLL
+                 begin
+                    if (slave_mode==mode_WR) //if the mode is waitrequest, then
+                                             // goto IDLE state directly
+                      next_state = IDLE;
+                    else
+                      next_state = LOCKED; //otherwise go the locked state
+                 end
+               else
+                  next_state = WAIT_ON_LOCK;
+            end
+              
+          LOCKED:
+            begin
+               if (status_read) // stay in LOCKED until user reads status 
+                 next_state = IDLE;
+               else
+                 next_state = LOCKED;
+            end
+
+          default: next_state = 2'bxx;
+          
+        endcase
+     end
+
+
+    // ask the pll to start reconfig
+    assign pll_start = (pll_start_asserted & (current_state==IDLE))  ;
+    assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK))  ;
+
+
+
+    // WRITE OPERATIONS
+    assign pll_start_asserted = slave_write & (slave_address == START_REG);
+    assign mif_start_out = pll_start & mif_reg_asserted;
+
+    //reading the mode register to determine what mode the slave will operate
+    //in.
+    always @(posedge clk)
+    begin
+        if (reset)
+          slave_mode <= mode_WR;
+        else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest)
+          slave_mode <= slave_writedata[0];
+    end
+
+    //record which values user wants to change.
+
+    //reading in the actual values that need to be reconfigged and sending
+    //them to the PLL
+    always @(posedge clk)
+    begin
+        if (reset)
+        begin
+            //reset all regs here
+            //BW signals reset
+            usr_bwctrl_value <= 0;
+            bwctrl_changed <= 0;
+            bwctrl_done_q <= 0;
+            //CP signals reset
+            usr_cp_current_value <= 0;
+            cp_current_changed <= 0;
+            cp_current_done_q <= 0;
+            //VCO signals reset
+            usr_vco_value <= 0;
+            vco_changed <= 0;
+            vco_done_q <= 0;
+            //DSM signals reset
+            usr_k_value <= 0;
+            dsm_k_changed <= 0;
+            dsm_k_done_q <= 0;
+            //N counter signals reset
+            usr_n_cnt_lo <= 0;
+            usr_n_cnt_hi <= 0;
+            usr_n_cnt_bypass_en <= 0;
+            usr_n_cnt_odd_duty_div_en <= 0;
+            n_cnt_changed <= 0;
+            n_cnt_done_q <= 0;
+            //M counter signals reset
+            usr_m_cnt_lo <= 0;
+            usr_m_cnt_hi <= 0;
+            usr_m_cnt_bypass_en <= 0;
+            usr_m_cnt_odd_duty_div_en <= 0;
+            m_cnt_changed <= 0;
+            m_cnt_done_q <= 0;
+            //C counter signals reset
+            usr_c_cnt_lo <= 0;
+            usr_c_cnt_hi <= 0;
+            usr_c_cnt_bypass_en <= 0;
+            usr_c_cnt_odd_duty_div_en <= 0;
+            any_c_cnt_changed <= 0;
+            all_c_cnt_done_q <= 0;
+            c_cnt_done_q <= 0;
+            //generic signals
+            dprio_start <= 0;
+            mif_start_assert <= 0;
+            dps_start_assert <= 0;
+            dprio_temp_m_n_c_readdata_1_q <= 0;
+            dprio_temp_m_n_c_readdata_2_q <= 0;
+            c_cnt_done_q <= 0;
+            //DPS signals
+            usr_up_dn <= 0;
+            usr_cnt_sel <= 0;
+            usr_num_shifts <= 0;
+            dps_changed <= 0;
+            //manual DPRIO signals
+            manual_dprio_changed <= 0;
+            usr_dprio_address <= 0;
+            usr_dprio_writedata_0 <= 0;
+            usr_r_w <= 0;
+	    operation_address <= 0;
+            mif_reg_asserted <= 0;
+            mif_base_addr <= 0;
+        end
+        else
+        begin
+            if (dprio_temp_read_1)
+            begin
+                dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d; 
+            end
+            if (dprio_temp_read_2)
+            begin
+                dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d; 
+            end
+            if ((dps_done)) dps_changed <= 0;
+            if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d;
+            if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d;
+            if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d;
+            if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d;
+            if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d;
+            if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d;
+            if (cp_current_done_d) cp_current_done_q <= cp_current_done_d;
+            if (vco_done_d) vco_done_q <= vco_done_d;
+            if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d;
+
+            if (mif_start_out == 1'b1)
+                mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle
+            
+            if (dps_done != 1'b1)
+                dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle
+
+            if (dprio_next_state == ONE)
+                dprio_start <= 0;
+            if (dprio_write_done)
+            begin
+                bwctrl_done_q <= 0;
+                cp_current_done_q <= 0;
+                vco_done_q <= 0;
+                dsm_k_done_q <= 0;
+                dsm_k_done_q <= 0;
+                n_cnt_done_q <= 0;
+                m_cnt_done_q <= 0;
+                all_c_cnt_done_q <= 0;
+                c_cnt_done_q <= 0;
+                dsm_k_changed <= 0;
+                n_cnt_changed <= 0;
+                m_cnt_changed <= 0;
+                any_c_cnt_changed <= 0;
+                bwctrl_changed <= 0;
+                cp_current_changed <= 0;
+                vco_changed <= 0;
+                manual_dprio_changed <= 0;
+                manual_dprio_done_q <= 0;
+                if (dps_changed | dps_changed_valid | !dps_done )
+                begin
+                    usr_cnt_sel <= usr_cnt_sel;
+                end
+                else 
+                begin
+                    usr_cnt_sel <= 0;
+                end
+                mif_reg_asserted <= 0;
+            end
+            else 
+            begin
+                dsm_k_changed <= dsm_k_changed;
+                n_cnt_changed <= n_cnt_changed;
+                m_cnt_changed <= m_cnt_changed;
+                any_c_cnt_changed <= any_c_cnt_changed;
+                manual_dprio_changed <= manual_dprio_changed;
+                mif_reg_asserted <= mif_reg_asserted;
+                usr_cnt_sel <= usr_cnt_sel;
+            end
+
+
+            if(slave_write & !slave_waitrequest)
+            begin
+                case(slave_address)
+                   //read in the values here from the user and act on them
+                DSM_REG:
+                begin
+                    operation_address <= DSM_REG;
+                    usr_k_value <= slave_writedata[31:0]; 
+                    dsm_k_changed <= 1'b1;
+                    dsm_k_done_q <= 0;
+                    dprio_start <= 1'b1;
+                end
+                N_REG:
+                begin
+                    operation_address <= N_REG;
+                    usr_n_cnt_lo <= slave_writedata[7:0]; 
+                    usr_n_cnt_hi <= slave_writedata[15:8];
+                    usr_n_cnt_bypass_en <= slave_writedata[16];
+                    usr_n_cnt_odd_duty_div_en <= slave_writedata[17];
+                    n_cnt_changed <= 1'b1;
+                    n_cnt_done_q <= 0;
+                    dprio_start <= 1'b1;
+                end
+                M_REG:
+                begin
+                    operation_address <= M_REG;
+                    usr_m_cnt_lo <= slave_writedata[7:0]; 
+                    usr_m_cnt_hi <= slave_writedata[15:8];
+                    usr_m_cnt_bypass_en <= slave_writedata[16];
+                    usr_m_cnt_odd_duty_div_en <= slave_writedata[17];
+                    m_cnt_changed <= 1'b1;
+                    m_cnt_done_q <= 0;
+                    dprio_start <= 1'b1;
+                end
+                DPS_REG:
+                begin
+                    operation_address <= DPS_REG;
+                    usr_num_shifts <= slave_writedata[15:0];
+                    usr_cnt_sel <= slave_writedata[20:16];
+                    usr_up_dn <= slave_writedata[21];
+                    dps_changed <= 1;
+                    dps_start_assert <= 1;
+                end
+                C_COUNTERS_REG:
+                begin
+						  operation_address <= C_COUNTERS_REG;
+                    usr_c_cnt_lo <= slave_writedata[7:0]; 
+                    usr_c_cnt_hi <= slave_writedata[15:8];
+                    usr_c_cnt_bypass_en <= slave_writedata[16];
+                    usr_c_cnt_odd_duty_div_en <= slave_writedata[17];
+                    usr_cnt_sel <= slave_writedata[22:18];
+                    any_c_cnt_changed <= 1'b1;
+                    all_c_cnt_done_q <= 0;
+                    dprio_start <= 1'b1;
+                end
+                BWCTRL_REG:
+                begin
+                    usr_bwctrl_value <= slave_writedata[3:0]; 
+                    bwctrl_changed <= 1'b1;
+                    bwctrl_done_q <= 0;
+                    dprio_start <= 1'b1;
+		    	  operation_address <= BWCTRL_REG;
+                end
+                CP_CURRENT_REG:
+                begin
+                    usr_cp_current_value <= slave_writedata[2:0]; 
+                    cp_current_changed <= 1'b1;
+                    cp_current_done_q <= 0;
+                    dprio_start <= 1'b1;
+		    operation_address <= CP_CURRENT_REG;
+                end
+                VCO_REG:
+                begin
+                    usr_vco_value <= slave_writedata[0]; 
+                    vco_changed <= 1'b1;
+                    vco_done_q <= 0;
+                    dprio_start <= 1'b1;
+		    operation_address <= VCO_REG;
+                end
+                ANY_DPRIO:
+                begin
+						  operation_address <= ANY_DPRIO;
+                    manual_dprio_changed <= 1'b1;
+                    usr_dprio_address <= slave_writedata[5:0];
+                    usr_dprio_writedata_0 <= slave_writedata[21:6];
+                    usr_r_w <= slave_writedata[22];
+                    manual_dprio_done_q <= 0;
+                    dprio_start <= 1'b1;
+                end
+                MIF_REG:
+                begin
+                    mif_reg_asserted <= 1'b1;
+                    mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0];
+                    mif_start_assert <= 1'b1;
+                end                
+                endcase
+             end
+        end 
+    end
+    //C Counter assigning values to the 2-d array of values for each C counter
+   
+    reg [4:0] j;
+    always @(posedge clk)
+    begin
+
+        if (reset)
+        begin
+            c_cnt_changed[17:0] <= 0;
+            for (j = 0; j < number_of_counters; j = j + 1'b1)
+            begin : c_cnt_reset
+                temp_c_cnt_bypass_en[j] <= 0;
+                temp_c_cnt_odd_duty_div_en[j] <= 0;
+                temp_c_cnt_lo[j][7:0] <= 0;
+                temp_c_cnt_hi[j][7:0] <= 0;
+            end
+        end
+        else 
+        begin
+            if (dprio_write_done)
+            begin
+                c_cnt_changed <= 0;
+            end
+            if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG))
+            begin
+                case (cnt_sel)
+                    CNT_0:
+                    begin
+                        temp_c_cnt_lo [0] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [0] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [0] <= 1'b1;
+                    end
+                    CNT_1:
+                    begin
+                        temp_c_cnt_lo [1] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [1] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [1] <= 1'b1;
+                    end
+                    CNT_2:
+                    begin
+                        temp_c_cnt_lo [2] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [2] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [2] <= 1'b1;
+                    end
+                    CNT_3:
+                    begin
+                        temp_c_cnt_lo [3] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [3] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [3] <= 1'b1;
+                    end
+                    CNT_4:
+                    begin
+                        temp_c_cnt_lo [4] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [4] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [4] <= 1'b1;
+                    end
+                    CNT_5:
+                    begin
+                        temp_c_cnt_lo [5] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [5] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [5] <= 1'b1;
+                    end
+                    CNT_6:
+                    begin
+                        temp_c_cnt_lo [6] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [6] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [6] <= 1'b1;
+                    end
+                    CNT_7:
+                    begin
+                        temp_c_cnt_lo [7] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [7] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [7] <= 1'b1;
+                    end
+                    CNT_8:
+                    begin
+                        temp_c_cnt_lo [8] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [8] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [8] <= 1'b1;
+                    end
+                    CNT_9:
+                    begin
+                        temp_c_cnt_lo [9] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [9] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [9] <= 1'b1;
+                    end
+                    CNT_10:
+                    begin
+                        temp_c_cnt_lo [10] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [10] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [10] <= 1'b1;
+                    end
+                    CNT_11:
+                    begin
+                        temp_c_cnt_lo [11] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [11] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [11] <= 1'b1;
+                    end
+                    CNT_12:
+                    begin
+                        temp_c_cnt_lo [12] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [12] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [12] <= 1'b1;
+                    end
+                    CNT_13:
+                    begin
+                        temp_c_cnt_lo [13] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [13] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [13] <= 1'b1;
+                    end
+                    CNT_14:
+                    begin
+                        temp_c_cnt_lo [14] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [14] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [14] <= 1'b1;
+                    end
+                    CNT_15:
+                    begin
+                        temp_c_cnt_lo [15] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [15] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [15] <= 1'b1;
+                    end
+                    CNT_16:
+                    begin
+                        temp_c_cnt_lo [16] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [16] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [16] <= 1'b1;
+                    end
+                    CNT_17:
+                    begin
+                        temp_c_cnt_lo [17] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [17] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [17] <= 1'b1;
+                    end
+                endcase
+
+            end
+        end
+    end
+
+
+    //logic to handle which writes the user indicated and wants to start.
+    assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed|vco_changed;
+
+     
+    //start the reconfig operations by writing to the DPRIO
+    reg break_loop;
+    reg [4:0] i;
+    always @(*)
+    begin 
+        dprio_temp_read_1 = 0;
+        dprio_temp_read_2 = 0;
+        dprio_temp_m_n_c_readdata_1_d = 0;
+        dprio_temp_m_n_c_readdata_2_d = 0;
+        break_loop = 0;
+        dprio_next_state = DPRIO_IDLE;
+        avmm_dprio_write = 0;
+        avmm_dprio_read = 0;
+        avmm_dprio_address = 0;
+        avmm_dprio_writedata = 0;
+        avmm_dprio_byteen = 0;
+        dprio_write_done = 1;
+        manual_dprio_done_d = 0;
+        n_cnt_done_d = 0;
+        dsm_k_done_d = 0;
+        dsm_k_ready_false_done_d = 0;
+        m_cnt_done_d = 0;
+        c_cnt_done_d[17:0] = 0;
+        all_c_cnt_done_d = 0;
+        bwctrl_done_d = 0;
+        cp_current_done_d = 0;
+        vco_done_d = 0;
+        i = 0;
+       
+        // Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes) 
+        if (dprio_start | mif_start_assert)
+            dprio_write_done = 0;
+
+        if (current_state == WAIT_ON_LOCK)
+        begin
+            case (dprio_cur_state)
+                ONE:
+                begin
+                    if (n_cnt_changed & !n_cnt_done_q) 
+                    begin
+			dprio_write_done = 0;
+                    	avmm_dprio_write = 1'b1;
+                    	avmm_dprio_byteen = 2'b11;
+                    	dprio_next_state = TWO;
+                        avmm_dprio_address = N_CNT_DIV_ADDR;
+                        avmm_dprio_writedata[7:0] = usr_n_cnt_lo;
+                        avmm_dprio_writedata[15:8] = usr_n_cnt_hi;
+                    end
+                    else if (m_cnt_changed & !m_cnt_done_q) 
+                    begin
+		    	dprio_write_done = 0;
+                    	avmm_dprio_write = 1'b1;
+                    	avmm_dprio_byteen = 2'b11;
+                    	dprio_next_state = TWO;
+                        avmm_dprio_address = M_CNT_DIV_ADDR;
+                        avmm_dprio_writedata[7:0] = usr_m_cnt_lo;
+                        avmm_dprio_writedata[15:8] = usr_m_cnt_hi;
+                    end
+                    else if (any_c_cnt_changed & !all_c_cnt_done_q)
+                    begin
+
+                        for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
+                        begin : c_cnt_write_hilo
+                            if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                            begin
+				dprio_write_done = 0;
+	                    	avmm_dprio_write = 1'b1;
+        	            	avmm_dprio_byteen = 2'b11;
+                	    	dprio_next_state = TWO;
+                                if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i;
+                                else avmm_dprio_address = C_CNT_0_DIV_ADDR + i;
+                                avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i];
+                                avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i];
+                                //To break from the loop, since only one counter
+                                //is addressed at a time
+                                break_loop = 1'b1;
+                            end
+                        end
+                    end
+                    else if (dsm_k_changed & !dsm_k_done_q) 
+                    begin
+		    	dprio_write_done = 0;
+                        avmm_dprio_write = 0;
+                        dprio_next_state = TWO;
+                    end
+                    else if (bwctrl_changed & !bwctrl_done_q) 
+                    begin
+		    	dprio_write_done = 0;
+                        avmm_dprio_write = 0;
+                        dprio_next_state = TWO;
+                    end
+                    else if (cp_current_changed & !cp_current_done_q) 
+                    begin
+		    	dprio_write_done = 0;		    
+                        avmm_dprio_write = 0;
+                        dprio_next_state = TWO;
+                    end
+                    else if (vco_changed & !vco_done_q) 
+                    begin
+		    	dprio_write_done = 0;		    
+                        avmm_dprio_write = 0;
+                        dprio_next_state = TWO;
+                    end
+                    else if (manual_dprio_changed & !manual_dprio_done_q)
+                    begin
+		    	dprio_write_done = 0;
+                    	avmm_dprio_byteen = 2'b11;
+                    	dprio_next_state = TWO;		    
+                        avmm_dprio_write = usr_r_w;
+                        avmm_dprio_address = usr_dprio_address;
+                        avmm_dprio_writedata[15:0] = usr_dprio_writedata_0;
+                    end
+                    else dprio_next_state = DPRIO_IDLE;
+                end
+            
+                TWO:
+                begin
+                    //handle reading the two setting bits on n_cnt, then
+                    //writing them back while preserving other bits.
+                    //Issue two consecutive reads then wait; readLatency=3
+                    dprio_write_done = 0;
+                    dprio_next_state = THREE;
+                    avmm_dprio_byteen = 2'b11;
+                    avmm_dprio_read = 1'b1;
+                    if (n_cnt_changed & !n_cnt_done_q)
+                    begin
+                        avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
+                    end
+                    else if (m_cnt_changed & !m_cnt_done_q)
+                    begin
+                        avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
+                    end
+                   
+                    else if (any_c_cnt_changed & !all_c_cnt_done_q)
+                    begin
+                        for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
+                        begin : c_cnt_read_bypass
+                            if (fpll_1)
+                            begin
+                                if (i > 13)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                            else
+                            begin
+                                if (i < 4)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                        end
+                    end
+                    //reading the K ready 16 bit word. Need to write 0 to it
+                    //afterwards to indicate that K has not been done writing
+                    else if (dsm_k_changed & !dsm_k_done_q) 
+                    begin
+                        avmm_dprio_address = DSM_K_READY_ADDR;
+                        dprio_next_state = FOUR;
+                    end
+                    else if (bwctrl_changed & !bwctrl_done_q) 
+                    begin
+                        avmm_dprio_address = BWCTRL_ADDR;
+                        dprio_next_state = FOUR;
+                    end
+                    else if (cp_current_changed & !cp_current_done_q) 
+                    begin
+                        avmm_dprio_address = CP_CURRENT_ADDR;
+                        dprio_next_state = FOUR;
+                    end
+                    else if (vco_changed & !vco_done_q) 
+                    begin
+                        avmm_dprio_address = VCO_ADDR;
+                        dprio_next_state = FOUR;
+                    end
+                    else if (manual_dprio_changed & !manual_dprio_done_q)
+                    begin
+                        avmm_dprio_read = ~usr_r_w;
+                        avmm_dprio_address = usr_dprio_address;
+                        dprio_next_state = DPRIO_DONE;
+                    end
+                    else dprio_next_state = DPRIO_IDLE;
+                end       
+                THREE:
+                begin
+                    dprio_write_done = 0;
+                    avmm_dprio_byteen = 2'b11;
+                    avmm_dprio_read = 1'b1;
+                    dprio_next_state = FOUR;
+                    if (n_cnt_changed & !n_cnt_done_q)
+                    begin
+                        avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
+                    end
+                    else if (m_cnt_changed & !m_cnt_done_q)
+                    begin
+                        avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
+                    end
+                    else if (any_c_cnt_changed & !all_c_cnt_done_q)
+                    begin
+                        for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
+                        begin : c_cnt_read_odd_div
+                            if (fpll_1)
+                            begin
+                                if (i > 13)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                            else
+                            begin
+                                if (i < 4)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                        end
+                    end   
+                    else dprio_next_state = DPRIO_IDLE;
+                end
+                FOUR:
+                begin
+                    dprio_temp_read_1 = 1'b1;
+                    dprio_write_done = 0;
+                    if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
+                    begin
+                        dprio_temp_m_n_c_readdata_1_d = dprio_readdata;
+                        dprio_next_state = FIVE;
+                    end
+                    else dprio_next_state = DPRIO_IDLE;
+                end
+                FIVE:
+                begin
+                    dprio_write_done = 0;
+                    dprio_temp_read_2 = 1'b1;
+                    if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
+                    begin
+                        //this is where DSM ready value comes.
+                        //Need to store in a register to be used later
+                        dprio_temp_m_n_c_readdata_2_d = dprio_readdata;
+                        dprio_next_state = SIX;
+                    end
+                    else dprio_next_state = DPRIO_IDLE;
+                end
+                SIX:
+                begin
+                    dprio_write_done = 0;
+                    avmm_dprio_write = 1'b1;
+                    avmm_dprio_byteen = 2'b11;
+                    dprio_next_state = SEVEN;
+                    avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q;
+                    if (n_cnt_changed & !n_cnt_done_q)
+                    begin
+                        avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
+                        avmm_dprio_writedata[5] = usr_n_cnt_bypass_en;
+                    end
+                    else if (m_cnt_changed & !m_cnt_done_q)
+                    begin
+                        avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
+                        avmm_dprio_writedata[4] = usr_m_cnt_bypass_en;
+                    end
+                    else if (any_c_cnt_changed & !all_c_cnt_done_q)
+                    begin
+                        for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
+                        begin : c_cnt_write_bypass
+                            if (fpll_1)
+                            begin
+                                if (i > 13)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
+                                        avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i];
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
+                                        avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i];
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                            else
+                            begin
+                                if (i < 4)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
+                                        avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i];
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
+                                        avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i];
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                        end
+                    end    
+                    else if (dsm_k_changed & !dsm_k_done_q)
+                    begin
+                        avmm_dprio_write = 0;
+                    end
+                    else if (bwctrl_changed & !bwctrl_done_q) 
+                    begin
+                        avmm_dprio_write = 0;
+                    end
+                    else if (cp_current_changed & !cp_current_done_q) 
+                    begin
+                        avmm_dprio_write = 0;
+                    end
+                    else if (vco_changed & !vco_done_q) 
+                    begin
+                        avmm_dprio_write = 0;
+                    end
+                    else dprio_next_state = DPRIO_IDLE;
+                end
+                SEVEN:
+                begin
+                    dprio_write_done = 0;
+                    dprio_next_state = EIGHT;
+                    avmm_dprio_write = 1'b1;
+                    avmm_dprio_byteen = 2'b11;
+                    avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
+                    if (n_cnt_changed & !n_cnt_done_q)
+                    begin
+                        avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
+                        avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en;
+                        n_cnt_done_d = 1'b1;
+                    end
+                    else if (m_cnt_changed & !m_cnt_done_q)
+                    begin
+                        avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
+                        avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en;
+                        m_cnt_done_d = 1'b1;
+                    end
+                         
+                    else if (any_c_cnt_changed & !all_c_cnt_done_q)
+                    begin
+                        for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
+                        begin : c_cnt_write_odd_div
+                            if (fpll_1)
+                            begin
+                                if (i > 13)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
+                                        avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i];
+                                        c_cnt_done_d[i] = 1'b1;
+                                        //have to OR the signals to prevent
+                                        //overwriting of previous dones
+                                        c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
+                                        avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i];
+                                        c_cnt_done_d[i] = 1'b1;
+                                        c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                            else
+                            begin
+                                if (i < 4)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
+                                        avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i];
+                                        c_cnt_done_d[i] = 1'b1;
+                                        //have to OR the signals to prevent
+                                        //overwriting of previous dones
+                                        c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
+                                        avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i];
+                                        c_cnt_done_d[i] = 1'b1;
+                                        c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                        end
+                    end
+                    else if (dsm_k_changed & !dsm_k_done_q)
+                    begin
+                        avmm_dprio_address = DSM_K_READY_ADDR;
+                        avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0;
+                        dsm_k_ready_false_done_d = 1'b1;
+                    end
+                    else if (bwctrl_changed & !bwctrl_done_q) 
+                    begin
+                        avmm_dprio_address = BWCTRL_ADDR;
+                        avmm_dprio_writedata[3:0] = usr_bwctrl_value;
+                        bwctrl_done_d = 1'b1;
+                    end
+                    else if (cp_current_changed & !cp_current_done_q) 
+                    begin
+                        avmm_dprio_address = CP_CURRENT_ADDR;
+                        avmm_dprio_writedata[2:0] = usr_cp_current_value;
+                        cp_current_done_d = 1'b1;
+                    end
+                    else if (vco_changed & !vco_done_q) 
+                    begin
+                        avmm_dprio_address = VCO_ADDR;
+                        avmm_dprio_writedata[8] = usr_vco_value;
+                        vco_done_d = 1'b1;
+                    end
+
+                   
+                    //if all C_cnt that were changed are done, then assert all_c_cnt_done
+                    if (c_cnt_done_d == c_cnt_changed)
+                        all_c_cnt_done_d = 1'b1;
+                    if (n_cnt_changed & n_cnt_done_d)
+                        dprio_next_state = DPRIO_DONE;
+                    if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q)
+                        dprio_next_state = ONE;
+                    else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q)
+                        dprio_next_state = ONE;
+                    else if (dsm_k_changed & !dsm_k_ready_false_done_d)
+                        dprio_next_state = TWO;
+                    else if (dsm_k_changed & !dsm_k_done_q)
+                        dprio_next_state = EIGHT;
+                    else if (bwctrl_changed & !bwctrl_done_d)
+                        dprio_next_state = TWO;
+                    else if (cp_current_changed & !cp_current_done_d)
+                        dprio_next_state = TWO;
+                    else if (vco_changed & !vco_done_d)
+                        dprio_next_state = TWO;
+                    else 
+                    begin
+                        dprio_next_state = DPRIO_DONE;
+                        dprio_write_done = 1'b1;
+                    end
+                end
+                //finish the rest of the DSM reads/writes
+                //writing k value, writing k_ready to 1.
+                EIGHT: 
+                begin
+                    dprio_write_done = 0;
+                    dprio_next_state = NINE;
+                    avmm_dprio_write = 1'b1;
+                    avmm_dprio_byteen = 2'b11;
+                    if (dsm_k_changed & !dsm_k_done_q)
+                    begin
+                        avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0;
+                        avmm_dprio_writedata[15:0] = usr_k_value[15:0];
+                    end
+                end
+                NINE: 
+                begin
+                    dprio_write_done = 0;
+                    dprio_next_state = TEN;
+                    avmm_dprio_write = 1'b1;
+                    avmm_dprio_byteen = 2'b11;
+                    if (dsm_k_changed & !dsm_k_done_q)
+                    begin
+                        avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1;
+                        avmm_dprio_writedata[15:0] = usr_k_value[31:16];
+                    end
+                end
+                TEN:
+                begin
+                    dprio_write_done = 0;
+                    dprio_next_state = ONE;
+                    avmm_dprio_write = 1'b1;
+                    avmm_dprio_byteen = 2'b11;
+                    if (dsm_k_changed & !dsm_k_done_q)
+                    begin
+                        avmm_dprio_address = DSM_K_READY_ADDR;
+                        //already have the readdata for DSM_K_READY_ADDR since we read it
+                        //earlier. Just reuse here 
+                        avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
+                        avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1;
+                        dsm_k_done_d = 1'b1;
+                    end
+                end
+                DPRIO_DONE:
+                begin
+                    dprio_write_done = 1'b1;
+                    if (dprio_start) dprio_next_state = DPRIO_IDLE;
+                    else dprio_next_state = DPRIO_DONE;
+                end
+                DPRIO_IDLE:
+                begin
+                    if (dprio_start) dprio_next_state = ONE;
+                    else dprio_next_state = DPRIO_IDLE;
+                end 
+                default:    dprio_next_state = 4'bxxxx;
+            endcase
+        end
+
+    end
+
+
+    //assert the waitreq signal according to the state of the slave
+    assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0;
+        
+    // Read operations
+    always @(*)
+    begin
+    status = 0;
+    if (slave_mode == mode_POLL)
+        //asserting status to 1 if the slave is done.
+       status = (current_state == LOCKED);
+    end
+    //************************************************************//
+    //************************************************************//
+    //******************** READ STATE MACHINE ********************//
+    //************************************************************//
+    //************************************************************//
+    reg  [1:0]      current_read_state;
+    reg  [1:0]      next_read_state;
+    reg  [5:0]      slave_address_int_d;
+    reg  [5:0]      slave_address_int_q;
+    reg             dprio_read_1;
+    reg  [5:0]      dprio_address_1;
+    reg  [1:0]      dprio_byteen_1;
+    reg  [4:0]      usr_cnt_sel_1;
+    localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10, READ_POST_WAIT = 2'b11; 
+    
+    always @(*)
+    begin
+      if(next_read_state == READ_IDLE)
+        begin
+          read_waitrequest <= 1'b0;
+        end
+      else
+        begin
+          read_waitrequest <= 1'b1;
+        end
+    end
+    
+    always @(posedge clk)
+    begin
+        if (reset)
+        begin
+            current_read_state <= READ_IDLE;
+            slave_address_int_q <= 0;
+            slave_readdata_q <= 0;
+        end
+        else
+        begin
+            current_read_state <= next_read_state;
+            slave_address_int_q <= slave_address_int_d;
+            slave_readdata_q <= slave_readdata_d;
+        end
+    end
+    always @(*)
+    begin
+        dprio_read_1 = 0;
+        dprio_address_1 = 0;
+        dprio_byteen_1 = 0;
+        slave_address_int_d = 0;
+        slave_readdata_d = 0;
+        status_read = 0;
+        usr_cnt_sel_1 = 0;
+        case(current_read_state)
+        READ_IDLE:
+        begin
+            slave_address_int_d = 0;
+            next_read_state = READ_IDLE;
+            if ((current_state != WAIT_ON_LOCK) && slave_read)
+            begin
+                slave_address_int_d = slave_address;
+                if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18))
+                begin
+                    next_read_state = READ_WAIT;
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE);
+                    if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel;
+                    else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel;
+                end
+                else
+                begin
+                case (slave_address)
+                MODE_REG:
+                begin
+                    next_read_state = READ_WAIT;
+                    slave_readdata_d = slave_mode;
+                end
+                STATUS_REG:
+                begin
+                    next_read_state = READ_WAIT;
+                    status_read = 1'b1;
+                    slave_readdata_d = status;
+                end
+                N_REG:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    dprio_address_1 = N_CNT_DIV_ADDR;
+                    next_read_state = READ_WAIT;
+                end
+                M_REG:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    dprio_address_1 = M_CNT_DIV_ADDR;
+                    next_read_state = READ_WAIT;
+                end
+                BWCTRL_REG:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    dprio_address_1 = BWCTRL_ADDR;
+                    next_read_state = READ_WAIT;
+                end
+                CP_CURRENT_REG:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    dprio_address_1 = CP_CURRENT_ADDR;
+                    next_read_state = READ_WAIT;
+                end
+                VCO_REG:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    dprio_address_1 = VCO_ADDR;
+                    next_read_state = READ_WAIT;
+                end
+                ANY_DPRIO:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = ~slave_writedata[22];
+                    dprio_address_1 = slave_writedata[5:0];
+                    next_read_state = READ_WAIT;
+                end
+                default : next_read_state = READ_IDLE;
+                endcase
+            end
+            end
+            else
+                next_read_state = READ_IDLE;
+        end
+        READ_WAIT:
+        begin
+            next_read_state = READ;
+            slave_address_int_d = slave_address_int_q;
+            case (slave_address_int_q)
+            MODE_REG:
+            begin
+                slave_readdata_d = slave_readdata_q;
+            end
+            STATUS_REG:
+            begin
+                slave_readdata_d = slave_readdata_q;
+            end
+    	    endcase
+        end
+        READ:
+        begin
+            next_read_state = READ_POST_WAIT;
+            slave_address_int_d = slave_address_int_q;
+            slave_readdata_d = dprio_readdata;
+            case (slave_address_int_q)
+            MODE_REG:
+            begin
+                slave_readdata_d = slave_readdata_q;
+            end
+            STATUS_REG:
+            begin
+                slave_readdata_d = slave_readdata_q;
+            end
+            BWCTRL_REG:
+            begin
+                slave_readdata_d = dprio_readdata[3:0];
+            end
+            CP_CURRENT_REG:
+            begin
+                slave_readdata_d = dprio_readdata[2:0];
+            end
+            VCO_REG:
+            begin
+                slave_readdata_d = dprio_readdata[8];
+            end
+            ANY_DPRIO:
+            begin
+                slave_readdata_d = dprio_readdata;
+            end
+    	    endcase
+        end
+        READ_POST_WAIT:
+        begin
+            next_read_state = READ_IDLE;
+        end
+        default: next_read_state = 2'bxx;
+        endcase
+     end
+
+
+    dyn_phase_shift dyn_phase_shift_inst (
+        .clk(clk), 
+        .reset(reset),
+        .phase_done(phase_done),
+        .pll_start_valid(pll_start_valid),
+        .dps_changed(dps_changed),
+        .dps_changed_valid(dps_changed_valid),
+        .dprio_write_done(dprio_write_done),
+        .usr_num_shifts(usr_num_shifts),
+        .usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1),
+        .usr_up_dn(usr_up_dn),
+        .locked(locked),
+        .dps_done(dps_done),
+        .phase_en(phase_en),
+        .up_dn(up_dn),
+        .cnt_sel(cnt_sel));
+    defparam dyn_phase_shift_inst.device_family = device_family;
+
+    assign dprio_clk = clk;
+    self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset);
+    
+    dprio_mux dprio_mux_inst (
+    .init_dprio_address(init_dprio_address),
+    .init_dprio_read(init_dprio_read),
+    .init_dprio_byteen(init_dprio_byteen),
+    .init_dprio_write(init_dprio_write),
+    .init_dprio_writedata(init_dprio_writedata),
+
+
+    .init_atpgmode(init_atpgmode),
+    .init_mdio_dis(init_mdio_dis),
+    .init_scanen(init_scanen),
+    .init_ser_shift_load(init_ser_shift_load),
+    .dprio_init_done(dprio_init_done),
+
+    // Inputs from avmm master
+    .avmm_dprio_address(avmm_dprio_address | dprio_address_1),
+    .avmm_dprio_read(avmm_dprio_read | dprio_read_1),
+    .avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1),
+    .avmm_dprio_write(avmm_dprio_write),
+    .avmm_dprio_writedata(avmm_dprio_writedata),
+
+    .avmm_atpgmode(avmm_atpgmode),
+    .avmm_mdio_dis(avmm_mdio_dis),
+    .avmm_scanen(avmm_scanen),
+
+    // Outputs to fpll
+    .dprio_address(dprio_address),
+    .dprio_read(dprio_read),
+    .dprio_byteen(dprio_byteen),
+    .dprio_write(dprio_write),
+    .dprio_writedata(dprio_writedata),
+
+    .atpgmode(dprio_atpgmode),
+    .mdio_dis(dprio_mdio_dis),
+    .scanen(dprio_scanen),
+    .ser_shift_load(dprio_ser_shift_load)
+    );
+
+
+    fpll_dprio_init fpll_dprio_init_inst (
+    .clk(clk),
+    .reset_n(~reset),
+    .locked(locked),
+
+    //outputs
+    .dprio_address(init_dprio_address),
+    .dprio_read(init_dprio_read),
+    .dprio_byteen(init_dprio_byteen),
+    .dprio_write(init_dprio_write),
+    .dprio_writedata(init_dprio_writedata),
+
+    .atpgmode(init_atpgmode),
+    .mdio_dis(init_mdio_dis),
+    .scanen(init_scanen),
+    .ser_shift_load(init_ser_shift_load),
+    .dprio_init_done(dprio_init_done));
+
+    //address luts, to be reconfigged by the Fitter
+    //FPLL_1 or 0 address lut
+    generic_lcell_comb lcell_fpll_0_1 (
+		.dataa(1'b0),
+        .combout (fpll_1));
+    defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA;
+	 defparam lcell_fpll_0_1.dont_touch = "on";
+	 defparam lcell_fpll_0_1.family = device_family;
+
+
+    wire dprio_read_combout;
+     generic_lcell_comb lcell_dprio_read (
+		.dataa(fpll_1),
+        .datab(dprio_read),
+        .datac(1'b0),
+        .datad(1'b0),
+        .datae(1'b0),
+        .dataf(1'b0),
+      .combout (dprio_read_combout));
+    defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC;
+	 defparam lcell_dprio_read.dont_touch = "on";
+	 defparam lcell_dprio_read.family = device_family;
+
+   
+    
+
+
+    //assign reconfig_to_pll signals
+    assign reconfig_to_pll[0] = dprio_clk;
+    assign reconfig_to_pll[1] = ~dprio_init_reset;
+    assign reconfig_to_pll[2] = dprio_write;
+    assign reconfig_to_pll[3] = dprio_read_combout;
+    assign reconfig_to_pll[9:4] = dprio_address;
+    assign reconfig_to_pll[25:10] = dprio_writedata;
+    assign reconfig_to_pll[27:26] = dprio_byteen;
+    assign reconfig_to_pll[28] = dprio_ser_shift_load;
+    assign reconfig_to_pll[29] = dprio_mdio_dis;
+    assign reconfig_to_pll[30] = phase_en;
+    assign reconfig_to_pll[31] = up_dn;
+    assign reconfig_to_pll[36:32] = cnt_sel;
+    assign reconfig_to_pll[37] = dprio_scanen;
+    assign reconfig_to_pll[38] = dprio_atpgmode;
+    //assign reconfig_to_pll[40:37] = clken;
+    assign reconfig_to_pll[63:39] = 0;
+
+    //assign reconfig_from_pll signals
+    assign dprio_readdata = reconfig_from_pll [15:0]; 
+    assign locked_orig    = reconfig_from_pll [16];
+    assign phase_done     = reconfig_from_pll [17];
+
+endmodule
+module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset);
+
+    localparam RESET_COUNTER_VALUE = 3'd2;
+    localparam INITIAL_WAIT_VALUE = 9'd340;
+    reg [9:0]counter;
+    reg local_reset;
+    reg usr_mode_init_wait;
+    initial 
+    begin
+        local_reset = 1'b1;
+        counter = 0;
+        usr_mode_init_wait = 0;
+    end
+
+    always @(posedge clk)
+    begin
+        if (mgmt_reset)
+        begin
+            counter <= 0;
+        end
+        else
+        begin
+            if (!usr_mode_init_wait)
+            begin
+                if (counter == INITIAL_WAIT_VALUE)
+                begin
+                    local_reset <= 0;
+                    usr_mode_init_wait <= 1'b1;
+                    counter <= 0;
+                end
+                else 
+                begin
+                counter <= counter + 1'b1;
+                end
+            end
+            else
+            begin
+                if (counter == RESET_COUNTER_VALUE)
+                    local_reset <= 0;
+                else 
+                    counter <= counter + 1'b1;
+            end
+        end
+    end
+    assign reset = mgmt_reset | local_reset;
+    assign init_reset = local_reset;
+endmodule
+
+module dprio_mux (
+    // Inputs from init block
+    input       [ 5:0]  init_dprio_address,
+    input               init_dprio_read,
+    input       [ 1:0]  init_dprio_byteen,
+    input               init_dprio_write,
+    input       [15:0]  init_dprio_writedata,
+
+    input               init_atpgmode,
+    input               init_mdio_dis,
+    input               init_scanen,
+    input               init_ser_shift_load,
+    input               dprio_init_done,
+
+    // Inputs from avmm master
+    input       [ 5:0]  avmm_dprio_address,
+    input               avmm_dprio_read,
+    input       [ 1:0]  avmm_dprio_byteen,
+    input               avmm_dprio_write,
+    input       [15:0]  avmm_dprio_writedata,
+
+    input               avmm_atpgmode,
+    input               avmm_mdio_dis,
+    input               avmm_scanen,
+    input               avmm_ser_shift_load,
+
+    // Outputs to fpll
+    output      [ 5:0]  dprio_address,
+    output              dprio_read,
+    output      [ 1:0]  dprio_byteen,
+    output              dprio_write,
+    output      [15:0]  dprio_writedata,
+
+    output              atpgmode,
+    output              mdio_dis,
+    output              scanen,
+    output              ser_shift_load
+);
+
+    assign  dprio_address   = dprio_init_done ? avmm_dprio_address    : init_dprio_address;
+    assign  dprio_read      = dprio_init_done ? avmm_dprio_read       : init_dprio_read;
+    assign  dprio_byteen    = dprio_init_done ? avmm_dprio_byteen     : init_dprio_byteen;
+    assign  dprio_write     = dprio_init_done ? avmm_dprio_write      : init_dprio_write;
+    assign  dprio_writedata = dprio_init_done ? avmm_dprio_writedata  : init_dprio_writedata;
+
+    assign  atpgmode        = init_atpgmode;
+    assign  scanen          = init_scanen;
+    assign  mdio_dis        = init_mdio_dis;
+    assign  ser_shift_load  = init_ser_shift_load ;
+endmodule
+module fpll_dprio_init (
+    input               clk,
+    input               reset_n,
+    input               locked,
+
+    output      [ 5:0]  dprio_address,
+    output              dprio_read,
+    output      [ 1:0]  dprio_byteen,
+    output              dprio_write,
+    output      [15:0]  dprio_writedata,
+
+    output  reg         atpgmode,
+    output  reg         mdio_dis,
+    output  reg         scanen,
+    output  reg         ser_shift_load,
+    output  reg         dprio_init_done
+);
+
+    reg [1:0] rst_n = 2'b00;
+    reg [6:0] count = 7'd0;
+    reg init_done_forever;
+
+    // Internal versions of control signals
+    wire  int_mdio_dis;
+    wire  int_ser_shift_load;
+    wire  int_dprio_init_done;
+    wire  int_atpgmode/*synthesis keep*/;
+    wire  int_scanen/*synthesis keep*/;
+
+
+    assign  dprio_address   = count[6] ? 5'b0 : count[5:0] ;
+    assign  dprio_byteen    = 2'b11;      // always enabled
+    assign  dprio_write     = ~count[6] & reset_n ;  // write for first 64 cycles
+    assign  dprio_read      = 1'b0;
+    assign  dprio_writedata = 16'd0;
+
+    assign  int_ser_shift_load  = count[6] ? |count[2:1]  : 1'b1; 
+    assign  int_mdio_dis        = count[6] ? ~count[2]    : 1'b1;
+    assign  int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0]  : 1'b0)
+                                                    : 1'b1;
+    assign  int_atpgmode        = 0;
+    assign  int_scanen          = 0;
+
+    initial begin
+        count             = 7'd0;
+        init_done_forever = 0;
+        mdio_dis          = 1'b1;
+        ser_shift_load    = 1'b1;
+        dprio_init_done   = 1'b0;
+        scanen            = 1'b0;
+        atpgmode          = 1'b0;
+    end
+
+    // reset synch.
+    always @(posedge clk or negedge reset_n)
+        if(!reset_n)  rst_n <= 2'b00;
+        else          rst_n <= {rst_n[0],1'b1};
+
+    // counter
+    always @(posedge clk)
+    begin
+        if (!rst_n[1])
+            init_done_forever <= 1'b0;
+        else
+        begin
+        if (count[6] && &count[1:0])
+            init_done_forever <= 1'b1;
+        end
+    end
+    always @(posedge clk or negedge rst_n[1])
+    begin
+        if(!rst_n[1])
+        begin
+            count <= 7'd0;
+        end
+        else if(~int_dprio_init_done) 
+        begin
+            count <= count + 7'd1;
+        end
+        else
+        begin
+            count <= count;
+        end
+    end
+
+    // outputs
+    always @(posedge clk) begin
+        mdio_dis        <= int_mdio_dis;
+        ser_shift_load  <= int_ser_shift_load;
+        dprio_init_done <= int_dprio_init_done;
+        atpgmode        <= int_atpgmode;
+        scanen          <= int_scanen;
+    end
+
+endmodule
+module dyn_phase_shift
+#(
+    parameter device_family       = "Stratix V"
+) ( 
+
+    input   wire        clk,
+    input   wire        reset,
+    input   wire        phase_done,
+    input   wire        pll_start_valid,
+    input   wire        dps_changed,
+    input   wire        dprio_write_done,
+    input   wire [15:0] usr_num_shifts,
+    input   wire [4:0]  usr_cnt_sel,
+    input   wire        usr_up_dn,
+    input   wire        locked,
+
+    //output
+    output  wire        dps_done,
+    output  reg         phase_en,
+    output  wire        up_dn,
+    output  wire        dps_changed_valid,
+    output  wire [4:0]  cnt_sel);
+    
+	
+
+    reg        first_phase_shift_d;
+    reg        first_phase_shift_q;
+    reg [15:0] phase_en_counter;
+    reg [3:0]       dps_current_state;
+    reg [3:0]       dps_next_state;
+    localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5; 
+    localparam PHASE_EN_WAIT_COUNTER = 5'd1;
+
+    reg [15:0] shifts_done_counter;
+    reg        phase_done_final;
+	 wire 		gnd /*synthesis keep*/;
+	 
+    //fsm
+    //always block controlling the state regs
+    always @(posedge clk)
+    begin
+        if (reset)
+        begin
+            dps_current_state <= DPS_DONE;
+        end
+        else
+        begin
+            dps_current_state <= dps_next_state;
+        end
+    end
+    //the combinational part. assigning the next state
+    //this turns on the phase_done_final signal when phase_done does this:
+    //_____         ______
+    //      |______|
+    always @(*)
+    begin
+        phase_done_final = 0;
+        first_phase_shift_d = 0;
+        phase_en = 0;
+        dps_next_state = DPS_DONE;
+        case (dps_current_state)
+            DPS_START:
+            begin
+                phase_en = 1'b1;
+                dps_next_state = DPS_WAIT_PHASE_EN;
+            end
+            DPS_WAIT_PHASE_EN:
+            begin
+                phase_en = 1'b1;
+                if (first_phase_shift_q)
+                begin
+                    first_phase_shift_d = 1'b1;
+                    dps_next_state = DPS_WAIT_PHASE_EN;
+                end
+                else
+                begin
+                    if (phase_en_counter == PHASE_EN_WAIT_COUNTER)
+                        dps_next_state = DPS_WAIT_PHASE_DONE;
+                    else dps_next_state = DPS_WAIT_PHASE_EN;
+                end
+            end
+            DPS_WAIT_PHASE_DONE:
+            begin
+                if (!phase_done | !locked)
+                begin
+                    dps_next_state = DPS_WAIT_PHASE_DONE;
+                end
+                else
+                begin
+                    if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0))
+                    begin
+                        dps_next_state = DPS_START;
+                        phase_done_final = 1'b1;
+                    end
+                    else
+                    begin
+                        dps_next_state = DPS_DONE;
+                    end
+
+                end
+            end
+            DPS_DONE:
+            begin
+                phase_done_final = 0;            
+                if (dps_changed) 
+                    dps_next_state = DPS_CHANGED;
+                else dps_next_state = DPS_DONE;
+
+            end
+			DPS_CHANGED:
+            begin
+                if (pll_start_valid)
+                    dps_next_state = DPS_WAIT_DPRIO_WRITING;
+                else
+                    dps_next_state = DPS_CHANGED;
+            end
+            DPS_WAIT_DPRIO_WRITING:
+            begin
+                if (dprio_write_done)
+                    dps_next_state = DPS_START;
+                else
+                    dps_next_state = DPS_WAIT_DPRIO_WRITING;
+            end
+
+            default: dps_next_state = 4'bxxxx;
+        endcase
+    
+    
+    end
+
+    always @(posedge clk)
+    begin
+
+        
+        if (dps_current_state == DPS_WAIT_PHASE_DONE)
+            phase_en_counter <= 0;
+        else if (dps_current_state == DPS_WAIT_PHASE_EN)
+            phase_en_counter <= phase_en_counter + 1'b1;
+
+        if (reset)
+        begin
+            phase_en_counter <= 0;
+            shifts_done_counter <= 1'b1;
+            first_phase_shift_q <= 1;
+        end
+        else
+        begin
+            if (first_phase_shift_d)
+                first_phase_shift_q <= 0;
+            if (dps_done)
+            begin
+                shifts_done_counter <= 1'b1;
+            end
+            else
+            begin
+                if (phase_done_final & (dps_next_state!= DPS_DONE))
+                    shifts_done_counter <= shifts_done_counter + 1'b1;
+                else
+                    shifts_done_counter <= shifts_done_counter;
+            end
+        end
+    end
+
+    assign dps_changed_valid = (dps_current_state == DPS_CHANGED);
+    assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED);
+    assign up_dn = usr_up_dn;
+	 assign gnd = 1'b0;
+	
+    //cnt select luts (5)
+    generic_lcell_comb lcell_cnt_sel_0 (
+        .dataa(usr_cnt_sel[0]),
+        .datab(usr_cnt_sel[1]),
+        .datac(usr_cnt_sel[2]),
+        .datad(usr_cnt_sel[3]),
+        .datae(usr_cnt_sel[4]),
+        .dataf(gnd),
+        .combout (cnt_sel[0]));
+    defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA;
+    defparam lcell_cnt_sel_0.dont_touch = "on";
+    defparam lcell_cnt_sel_0.family = device_family;
+    generic_lcell_comb lcell_cnt_sel_1 (
+        .dataa(usr_cnt_sel[0]),
+        .datab(usr_cnt_sel[1]),
+        .datac(usr_cnt_sel[2]),
+        .datad(usr_cnt_sel[3]),
+        .datae(usr_cnt_sel[4]),
+        .dataf(gnd),
+        .combout (cnt_sel[1]));
+    defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC;
+    defparam lcell_cnt_sel_1.dont_touch = "on";
+    defparam lcell_cnt_sel_1.family = device_family;
+    generic_lcell_comb lcell_cnt_sel_2 (
+        .dataa(usr_cnt_sel[0]),
+        .datab(usr_cnt_sel[1]),
+        .datac(usr_cnt_sel[2]),
+        .datad(usr_cnt_sel[3]),
+        .datae(usr_cnt_sel[4]),
+        .dataf(gnd),
+        .combout (cnt_sel[2]));
+    defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0;
+    defparam lcell_cnt_sel_2.dont_touch = "on";
+    defparam lcell_cnt_sel_2.family = device_family;
+    generic_lcell_comb lcell_cnt_sel_3 (
+        .dataa(usr_cnt_sel[0]),
+        .datab(usr_cnt_sel[1]),
+        .datac(usr_cnt_sel[2]),
+        .datad(usr_cnt_sel[3]),
+        .datae(usr_cnt_sel[4]),
+        .dataf(gnd),
+        .combout (cnt_sel[3]));
+    defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00;
+    defparam lcell_cnt_sel_3.dont_touch = "on";
+    defparam lcell_cnt_sel_3.family = device_family;
+    generic_lcell_comb lcell_cnt_sel_4 (
+        .dataa(usr_cnt_sel[0]),
+        .datab(usr_cnt_sel[1]),
+        .datac(usr_cnt_sel[2]),
+        .datad(usr_cnt_sel[3]),
+        .datae(usr_cnt_sel[4]),
+        .dataf(gnd),
+        .combout (cnt_sel[4]));
+    defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000;
+    defparam lcell_cnt_sel_4.dont_touch = "on";
+    defparam lcell_cnt_sel_4.family = device_family;
+   
+    
+endmodule
+
+module generic_lcell_comb
+#(
+    //parameter
+    parameter family             = "Stratix V",
+    parameter lut_mask           = 64'hAAAAAAAAAAAAAAAA,
+    parameter dont_touch         = "on"
+) ( 
+
+    input    dataa,
+    input    datab,
+    input    datac,
+    input    datad,
+    input    datae,
+    input    dataf,
+
+    output   combout
+);
+
+    generate
+        if (family == "Stratix V")
+        begin
+            stratixv_lcell_comb lcell_inst (
+                    .dataa(dataa),
+                    .datab(datab),
+                    .datac(datac),
+                    .datad(datad),
+                    .datae(datae),
+                    .dataf(dataf),
+                    .combout (combout));
+            defparam lcell_inst.lut_mask = lut_mask;
+            defparam lcell_inst.dont_touch = dont_touch;
+        end
+        else if (family == "Arria V")
+        begin
+            arriav_lcell_comb lcell_inst (
+                    .dataa(dataa),
+                    .datab(datab),
+                    .datac(datac),
+                    .datad(datad),
+                    .datae(datae),
+                    .dataf(dataf),
+                    .combout (combout));
+            defparam lcell_inst.lut_mask = lut_mask;
+            defparam lcell_inst.dont_touch = dont_touch;
+        end
+        else if (family == "Arria V GZ")
+        begin
+            arriavgz_lcell_comb lcell_inst (
+                    .dataa(dataa),
+                    .datab(datab),
+                    .datac(datac),
+                    .datad(datad),
+                    .datae(datae),
+                    .dataf(dataf),
+                    .combout (combout));
+            defparam lcell_inst.lut_mask = lut_mask;
+            defparam lcell_inst.dont_touch = dont_touch;
+        end
+        else if (family == "Cyclone V")
+        begin
+            cyclonev_lcell_comb lcell_inst (
+                    .dataa(dataa),
+                    .datab(datab),
+                    .datac(datac),
+                    .datad(datad),
+                    .datae(datae),
+                    .dataf(dataf),
+                    .combout (combout));
+            defparam lcell_inst.lut_mask = lut_mask;
+            defparam lcell_inst.dont_touch = dont_touch;
+        end
+        endgenerate
+endmodule
diff --git a/sys/pll_hdmi_cfg/altera_pll_reconfig_top.v b/sys/pll_hdmi_cfg/altera_pll_reconfig_top.v
new file mode 100644
index 0000000..c1bfa8b
--- /dev/null
+++ b/sys/pll_hdmi_cfg/altera_pll_reconfig_top.v
@@ -0,0 +1,428 @@
+// (C) 2001-2017 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1ps/1ps
+
+module altera_pll_reconfig_top
+#(
+    parameter   reconf_width            = 64,
+    parameter   device_family           = "Stratix V",
+    parameter   RECONFIG_ADDR_WIDTH     = 6,
+    parameter   RECONFIG_DATA_WIDTH     = 32,
+    
+	parameter   ROM_ADDR_WIDTH          = 9,
+    parameter   ROM_DATA_WIDTH          = 32,
+	parameter	ROM_NUM_WORDS           = 512,
+
+    parameter   ENABLE_MIF              = 0,    
+    parameter   MIF_FILE_NAME           = "",
+	
+	parameter 	ENABLE_BYTEENABLE		= 0,
+	parameter	BYTEENABLE_WIDTH		= 4,
+    parameter   WAIT_FOR_LOCK           = 1
+) ( 
+
+    //input
+    input   wire    mgmt_clk,
+    input   wire    mgmt_reset,
+
+
+    //conduits
+    output  wire [reconf_width-1:0] reconfig_to_pll,
+    input  wire [reconf_width-1:0] reconfig_from_pll,
+
+    // user data (avalon-MM slave interface)
+    output  wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata,
+    output  wire        mgmt_waitrequest,
+    input   wire [RECONFIG_ADDR_WIDTH-1:0]  mgmt_address,
+    input   wire        mgmt_read,
+    input   wire        mgmt_write,
+    input   wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata,
+	
+	//conditional input 
+	input 	wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable
+);
+
+localparam  NM28_START_REG 		= 6'b000010;
+localparam  NM20_START_REG 		= 9'b000000000;
+localparam 	NM20_MIFSTART_ADDR	= 9'b000010000;
+
+localparam MIF_STATE_DONE = 2'b00;
+localparam MIF_STATE_START = 2'b01;
+localparam MIF_STATE_BUSY = 2'b10;
+
+wire mgmt_byteenable_write;
+assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ? 
+										((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) : 
+										mgmt_write;
+										
+generate
+if (device_family == "Arria 10")
+begin:nm20_reconfig
+	if(ENABLE_MIF == 1)
+	begin:mif_reconfig_20nm // Generate Reconfig with MIF
+	
+		// MIF-related regs/wires
+        reg [RECONFIG_ADDR_WIDTH-1:0]   reconfig_mgmt_addr; 
+        reg                             reconfig_mgmt_read;
+        reg                             reconfig_mgmt_write;
+        reg [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_writedata;
+        wire                            reconfig_mgmt_waitrequest;
+        wire [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_readdata;
+
+        wire [RECONFIG_ADDR_WIDTH-1:0]   mif2reconfig_addr;
+        wire							 mif_busy;
+        wire                             mif2reconfig_read;
+        wire                             mif2reconfig_write;
+        wire [RECONFIG_DATA_WIDTH-1:0]   mif2reconfig_writedata;
+        wire [ROM_ADDR_WIDTH-1:0]        mif_base_addr;
+        reg mif_select;
+		//wire 							mif_user_start; // start signal provided by user to start mif
+        //reg user_start;
+
+		reg [1:0] mif_curstate;
+		reg [1:0] mif_nextstate;
+
+        wire mif_start; //start signal to mif reader
+
+        assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start;
+        // Don't output readdata if MIF streaming is taking place
+        assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
+
+		//user must lower this by the time mif streaming is done - suggest to lower after 1 cycle
+		assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR);
+		
+		//mif base addr is initially specified by the user
+		assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0];
+		
+		//MIF statemachine
+		always @(posedge mgmt_clk)
+		begin
+			if(mgmt_reset)
+				mif_curstate <= MIF_STATE_DONE;
+			else
+				mif_curstate <= mif_nextstate;
+		end
+		
+		always @(*)
+		begin
+			case (mif_curstate)
+				MIF_STATE_DONE:
+				begin
+					if(mif_start)
+						mif_nextstate <= MIF_STATE_START;
+					else
+						mif_nextstate <= MIF_STATE_DONE;
+				end
+				MIF_STATE_START:
+				begin
+					mif_nextstate <= MIF_STATE_BUSY;
+				end				
+				MIF_STATE_BUSY:
+				begin
+					if(mif_busy)
+						mif_nextstate <= MIF_STATE_BUSY;
+					else
+						mif_nextstate <= MIF_STATE_DONE;
+				end
+			endcase
+		end
+		
+		//Mif muxes
+        always @(*)
+        begin
+            if (mgmt_reset)
+            begin
+                reconfig_mgmt_addr      <= 0;
+                reconfig_mgmt_read      <= 0;
+                reconfig_mgmt_write     <= 0;
+                reconfig_mgmt_writedata <= 0;
+                //user_start              <= 0;
+            end
+            else
+            begin
+                reconfig_mgmt_addr      <= (mif_select) ? mif2reconfig_addr : mgmt_address;
+                reconfig_mgmt_read      <= (mif_select) ? mif2reconfig_read : mgmt_read;
+                reconfig_mgmt_write     <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
+                reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
+                //user_start              <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
+            end
+        end
+
+        always @(*)
+        begin
+            if (mgmt_reset)
+            begin
+                mif_select <= 0;
+            end
+            else 
+            begin
+                mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0;
+            end
+        end
+	
+        twentynm_pll_reconfig_mif_reader  
+        #(
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS),
+            .DEVICE_FAMILY(device_family),
+            .ENABLE_MIF(ENABLE_MIF),
+            .MIF_FILE_NAME(MIF_FILE_NAME)
+        ) twentynm_pll_reconfig_mif_reader_inst0 (
+            .mif_clk(mgmt_clk),
+            .mif_rst(mgmt_reset),
+            
+            //Altera_PLL Reconfig interface
+            //inputs
+            .reconfig_waitrequest(reconfig_mgmt_waitrequest),
+			//.reconfig_read_data(reconfig_mgmt_readdata),
+            //outputs
+            .reconfig_write_data(mif2reconfig_writedata),
+            .reconfig_addr(mif2reconfig_addr),
+            .reconfig_write(mif2reconfig_write),
+            .reconfig_read(mif2reconfig_read),
+
+            //MIF Ctrl Interface
+            //inputs
+            .mif_base_addr(mif_base_addr),
+            .mif_start(mif_start),
+            //outputs
+            .mif_busy(mif_busy)
+        );
+		
+        // ------ END MIF-RELATED MANAGEMENT ------	
+		
+		twentynm_iopll_reconfig_core 
+        #(
+            .WAIT_FOR_LOCK(WAIT_FOR_LOCK)
+        ) twentynm_iopll_reconfig_core_inst	(
+			// Inputs
+			.mgmt_clk(mgmt_clk),
+			.mgmt_rst_n(~mgmt_reset),
+			.mgmt_read(reconfig_mgmt_read),
+			.mgmt_write(reconfig_mgmt_write),
+			.mgmt_address(reconfig_mgmt_addr),
+			.mgmt_writedata(reconfig_mgmt_writedata),
+
+			// Outputs
+			.mgmt_readdata(reconfig_mgmt_readdata),
+			.mgmt_waitrequest(reconfig_mgmt_waitrequest),
+			
+			// PLL Conduits
+			.reconfig_to_pll(reconfig_to_pll),
+			.reconfig_from_pll(reconfig_from_pll)
+		);
+		
+	end // End generate reconfig with MIF
+	else 
+	begin:reconfig_core_20nm
+		twentynm_iopll_reconfig_core 
+        #(
+            .WAIT_FOR_LOCK(WAIT_FOR_LOCK)
+        ) twentynm_iopll_reconfig_core_inst	(
+			// Inputs
+			.mgmt_clk(mgmt_clk),
+			.mgmt_rst_n(~mgmt_reset),
+			.mgmt_read(mgmt_read),
+			.mgmt_write(mgmt_byteenable_write),
+			.mgmt_address(mgmt_address),
+			.mgmt_writedata(mgmt_writedata),
+
+			// Outputs
+			.mgmt_readdata(mgmt_readdata),
+			.mgmt_waitrequest(mgmt_waitrequest),
+			
+			// PLL Conduits
+			.reconfig_to_pll(reconfig_to_pll),
+			.reconfig_from_pll(reconfig_from_pll)
+		);
+	end
+end // 20nm reconfig
+else
+begin:NM28_reconfig
+    if (ENABLE_MIF == 1)
+    begin:mif_reconfig // Generate Reconfig with MIF
+
+        // MIF-related regs/wires
+        reg [RECONFIG_ADDR_WIDTH-1:0]   reconfig_mgmt_addr;
+        reg                             reconfig_mgmt_read;
+        reg                             reconfig_mgmt_write;
+        reg [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_writedata;
+        wire                            reconfig_mgmt_waitrequest;
+        wire [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_readdata;
+
+        wire [RECONFIG_ADDR_WIDTH-1:0]   mif2reconfig_addr;
+        wire										mif2reconfig_busy;
+        wire                             mif2reconfig_read;
+        wire                             mif2reconfig_write;
+        wire [RECONFIG_DATA_WIDTH-1:0]   mif2reconfig_writedata;
+        wire  [ROM_ADDR_WIDTH-1:0]        mif_base_addr;
+        reg mif_select;
+        reg user_start;
+
+        wire reconfig2mif_start_out;
+
+        assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
+        // Don't output readdata if MIF streaming is taking place
+        assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
+
+        always @(posedge mgmt_clk)
+        begin
+            if (mgmt_reset)
+            begin
+                reconfig_mgmt_addr      <= 0;
+                reconfig_mgmt_read      <= 0;
+                reconfig_mgmt_write     <= 0;
+                reconfig_mgmt_writedata <= 0;
+                user_start              <= 0;
+            end
+            else
+            begin
+                reconfig_mgmt_addr      <= (mif_select) ? mif2reconfig_addr : mgmt_address;
+                reconfig_mgmt_read      <= (mif_select) ? mif2reconfig_read : mgmt_read;
+                reconfig_mgmt_write     <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
+                reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
+                user_start              <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0;
+            end
+        end
+
+        always @(*)
+        begin
+            if (mgmt_reset)
+            begin
+                mif_select <= 0;
+            end
+            else 
+            begin
+                mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
+            end
+        end
+
+        altera_pll_reconfig_mif_reader 
+        #(
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS),
+            .DEVICE_FAMILY(device_family),
+            .ENABLE_MIF(ENABLE_MIF),
+            .MIF_FILE_NAME(MIF_FILE_NAME)
+        ) altera_pll_reconfig_mif_reader_inst0 (
+            .mif_clk(mgmt_clk),
+            .mif_rst(mgmt_reset),
+            
+            //Altera_PLL Reconfig interface
+            //inputs
+            .reconfig_busy(reconfig_mgmt_waitrequest),
+            .reconfig_read_data(reconfig_mgmt_readdata),
+            //outputs
+            .reconfig_write_data(mif2reconfig_writedata),
+            .reconfig_addr(mif2reconfig_addr),
+            .reconfig_write(mif2reconfig_write),
+            .reconfig_read(mif2reconfig_read),
+
+            //MIF Ctrl Interface
+            //inputs
+            .mif_base_addr(mif_base_addr),
+            .mif_start(reconfig2mif_start_out),
+            //outputs
+            .mif_busy(mif2reconfig_busy)
+        );
+
+        // ------ END MIF-RELATED MANAGEMENT ------
+
+
+        altera_pll_reconfig_core
+        #(
+            .reconf_width(reconf_width),
+            .device_family(device_family),
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS)
+        ) altera_pll_reconfig_core_inst0 (
+            //inputs
+            .mgmt_clk(mgmt_clk),
+            .mgmt_reset(mgmt_reset),
+
+            //PLL interface conduits
+            .reconfig_to_pll(reconfig_to_pll),
+            .reconfig_from_pll(reconfig_from_pll),
+
+            //User data outputs
+            .mgmt_readdata(reconfig_mgmt_readdata),
+            .mgmt_waitrequest(reconfig_mgmt_waitrequest),
+            
+            //User data inputs
+            .mgmt_address(reconfig_mgmt_addr),
+            .mgmt_read(reconfig_mgmt_read),
+            .mgmt_write(reconfig_mgmt_write),
+            .mgmt_writedata(reconfig_mgmt_writedata),
+
+            // other
+            .mif_start_out(reconfig2mif_start_out),
+            .mif_base_addr(mif_base_addr)
+        );
+
+    end // End generate reconfig with MIF
+    else
+    begin:reconfig_core // Generate Reconfig core only
+
+        wire reconfig2mif_start_out;
+        wire  [ROM_ADDR_WIDTH-1:0]        mif_base_addr;
+
+        altera_pll_reconfig_core
+        #(
+            .reconf_width(reconf_width),
+            .device_family(device_family),
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS)
+        ) altera_pll_reconfig_core_inst0 (
+            //inputs
+            .mgmt_clk(mgmt_clk),
+            .mgmt_reset(mgmt_reset),
+
+            //PLL interface conduits
+            .reconfig_to_pll(reconfig_to_pll),
+            .reconfig_from_pll(reconfig_from_pll),
+
+            //User data outputs
+            .mgmt_readdata(mgmt_readdata),
+            .mgmt_waitrequest(mgmt_waitrequest),
+            
+            //User data inputs
+            .mgmt_address(mgmt_address),
+            .mgmt_read(mgmt_read),
+            .mgmt_write(mgmt_byteenable_write),
+            .mgmt_writedata(mgmt_writedata),
+
+            // other
+            .mif_start_out(reconfig2mif_start_out),
+            .mif_base_addr(mif_base_addr)
+        );
+
+        
+    end // End generate reconfig core only
+end // End 28nm Reconfig
+endgenerate
+
+endmodule
+
diff --git a/sys/pll_hdmi_q13.qip b/sys/pll_hdmi_q13.qip
new file mode 100644
index 0000000..705d514
--- /dev/null
+++ b/sys/pll_hdmi_q13.qip
@@ -0,0 +1,13 @@
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+
+set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
+set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
+set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"]
+
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
diff --git a/sys/scandoubler.v b/sys/scandoubler.v
new file mode 100644
index 0000000..9997cf6
--- /dev/null
+++ b/sys/scandoubler.v
@@ -0,0 +1,195 @@
+//
+// scandoubler.v
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2017-2019 Sorgelig
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+
+// TODO: Delay vsync one line
+
+module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	// system interface
+	input             clk_sys,
+	input             ce_pix,
+	output            ce_pix_out,
+
+	input             hq2x,
+
+	// shifter video interface
+	input             hs_in,
+	input             vs_in,
+	input             hb_in,
+	input             vb_in,
+
+	input  [DWIDTH:0] r_in,
+	input  [DWIDTH:0] g_in,
+	input  [DWIDTH:0] b_in,
+	input             mono,
+
+	// output interface
+	output reg        hs_out,
+	output            vs_out,
+	output            hb_out,
+	output            vb_out,
+	output [DWIDTH:0] r_out,
+	output [DWIDTH:0] g_out,
+	output [DWIDTH:0] b_out
+);
+
+
+localparam DWIDTH = HALF_DEPTH ? 3 : 7;
+
+assign vs_out = vso[3];
+assign ce_pix_out = hq2x ? ce_x4 : ce_x2;
+
+//Compensate picture shift after HQ2x
+assign vb_out = vbo[3];
+assign hb_out = hbo[6];
+
+reg  [7:0] pix_len = 0;
+reg  [7:0] pix_cnt = 0;
+wire [7:0] pl = pix_len + 1'b1;
+wire [7:0] pc = pix_cnt + 1'b1;
+
+reg ce_x4, ce_x2, ce_x1;
+always @(negedge clk_sys) begin
+	reg old_ce, valid, hs;
+	reg [2:0] ce_cnt;
+
+	reg [7:0] pixsz, pixsz2, pixsz4 = 0;
+
+	if(~&pix_len) pix_len <= pl;
+	if(~&pix_cnt) pix_cnt <= pc;
+
+	ce_x4 <= 0;
+	ce_x2 <= 0;
+	ce_x1 <= 0;
+
+	// use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4.
+	if((pc == pixsz4) || (pc == pixsz2) || (pc == (pixsz2+pixsz4))) ce_x4 <= 1;
+	if( pc == pixsz2) ce_x2 <= 1;
+
+	old_ce <= ce_pix;
+	if(~old_ce & ce_pix) begin
+		if(valid & ~hb_in & ~vb_in) begin
+			pixsz  <= pl;
+			pixsz2 <= {1'b0,  pl[7:1]};
+			pixsz4 <= {2'b00, pl[7:2]};
+		end
+		pix_len <= 0;
+		valid <= 1;
+	end
+
+	if(hb_in | vb_in) valid <= 0;
+
+	hs <= hs_out;
+	if((~hs & hs_out) || (pc >= pixsz)) begin
+		ce_x2 <= 1;
+		ce_x4 <= 1;
+		ce_x1 <= 1;
+		pix_cnt <= 0;
+	end
+end
+
+Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
+(
+	.clk(clk_sys),
+	.ce_x4(ce_x4),
+	.inputpixel({b_d,g_d,r_d}),
+	.mono(mono),
+	.disable_hq2x(~hq2x),
+	.reset_frame(vb_in),
+	.reset_line(req_line_reset),
+	.read_y(sd_line),
+	.hblank(hbo[0]&hbo[8]),
+	.outpixel({b_out,g_out,r_out})
+);
+
+reg [DWIDTH:0] r_d;
+reg [DWIDTH:0] g_d;
+reg [DWIDTH:0] b_d;
+
+reg [1:0] sd_line;
+reg [3:0] vbo;
+reg [3:0] vso;
+reg [8:0] hbo;
+
+reg req_line_reset;
+always @(posedge clk_sys) begin
+
+	reg [31:0] hcnt;
+	reg [30:0] sd_hcnt;
+	reg [30:0] hs_start, hs_end;
+	reg [30:0] hde_start, hde_end;
+
+	reg hs, hb;
+
+	if(ce_x4) begin
+		hbo[8:1] <= hbo[7:0];
+	end
+
+	// output counter synchronous to input and at twice the rate
+	sd_hcnt <= sd_hcnt + 1'd1;
+	if(sd_hcnt == hde_start) begin
+		sd_hcnt <= 0;
+		vbo[3:1] <= vbo[2:0];
+	end
+
+	if(sd_hcnt == hs_end) begin
+		sd_line <= sd_line + 1'd1;
+		if(&vbo[3:2]) sd_line <= 1;
+		vso[3:1] <= vso[2:0];
+	end
+
+	if(sd_hcnt == hde_start)hbo[0] <= 0;
+	if(sd_hcnt == hde_end)  hbo[0] <= 1;
+
+	// replicate horizontal sync at twice the speed
+	if(sd_hcnt == hs_end)   hs_out <= 0;
+	if(sd_hcnt == hs_start) hs_out <= 1;
+
+	hs <= hs_in;
+	hb <= hb_in;
+
+	if(ce_x1) begin
+		req_line_reset <= hb_in;
+		r_d <= r_in;
+		g_d <= g_in;
+		b_d <= b_in;
+	end
+
+	hcnt <= hcnt + 1'd1;
+	if(hb && !hb_in) begin
+		hde_start <= hcnt[31:1];
+		hbo[0] <= 0;
+		hcnt <= 0;
+		sd_hcnt <= 0;
+		vbo <= {vbo[2:0],vb_in};
+	end
+
+	if(!hb && hb_in) hde_end <= hcnt[31:1];
+
+	// falling edge of hsync indicates start of line
+	if(hs && !hs_in) begin
+		hs_end <= hcnt[31:1];
+		vso[0] <= vs_in;
+	end
+
+	// save position of rising edge
+	if(!hs && hs_in) hs_start <= hcnt[31:1];
+end
+
+endmodule
diff --git a/sys/scanlines.v b/sys/scanlines.v
new file mode 100644
index 0000000..96aa6e3
--- /dev/null
+++ b/sys/scanlines.v
@@ -0,0 +1,52 @@
+module scanlines #(parameter v2=0)
+(
+	input         clk,
+
+	input       [1:0] scanlines,
+	input      [23:0] din,
+	output reg [23:0] dout,
+	input             hs,vs
+);
+
+reg [1:0] scanline;
+always @(posedge clk) begin
+	reg old_hs, old_vs;
+
+	old_hs <= hs;
+	old_vs <= vs;
+	
+	if(old_hs && ~hs) begin
+		if(v2) begin
+			scanline <= scanline + 1'd1;
+			if (scanline == scanlines) scanline <= 0;
+		end
+		else scanline <= scanline ^ scanlines;
+	end
+	if(old_vs && ~vs) scanline <= 0;
+end
+
+wire [7:0] r,g,b;
+assign {r,g,b} = din;
+
+always @(*) begin
+	case(scanline)
+		1: // reduce 25% = 1/2 + 1/4
+			dout = {{1'b0, r[7:1]} + {2'b00, r[7:2]},
+					  {1'b0, g[7:1]} + {2'b00, g[7:2]},
+					  {1'b0, b[7:1]} + {2'b00, b[7:2]}};
+
+		2: // reduce 50% = 1/2
+			dout = {{1'b0, r[7:1]},
+					  {1'b0, g[7:1]},
+					  {1'b0, b[7:1]}};
+
+		3: // reduce 75% = 1/4
+			dout = {{2'b00, r[7:2]},
+					  {2'b00, g[7:2]},
+					  {2'b00, b[7:2]}};
+
+		default: dout = {r,g,b};
+	endcase
+end
+
+endmodule
diff --git a/sys/sd_card.v b/sys/sd_card.v
new file mode 100644
index 0000000..6f7080d
--- /dev/null
+++ b/sys/sd_card.v
@@ -0,0 +1,538 @@
+// 
+// sd_card.v
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+// Copyright (c) 2015-2018 Sorgelig
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the Lesser GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+// http://elm-chan.org/docs/mmc/mmc_e.html
+//
+/////////////////////////////////////////////////////////////////////////
+
+//
+// Made module syncrhronous. Total code refactoring. (Sorgelig)
+// clk_spi must be at least 4 x sck for proper work.
+
+module sd_card
+(
+	input         clk_sys,
+	input         reset,
+
+	input         sdhc,
+	
+	output [31:0] sd_lba,
+	output reg    sd_rd,
+	output reg    sd_wr,
+	input         sd_ack,
+	input         sd_ack_conf,
+
+	input   [8:0] sd_buff_addr,
+	input   [7:0] sd_buff_dout,
+	output  [7:0] sd_buff_din,
+	input         sd_buff_wr,
+
+	// SPI interface
+	input         clk_spi,
+
+	input         ss,
+	input         sck,
+	input         mosi,
+	output reg    miso
+);
+
+assign sd_lba = sdhc ? lba : {9'd0, lba[31:9]};
+
+wire[31:0] OCR = { 1'b1, sdhc, 30'd0 };  // bit30 = 1 -> high capaciry card (sdhc) // bit31 = 0 -> card power up finished
+wire [7:0] READ_DATA_TOKEN     = 8'hfe;
+wire [7:0] WRITE_DATA_RESPONSE = 8'h05;
+
+// number of bytes to wait after a command before sending the reply
+localparam NCR=3;
+
+localparam RD_STATE_IDLE       = 0;
+localparam RD_STATE_WAIT_IO    = 1;
+localparam RD_STATE_SEND_TOKEN = 2;
+localparam RD_STATE_SEND_DATA  = 3;
+localparam RD_STATE_WAIT_M     = 4;
+
+localparam WR_STATE_IDLE       = 0;
+localparam WR_STATE_EXP_DTOKEN = 1;
+localparam WR_STATE_RECV_DATA  = 2;
+localparam WR_STATE_RECV_CRC0  = 3;
+localparam WR_STATE_RECV_CRC1  = 4;
+localparam WR_STATE_SEND_DRESP = 5;
+localparam WR_STATE_BUSY       = 6;
+
+sdbuf buffer
+(
+	.clock_a(clk_sys),
+	.address_a(sd_buff_addr),
+	.data_a(sd_buff_dout),
+	.wren_a(sd_ack & sd_buff_wr),
+	.q_a(sd_buff_din),
+
+	.clock_b(clk_spi),
+	.address_b(buffer_ptr),
+	.data_b(buffer_din),
+	.wren_b(buffer_wr),
+	.q_b(buffer_dout)
+);
+
+sdbuf conf
+(
+	.clock_a(clk_sys),
+	.address_a(sd_buff_addr),
+	.data_a(sd_buff_dout),
+	.wren_a(sd_ack_conf & sd_buff_wr),
+
+	.clock_b(clk_spi),
+	.address_b(buffer_ptr),
+	.q_b(config_dout)
+);
+
+reg [31:0] lba, new_lba;
+reg  [8:0] buffer_ptr;
+reg  [7:0] buffer_din;
+wire [7:0] buffer_dout;
+wire [7:0] config_dout;
+reg        buffer_wr;
+
+always @(posedge clk_spi) begin
+	reg [2:0] read_state;
+	reg [2:0] write_state;
+	reg [6:0] sbuf;
+	reg       cmd55;
+	reg [7:0] cmd;
+	reg [2:0] bit_cnt;
+	reg [3:0] byte_cnt;
+	reg [7:0] reply;
+	reg [7:0] reply0, reply1, reply2, reply3;
+	reg [3:0] reply_len;
+	reg       tx_finish;
+	reg       rx_finish;
+	reg       old_sck;
+	reg       synced;
+	reg [5:0] ack;
+	reg       io_ack;
+	reg [4:0] idle_cnt = 0;
+	reg [2:0] wait_m_cnt;
+
+	if(buffer_wr & ~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1;
+	buffer_wr <= 0;
+
+	ack <= {ack[4:0], sd_ack};
+	if(ack[5:4] == 2'b10) io_ack <= 1;
+	if(ack[5:4] == 2'b01) {sd_rd,sd_wr} <= 0;
+
+	old_sck <= sck;
+	
+	if(~ss)                              idle_cnt <= 31;
+	else if(~old_sck && sck && idle_cnt) idle_cnt <= idle_cnt - 1'd1;
+
+	if(reset || !idle_cnt) begin
+		bit_cnt     <= 0;
+		byte_cnt    <= 15;
+		synced      <= 0;
+		miso        <= 1;
+		sbuf        <= 7'b1111111;
+		tx_finish   <= 0;
+		rx_finish   <= 0;
+		read_state  <= RD_STATE_IDLE;
+		write_state <= WR_STATE_IDLE;
+	end
+
+	if(old_sck & ~sck & ~ss) begin
+		tx_finish <= 0;
+		miso <= 1;				// default: send 1's (busy/wait)
+
+		if(byte_cnt == 5+NCR) begin
+			miso <= reply[~bit_cnt];
+
+			if(bit_cnt == 7) begin
+				// these three commands all have a reply_len of 0 and will thus
+				// not send more than a single reply byte
+
+				// CMD9: SEND_CSD
+				// CMD10: SEND_CID
+				if((cmd == 'h49) | (cmd ==  'h4a))
+					read_state <= RD_STATE_SEND_TOKEN;      // jump directly to data transmission
+						
+				// CMD17/CMD18
+				if((cmd == 'h51) | (cmd == 'h52)) begin
+					io_ack <= 0;
+					read_state <= RD_STATE_WAIT_IO;         // start waiting for data from io controller
+					lba <= new_lba;
+					sd_rd <= 1;                      // trigger request to io controller
+				end
+			end
+		end
+		else if((reply_len > 0) && (byte_cnt == 5+NCR+1)) miso <= reply0[~bit_cnt];
+		else if((reply_len > 1) && (byte_cnt == 5+NCR+2)) miso <= reply1[~bit_cnt];
+		else if((reply_len > 2) && (byte_cnt == 5+NCR+3)) miso <= reply2[~bit_cnt];
+		else if((reply_len > 3) && (byte_cnt == 5+NCR+4)) miso <= reply3[~bit_cnt];
+		else begin
+			if(byte_cnt > 5+NCR && read_state==RD_STATE_IDLE && write_state==WR_STATE_IDLE) tx_finish <= 1;
+		end
+
+		// ---------- read state machine processing -------------
+
+		case(read_state)
+			RD_STATE_IDLE: ; // do nothing
+
+
+			// waiting for io controller to return data
+			RD_STATE_WAIT_IO: begin
+				if(io_ack & (bit_cnt == 7)) read_state <= RD_STATE_SEND_TOKEN;
+			end
+
+			// send data token
+			RD_STATE_SEND_TOKEN: begin
+				miso <= READ_DATA_TOKEN[~bit_cnt];
+	
+				if(bit_cnt == 7) begin
+					read_state <= RD_STATE_SEND_DATA;   // next: send data
+					buffer_ptr <= 0;
+					if(cmd == 'h49) buffer_ptr <= 16;
+				end
+			end
+
+			// send data
+			RD_STATE_SEND_DATA: begin
+
+				miso <= ((cmd == 'h49) | (cmd == 'h4A)) ? config_dout[~bit_cnt] : buffer_dout[~bit_cnt];
+
+				if(bit_cnt == 7) begin
+
+					// sent 512 sector data bytes?
+					if((cmd == 'h51) & &buffer_ptr) read_state <= RD_STATE_IDLE;
+					else if((cmd == 'h52) & &buffer_ptr) begin
+						read_state <= RD_STATE_WAIT_M;
+						wait_m_cnt <= 0;
+					end
+
+					// sent 16 cid/csd data bytes?
+					else if(((cmd == 'h49) | (cmd == 'h4a)) & (&buffer_ptr[3:0])) read_state <= RD_STATE_IDLE;
+
+					// not done yet -> trigger read of next data byte
+					else buffer_ptr <= buffer_ptr + 1'd1;
+				end
+			end
+
+			RD_STATE_WAIT_M: begin
+				if(bit_cnt == 7) begin
+					wait_m_cnt <= wait_m_cnt + 1'd1;
+					if(&wait_m_cnt) begin
+						lba <= lba + 1;
+						io_ack <= 0;
+						sd_rd <= 1;
+						read_state <= RD_STATE_WAIT_IO;
+					end
+				end
+			end
+		endcase
+
+		// ------------------ write support ----------------------
+		// send write data response
+		if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt];
+
+		// busy after write until the io controller sends ack
+		if(write_state == WR_STATE_BUSY) miso <= 0;
+   end
+
+	if(~old_sck & sck & ~ss) begin
+
+	   if(synced) bit_cnt <= bit_cnt + 1'd1;
+
+		// assemble byte
+		if(bit_cnt != 7) begin
+			sbuf[6:0] <= { sbuf[5:0], mosi };
+
+			// resync while waiting for token
+			if(write_state==WR_STATE_EXP_DTOKEN) begin
+				if(cmd == 'h58) begin
+					if({sbuf,mosi} == 8'hfe) begin
+						write_state <= WR_STATE_RECV_DATA;
+						buffer_ptr <= 0;
+						bit_cnt <= 0;
+					end
+				end
+				else begin
+					if({sbuf,mosi} == 8'hfc) begin
+						write_state <= WR_STATE_RECV_DATA;
+						buffer_ptr <= 0;
+						bit_cnt <= 0;
+					end
+					if({sbuf,mosi} == 8'hfd) begin
+						write_state <= WR_STATE_IDLE;
+						rx_finish <= 1;
+						bit_cnt <= 0;
+					end
+				end
+			end
+		end
+		else begin
+			// finished reading one byte
+			// byte counter runs against 15 byte boundary
+			if(byte_cnt != 15) byte_cnt <= byte_cnt + 1'd1;
+
+			// byte_cnt > 6 -> complete command received
+			// first byte of valid command is 01xxxxxx
+			// don't accept new commands once a write or read command has been accepted
+ 			if((byte_cnt > 5) & (write_state == WR_STATE_IDLE) & (read_state == RD_STATE_IDLE) && !rx_finish) begin
+				byte_cnt <= 0;
+				cmd <= { sbuf, mosi};
+
+			   // set cmd55 flag if previous command was 55
+			   cmd55 <= (cmd == 'h77);
+			end
+
+ 			if((byte_cnt > 5) & (read_state == RD_STATE_WAIT_M) && ({sbuf, mosi} == 8'h4c)) begin
+				byte_cnt <= 0;
+				rx_finish <= 0;
+				cmd <= {sbuf, mosi};
+				read_state <= RD_STATE_IDLE;
+			end
+
+			// parse additional command bytes
+			if(byte_cnt == 0) new_lba[31:24] <= { sbuf, mosi};
+			if(byte_cnt == 1) new_lba[23:16] <= { sbuf, mosi};
+			if(byte_cnt == 2) new_lba[15:8]  <= { sbuf, mosi};
+			if(byte_cnt == 3) new_lba[7:0]   <= { sbuf, mosi};
+
+			// last byte (crc) received, evaluate
+			if(byte_cnt == 4) begin
+
+				// default:
+				reply <= 4;      // illegal command
+				reply_len <= 0;  // no extra reply bytes
+				rx_finish <= 1;
+
+				case(cmd)
+					// CMD0: GO_IDLE_STATE
+					'h40: reply <= 1;    // ok, busy
+
+					// CMD1: SEND_OP_COND
+					'h41: reply <= 0;    // ok, not busy
+
+					// CMD8: SEND_IF_COND (V2 only)
+					'h48: begin
+							reply  <= 1;   // ok, busy
+
+							reply0 <= 'h00;
+							reply1 <= 'h00;
+							reply2 <= 'h01;
+							reply3 <= 'hAA;
+							reply_len <= 4;
+						end
+
+					// CMD9: SEND_CSD
+					'h49: reply <= 0;    // ok
+
+					// CMD10: SEND_CID
+					'h4a: reply <= 0;    // ok
+
+					// CMD12: STOP_TRANSMISSION 
+					'h4c: reply <= 0;    // ok
+
+					// CMD16: SET_BLOCKLEN
+					'h50: begin
+							// we only support a block size of 512
+							if(new_lba == 512) reply <= 0;  // ok
+								else reply <= 'h40;         // parmeter error
+						end
+
+					// CMD17: READ_SINGLE_BLOCK
+					'h51: reply <= 0;    // ok
+
+					// CMD18: READ_MULTIPLE
+					'h52: reply <= 0;    // ok
+
+					// CMD24: WRITE_BLOCK
+					'h58,
+					// CMD25: WRITE_MULTIPLE
+					'h59: begin
+							reply <= 0;    // ok
+							write_state <= WR_STATE_EXP_DTOKEN;  // expect data token
+							rx_finish <=0;
+							lba <= new_lba;
+						end
+
+					// ACMD41: APP_SEND_OP_COND
+					'h69: if(cmd55) reply <= 0;    // ok, not busy
+
+					// CMD55: APP_COND
+					'h77: reply <= 1;    // ok, busy
+
+					// CMD58: READ_OCR
+					'h7a: begin
+							reply <= 0;    // ok
+
+							reply0 <= OCR[31:24];   // bit 30 = 1 -> high capacity card
+							reply1 <= OCR[23:16];
+							reply2 <= OCR[15:8];
+							reply3 <= OCR[7:0];
+							reply_len <= 4;
+						end
+
+					// CMD59: CRC_ON_OFF
+					'h7b: reply <= 0;    // ok
+				endcase
+			end
+
+				// ---------- handle write -----------
+			case(write_state)
+				// do nothing in idle state
+				WR_STATE_IDLE: ;
+
+				// waiting for data token
+				WR_STATE_EXP_DTOKEN: begin
+					buffer_ptr <= 0;
+					if(cmd == 'h58) begin
+						if({sbuf,mosi} == 8'hfe) write_state <= WR_STATE_RECV_DATA;
+					end
+					else begin
+						if({sbuf,mosi} == 8'hfc) write_state <= WR_STATE_RECV_DATA;
+						if({sbuf,mosi} == 8'hfd) begin
+							write_state <= WR_STATE_IDLE;
+							rx_finish <= 1;
+						end
+					end
+				end
+
+				// transfer 512 bytes
+				WR_STATE_RECV_DATA: begin
+					// push one byte into local buffer
+					buffer_wr  <= 1;
+					buffer_din <= {sbuf, mosi};
+
+					// all bytes written?
+					if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0;
+				end
+
+				// transfer 1st crc byte
+				WR_STATE_RECV_CRC0:
+					write_state <= WR_STATE_RECV_CRC1;
+
+				// transfer 2nd crc byte
+				WR_STATE_RECV_CRC1:
+					write_state <= WR_STATE_SEND_DRESP;
+
+				// send data response
+				WR_STATE_SEND_DRESP: begin
+					write_state <= WR_STATE_BUSY;
+					io_ack <= 0;
+					sd_wr <= 1;
+				end
+
+				// wait for io controller to accept data
+				WR_STATE_BUSY:
+					if(io_ack) begin
+						if(cmd == 'h59) begin
+							write_state <= WR_STATE_EXP_DTOKEN;
+							lba <= lba + 1;
+						end
+						else begin
+							write_state <= WR_STATE_IDLE;
+							rx_finish <= 1;
+						end
+					end
+			endcase
+		end
+		
+		// wait for first 0 bit until start counting bits
+		if(!synced && !mosi) begin
+			synced   <= 1;
+			bit_cnt  <= 1; // byte assembly prepare for next time loop
+			sbuf     <= 7'b1111110; // byte assembly prepare for next time loop
+			rx_finish<= 0;
+		end else if (synced && tx_finish && rx_finish ) begin
+			synced   <= 0;
+			bit_cnt  <= 0;
+			rx_finish<= 0;
+		end
+	end
+end
+
+endmodule
+
+module sdbuf
+(
+	input	       clock_a,
+	input	       clock_b,
+	input	 [8:0] address_a,
+	input	 [8:0] address_b,
+	input	 [7:0] data_a,
+	input	 [7:0] data_b,
+	input	       wren_a,
+	input	       wren_b,
+	output [7:0] q_a,
+	output [7:0] q_b
+);
+
+altsyncram	altsyncram_component
+(
+	.address_a (address_a),
+	.address_b (address_b),
+	.clock0 (clock_a),
+	.clock1 (clock_b),
+	.data_a (data_a),
+	.data_b (data_b),
+	.wren_a (wren_a),
+	.wren_b (wren_b),
+	.q_a (q_a),
+	.q_b (q_b),
+	.aclr0 (1'b0),
+	.aclr1 (1'b0),
+	.addressstall_a (1'b0),
+	.addressstall_b (1'b0),
+	.byteena_a (1'b1),
+	.byteena_b (1'b1),
+	.clocken0 (1'b1),
+	.clocken1 (1'b1),
+	.clocken2 (1'b1),
+	.clocken3 (1'b1),
+	.eccstatus (),
+	.rden_a (1'b1),
+	.rden_b (1'b1)
+);
+defparam
+	altsyncram_component.address_reg_b = "CLOCK1",
+	altsyncram_component.clock_enable_input_a = "BYPASS",
+	altsyncram_component.clock_enable_input_b = "BYPASS",
+	altsyncram_component.clock_enable_output_a = "BYPASS",
+	altsyncram_component.clock_enable_output_b = "BYPASS",
+	altsyncram_component.indata_reg_b = "CLOCK1",
+	altsyncram_component.intended_device_family = "Cyclone V",
+	altsyncram_component.lpm_type = "altsyncram",
+	altsyncram_component.numwords_a = 512,
+	altsyncram_component.numwords_b = 512,
+	altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+	altsyncram_component.outdata_aclr_a = "NONE",
+	altsyncram_component.outdata_aclr_b = "NONE",
+	altsyncram_component.outdata_reg_a = "UNREGISTERED",
+	altsyncram_component.outdata_reg_b = "UNREGISTERED",
+	altsyncram_component.power_up_uninitialized = "FALSE",
+	altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+	altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
+	altsyncram_component.widthad_a = 9,
+	altsyncram_component.widthad_b = 9,
+	altsyncram_component.width_a = 8,
+	altsyncram_component.width_b = 8,
+	altsyncram_component.width_byteena_a = 1,
+	altsyncram_component.width_byteena_b = 1,
+	altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+endmodule
+
diff --git a/sys/sigma_delta_dac.v b/sys/sigma_delta_dac.v
new file mode 100644
index 0000000..d0d6be0
--- /dev/null
+++ b/sys/sigma_delta_dac.v
@@ -0,0 +1,33 @@
+//
+// PWM DAC
+//
+// MSBI is the highest bit number. NOT amount of bits!
+//
+module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1)
+(
+   output reg      DACout, //Average Output feeding analog lowpass
+   input  [MSBI:0] DACin,  //DAC input (excess 2**MSBI)
+   input           CLK,
+   input           RESET
+);
+
+reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
+reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
+reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
+reg [MSBI+2:0] DeltaB;     //B input of Delta Adder
+
+always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
+always @(*) DeltaAdder = DACin + DeltaB;
+always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
+
+always @(posedge CLK or posedge RESET) begin
+   if(RESET) begin
+      SigmaLatch <= 1'b1 << (MSBI+1);
+      DACout <= INV;
+   end else begin
+      SigmaLatch <= SigmaAdder;
+      DACout <= SigmaLatch[MSBI+2] ^ INV;
+   end
+end
+
+endmodule
diff --git a/sys/spdif.v b/sys/spdif.v
new file mode 100644
index 0000000..add51d3
--- /dev/null
+++ b/sys/spdif.v
@@ -0,0 +1,445 @@
+//-----------------------------------------------------------------
+//                        SPDIF Transmitter
+//                              V0.1
+//                        Ultra-Embedded.com
+//                          Copyright 2012
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: GPL
+// If you would like a version with a more permissive license for
+// use in closed source commercial applications please contact me
+// for details.
+//-----------------------------------------------------------------
+//
+// This file is open source HDL; you can redistribute it and/or 
+// modify it under the terms of the GNU General Public License as 
+// published by the Free Software Foundation; either version 2 of 
+// the License, or (at your option) any later version.
+//
+// This file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public 
+// License along with this file; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//-----------------------------------------------------------------
+// altera message_off 10762
+// altera message_off 10240
+
+module spdif
+
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+    parameter CLK_RATE              = 50000000,
+    parameter AUDIO_RATE            = 48000,
+
+    // Generated params
+    parameter WHOLE_CYCLES          = (CLK_RATE) / (AUDIO_RATE*128),
+    parameter ERROR_BASE            = 10000,
+    parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE)
+)
+
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+    input        clk_i,
+    input        rst_i,
+    input        half_rate,
+
+    // Output
+    output       spdif_o,
+
+    // Audio interface (16-bit x 2 = RL)
+    input [15:0] audio_r,
+    input [15:0] audio_l,
+    output       sample_req_o
+);
+
+reg lpf_ce;
+always @(posedge clk_i) begin
+	reg [2:0] div;
+
+	if(bit_clk_q) div <= div + 1'd1;
+	lpf_ce <= !div;
+end
+
+wire [15:0] al, ar;
+
+lpf_spdif lpf_l
+(
+   .CLK(clk_i),
+   .CE(lpf_ce),
+   .IDATA(audio_l),
+   .ODATA(al)
+);
+
+lpf_spdif lpf_r
+(
+   .CLK(clk_i),
+   .CE(lpf_ce),
+
+   .IDATA(audio_r),
+   .ODATA(ar)
+);
+
+reg         bit_clk_q;
+
+// Clock pulse generator
+always @ (posedge rst_i or posedge clk_i) begin
+	reg [31:0]  count_q;
+	reg [31:0]  error_q;
+	reg ce;
+
+	if (rst_i) begin
+		count_q   <= 0;
+		error_q   <= 0;
+		bit_clk_q <= 1;
+		ce        <= 0;
+	end
+	else
+	begin
+		if(count_q == WHOLE_CYCLES-1) begin
+			if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0];
+				count_q <= 0;
+			end else begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
+				count_q <= count_q + 1;
+			end
+		end else if(count_q == WHOLE_CYCLES) begin
+			count_q <= 0;
+		end else begin
+			count_q <= count_q + 1;
+		end
+
+		bit_clk_q <= 0;
+		if(!count_q) begin
+			ce <= ~ce;
+			if(~half_rate || ce) bit_clk_q <= 1;
+		end
+	end
+end
+
+//-----------------------------------------------------------------
+// Core SPDIF
+//-----------------------------------------------------------------
+
+wire [31:0] sample_i = {ar, al};
+
+spdif_core
+u_core
+(
+    .clk_i(clk_i),
+    .rst_i(rst_i),
+
+    .bit_out_en_i(bit_clk_q),
+
+    .spdif_o(spdif_o),
+
+    .sample_i(sample_i),
+    .sample_req_o(sample_req_o)
+);
+
+endmodule
+
+module spdif_core
+(
+    input           clk_i,
+    input           rst_i,
+
+    // SPDIF bit output enable
+    // Single cycle pulse synchronous to clk_i which drives
+    // the output bit rate.
+    // For 44.1KHz, 44100×32×2×2 = 5,644,800Hz
+    // For 48KHz,   48000×32×2×2 = 6,144,000Hz
+    input           bit_out_en_i,
+
+    // Output
+    output          spdif_o,
+
+    // Audio interface (16-bit x 2 = RL)
+    input [31:0]    sample_i,
+    output reg      sample_req_o
+);
+
+//-----------------------------------------------------------------
+// Registers
+//-----------------------------------------------------------------
+reg [15:0]  audio_sample_q;
+reg [8:0]   subframe_count_q;
+
+reg         load_subframe_q;
+reg [7:0]   preamble_q;
+wire [31:0] subframe_w;
+
+reg [5:0]   bit_count_q;
+reg         bit_toggle_q;
+
+reg         spdif_out_q;
+
+reg [5:0]   parity_count_q;
+
+//-----------------------------------------------------------------
+// Subframe Counter
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i )
+begin
+    if (rst_i == 1'b1)
+        subframe_count_q    <= 9'd0;
+    else if (load_subframe_q)
+    begin
+        // 192 frames (384 subframes) in an audio block
+        if (subframe_count_q == 9'd383)
+            subframe_count_q <= 9'd0;
+        else
+            subframe_count_q <= subframe_count_q + 9'd1;
+    end
+end
+
+//-----------------------------------------------------------------
+// Sample capture
+//-----------------------------------------------------------------
+reg [15:0] sample_buf_q;
+
+always @ (posedge rst_i or posedge clk_i )
+begin
+   if (rst_i == 1'b1)
+   begin
+        audio_sample_q      <= 16'h0000;
+        sample_buf_q        <= 16'h0000;
+        sample_req_o        <= 1'b0;
+   end
+   else if (load_subframe_q)
+   begin
+        // Start of frame (first subframe)?
+        if (subframe_count_q[0] == 1'b0)
+        begin
+            // Use left sample
+            audio_sample_q <= sample_i[15:0];
+
+            // Store right sample
+            sample_buf_q <= sample_i[31:16];
+
+            // Request next sample
+            sample_req_o <= 1'b1;
+        end
+        else
+        begin
+            // Use right sample
+            audio_sample_q <= sample_buf_q;
+
+            sample_req_o <= 1'b0;
+        end
+   end
+   else
+        sample_req_o <= 1'b0;
+end
+
+// Timeslots 3 - 0 = Preamble
+assign subframe_w[3:0] = 4'b0000;
+
+// Timeslots 7 - 4 = 24-bit audio LSB
+assign subframe_w[7:4] = 4'b0000;
+
+// Timeslots 11 - 8 = 20-bit audio LSB
+assign subframe_w[11:8] = 4'b0000;
+
+// Timeslots 27 - 12 = 16-bit audio
+assign subframe_w[27:12] = audio_sample_q;
+
+// Timeslots 28 = Validity
+assign subframe_w[28] = 1'b0; // Valid
+
+// Timeslots 29 = User bit
+assign subframe_w[29] = 1'b0;
+
+// Timeslots 30 = Channel status bit
+assign subframe_w[30] = 1'b0;
+
+// Timeslots 31 = Even Parity bit (31:4)
+assign subframe_w[31] = 1'b0;
+
+//-----------------------------------------------------------------
+// Preamble
+//-----------------------------------------------------------------
+localparam PREAMBLE_Z = 8'b00010111;
+localparam PREAMBLE_Y = 8'b00100111;
+localparam PREAMBLE_X = 8'b01000111;
+
+reg [7:0] preamble_r;
+
+always @ *
+begin
+    // Start of audio block?
+    // Z(B) - Left channel
+    if (subframe_count_q == 9'd0)
+        preamble_r = PREAMBLE_Z; // Z(B)
+    // Right Channel?
+    else if (subframe_count_q[0] == 1'b1)
+        preamble_r = PREAMBLE_Y; // Y(W)
+    // Left Channel (but not start of block)?
+    else
+        preamble_r = PREAMBLE_X; // X(M)
+end
+
+always @ (posedge rst_i or posedge clk_i )
+if (rst_i == 1'b1)
+    preamble_q  <= 8'h00;
+else if (load_subframe_q)
+    preamble_q  <= preamble_r;
+
+//-----------------------------------------------------------------
+// Parity Counter
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i )
+begin
+   if (rst_i == 1'b1)
+   begin
+        parity_count_q  <= 6'd0;
+   end
+   // Time to output a bit?
+   else if (bit_out_en_i)
+   begin
+        // Preamble bits?
+        if (bit_count_q < 6'd8)
+        begin
+            parity_count_q  <= 6'd0;
+        end
+        // Normal timeslots
+        else if (bit_count_q < 6'd62)
+        begin
+            // On first pass through this timeslot, count number of high bits
+            if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1)
+                parity_count_q <= parity_count_q + 6'd1;
+        end
+   end
+end
+
+//-----------------------------------------------------------------
+// Bit Counter
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i)
+begin
+    if (rst_i == 1'b1)
+    begin
+        bit_count_q     <= 6'b0;
+        load_subframe_q <= 1'b1;
+    end
+    // Time to output a bit?
+    else if (bit_out_en_i)
+    begin
+        // 32 timeslots (x2 for double frequency)
+        if (bit_count_q == 6'd63)
+        begin
+            bit_count_q     <= 6'd0;
+            load_subframe_q <= 1'b1;
+        end
+        else
+        begin
+            bit_count_q     <= bit_count_q + 6'd1;
+            load_subframe_q <= 1'b0;
+        end
+    end
+    else
+        load_subframe_q <= 1'b0;
+end
+
+//-----------------------------------------------------------------
+// Bit half toggle
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i)
+if (rst_i == 1'b1)
+    bit_toggle_q    <= 1'b0;
+// Time to output a bit?
+else if (bit_out_en_i)
+    bit_toggle_q <= ~bit_toggle_q;
+
+//-----------------------------------------------------------------
+// Output bit (BMC encoded)
+//-----------------------------------------------------------------
+reg bit_r;
+
+always @ *
+begin
+    bit_r = spdif_out_q;
+
+    // Time to output a bit?
+    if (bit_out_en_i)
+    begin
+        // Preamble bits?
+        if (bit_count_q < 6'd8)
+        begin
+            bit_r = preamble_q[bit_count_q[2:0]];
+        end
+        // Normal timeslots
+        else if (bit_count_q < 6'd62)
+        begin
+            if (subframe_w[bit_count_q / 2] == 1'b0)
+            begin
+                if (bit_toggle_q == 1'b0)
+                    bit_r = ~spdif_out_q;
+                else
+                    bit_r = spdif_out_q;
+            end
+            else
+                bit_r = ~spdif_out_q;
+        end
+        // Parity timeslot
+        else
+        begin
+            // Even number of high bits, make odd
+            if (parity_count_q[0] == 1'b0)
+            begin
+                if (bit_toggle_q == 1'b0)
+                    bit_r = ~spdif_out_q;
+                else
+                    bit_r = spdif_out_q;
+            end
+            else
+                bit_r = ~spdif_out_q;
+        end
+    end
+end
+
+always @ (posedge rst_i or posedge clk_i )
+if (rst_i == 1'b1)
+    spdif_out_q <= 1'b0;
+else
+    spdif_out_q <= bit_r;
+
+assign spdif_o  = spdif_out_q;
+
+endmodule
+
+module lpf_spdif
+(
+   input         CLK,
+   input         CE,
+   input  [15:0] IDATA,
+   output reg [15:0] ODATA
+);
+
+reg [511:0] acc;
+reg [20:0] sum;
+
+always @(*) begin
+	integer i;
+	sum = 0;
+	for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
+end
+
+always @(posedge CLK) begin
+	if(CE) begin
+		acc <= {acc[495:0], IDATA};
+		ODATA <= sum[20:5];
+	end
+end
+
+endmodule
diff --git a/sys/sys.qip b/sys/sys.qip
new file mode 100644
index 0000000..a0d70ab
--- /dev/null
+++ b/sys/sys.qip
@@ -0,0 +1,25 @@
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sys_top.v ]
+set_global_assignment -name SDC_FILE           [file join $::quartus(qip_path) sys_top.sdc ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll.qip ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_hdmi.qip ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_hdmi_cfg.qip ]
+set_global_assignment -name VHDL_FILE          [file join $::quartus(qip_path) ascal.vhd ]
+set_global_assignment -name VHDL_FILE          [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) scandoubler.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) scanlines.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) arcade_video.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) osd.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2c.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2s.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) spdif.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sigma_delta_dac.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sd_card.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) hps_io.v ]
+set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
diff --git a/sys/sys_q13.qip b/sys/sys_q13.qip
new file mode 100644
index 0000000..3642586
--- /dev/null
+++ b/sys/sys_q13.qip
@@ -0,0 +1,29 @@
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sys_top.v ]
+set_global_assignment -name SDC_FILE           [file join $::quartus(qip_path) sys_top.sdc ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll/pll_0002.v ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll/pll_0002.qip ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_hdmi_q13.qip ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll_hdmi_cfg.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_core.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_top.v ]
+set_global_assignment -name VHDL_FILE          [file join $::quartus(qip_path) ascal.vhd ]
+set_global_assignment -name VHDL_FILE          [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) scandoubler.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) scanlines.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) arcade_video.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) osd.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2c.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2s.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) spdif.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sigma_delta_dac.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sd_card.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) hps_io.v ]
+set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc
new file mode 100644
index 0000000..b66f9a3
--- /dev/null
+++ b/sys/sys_top.sdc
@@ -0,0 +1,38 @@
+# Specify root clocks
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
+create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] 
+create_clock -period 10.0 [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
+
+derive_pll_clocks
+
+# Specify PLL-generated clock(s)
+create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
+                       -name HDMI_CLK [get_ports HDMI_TX_CLK]
+
+derive_clock_uncertainty
+
+# Decouple different clock groups (to simplify routing)
+set_clock_groups -asynchronous \
+   -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+   -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
+   -group [get_clocks { *|h2f_user0_clk}] \
+   -group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
+
+set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
+set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
+
+set_false_path -from {*} -to [get_registers {wcalc[*] hcalc[*]}]
+
+
+# Put constraints on input ports
+set_false_path -from [get_ports {KEY*}] -to *
+set_false_path -from [get_ports {BTN_*}] -to *
+
+# Put constraints on output ports
+set_false_path -from * -to [get_ports {LED_*}]
+set_false_path -from * -to [get_ports {VGA_*}]
+set_false_path -from * -to [get_ports {AUDIO_SPDIF}]
+set_false_path -from * -to [get_ports {AUDIO_L}]
+set_false_path -from * -to [get_ports {AUDIO_R}]
diff --git a/sys/sys_top.v b/sys/sys_top.v
new file mode 100644
index 0000000..70adb80
--- /dev/null
+++ b/sys/sys_top.v
@@ -0,0 +1,933 @@
+//============================================================================
+//
+//  MiSTer hardware abstraction module (Arcade version)
+//  (c)2017-2019 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//
+//============================================================================
+
+module sys_top
+(
+	/////////// CLOCK //////////
+	input         FPGA_CLK1_50,
+	input         FPGA_CLK2_50,
+	input         FPGA_CLK3_50,
+
+	//////////// VGA ///////////
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	inout         VGA_HS,  // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive)
+	output		  VGA_VS,
+	input         VGA_EN,  // active low
+
+	/////////// AUDIO //////////
+	output		  AUDIO_L,
+	output		  AUDIO_R,
+	output		  AUDIO_SPDIF,
+
+	//////////// HDMI //////////
+	output        HDMI_I2C_SCL,
+	inout         HDMI_I2C_SDA,
+
+	output        HDMI_MCLK,
+	output        HDMI_SCLK,
+	output        HDMI_LRCLK,
+	output        HDMI_I2S,
+
+	output        HDMI_TX_CLK,
+	output        HDMI_TX_DE,
+	output [23:0] HDMI_TX_D,
+	output        HDMI_TX_HS,
+	output        HDMI_TX_VS,
+	
+	input         HDMI_TX_INT,
+
+	//////////// SDR ///////////
+	output [12:0] SDRAM_A,
+	inout  [15:0] SDRAM_DQ,
+	output        SDRAM_DQML,
+	output        SDRAM_DQMH,
+	output        SDRAM_nWE,
+	output        SDRAM_nCAS,
+	output        SDRAM_nRAS,
+	output        SDRAM_nCS,
+	output  [1:0] SDRAM_BA,
+	output        SDRAM_CLK,
+	output        SDRAM_CKE,
+
+	//////////// I/O ///////////
+	output        LED_USER,
+	output        LED_HDD,
+	output        LED_POWER,
+	input         BTN_USER,
+	input         BTN_OSD,
+	input         BTN_RESET,
+
+	//////////// SDIO ///////////
+	inout   [3:0] SDIO_DAT,
+	inout         SDIO_CMD,
+	output        SDIO_CLK,
+	input         SDIO_CD,
+
+	////////// MB KEY ///////////
+	input   [1:0] KEY,
+
+	////////// MB SWITCH ////////
+	input   [3:0] SW,
+
+	////////// MB LED ///////////
+	output  [7:0] LED,
+
+	///////// USER IO ///////////
+	inout   [5:0] USER_IO
+);
+
+
+assign SDIO_DAT[2:1] = 2'bZZ;
+
+
+//////////////////////////  LEDs  ///////////////////////////////////////
+
+reg [7:0] led_overtake = 0;
+reg [7:0] led_state    = 0;
+
+wire led_p =  led_power[1] ? ~led_power[0] : 1'b0;
+wire led_d =  led_disk[1]  ? ~led_disk[0]  : ~(led_disk[0] | gp_out[29]);
+wire led_u = ~led_user;
+wire led_locked;
+
+assign LED_POWER = led_p ? 1'bZ : 1'b0;
+assign LED_HDD   = led_d ? 1'bZ : 1'b0;
+assign LED_USER  = led_u ? 1'bZ : 1'b0;
+
+//LEDs on main board
+assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u});
+
+
+//////////////////////////  Buttons  ///////////////////////////////////
+reg btn_user, btn_osd;
+always @(posedge FPGA_CLK2_50) begin
+	integer div;
+	reg [7:0] deb_user;
+	reg [7:0] deb_osd;
+
+	div <= div + 1'b1;
+	if(div > 100000) div <= 0;
+	
+	if(!div) begin
+		deb_user <= {deb_user[6:0], ~(BTN_USER & KEY[1])};
+		if(&deb_user) btn_user <= 1;
+		if(!deb_user) btn_user <= 0;
+
+		deb_osd <= {deb_osd[6:0], ~(BTN_OSD & KEY[0])};
+		if(&deb_osd) btn_osd <= 1;
+		if(!deb_osd) btn_osd <= 0;
+	end
+end
+
+reg btn_reset = 1;
+always @(posedge FPGA_CLK2_50) btn_reset <= BTN_RESET;
+
+
+/////////////////////////  HPS I/O  /////////////////////////////////////
+
+// gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode)
+//                 used to avoid lockups while JTAG loading
+wire [31:0] gp_in = {1'b0, btn_user, btn_osd, 9'd0, io_ver, io_ack, io_wide, io_dout};
+wire [31:0] gp_out;
+
+wire  [1:0] io_ver    = 1; // 0 - standard MiST I/O (for quick porting of complex MiST cores). 1 - optimized HPS I/O. 2,3 - reserved for future.
+wire        io_wait;
+wire        io_wide;
+wire [15:0] io_dout;                  
+wire [15:0] io_din    = gp_outr[15:0];
+wire        io_clk    = gp_outr[17];
+wire        io_fpga   = gp_outr[18];
+wire        io_osd    = gp_outr[19];
+wire        io_uio    = gp_outr[20];
+//wire        io_sdd    = gp_outr[21]; // used only in ST core
+
+reg  io_ack;
+reg  rack;
+wire io_strobe = ~rack & io_clk;
+
+always @(posedge clk_sys) begin
+	if(~io_wait | io_strobe) begin
+		rack <= io_clk;
+		io_ack <= rack;
+	end
+end
+
+reg [31:0] gp_outr;
+always @(posedge clk_sys) begin
+	reg [31:0] gp_outd;
+	gp_outr <= gp_outd;
+	gp_outd <= gp_out;
+end
+
+wire  [7:0] core_type  = 'hA4; // A4 - generic core.
+
+// HPS will not communicate to core if magic is different
+wire [31:0] core_magic = {24'h5CA623, core_type};
+
+cyclonev_hps_interface_mpu_general_purpose h2f_gp
+(
+	.gp_in({~gp_out[31] ? core_magic : gp_in}),
+	.gp_out(gp_out)
+);
+
+
+reg [15:0] cfg;
+
+reg  cfg_got   = 0;
+reg  cfg_set   = 0;
+//wire [2:0] hdmi_res  = cfg[10:8];
+wire dvi_mode  = cfg[7];
+wire audio_96k = cfg[6];
+wire ypbpr_en  = cfg[5];
+wire csync     = cfg[3];
+wire vga_scaler= cfg[2];
+
+reg        cfg_custom_t = 0;
+reg  [5:0] cfg_custom_p1;
+reg [31:0] cfg_custom_p2;
+
+reg  [4:0] vol_att = 0;
+
+reg  [6:0] coef_addr;
+reg  [8:0] coef_data;
+reg        coef_wr = 0;
+
+wire  [7:0] ARX, ARY;
+reg  [11:0] VSET = 0;
+reg   [2:0] scaler_flt;
+reg         lowlat = 0;
+
+always@(posedge clk_sys) begin
+	reg  [7:0] cmd;
+	reg        has_cmd;
+	reg        old_strobe;
+	reg  [7:0] cnt = 0;
+
+	old_strobe <= io_strobe;
+	coef_wr <= 0;
+
+	if(~io_uio) begin
+		has_cmd <= 0;
+	end
+	else
+	if(~old_strobe & io_strobe) begin
+		if(!has_cmd) begin
+			has_cmd <= 1;
+			cmd <= io_din[7:0];
+			cnt <= 0;
+		end
+		else begin
+			if(cmd == 1) begin
+				cfg <= io_din;
+				cfg_set <= 1;
+			end
+			if(cmd == 'h20) begin
+				cfg_set <= 0;
+				cnt <= cnt + 1'd1;
+				if(cnt<8) begin
+					case(cnt)
+						0: if(WIDTH  != io_din[11:0]) begin WIDTH  <= io_din[11:0]; end
+						1: if(HFP    != io_din[11:0]) begin HFP    <= io_din[11:0]; end
+						2: if(HS     != io_din[11:0]) begin HS     <= io_din[11:0]; end
+						3: if(HBP    != io_din[11:0]) begin HBP    <= io_din[11:0]; end
+						4: if(HEIGHT != io_din[11:0]) begin HEIGHT <= io_din[11:0]; end
+						5: if(VFP    != io_din[11:0]) begin VFP    <= io_din[11:0]; end
+						6: if(VS     != io_din[11:0]) begin VS     <= io_din[11:0]; end
+						7: if(VBP    != io_din[11:0]) begin VBP    <= io_din[11:0]; end
+					endcase
+					if(cnt == 1) begin
+						cfg_custom_p1 <= 0;
+						cfg_custom_p2 <= 0;
+						cfg_custom_t <= ~cfg_custom_t;
+					end
+				end
+				else begin
+					if(cnt[1:0]==0) cfg_custom_p1 <= io_din[5:0];
+					if(cnt[1:0]==1) cfg_custom_p2[15:0]  <= io_din;
+					if(cnt[1:0]==2) begin
+						cfg_custom_p2[31:16] <= io_din;
+						cfg_custom_t <= ~cfg_custom_t;
+						cnt[2:0] <= 3'b100;
+					end
+					if(cnt == 8) lowlat <= io_din[15];
+				end
+			end
+			if(cmd == 'h25) {led_overtake, led_state} <= io_din;
+			if(cmd == 'h26) vol_att <= io_din[4:0];
+			if(cmd == 'h27) VSET    <= io_din[11:0];
+			if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
+			if(cmd == 'h2B) scaler_flt <= io_din[2:0];
+		end
+	end
+end
+
+always @(posedge clk_sys) begin
+	reg vsd, vsd2;
+	if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set;
+	else begin
+		vsd  <= HDMI_TX_VS;
+		vsd2 <= vsd;
+		if(~vsd2 & vsd) cfg_got <= cfg_set;
+	end
+end
+
+wire aspi_sck,aspi_mosi,aspi_ss;
+cyclonev_hps_interface_peripheral_spi_master spi
+(
+	.sclk_out(aspi_sck),
+	.txd(aspi_mosi), // mosi
+	.rxd(1),         // miso
+
+	.ss_0_n(aspi_ss),
+	.ss_in_n(1)
+);
+
+
+///////////////////////////  RESET  ///////////////////////////////////
+
+reg reset_req = 0;
+always @(posedge FPGA_CLK2_50) begin
+	reg [1:0] resetd, resetd2;
+	reg       old_reset;
+
+	//latch the reset
+	old_reset <= reset;
+	if(~old_reset & reset) reset_req <= 1;
+
+	//special combination to set/clear the reset
+	//preventing of accidental reset control
+	if(resetd==1) reset_req <= 1;
+	if(resetd==2 && resetd2==0) reset_req <= 0;
+
+	resetd  <= gp_out[31:30];
+	resetd2 <= resetd;
+end
+
+wire clk_100m;
+wire clk_hdmi  = ~HDMI_TX_CLK;  // Internal HDMI clock, inverted in relation to external clock
+wire clk_audio = FPGA_CLK3_50;
+
+////////////////////  SYSTEM MEMORY & SCALER  /////////////////////////
+
+wire reset;
+sysmem_lite sysmem
+(
+	//Reset/Clock
+	.reset_core_req(reset_req),
+	.reset_out(reset),
+	.clock(clk_100m),
+
+	//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
+	.reset_hps_cold_req(~btn_reset),
+
+	//64-bit DDR3 RAM access
+	.ram2_clk(clk_audio),
+	.ram2_address(aram_address),
+	.ram2_burstcount(aram_burstcount),
+	.ram2_waitrequest(aram_waitrequest),
+	.ram2_readdata(aram_readdata),
+	.ram2_readdatavalid(aram_readdatavalid),
+	.ram2_read(aram_read),
+	.ram2_writedata(0),
+	.ram2_byteenable(8'hFF),
+	.ram2_write(0),
+
+	// HDMI frame buffer
+	.vbuf_clk(clk_100m),
+	.vbuf_address(vbuf_address),
+	.vbuf_burstcount(vbuf_burstcount),
+	.vbuf_waitrequest(vbuf_waitrequest),
+	.vbuf_writedata(vbuf_writedata),
+	.vbuf_byteenable(vbuf_byteenable),
+	.vbuf_write(vbuf_write),
+	.vbuf_readdata(vbuf_readdata),
+	.vbuf_readdatavalid(vbuf_readdatavalid),
+	.vbuf_read(vbuf_read)
+);
+
+wire  [27:0] vbuf_address;
+wire   [7:0] vbuf_burstcount;
+wire         vbuf_waitrequest;
+wire [127:0] vbuf_readdata;
+wire         vbuf_readdatavalid;
+wire         vbuf_read;
+wire [127:0] vbuf_writedata;
+wire  [15:0] vbuf_byteenable;
+wire         vbuf_write;
+
+ascal 
+#(
+	.RAMBASE(32'h20000000),
+	.N_DW(128),
+	.N_AW(28)
+)
+ascal
+(
+	.reset_na (~reset_req),
+	.run      (1),
+	.freeze   (0),
+
+	.i_clk  (clk_ihdmi),
+	.i_ce   (ce_hpix),
+	.i_r    (hr_out),
+	.i_g    (hg_out),
+	.i_b    (hb_out),
+	.i_hs   (hhs),
+	.i_vs   (hvs),
+	.i_fl   (0),
+	.i_de   (hde),
+	.iauto  (1),
+	.himin  (0),
+	.himax  (0),
+	.vimin  (0),
+	.vimax  (0),
+
+	.o_clk  (clk_hdmi),
+	.o_ce   (1),
+	.o_r    (hdmi_data[23:16]),
+	.o_g    (hdmi_data[15:8]),
+	.o_b    (hdmi_data[7:0]),
+	.o_hs   (HDMI_TX_HS),
+	.o_vs   (HDMI_TX_VS),
+	.o_de   (hdmi_de),
+	.o_lltune (lltune),
+	.htotal (WIDTH+HFP+HBP+HS),
+	.hsstart(WIDTH + HFP),
+	.hsend  (WIDTH + HFP + HS),
+	.hdisp  (WIDTH),
+	.hmin   (hmin),
+	.hmax   (hmax),
+	.vtotal (HEIGHT+VFP+VBP+VS),
+	.vsstart(HEIGHT + VFP),
+	.vsend  (HEIGHT + VFP + VS),
+	.vdisp  (HEIGHT),
+	.vmin   (vmin),
+	.vmax   (vmax),
+
+	.mode     ({~lowlat,|scaler_flt,2'b00}),
+	.poly_clk (clk_sys),
+	.poly_a   (coef_addr),
+	.poly_dw  (coef_data),
+	.poly_wr  (coef_wr),
+
+	.avl_clk          (clk_100m),
+	.avl_waitrequest  (vbuf_waitrequest),
+	.avl_readdata     (vbuf_readdata),
+	.avl_readdatavalid(vbuf_readdatavalid),
+	.avl_burstcount   (vbuf_burstcount),
+	.avl_writedata    (vbuf_writedata),
+	.avl_address      (vbuf_address),
+	.avl_write        (vbuf_write),
+	.avl_read         (vbuf_read),
+	.avl_byteenable   (vbuf_byteenable)
+);
+
+reg [11:0] hmin;
+reg [11:0] hmax;
+reg [11:0] vmin;
+reg [11:0] vmax;
+
+always @(posedge clk_vid) begin
+	reg [31:0] wcalc;
+	reg [31:0] hcalc;
+	reg  [2:0] state;
+	reg [11:0] videow;
+	reg [11:0] videoh;
+
+	state <= state + 1'd1;
+	case(state)
+		0: begin
+				wcalc <= VSET ? (VSET*ARX)/ARY : (HEIGHT*ARX)/ARY;
+				hcalc <= (WIDTH*ARY)/ARX;
+			end
+		6: begin
+				videow <= (!VSET && (wcalc > WIDTH))     ? WIDTH  : wcalc[11:0];
+				videoh <= VSET ? VSET : (hcalc > HEIGHT) ? HEIGHT : hcalc[11:0];
+			end
+		7: begin
+				hmin <= ((WIDTH  - videow)>>1);
+				hmax <= ((WIDTH  - videow)>>1) + videow - 1'd1;
+				vmin <= ((HEIGHT - videoh)>>1);
+				vmax <= ((HEIGHT - videoh)>>1) + videoh - 1'd1;
+			end
+	endcase
+end
+
+wire [15:0] lltune;
+
+pll_hdmi_adj pll_hdmi_adj
+(
+   .clk(FPGA_CLK1_50),
+	.reset_na(~reset_req),
+
+	.llena(lowlat),
+	.lltune(lltune),
+	.locked(led_locked),
+	.i_waitrequest(adj_waitrequest),
+	.i_write(adj_write),
+	.i_address(adj_address),
+	.i_writedata(adj_data),
+	.o_waitrequest(cfg_waitrequest),
+	.o_write(cfg_write),
+	.o_address(cfg_address),
+	.o_writedata(cfg_data)
+);
+
+
+/////////////////////////  HDMI output  /////////////////////////////////
+
+pll_hdmi pll_hdmi
+(
+	.refclk(FPGA_CLK1_50),
+	.rst(reset_req),
+	.reconfig_to_pll(reconfig_to_pll),
+	.reconfig_from_pll(reconfig_from_pll),
+	.outclk_0(HDMI_TX_CLK)
+);
+
+//1920x1080@60 PCLK=148.5MHz CEA
+reg  [11:0] WIDTH  = 1920;
+reg  [11:0] HFP    = 88;
+reg  [11:0] HS     = 48;
+reg  [11:0] HBP    = 148;
+reg  [11:0] HEIGHT = 1080;
+reg  [11:0] VFP    = 4;
+reg  [11:0] VS     = 5;
+reg  [11:0] VBP    = 36;
+
+wire [63:0] reconfig_to_pll;
+wire [63:0] reconfig_from_pll;
+wire        cfg_waitrequest,adj_waitrequest;
+reg         cfg_write,adj_write;
+reg   [5:0] cfg_address,adj_address;
+reg  [31:0] cfg_data,adj_data;
+
+pll_hdmi_cfg pll_hdmi_cfg
+(
+	.mgmt_clk(FPGA_CLK1_50),
+	.mgmt_reset(reset_req),
+	.mgmt_waitrequest(cfg_waitrequest),
+	.mgmt_read(0),
+	.mgmt_readdata(),
+	.mgmt_write(cfg_write),
+	.mgmt_address(cfg_address),
+	.mgmt_writedata(cfg_data),
+	.reconfig_to_pll(reconfig_to_pll),
+	.reconfig_from_pll(reconfig_from_pll)
+);
+
+reg cfg_ready = 0;
+
+always @(posedge FPGA_CLK1_50) begin
+	reg gotd = 0, gotd2 = 0;
+	reg custd = 0, custd2 = 0;
+	reg old_wait = 0;
+
+	gotd  <= cfg_got;
+	gotd2 <= gotd;
+	
+	adj_write <= 0;
+	
+	custd <= cfg_custom_t;
+	custd2 <= custd;
+	if(custd2 != custd & ~gotd) begin
+		adj_address <= cfg_custom_p1;
+		adj_data <= cfg_custom_p2;
+		adj_write <= 1;
+	end
+
+	if(~gotd2 & gotd) begin
+		adj_address <= 2;
+		adj_data <= 0;
+		adj_write <= 1;
+	end
+
+	old_wait <= adj_waitrequest;
+	if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1;
+end
+
+hdmi_config hdmi_config
+(
+	.iCLK(FPGA_CLK1_50),
+	.iRST_N(cfg_ready & ~HDMI_TX_INT),
+
+	.I2C_SCL(HDMI_I2C_SCL),
+	.I2C_SDA(HDMI_I2C_SDA),
+
+	.dvi_mode(dvi_mode),
+	.audio_96k(audio_96k)
+);
+
+wire [23:0] hdmi_data;
+wire [23:0] hdmi_data_sl;
+wire        hdmi_de;
+
+scanlines #(1) HDMI_scanlines
+(
+	.clk(clk_hdmi),
+
+	.scanlines(scanlines),
+	.din(hdmi_data),
+	.dout(hdmi_data_sl),
+	.hs(HDMI_TX_HS),
+	.vs(HDMI_TX_VS)
+);
+
+osd hdmi_osd
+(
+	.clk_sys(clk_sys),
+
+	.io_osd(io_osd),
+	.io_strobe(io_strobe),
+	.io_din(io_din),
+
+	.clk_video(clk_hdmi),
+	.din(hdmi_data_sl),
+	.dout(HDMI_TX_D),
+	.de_in(hdmi_de),
+	.de_out(HDMI_TX_DE)
+);
+
+/////////////////////////  VGA output  //////////////////////////////////
+
+wire [23:0] vga_data_sl;
+
+scanlines #(0) VGA_scanlines
+(
+	.clk(clk_vid),
+
+	.scanlines(scanlines),
+	.din(de ? {r_out, g_out, b_out} : 24'd0),
+	.dout(vga_data_sl),
+	.hs(hs1),
+	.vs(vs1)
+);
+
+osd vga_osd
+(
+	.clk_sys(clk_sys),
+
+	.io_osd(io_osd),
+	.io_strobe(io_strobe),
+	.io_din(io_din),
+
+	.clk_video(clk_vid),
+	.din(vga_data_sl),
+	.dout(vga_q),
+	.de_in(de)
+);
+
+wire [23:0] vga_q;
+wire [23:0] vga_o;
+
+vga_out vga_out
+(
+	.ypbpr_full(1),
+	.ypbpr_en(ypbpr_en),
+	.dout(vga_o),
+	.din(vga_scaler ? {24{HDMI_TX_DE}} & HDMI_TX_D : vga_q)
+);
+
+wire vs1 = vga_scaler ? HDMI_TX_VS : vs;
+wire hs1 = vga_scaler ? HDMI_TX_HS : hs;
+
+assign VGA_VS = VGA_EN ? 1'bZ      : csync ?     1'b1     : ~vs1;
+assign VGA_HS = VGA_EN ? 1'bZ      : csync ? ~(vs1 ^ hs1) : ~hs1;
+assign VGA_R  = VGA_EN ? 6'bZZZZZZ : vga_o[23:18];
+assign VGA_G  = VGA_EN ? 6'bZZZZZZ : vga_o[15:10];
+assign VGA_B  = VGA_EN ? 6'bZZZZZZ : vga_o[7:2];
+
+
+/////////////////////////  Audio output  ////////////////////////////////
+
+assign AUDIO_SPDIF = SW[0] ? HDMI_LRCLK : aspdif;
+assign AUDIO_R     = SW[0] ? HDMI_I2S   : anr;
+assign AUDIO_L     = SW[0] ? HDMI_SCLK  : anl;
+
+assign HDMI_MCLK = 0;
+i2s i2s
+(
+	.clk_sys(clk_audio),
+	.reset(reset),
+
+	.half_rate(~audio_96k),
+
+	.sclk(HDMI_SCLK),
+	.lrclk(HDMI_LRCLK),
+	.sdata(HDMI_I2S),
+
+	.left_chan (audio_l),
+	.right_chan(audio_r)
+);
+
+wire anl;
+sigma_delta_dac #(15) dac_l
+(
+	.CLK(clk_audio),
+	.RESET(reset),
+	.DACin({~audio_l[15], audio_l[14:0]}),
+	.DACout(anl)
+);
+
+wire anr;
+sigma_delta_dac #(15) dac_r
+(
+	.CLK(clk_audio),
+	.RESET(reset),
+	.DACin({~audio_r[15], audio_r[14:0]}),
+	.DACout(anr)
+);
+
+wire aspdif;
+spdif toslink
+(
+	.clk_i(clk_audio),
+
+	.rst_i(reset),
+	.half_rate(0),
+
+	.audio_l(audio_l),
+	.audio_r(audio_r),
+
+	.spdif_o(aspdif)
+);
+
+wire [15:0] audio_l, audio_l_pre;
+aud_mix_top audmix_l
+(
+	.clk(clk_audio),
+	.att(vol_att),
+	.mix(audio_mix),
+	.is_signed(audio_s),
+
+	.core_audio(audio_ls),
+	.pre_in(audio_r_pre),
+	.linux_audio(alsa_l),
+
+	.pre_out(audio_l_pre),
+	.out(audio_l)
+);
+
+wire [15:0] audio_r, audio_r_pre;
+aud_mix_top audmix_r
+(
+	.clk(clk_audio),
+	.att(vol_att),
+	.mix(audio_mix),
+	.is_signed(audio_s),
+
+	.core_audio(audio_rs),
+	.pre_in(audio_l_pre),
+	.linux_audio(alsa_r),
+
+	.pre_out(audio_r_pre),
+	.out(audio_r)
+);
+
+wire [28:0] aram_address;
+wire  [7:0] aram_burstcount;
+wire        aram_waitrequest;
+wire [63:0] aram_readdata;
+wire        aram_readdatavalid;
+wire        aram_read;
+
+wire [15:0] alsa_l, alsa_r;
+
+alsa alsa
+(
+	.reset(reset),
+
+	.ram_clk(clk_audio),
+	.ram_address(aram_address),
+	.ram_burstcount(aram_burstcount),
+	.ram_waitrequest(aram_waitrequest),
+	.ram_readdata(aram_readdata),
+	.ram_readdatavalid(aram_readdatavalid),
+	.ram_read(aram_read),
+
+	.spi_ss(aspi_ss),
+	.spi_sck(aspi_sck),
+	.spi_mosi(aspi_mosi),
+
+	.pcm_l(alsa_l),
+	.pcm_r(alsa_r)
+);
+
+
+////////////////  User I/O (USB 3.0 connector) /////////////////////////
+
+assign USER_IO[0] = 1'bZ;
+assign USER_IO[1] = 1'bZ;
+assign USER_IO[2] = (SW[1] & ~HDMI_I2S)   ? 1'b0 : 1'bZ;
+assign USER_IO[3] = 1'bZ;
+assign USER_IO[4] = (SW[1] & ~HDMI_SCLK)  ? 1'b0 : 1'bZ;
+assign USER_IO[5] = (SW[1] & ~HDMI_LRCLK) ? 1'b0 : 1'bZ;
+
+
+///////////////////  User module connection ////////////////////////////
+
+wire [15:0] audio_ls, audio_rs;
+wire        audio_s;
+wire  [1:0] audio_mix;
+wire  [7:0] r_out, g_out, b_out;
+wire        vs, hs, de;
+wire  [1:0] scanlines;
+wire        clk_sys, clk_vid, ce_pix;
+wire        led_user;
+wire  [1:0] led_power;
+wire  [1:0] led_disk;
+
+wire  [7:0] hr_out, hg_out, hb_out;
+wire        hvs, hhs, hde;
+wire        clk_ihdmi, ce_hpix;
+
+wire hvs_emu, hhs_emu;
+sync_fix hdmi_sync_v(clk_ihdmi, hvs_emu, hvs);
+sync_fix hdmi_sync_h(clk_ihdmi, hhs_emu, hhs);
+
+wire vs_emu, hs_emu;
+sync_fix sync_v(clk_vid, vs_emu, vs);
+sync_fix sync_h(clk_vid, hs_emu, hs);
+
+assign audio_mix = 0;
+assign {SDIO_CLK, SDIO_CMD, SDIO_DAT[3]} = {3{1'bZ}};
+assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = {39{1'bZ}};
+
+emu emu
+(
+	.CLK_50M(FPGA_CLK3_50),
+	.RESET(reset),
+	.HPS_BUS({HDMI_TX_VS, clk_100m, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
+
+	.VGA_CLK(clk_vid),
+	.VGA_CE(ce_pix),
+	.VGA_R(r_out),
+	.VGA_G(g_out),
+	.VGA_B(b_out),
+	.VGA_HS(hs_emu),
+	.VGA_VS(vs_emu),
+	.VGA_DE(de),
+
+	.HDMI_CLK(clk_ihdmi),
+	.HDMI_CE(ce_hpix),
+	.HDMI_R(hr_out),
+	.HDMI_G(hg_out),
+	.HDMI_B(hb_out),
+	.HDMI_HS(hhs_emu),
+	.HDMI_VS(hvs_emu),
+	.HDMI_DE(hde),
+	.HDMI_SL(scanlines),
+	.HDMI_ARX(ARX),
+	.HDMI_ARY(ARY),
+
+	.LED_USER(led_user),
+	.LED_POWER(led_power),
+	.LED_DISK(led_disk),
+
+	.AUDIO_L(audio_ls),
+	.AUDIO_R(audio_rs),
+	.AUDIO_S(audio_s)
+);
+
+endmodule
+
+/////////////////////////////////////////////////////////////////////
+
+module sync_fix
+(
+	input clk,
+	
+	input sync_in,
+	output sync_out
+);
+
+assign sync_out = sync_in ^ pol;
+
+reg pol;
+always @(posedge clk) begin
+	integer pos = 0, neg = 0, cnt = 0;
+	reg s1,s2;
+
+	s1 <= sync_in;
+	s2 <= s1;
+
+	if(~s2 & s1) neg <= cnt;
+	if(s2 & ~s1) pos <= cnt;
+
+	cnt <= cnt + 1;
+	if(s2 != s1) cnt <= 0;
+
+	pol <= pos > neg;
+end
+
+endmodule
+
+/////////////////////////////////////////////////////////////////////
+
+module aud_mix_top
+(
+	input             clk,
+
+	input       [4:0] att,
+	input       [1:0] mix,
+	input             is_signed,
+
+	input      [15:0] core_audio,
+	input      [15:0] linux_audio,
+	input      [15:0] pre_in,
+
+	output reg [15:0] pre_out,
+	output reg [15:0] out
+);
+
+reg [15:0] ca;
+always @(posedge clk) begin
+	reg [15:0] d1,d2,d3;
+
+	d1 <= core_audio; d2<=d1; d3<=d2;
+	if(d2 == d3) ca <= d2;
+end
+
+always @(posedge clk) begin
+	reg signed [16:0] a1, a2, a3, a4;
+
+	a1 <= is_signed ? {ca[15],ca} : {2'b00,ca[15:1]};
+	a2 <= a1 + {linux_audio[15],linux_audio};
+
+	pre_out <= a2[16:1];
+
+	case(mix)
+		0: a3 <= a2;
+		1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]);
+		2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]);
+		3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in};
+	endcase
+
+	if(att[4]) a4 <= 0;
+	else a4 <= a3 >>> att[3:0];
+
+	//clamping
+	out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0];
+end
+
+endmodule
diff --git a/sys/sysmem.sv b/sys/sysmem.sv
new file mode 100644
index 0000000..c90395e
--- /dev/null
+++ b/sys/sysmem.sv
@@ -0,0 +1,429 @@
+`timescale 1 ps / 1 ps
+module sysmem_lite
+(
+	output         clock,
+	output         reset_out,
+
+	input          reset_hps_cold_req,
+	input          reset_hps_warm_req,
+	input          reset_core_req,
+
+	input          ram1_clk,
+	input   [28:0] ram1_address,
+	input    [7:0] ram1_burstcount,
+	output         ram1_waitrequest,
+	output  [63:0] ram1_readdata,
+	output         ram1_readdatavalid,
+	input          ram1_read,
+	input   [63:0] ram1_writedata,
+	input    [7:0] ram1_byteenable,
+	input          ram1_write,
+
+	input          ram2_clk,
+	input   [28:0] ram2_address,
+	input    [7:0] ram2_burstcount,
+	output         ram2_waitrequest,
+	output  [63:0] ram2_readdata,
+	output         ram2_readdatavalid,
+	input          ram2_read,
+	input   [63:0] ram2_writedata,
+	input    [7:0] ram2_byteenable,
+	input          ram2_write,
+
+	input          vbuf_clk,
+	input   [27:0] vbuf_address,
+	input    [7:0] vbuf_burstcount,
+	output         vbuf_waitrequest,
+	output [127:0] vbuf_readdata,
+	output         vbuf_readdatavalid,
+	input          vbuf_read,
+	input  [127:0] vbuf_writedata,
+	input   [15:0] vbuf_byteenable,
+	input          vbuf_write
+);
+
+assign reset_out = ~init_reset_n | ~hps_h2f_reset_n | reset_core_req;
+
+sysmem_HPS_fpga_interfaces fpga_interfaces (
+	.f2h_cold_rst_req_n       (~reset_hps_cold_req),
+	.f2h_warm_rst_req_n       (~reset_hps_warm_req),
+	.h2f_user0_clk            (clock),
+	.h2f_rst_n                (hps_h2f_reset_n),
+	.f2h_sdram0_clk           (vbuf_clk),
+	.f2h_sdram0_ADDRESS       (vbuf_address),
+	.f2h_sdram0_BURSTCOUNT    (vbuf_burstcount),
+	.f2h_sdram0_WAITREQUEST   (vbuf_waitrequest),
+	.f2h_sdram0_READDATA      (vbuf_readdata),
+	.f2h_sdram0_READDATAVALID (vbuf_readdatavalid),
+	.f2h_sdram0_READ          (vbuf_read),
+	.f2h_sdram0_WRITEDATA     (vbuf_writedata),
+	.f2h_sdram0_BYTEENABLE    (vbuf_byteenable),
+	.f2h_sdram0_WRITE         (vbuf_write),
+	.f2h_sdram1_clk           (ram1_clk),
+	.f2h_sdram1_ADDRESS       (ram1_address),
+	.f2h_sdram1_BURSTCOUNT    (ram1_burstcount),
+	.f2h_sdram1_WAITREQUEST   (ram1_waitrequest),
+	.f2h_sdram1_READDATA      (ram1_readdata),
+	.f2h_sdram1_READDATAVALID (ram1_readdatavalid),
+	.f2h_sdram1_READ          (ram1_read),
+	.f2h_sdram1_WRITEDATA     (ram1_writedata),
+	.f2h_sdram1_BYTEENABLE    (ram1_byteenable),
+	.f2h_sdram1_WRITE         (ram1_write),
+	.f2h_sdram2_clk           (ram2_clk),
+	.f2h_sdram2_ADDRESS       (ram2_address),
+	.f2h_sdram2_BURSTCOUNT    (ram2_burstcount),
+	.f2h_sdram2_WAITREQUEST   (ram2_waitrequest),
+	.f2h_sdram2_READDATA      (ram2_readdata),
+	.f2h_sdram2_READDATAVALID (ram2_readdatavalid),
+	.f2h_sdram2_READ          (ram2_read),
+	.f2h_sdram2_WRITEDATA     (ram2_writedata),
+	.f2h_sdram2_BYTEENABLE    (ram2_byteenable),
+	.f2h_sdram2_WRITE         (ram2_write)
+);
+
+wire hps_h2f_reset_n;
+
+reg init_reset_n = 0;
+always @(posedge clock) begin
+	integer timeout = 0;
+
+	if(timeout < 2000000) begin
+		init_reset_n <= 0;
+		timeout <= timeout + 1;
+	end
+	else init_reset_n <= 1;
+end
+
+endmodule
+
+
+module sysmem_HPS_fpga_interfaces
+(
+	// h2f_reset
+	output wire [1 - 1 : 0 ] h2f_rst_n
+
+	// f2h_cold_reset_req
+	,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
+
+	// f2h_warm_reset_req
+	,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
+
+	// h2f_user0_clock
+	,output wire [1 - 1 : 0 ] h2f_user0_clk
+
+	// f2h_sdram0_data
+	,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
+	,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
+	,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
+	,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
+	,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
+	,input wire [1 - 1 : 0 ] f2h_sdram0_READ
+	,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
+	,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
+	,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
+
+	// f2h_sdram0_clock
+	,input wire [1 - 1 : 0 ] f2h_sdram0_clk
+
+	// f2h_sdram1_data
+	,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
+	,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
+	,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
+	,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
+	,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
+	,input wire [1 - 1 : 0 ] f2h_sdram1_READ
+	,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
+	,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
+	,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE
+
+	// f2h_sdram1_clock
+	,input wire [1 - 1 : 0 ] f2h_sdram1_clk
+
+	// f2h_sdram2_data
+	,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
+	,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
+	,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
+	,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
+	,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
+	,input wire [1 - 1 : 0 ] f2h_sdram2_READ
+	,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
+	,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
+	,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE
+
+	// f2h_sdram2_clock
+	,input wire [1 - 1 : 0 ] f2h_sdram2_clk
+);
+
+
+wire [29 - 1 : 0] intermediate;
+assign intermediate[0:0] = ~intermediate[1:1];
+assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
+assign intermediate[2:2] = intermediate[9:9];
+assign intermediate[3:3] = intermediate[9:9];
+assign intermediate[5:5] = intermediate[9:9];
+assign intermediate[6:6] = intermediate[9:9];
+assign intermediate[10:10] = intermediate[9:9];
+assign intermediate[11:11] = ~intermediate[12:12];
+assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
+assign intermediate[13:13] = intermediate[18:18];
+assign intermediate[15:15] = intermediate[18:18];
+assign intermediate[19:19] = intermediate[18:18];
+assign intermediate[20:20] = ~intermediate[21:21];
+assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
+assign intermediate[22:22] = intermediate[27:27];
+assign intermediate[24:24] = intermediate[27:27];
+assign intermediate[28:28] = intermediate[27:27];
+assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
+assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
+assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
+assign intermediate[4:4] = f2h_sdram0_READ[0:0];
+assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
+assign intermediate[9:9] = f2h_sdram0_clk[0:0];
+assign intermediate[14:14] = f2h_sdram1_READ[0:0];
+assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
+assign intermediate[18:18] = f2h_sdram1_clk[0:0];
+assign intermediate[23:23] = f2h_sdram2_READ[0:0];
+assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
+assign intermediate[27:27] = f2h_sdram2_clk[0:0];
+
+cyclonev_hps_interface_clocks_resets clocks_resets(
+ .f2h_warm_rst_req_n({
+    f2h_warm_rst_req_n[0:0] // 0:0
+  })
+,.f2h_pending_rst_ack({
+    1'b1 // 0:0
+  })
+,.f2h_dbg_rst_req_n({
+    1'b1 // 0:0
+  })
+,.h2f_rst_n({
+    h2f_rst_n[0:0] // 0:0
+  })
+,.f2h_cold_rst_req_n({
+    f2h_cold_rst_req_n[0:0] // 0:0
+  })
+,.h2f_user0_clk({
+    h2f_user0_clk[0:0] // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_dbg_apb debug_apb(
+ .DBG_APB_DISABLE({
+    1'b0 // 0:0
+  })
+,.P_CLK_EN({
+    1'b0 // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_tpiu_trace tpiu(
+ .traceclk_ctl({
+    1'b1 // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
+ .boot_from_fpga_ready({
+    1'b0 // 0:0
+  })
+,.boot_from_fpga_on_failure({
+    1'b0 // 0:0
+  })
+,.bsel_en({
+    1'b0 // 0:0
+  })
+,.csel_en({
+    1'b0 // 0:0
+  })
+,.csel({
+    2'b01 // 1:0
+  })
+,.bsel({
+    3'b001 // 2:0
+  })
+);
+
+
+cyclonev_hps_interface_fpga2hps fpga2hps(
+ .port_size_config({
+    2'b11 // 1:0
+  })
+);
+
+
+cyclonev_hps_interface_hps2fpga hps2fpga(
+ .port_size_config({
+    2'b11 // 1:0
+  })
+);
+
+
+cyclonev_hps_interface_fpga2sdram f2sdram(
+ .cfg_rfifo_cport_map({
+    16'b0010000100000000 // 15:0
+  })
+,.cfg_wfifo_cport_map({
+    16'b0010000100000000 // 15:0
+  })
+,.rd_ready_3({
+    1'b1 // 0:0
+  })
+,.cmd_port_clk_2({
+    intermediate[28:28] // 0:0
+  })
+,.rd_ready_2({
+    1'b1 // 0:0
+  })
+,.cmd_port_clk_1({
+    intermediate[19:19] // 0:0
+  })
+,.rd_ready_1({
+    1'b1 // 0:0
+  })
+,.cmd_port_clk_0({
+    intermediate[10:10] // 0:0
+  })
+,.rd_ready_0({
+    1'b1 // 0:0
+  })
+,.wrack_ready_2({
+    1'b1 // 0:0
+  })
+,.wrack_ready_1({
+    1'b1 // 0:0
+  })
+,.wrack_ready_0({
+    1'b1 // 0:0
+  })
+,.cmd_ready_2({
+    intermediate[21:21] // 0:0
+  })
+,.cmd_ready_1({
+    intermediate[12:12] // 0:0
+  })
+,.cmd_ready_0({
+    intermediate[1:1] // 0:0
+  })
+,.cfg_port_width({
+    12'b000000010110 // 11:0
+  })
+,.rd_valid_3({
+    f2h_sdram2_READDATAVALID[0:0] // 0:0
+  })
+,.rd_valid_2({
+    f2h_sdram1_READDATAVALID[0:0] // 0:0
+  })
+,.rd_valid_1({
+    f2h_sdram0_READDATAVALID[0:0] // 0:0
+  })
+,.rd_clk_3({
+    intermediate[22:22] // 0:0
+  })
+,.rd_data_3({
+    f2h_sdram2_READDATA[63:0] // 63:0
+  })
+,.rd_clk_2({
+    intermediate[13:13] // 0:0
+  })
+,.rd_data_2({
+    f2h_sdram1_READDATA[63:0] // 63:0
+  })
+,.rd_clk_1({
+    intermediate[3:3] // 0:0
+  })
+,.rd_data_1({
+    f2h_sdram0_READDATA[127:64] // 63:0
+  })
+,.rd_clk_0({
+    intermediate[2:2] // 0:0
+  })
+,.rd_data_0({
+    f2h_sdram0_READDATA[63:0] // 63:0
+  })
+,.cfg_axi_mm_select({
+    6'b000000 // 5:0
+  })
+,.cmd_valid_2({
+    intermediate[26:26] // 0:0
+  })
+,.cmd_valid_1({
+    intermediate[17:17] // 0:0
+  })
+,.cmd_valid_0({
+    intermediate[8:8] // 0:0
+  })
+,.cfg_cport_rfifo_map({
+    18'b000000000011010000 // 17:0
+  })
+,.wr_data_3({
+    2'b00 // 89:88
+   ,f2h_sdram2_BYTEENABLE[7:0] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram2_WRITEDATA[63:0] // 63:0
+  })
+,.wr_data_2({
+    2'b00 // 89:88
+   ,f2h_sdram1_BYTEENABLE[7:0] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram1_WRITEDATA[63:0] // 63:0
+  })
+,.wr_data_1({
+    2'b00 // 89:88
+   ,f2h_sdram0_BYTEENABLE[15:8] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram0_WRITEDATA[127:64] // 63:0
+  })
+,.cfg_cport_type({
+    12'b000000111111 // 11:0
+  })
+,.wr_data_0({
+    2'b00 // 89:88
+   ,f2h_sdram0_BYTEENABLE[7:0] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram0_WRITEDATA[63:0] // 63:0
+  })
+,.cfg_cport_wfifo_map({
+    18'b000000000011010000 // 17:0
+  })
+,.wr_clk_3({
+    intermediate[24:24] // 0:0
+  })
+,.wr_clk_2({
+    intermediate[15:15] // 0:0
+  })
+,.wr_clk_1({
+    intermediate[6:6] // 0:0
+  })
+,.wr_clk_0({
+    intermediate[5:5] // 0:0
+  })
+,.cmd_data_2({
+    18'b000000000000000000 // 59:42
+   ,f2h_sdram2_BURSTCOUNT[7:0] // 41:34
+   ,3'b000 // 33:31
+   ,f2h_sdram2_ADDRESS[28:0] // 30:2
+   ,intermediate[25:25] // 1:1
+   ,intermediate[23:23] // 0:0
+  })
+,.cmd_data_1({
+    18'b000000000000000000 // 59:42
+   ,f2h_sdram1_BURSTCOUNT[7:0] // 41:34
+   ,3'b000 // 33:31
+   ,f2h_sdram1_ADDRESS[28:0] // 30:2
+   ,intermediate[16:16] // 1:1
+   ,intermediate[14:14] // 0:0
+  })
+,.cmd_data_0({
+    18'b000000000000000000 // 59:42
+   ,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
+   ,4'b0000 // 33:30
+   ,f2h_sdram0_ADDRESS[27:0] // 29:2
+   ,intermediate[7:7] // 1:1
+   ,intermediate[4:4] // 0:0
+  })
+);
+
+endmodule
diff --git a/sys/vga_out.sv b/sys/vga_out.sv
new file mode 100644
index 0000000..e316000
--- /dev/null
+++ b/sys/vga_out.sv
@@ -0,0 +1,65 @@
+
+module vga_out
+(
+	input         ypbpr_full,
+	input         ypbpr_en,
+
+	input  [23:0] din,
+	output [23:0] dout
+);
+
+wire [5:0] yuv_full[225] = '{
+  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
+  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
+  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
+  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
+  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
+  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
+  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
+  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
+  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
+  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
+  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
+  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
+  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
+  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
+  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
+  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
+  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
+  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
+  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
+  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
+  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
+  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
+  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
+  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
+  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
+  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
+  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
+  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
+  6'd63
+};
+
+wire [5:0] red   = din[23:18];
+wire [5:0] green = din[15:10];
+wire [5:0] blue  = din[7:2];
+
+// http://marsee101.blog19.fc2.com/blog-entry-2311.html
+// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
+// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
+// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
+
+wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
+wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
+wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
+
+wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
+wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
+wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
+
+assign dout[23:16] = ypbpr_en ? {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00} : din[23:16];
+assign dout[15:8]  = ypbpr_en ? {(ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]), 2'b00} : din[15:8];
+assign dout[7:0]   = ypbpr_en ? {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00} : din[7:0];
+
+
+endmodule
diff --git a/sys/video_cleaner.sv b/sys/video_cleaner.sv
new file mode 100644
index 0000000..36227ba
--- /dev/null
+++ b/sys/video_cleaner.sv
@@ -0,0 +1,91 @@
+//
+//
+// Copyright (c) 2018 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+module video_cleaner
+(
+	input            clk_vid,
+	input            ce_pix,
+
+	input      [7:0] R,
+	input      [7:0] G,
+	input      [7:0] B,
+
+	input            HSync,
+	input            VSync,
+	input            HBlank,
+	input            VBlank,
+
+	// video output signals
+	output reg [7:0] VGA_R,
+	output reg [7:0] VGA_G,
+	output reg [7:0] VGA_B,
+	output reg       VGA_VS,
+	output reg       VGA_HS,
+	output           VGA_DE,
+	
+	// optional aligned blank
+	output reg       HBlank_out,
+	output reg       VBlank_out
+);
+
+wire hs, vs;
+s_fix sync_v(clk_vid, HSync, hs);
+s_fix sync_h(clk_vid, VSync, vs);
+
+wire hbl = hs | HBlank;
+wire vbl = vs | VBlank;
+
+assign VGA_DE = ~(HBlank_out | VBlank_out);
+
+always @(posedge clk_vid) begin
+	if(ce_pix) begin
+		HBlank_out <= hbl;
+
+		VGA_VS <= vs;
+		VGA_HS <= hs;
+		VGA_R  <= R;
+		VGA_G  <= G;
+		VGA_B  <= B;
+
+		if(HBlank_out & ~hbl) VBlank_out <= vbl;
+	end
+end
+
+endmodule
+
+module s_fix
+(
+	input clk,
+	
+	input sync_in,
+	output sync_out
+);
+
+assign sync_out = sync_in ^ pol;
+
+reg pol;
+always @(posedge clk) begin
+	integer pos = 0, neg = 0, cnt = 0;
+	reg s1,s2;
+
+	s1 <= sync_in;
+	s2 <= s1;
+
+	if(~s2 & s1) neg <= cnt;
+	if(s2 & ~s1) pos <= cnt;
+
+	cnt <= cnt + 1;
+	if(s2 != s1) cnt <= 0;
+
+	pol <= pos > neg;
+end
+
+endmodule
diff --git a/sys/video_mixer.sv b/sys/video_mixer.sv
new file mode 100644
index 0000000..c9d358d
--- /dev/null
+++ b/sys/video_mixer.sv
@@ -0,0 +1,167 @@
+//
+//
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+//
+// LINE_LENGTH: Length of  display line in pixels
+//              Usually it's length from HSync to HSync.
+//              May be less if line_start is used.
+//
+// HALF_DEPTH:  If =1 then color dept is 4 bits per component
+//              For half depth 8 bits monochrome is available with
+//              mono signal enabled and color = {G, R}
+
+module video_mixer
+#(
+	parameter LINE_LENGTH  = 768,
+	parameter HALF_DEPTH   = 0
+)
+(
+	// master clock
+	// it should be multiple by (ce_pix*4).
+	input            clk_sys,
+	
+	// Pixel clock or clock_enable (both are accepted).
+	input            ce_pix,
+	output           ce_pix_out,
+
+	input            scandoubler,
+
+	// scanlines (00-none 01-25% 10-50% 11-75%)
+	input      [1:0] scanlines,
+
+	// High quality 2x scaling
+	input            hq2x,
+
+	// color
+	input [DWIDTH:0] R,
+	input [DWIDTH:0] G,
+	input [DWIDTH:0] B,
+
+	// Monochrome mode (for HALF_DEPTH only)
+	input            mono,
+
+	// Positive pulses.
+	input            HSync,
+	input            VSync,
+	input            HBlank,
+	input            VBlank,
+
+	// video output signals
+	output reg [7:0] VGA_R,
+	output reg [7:0] VGA_G,
+	output reg [7:0] VGA_B,
+	output reg       VGA_VS,
+	output reg       VGA_HS,
+	output reg       VGA_DE
+);
+
+localparam DWIDTH = HALF_DEPTH ? 3 : 7;
+
+wire [DWIDTH:0] R_sd;
+wire [DWIDTH:0] G_sd;
+wire [DWIDTH:0] B_sd;
+wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
+
+scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd
+(
+	.*,
+	.hs_in(HSync),
+	.vs_in(VSync),
+	.hb_in(HBlank),
+	.vb_in(VBlank),
+	.r_in(R),
+	.g_in(G),
+	.b_in(B),
+
+	.ce_pix_out(ce_pix_sd),
+	.hs_out(hs_sd),
+	.vs_out(vs_sd),
+	.hb_out(hb_sd),
+	.vb_out(vb_sd),
+	.r_out(R_sd),
+	.g_out(G_sd),
+	.b_out(B_sd)
+);
+
+wire [DWIDTH:0] rt  = (scandoubler ? R_sd : R);
+wire [DWIDTH:0] gt  = (scandoubler ? G_sd : G);
+wire [DWIDTH:0] bt  = (scandoubler ? B_sd : B);
+
+generate
+	if(HALF_DEPTH) begin
+		wire [7:0] r  = mono ? {gt,rt} : {rt,rt};
+		wire [7:0] g  = mono ? {gt,rt} : {gt,gt};
+		wire [7:0] b  = mono ? {gt,rt} : {bt,bt};
+	end else begin
+		wire [7:0] r  = rt;
+		wire [7:0] g  = gt;
+		wire [7:0] b  = bt;
+	end
+endgenerate
+
+wire hs = (scandoubler ? hs_sd : HSync);
+wire vs = (scandoubler ? vs_sd : VSync);
+
+assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
+
+
+reg scanline = 0;
+always @(posedge clk_sys) begin
+	reg old_hs, old_vs;
+	
+	old_hs <= hs;
+	old_vs <= vs;
+	
+	if(old_hs && ~hs) scanline <= ~scanline;
+	if(old_vs && ~vs) scanline <= 0;
+end
+
+wire hde = scandoubler ? ~hb_sd : ~HBlank;
+wire vde = scandoubler ? ~vb_sd : ~VBlank;
+
+always @(posedge clk_sys) begin
+	reg old_hde;
+
+	case(scanlines & {scanline, scanline})
+		1: begin // reduce 25% = 1/2 + 1/4
+			VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
+			VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
+			VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
+		end
+
+		2: begin // reduce 50% = 1/2
+			VGA_R <= {1'b0, r[7:1]};
+			VGA_G <= {1'b0, g[7:1]};
+			VGA_B <= {1'b0, b[7:1]};
+		end
+
+		3: begin // reduce 75% = 1/4
+			VGA_R <= {2'b00, r[7:2]};
+			VGA_G <= {2'b00, g[7:2]};
+			VGA_B <= {2'b00, b[7:2]};
+		end
+
+		default: begin
+			VGA_R <= r;
+			VGA_G <= g;
+			VGA_B <= b;
+		end
+	endcase
+
+	VGA_VS <= vs;
+	VGA_HS <= hs;
+
+	old_hde <= hde;
+	if(~old_hde && hde) VGA_DE <= vde;
+	if(old_hde && ~hde) VGA_DE <= 0;
+end
+
+endmodule