ioc_irq.v

`timescale 1ns / 1ps
/* ioc_irq.v

 Copyright (c) 2012-2014, Stephen J. Leary
 All rights reserved.
 
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 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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 * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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 */
 
 module ioc_irq #(
 parameter ADDRESS=2'b01, 
 parameter CANCLEAR=8'b1111_1111, 
 parameter PERMBITS=8'h00) 
 (
	
		input 	 			clkcpu, // cpu bus clock domain
		input 	 			reset,

		input [7:0]			i,
		input [7:0]			c,
		output				irq,
			
		// cpu interface
		input				write,
		
		input [6:2]			addr,			
		input [7:0]			din,
		output [7:0]		dout,
		output				sel
);

reg [7:0]	mask = 8'h00;
reg	[7:0]	status = 8'h00;

wire		selected = ~addr[6] & (addr[5:4] == ADDRESS);

always @(posedge clkcpu) begin

	if (reset) begin
		mask   <= 8'h00;
		status <= 8'h00;
	end else begin

		status <= status & CANCLEAR | status & ~CANCLEAR & ~c | i | PERMBITS;

		if (selected & write) begin
			if (addr[3:2] == 2'b10)  mask <= din;
			if (addr[3:2] == 2'b01) begin
				status <= (status & ~CANCLEAR) | (status & ~din & CANCLEAR) | PERMBITS;
			end
		end
	end

end

assign sel = selected;

assign irq =  | (mask & status);

assign dout = 	addr[3:2] == 2'b00 ? status :
				addr[3:2] == 2'b01 ? mask & status :
				addr[3:2] == 2'b10 ? mask : 8'd0;
				
endmodule