From 472bcfbb982dc2b758189c50698a07a3a25145b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Aitor=20G=C3=B3mez?= Date: Sun, 21 Aug 2022 19:55:15 +0200 Subject: [PATCH] COM2 port (2F8h) on USER_IO --- PCXT.sv | 71 ++++++++++++++++++++-------------- rtl/KFPC-XT/HDL/Chipset.sv | 44 ++++++++++++++------- rtl/KFPC-XT/HDL/Peripherals.sv | 61 +++++++++++++++++++++++++---- 3 files changed, 125 insertions(+), 51 deletions(-) diff --git a/PCXT.sv b/PCXT.sv index 97d6ac1..7355410 100644 --- a/PCXT.sv +++ b/PCXT.sv @@ -174,7 +174,7 @@ module emu ///////// Default values for ports not used in this core ///////// assign ADC_BUS = 'Z; -assign USER_OUT = '1; +//assign USER_OUT = '1; //assign {UART_RTS, UART_TXD, UART_DTR} = 0; //assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; //assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; @@ -242,12 +242,10 @@ localparam CONF_STR = { "P3-;", "P3OB,Lo-tech 2MB EMS, Enabled, Disabled;", "P3OCD,EMS Frame,A000,C000,D000;", - "P3-;", "-;", -// "F1,ROM,Load BIOS (F000);", -// "F2,ROM,Load XTIDE (EC00);", -// "-;", -// "T0,Reset;", + "F1,ROM,Load BIOS (F000);", + "F2,ROM,Load XTIDE (EC00);", + "-;", "R0,Reset and close OSD;", "V,v",`BUILD_DATE }; @@ -670,14 +668,21 @@ end .ioctl_wr (ioctl_wr), .ioctl_addr (ioctl_addr), .ioctl_data (ioctl_data), - .clk_uart (clk_uart), - .uart_rx (uart_rx), - .uart_tx (uart_tx), - .uart_cts_n (uart_cts), - .uart_dcd_n (uart_dcd), - .uart_dsr_n (uart_dsr), - .uart_rts_n (uart_rts), - .uart_dtr_n (uart_dtr), + .clk_uart (clk_uart), + .uart_rx (uart_rx), + .uart_tx (uart_tx), + .uart_cts_n (uart_cts), + .uart_dcd_n (uart_dcd), + .uart_dsr_n (uart_dsr), + .uart_rts_n (uart_rts), + .uart_dtr_n (uart_dtr), + .uart2_rx (uart2_rx), + .uart2_tx (uart2_tx), + .uart2_cts_n (uart2_cts), + .uart2_dcd_n (uart2_dcd), + .uart2_dsr_n (uart2_dsr), + .uart2_rts_n (uart2_rts), + .uart2_dtr_n (uart2_dtr), .enable_sdram (1'b1), .sdram_clock (SDRAM_CLK), .sdram_address (SDRAM_A), @@ -731,21 +736,6 @@ end /// UART - - //assign USER_OUT = {1'b1, 1'b1, uart_dtr, 1'b1, uart_rts, uart_tx, 1'b1}; - - // - // Pin | USB Name | |Signal - // ----+----------+---+------------- - // 0 | D+ | I |RX - // 1 | D- | O |TX - // 2 | TX- | O |RTS - // 3 | GND_d | I |CTS - // 4 | RX+ | O |DTR - // 5 | RX- | I |DSR - // 6 | TX+ | I |DCD - // - wire uart_tx, uart_rts, uart_dtr; assign UART_TXD = uart_tx; @@ -763,6 +753,29 @@ end else cpu_address <= cpu_address; end + /// UART2 + + assign USER_OUT = {1'b1, 1'b1, uart2_dtr, 1'b1, uart2_rts, uart2_tx, 1'b1}; + + // + // Pin | USB Name | |Signal + // ----+----------+---+------------- + // 0 | D+ | I |RX + // 1 | D- | O |TX + // 2 | TX- | O |RTS + // 3 | GND_d | I |CTS + // 4 | RX+ | O |DTR + // 5 | RX- | I |DSR + // 6 | TX+ | I |DCD + // + + wire uart2_tx, uart2_rts, uart2_dtr; + + wire uart2_rx = USER_IN[0]; + wire uart2_cts = USER_IN[3]; + wire uart2_dsr = USER_IN[5]; + wire uart2_dcd = USER_IN[6]; + /// VIDEO diff --git a/rtl/KFPC-XT/HDL/Chipset.sv b/rtl/KFPC-XT/HDL/Chipset.sv index c2e59f5..1f41bde 100644 --- a/rtl/KFPC-XT/HDL/Chipset.sv +++ b/rtl/KFPC-XT/HDL/Chipset.sv @@ -102,6 +102,13 @@ module CHIPSET ( input logic uart_dsr_n, output logic uart_rts_n, output logic uart_dtr_n, + input logic uart2_rx, + output logic uart2_tx, + input logic uart2_cts_n, + input logic uart2_dcd_n, + input logic uart2_dsr_n, + output logic uart2_rts_n, + output logic uart2_dtr_n, // SDRAM input logic enable_sdram, input logic sdram_clock, // 50MHz @@ -286,21 +293,28 @@ module CHIPSET ( .ioctl_wr (ioctl_wr), .ioctl_addr (ioctl_addr), .ioctl_data (ioctl_data), - .uart_rx (uart_rx), - .uart_tx (uart_tx), - .uart_cts_n (uart_cts_n), - .uart_dcd_n (uart_dcd_n), - .uart_dsr_n (uart_dsr_n), - .uart_rts_n (uart_rts_n), - .uart_dtr_n (uart_dtr_n), - .ems_enabled (ems_enabled), - .ems_address (ems_address), - .map_ems (map_ems), - .ena_ems (ena_ems), - .ems_b1 (ems_b1), - .ems_b2 (ems_b2), - .ems_b3 (ems_b3), - .ems_b4 (ems_b4), + .uart_rx (uart_rx), + .uart_tx (uart_tx), + .uart_cts_n (uart_cts_n), + .uart_dcd_n (uart_dcd_n), + .uart_dsr_n (uart_dsr_n), + .uart_rts_n (uart_rts_n), + .uart_dtr_n (uart_dtr_n), + .uart2_rx (uart2_rx), + .uart2_tx (uart2_tx), + .uart2_cts_n (uart2_cts_n), + .uart2_dcd_n (uart2_dcd_n), + .uart2_dsr_n (uart2_dsr_n), + .uart2_rts_n (uart2_rts_n), + .uart2_dtr_n (uart2_dtr_n), + .ems_enabled (ems_enabled), + .ems_address (ems_address), + .map_ems (map_ems), + .ena_ems (ena_ems), + .ems_b1 (ems_b1), + .ems_b2 (ems_b2), + .ems_b3 (ems_b3), + .ems_b4 (ems_b4), .tandy_mode (tandy_mode) ); diff --git a/rtl/KFPC-XT/HDL/Peripherals.sv b/rtl/KFPC-XT/HDL/Peripherals.sv index 25b0c3e..3d83101 100644 --- a/rtl/KFPC-XT/HDL/Peripherals.sv +++ b/rtl/KFPC-XT/HDL/Peripherals.sv @@ -85,6 +85,14 @@ module PERIPHERALS #( input logic uart_dsr_n, output logic uart_rts_n, output logic uart_dtr_n, + // UART 2 + input logic uart2_rx, + output logic uart2_tx, + input logic uart2_cts_n, + input logic uart2_dcd_n, + input logic uart2_dsr_n, + output logic uart2_rts_n, + output logic uart2_dtr_n, // EMS input logic ems_enabled, input logic [1:0] ems_address, @@ -140,6 +148,7 @@ module PERIPHERALS #( wire bios_select_n = ~(~iorq && ~address_enable_n && address[19:16] == 4'b1111); // F0000 - FFFFF (64 KB) wire xtide_select_n = ~(~iorq && ~address_enable_n && address[19:14] == 6'b111011); // EC000 - EFFFF (16 KB) wire uart_cs = (~address_enable_n && {address[15:3], 3'd0} == 16'h03F8); + wire uart2_cs = (~address_enable_n && {address[15:3], 3'd0} == 16'h02F8); wire lpt_cs = (iorq && ~address_enable_n && {address[15:3], 3'd0} == 16'h0378); wire lpt_ctl_cs = (iorq && ~address_enable_n && {address[15:3], 3'd0} == 16'h0379); @@ -190,6 +199,7 @@ module PERIPHERALS #( logic timer_interrupt; logic keybord_interrupt; logic uart_interrupt; + logic uart2_interrupt; logic [7:0] interrupt_data_bus_out; KF8259 u_KF8259 ( @@ -212,7 +222,7 @@ module PERIPHERALS #( //.slave_program_or_enable_buffer (), .interrupt_acknowledge_n (interrupt_acknowledge_n), .interrupt_to_cpu (interrupt_to_cpu), - .interrupt_request ({interrupt_request[7:5], uart_interrupt, interrupt_request[3:2], + .interrupt_request ({interrupt_request[7:5], uart_interrupt, uart2_interrupt, interrupt_request[2], keybord_interrupt, timer_interrupt}) ); @@ -447,9 +457,11 @@ module PERIPHERALS #( logic prev_io_read_n; logic prev_io_write_n; logic [7:0] write_to_uart; - logic [7:0] uart_readdata_1; - logic [7:0] uart_readdata_2; + logic [7:0] write_to_uart2; + logic [7:0] uart_readdata_1; logic [7:0] uart_readdata; + logic [7:0] uart2_readdata_1; + logic [7:0] uart2_readdata; always_ff @(posedge clock) begin prev_io_read_n <= io_read_n; @@ -470,10 +482,13 @@ module PERIPHERALS #( reg [7:0] lpt_data = 8'hFF; always_ff @(posedge clock) begin - if (~io_write_n) + if (~io_write_n) begin write_to_uart <= internal_data_bus; - else + write_to_uart2 <= internal_data_bus; + end else begin write_to_uart <= write_to_uart; + write_to_uart2 <= write_to_uart2; + end if ((lpt_cs) && (~io_write_n)) lpt_data <= internal_data_bus; @@ -504,14 +519,42 @@ module PERIPHERALS #( .ri_n (1), .irq (uart_interrupt) + ); + + uart uart2 + ( + .clk (clock), + .br_clk (clk_uart), + .reset (reset), + + .address (address[2:0]), + .writedata (write_to_uart2), + .read (~io_read_n & prev_io_read_n), + .write (io_write_n & ~prev_io_write_n), + .readdata (uart2_readdata_1), + .cs (uart2_cs & iorq_uart), + + .rx (uart2_rx), + .tx (uart2_tx), + .cts_n (uart2_cts_n), + .dcd_n (uart2_dcd_n), + .dsr_n (uart2_dsr_n), + .rts_n (uart2_rts_n), + .dtr_n (uart2_dtr_n), + .ri_n (1), + + .irq (uart2_interrupt) ); // Timing of the readings may need to be reviewed. always_ff @(posedge clock) begin - if (~io_read_n) + if (~io_read_n) begin uart_readdata <= uart_readdata_1; - else + uart2_readdata <= uart2_readdata_1; + end else begin uart_readdata <= uart_readdata; + uart2_readdata <= uart2_readdata; + end end @@ -921,6 +964,10 @@ module PERIPHERALS #( else if ((uart_cs) && (~io_read_n)) begin data_bus_out_from_chipset <= 1'b1; data_bus_out <= uart_readdata; + end + else if ((uart2_cs) && (~io_read_n)) begin + data_bus_out_from_chipset <= 1'b1; + data_bus_out <= uart2_readdata; end else if ((ems_oe) && (~io_read_n)) begin data_bus_out_from_chipset <= 1'b1;