From b41a2e1ade7b5a5c750e0febba324192887d669c Mon Sep 17 00:00:00 2001 From: sorgelig Date: Sat, 15 Sep 2018 21:05:33 +0800 Subject: [PATCH] Some tweaks in HUC6202. --- huc6202.vhd | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/huc6202.vhd b/huc6202.vhd index eee8fbd..368e6e1 100644 --- a/huc6202.vhd +++ b/huc6202.vhd @@ -54,8 +54,9 @@ signal X : std_logic_vector(9 downto 0); signal PRIN : std_logic_vector(1 downto 0); signal PRI : std_logic_vector(3 downto 0); -signal HS_N_PREV : std_logic; -signal VDC_PRI : std_logic_vector(8 downto 0); +signal HS_N_PREV : std_logic; +signal VDC_PRI : std_logic_vector(8 downto 0); +signal INMIX : std_logic; begin @@ -101,8 +102,9 @@ begin end case; end case; - if PRI(1 downto 0) /= "01" and VDCDATA(7 downto 0) = x"00" then - VDC_OUT <= "100000000"; -- this looks wrong but fixes 1941's white flash + if INMIX = '1' and PRI(1 downto 0) /= "00" and VDCDATA(7 downto 0) = x"00" then + -- replace color 0 -> 256 if in mixing and one of VDC is enabled + VDC_OUT <= "100000000"; else VDC_OUT <= VDCDATA; end if; @@ -119,12 +121,13 @@ process( CLK ) begin PRI1 <= "00010001"; WIN1 <= (others => '0'); WIN2 <= (others => '0'); - VDCNUM <= '0'; + VDCNUM <= '0'; + INMIX <= '0'; else if CE_N = '0' and WR_N = '0' then case A is - when "000" => PRI0 <= DI; - when "001" => PRI1 <= DI; + when "000" => PRI0 <= DI; INMIX <= '1'; + when "001" => PRI1 <= DI; INMIX <= '1'; when "010" => WIN1(7 downto 0) <= DI; when "011" => WIN1(9 downto 8) <= DI(1 downto 0); when "100" => WIN2(7 downto 0) <= DI;