/*
 * Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sx.dtsi"

/ {
	model = "Freescale i.MX6 SoloX SG base Board";
	compatible = "fsl,imx6sx-sg", "fsl,imx6sx";
	
	aliases {
        
    };
	
	chosen {
		stdout-path = &uart1;
		//stdout-path = &mxcfb1;
	};

	memory {
		linux,usable-memory = <0x80000000 0x1FF00000>;
	};
	
	lcd-control {
		compatible = "gpio-leds";
	};

	pxp_v4l2_out {
		compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
		status = "okay";
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

        bt_reset: bt-reset {
			compatible = "gpio-reset";
			reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
			reset-delay-us = <1000>;
			#reset-cells = <0>;
		};

		reg_usb_otg1_vbus: usb_otg1_vbus {
			compatible = "regulator-fixed";
			reg = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
			regulator-name = "usb_otg1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usb_otg2_vbus: usb_otg2_vbus {
			compatible = "regulator-fixed";
			reg = <2>;
			pinctrl-names = "default";
			regulator-name = "usb_otg2_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_psu_5v: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			regulator-name = "PSU-5V0";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
		};

		reg_vref_3v3: regulator@7 {
			compatible = "regulator-fixed";
			reg = <7>;
			regulator-name = "vref-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};

		reg_can_en: regulator@9 {
			compatible = "regulator-fixed";
			reg = <9>;
			regulator-name = "can-en";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};

		reg_can_stby: regulator@10 {
			compatible = "regulator-fixed";
			reg = <10>;
			regulator-name = "can-stby";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};
	};

	sound {
		compatible = "fsl,imx-audio-nau8822";
		model = "nau8822-audio";
		ssi-controller = <&ssi2>;
		audio-codec = <&codec>;
		audio-routing =
			"Mic Bias", "AMIC";
		mux-int-port = <2>;
		mux-ext-port = <3>;
	};
	beeper {
        compatible = "pwm-beeper";
        pwms = <&pwm4 0 1000000>;
        status = "okay";
    };
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	status = "disabled"; 
	partition@0 {
	label = "uboot";
	reg = <0 0x800000>;
	};
	partition@0x800000 {
		label = "env";
		reg = <0x800000 0x400000>;
	};
	partition@0xc00000 {
	label = "system";
	reg = <0xc00000 0x2000000>;
	};
	partition@0x1c00000 {
	label = "rootfs";
	reg = <0x2c00000 0x3d400000>;
	};
};

&adc1 {
	vref-supply = <&reg_vref_3v3>;
	status = "okay";
};

&adc2 {
	vref-supply = <&reg_vref_3v3>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1_1>;
	phy-mode = "rgmii-txid";
	phy-reset-gpios = <&gpio2 4 1>;
	phy-reset-duration =<20>;
	local-mac-address = [00 04 9F 01 1B 58];
	status = "okay";

	fixed-link{
		speed = <1000>;
		full-duplex;
	};

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2_1>;
	phy-mode = "rgmii-txid";
	phy-reset-gpios = <&gpio2 2 1>;
	phy-reset-duration =<20>;
	local-mac-address = [00 04 9F 01 1B 68];
	status = "okay";

	fixed-link{
		speed = <1000>;
		full-duplex;
	};

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
	};
};

&lcdif2 {
	//pinctrl-names = "default";
	//pinctrl-0 = <&pinctrl_lcd>;
	display = <&display1>;
	disp-dev = "ldb";
	status = "okay";
	display1: display {
		bits-per-pixel = <32>;
		bus-width = <24>;
	};
};
&ldb {
    status = "okay";
	lvds-channel@0 {
		fsl,data-mapping = "spwg";//"jeida";
		fsl,data-width = <24>;
		crtc = "lcdif2";
		status = "okay";
		display-timings {
			native-mode = <&timing1>;
			timing1: timing1 {
				clock-frequency = <51200000>;
				hactive = <1024>;
				vactive = <600>;
				hback-porch = <100>;
				hfront-porch = <100>;
				hsync-len = <120>;
				vback-porch = <10>;
				vfront-porch = <10>;
				vsync-len = <15>;
				//de-active = <1>;
			};
		};
	};
};

&csi2 {
	status = "okay";
	port {
		csi2_ep: endpoint {
			remote-endpoint = <&vadc_ep>;
		};
	};
};

&dcic1 {
	dcic_id = <0>;
	dcic_mux = "dcic-lcdif1";
	status = "okay";
};

&dcic2 {
	dcic_id = <1>;
	dcic_mux = "dcic-lvds";
	status = "okay";
};

&csi1 {
    status = "okay";

    port {
        csi1_ep: endpoint {
            remote-endpoint = <&ov5640_ep>;
        };
    };
};

&ocram {
	reg = <0x00901000 0xf000>;
};

&qspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi2>;
	status = "okay";
	ddrsmp=<0>;	//or 2

	flash0: w25q128@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "winbond,w25q128";
		spi-max-frequency = <15625000>;
		reg = <0>;
	};
};

&qspi_m4 {
	status = "okay";
};

&rpmsg
{
	vdev-nums = <1>;
	reg = <0xbfff0000 0x10000>;
	status = "okay";
};

&clks {
	fsl,shared-clks-number = <0x23>;//<0x1A>;
	fsl,shared-clks-index = <IMX6SX_CLK_PLL2_BUS IMX6SX_CLK_PLL2_PFD0
			IMX6SX_CLK_PLL2_PFD2 IMX6SX_CLK_PLL3_USB_OTG
			IMX6SX_CLK_PLL3_PFD1 IMX6SX_CLK_PLL3_PFD2
			IMX6SX_CLK_PLL3_PFD3 IMX6SX_CLK_PLL4_AUDIO
			IMX6SX_CLK_PLL5_VIDEO
			IMX6SX_CLK_OCRAM IMX6SX_CLK_CAN1_SERIAL
			IMX6SX_CLK_CAN1_IPG IMX6SX_CLK_CAN2_SERIAL
			IMX6SX_CLK_CAN2_IPG IMX6SX_CLK_CANFD
			IMX6SX_CLK_ECSPI1 IMX6SX_CLK_ECSPI2
			IMX6SX_CLK_ECSPI3 IMX6SX_CLK_ECSPI4
			IMX6SX_CLK_ECSPI5 IMX6SX_CLK_QSPI1
			IMX6SX_CLK_QSPI2 IMX6SX_CLK_SSI1
			IMX6SX_CLK_SSI2 IMX6SX_CLK_SSI3
			IMX6SX_CLK_UART_SERIAL IMX6SX_CLK_UART_IPG
			IMX6SX_CLK_PERIPH_CLK2_SEL IMX6SX_CLK_DUMMY
			IMX6SX_CLK_I2C1 IMX6SX_CLK_I2C2
			IMX6SX_CLK_I2C3 IMX6SX_CLK_I2C4
			IMX6SX_CLK_EPIT1 IMX6SX_CLK_EPIT2>;
	fsl,shared-mem-addr = <0x91F000>;
	fsl,shared-mem-size = <0x1000>;
};

//PORT P1: Common module
&ecspi1 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	//pinctrl-0 = <&pinctrl_ecspi1>;
	status = "disabled";
	spidev@0 {
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <20000000>;
		reg = <0>;
		dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
		dma-names = "rx", "tx";
	};
};

//Port P2: Common module
&ecspi3 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	status = "okay";

	ksz9897: ksz9897@0 {
		compatible = "microchip,ksz9897";
		reg = <0>;
		phy-mode = "rgmii-txid";

		spi-max-frequency = <10000000>;
		spi-cpha;
		spi-cpol;
		interrupt-parent = <&gpio2>;
		interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				label = "lan1";
			};
			port@1 {
				reg = <1>;
				label = "lan2";
			};
			port@2 {
				reg = <2>;
				label = "lan3";
			};
			port@3 {
				reg = <3>;
				label = "lan4";
			};
			port@4 {
				reg = <4>;
				label = "lan5";
			};
			port@5 {
				reg = <5>;
				label = "lan6";
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
			port@6 {
				reg = <6>;
				label = "cpu";
				ethernet = <&fec2>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
		};
	};
};

//Port P3: LTE EXPANSION
&ecspi5 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi5>;
	status = "okay";

	ksz9477: ksz9477@0 {
		compatible = "microchip,ksz9477";
		reg = <0>;
		phy-mode = "rgmii-txid";

		spi-max-frequency = <10000000>;
		spi-cpha;
		spi-cpol;
		interrupt-parent = <&gpio2>;
		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				label = "lan1";
			};
			port@1 {
				reg = <1>;
				label = "lan2";
			};
			port@2 {
				reg = <2>;
				label = "lan3";
			};
			port@3 {
				reg = <3>;
				label = "lan4";
			};
			port@4 {
				reg = <4>;
				label = "lan5";
			};
			port@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&fec1>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
			port@6 {
				reg = <6>;
				label = "lan6";
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
		};
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <
        &pinctrl_hog_1
        &pinctrl_button
        &pinctrl_digital_gpio
    >;
	imx6x-sg {
		pinctrl_hog_1: hoggrp-1 {
			fsl,pins = <
				MX6SX_PAD_USB_H_DATA__GPIO7_IO_10	0x83030
			>;
		};
		
        pinctrl_button: hoggrp-2 {
            fsl,pins = <
                /* button pull up */
                /*MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11        0xF000*/
                MX6SX_PAD_NAND_RE_B__GPIO4_IO_12         0xF000
            >;
        };

        pinctrl_digital_gpio: hoggrp-3 {
            fsl,pins = <
				MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1        0x110b0
				MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2        0x110b0
                MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3        0x110b0
                MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24       0x110b0
           >;
        };

		pinctrl_enet1_1: enet1grp-1 {
			fsl,pins = <
				MX6SX_PAD_ENET2_COL__ENET1_MDC        	0xa0b1 
				MX6SX_PAD_ENET2_CRS__ENET1_MDIO        	0xa0b1 
				MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b9
				MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
				MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
				MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2	0xa0b1
				MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3	0xa0b1
				MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN	0xa0b1
				MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 	0x3081
				MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
				MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN   	0x3081
				MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 	0xb099
				//MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4000b099 
				MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5	0xb099
				MX6SX_PAD_SD3_CLK__GPIO7_IO_0		0x1b0b1
				// TODO : Uncomment below to reset DP83869 PHY
				//MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 	0x110b0    // SFP_PORT_RST_N
			>;
		};

		
		pinctrl_enet2_1: enet2grp-1{
			fsl,pins = <
				MX6SX_PAD_ENET1_COL__ENET2_MDC          0xa0b1 
				MX6SX_PAD_ENET1_CRS__ENET2_MDIO         0xa0b1
				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1 
				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0xa0b1
				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0xa0b1
				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK  0x3081
				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081
				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081
				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
				MX6SX_PAD_ENET1_MDC__GPIO2_IO_2       0xb099   
				//MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4000b099
				MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9	0xb099
				// TODO : Uncomment below to reset ADIN1200 and ADIN1100 PHY
				//MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 	0x110b0     // 10BASE-T1L_PORT_RST_N
                >;
		};

        pinctrl_ecspi3: ecspi3grp {
            fsl,pins = <
                MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x1b091
                MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x1b091
                MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK  0x1b099
                MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x0b0b9
            >;
        };
                        
		//Port P3: LTE EXPANSION
		pinctrl_ecspi5: ecspi5grp {
			fsl,pins = <
				MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI   0x1b091
				MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x1b091
				MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x1b099
				MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28   0x0b0b9
			>;
		};
	};
};