From 1f07a21112003a378c2567916b3b0c22afe6ebcb Mon Sep 17 00:00:00 2001
From: Pedro Miguel Justo <40605312+pmsjt@users.noreply.github.com>
Date: Fri, 14 Feb 2020 17:05:58 -0800
Subject: [PATCH] Update nf-processthreadsapi-isprocessorfeaturepresent.md
---
...essthreadsapi-isprocessorfeaturepresent.md | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/sdk-api-src/content/processthreadsapi/nf-processthreadsapi-isprocessorfeaturepresent.md b/sdk-api-src/content/processthreadsapi/nf-processthreadsapi-isprocessorfeaturepresent.md
index 318edf4287a2..2c08c5589bbe 100644
--- a/sdk-api-src/content/processthreadsapi/nf-processthreadsapi-isprocessorfeaturepresent.md
+++ b/sdk-api-src/content/processthreadsapi/nf-processthreadsapi-isprocessorfeaturepresent.md
@@ -357,6 +357,51 @@ The processor implements the XSAVE and XRSTOR instructions.
+
+
+
+- PF_ARM_V8_INSTRUCTIONS_AVAILABLE
+- 29
+
+ |
+
+This ARM processor implements the the ARM v8 instructions set.
+ |
+
+
+
+
+- PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE
+- 30
+
+ |
+
+This ARM processor implements the ARM v8 extra cryptographic instructions (i.e. AES, SHA1 and SHA2).
+ |
+
+
+
+
+- PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE
+- 31
+
+ |
+
+This ARM processor implements the ARM v8 extra CRC32 instructions.
+ |
+
+
+
+
+- PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE
+- 34
+
+ |
+
+This ARM processor implements the ARM v8.1 atomic instructions (e.g. CAS, SWP).
+ |
+
+