diff --git a/1564503707611.jpg b/1564503707611.jpg new file mode 100644 index 00000000..f40e95a2 Binary files /dev/null and b/1564503707611.jpg differ diff --git a/CH5/CH5-3/BCD_adder_1D.bdf b/CH5/CH5-3/BCD_adder_1D.bdf new file mode 100644 index 00000000..2de80c0c --- /dev/null +++ b/CH5/CH5-3/BCD_adder_1D.bdf @@ -0,0 +1,806 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 112 208) + (text "BCD_adder_1D" (rect 5 0 98 12)(font "Arial" (font_size 8))) + (text "inst" (rect 8 178 25 188)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "A3" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "A3" (rect 21 27 38 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "B3" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "B3" (rect 21 43 38 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "A2" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "A2" (rect 21 59 38 71)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 0 80) + (input) + (text "B2" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "B2" (rect 21 75 38 87)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 16 80)) + ) + (port + (pt 0 96) + (input) + (text "A1" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "A1" (rect 21 91 38 103)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)) + ) + (port + (pt 0 112) + (input) + (text "B1" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "B1" (rect 21 107 38 119)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 16 112)) + ) + (port + (pt 0 128) + (input) + (text "A0" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "A0" (rect 21 123 38 135)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)) + ) + (port + (pt 0 144) + (input) + (text "B0" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "B0" (rect 21 139 38 151)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 16 144)) + ) + (port + (pt 0 160) + (input) + (text "C0" (rect 0 0 18 12)(font "Arial" (font_size 8))) + (text "C0" (rect 21 155 39 167)(font "Arial" (font_size 8))) + (line (pt 0 160)(pt 16 160)) + ) + (port + (pt 96 32) + (output) + (text "S3" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "S3" (rect 58 27 75 39)(font "Arial" (font_size 8))) + (line (pt 96 32)(pt 80 32)) + ) + (port + (pt 96 48) + (output) + (text "S2" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "S2" (rect 58 43 75 55)(font "Arial" (font_size 8))) + (line (pt 96 48)(pt 80 48)) + ) + (port + (pt 96 64) + (output) + (text "S1" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "S1" (rect 58 59 75 71)(font "Arial" (font_size 8))) + (line (pt 96 64)(pt 80 64)) + ) + (port + (pt 96 80) + (output) + (text "S0" (rect 0 0 17 12)(font "Arial" (font_size 8))) + (text "S0" (rect 58 75 75 87)(font "Arial" (font_size 8))) + (line (pt 96 80)(pt 80 80)) + ) + (port + (pt 96 96) + (output) + (text "C4" (rect 0 0 18 12)(font "Arial" (font_size 8))) + (text "C4" (rect 57 91 75 103)(font "Arial" (font_size 8))) + (line (pt 96 96)(pt 80 96)) + ) + (drawing + (rectangle (rect 16 16 80 176)) + ) +) diff --git a/CH5/CH5-3/BCD_adder_1D.qpf b/CH5/CH5-3/BCD_adder_1D.qpf new file mode 100644 index 00000000..a925e05c --- /dev/null +++ b/CH5/CH5-3/BCD_adder_1D.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 19:10:01 September 05, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "19:10:01 September 05, 2019" + +# Revisions + +PROJECT_REVISION = "BCD_adder_1D" diff --git a/CH5/CH5-3/BCD_adder_1D.qsf b/CH5/CH5-3/BCD_adder_1D.qsf new file mode 100644 index 00000000..78d6738e --- /dev/null +++ b/CH5/CH5-3/BCD_adder_1D.qsf @@ -0,0 +1,75 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 19:10:01 September 05, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# BCD_adder_1D_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C16F484C6 +set_global_assignment -name TOP_LEVEL_ENTITY BCD_adder_1D +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:10:01 SEPTEMBER 05, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name BDF_FILE BCD_adder_7483.bdf +set_global_assignment -name BDF_FILE "../CH5-1/Full_adder_S.bdf" +set_global_assignment -name BDF_FILE "../CH5-1/four_bir_adder.bdf" +set_global_assignment -name BDF_FILE "../CH5-1/eight_bit_adder.bdf" +set_global_assignment -name BDF_FILE "../CH5-1/Half_adder.bdf" +set_global_assignment -name BDF_FILE BCD_adder_1D.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_location_assignment PIN_H7 -to A0 +set_location_assignment PIN_E3 -to A1 +set_location_assignment PIN_E4 -to A2 +set_location_assignment PIN_D2 -to A3 +set_location_assignment PIN_H6 -to B0 +set_location_assignment PIN_G4 -to B1 +set_location_assignment PIN_G5 -to B2 +set_location_assignment PIN_J7 -to B3 +set_location_assignment PIN_B1 -to C4 +set_location_assignment PIN_E1 -to S0 +set_location_assignment PIN_C1 -to S1 +set_location_assignment PIN_C2 -to S2 +set_location_assignment PIN_B2 -to S3 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/CH5/CH5-3/BCD_adder_1D.qws b/CH5/CH5-3/BCD_adder_1D.qws new file mode 100644 index 00000000..7ebc4f10 Binary files /dev/null and b/CH5/CH5-3/BCD_adder_1D.qws differ diff --git a/CH5/CH5-3/BCD_adder_1D_G.bdf b/CH5/CH5-3/BCD_adder_1D_G.bdf new file mode 100644 index 00000000..bf16cd85 --- /dev/null +++ b/CH5/CH5-3/BCD_adder_1D_G.bdf @@ -0,0 +1,778 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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files /dev/null and b/CH5/CH5-3/BCD_adder_1D_G.ipinfo differ diff --git a/CH5/CH5-3/BCD_adder_1D_G.qpf b/CH5/CH5-3/BCD_adder_1D_G.qpf new file mode 100644 index 00000000..3fad7fca --- /dev/null +++ b/CH5/CH5-3/BCD_adder_1D_G.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 20:23:21 September 09, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "20:23:21 September 09, 2019" + +# Revisions + +PROJECT_REVISION = "BCD_adder_1D_G" diff --git a/CH5/CH5-3/BCD_adder_1D_G.qsf b/CH5/CH5-3/BCD_adder_1D_G.qsf new file mode 100644 index 00000000..ada6848e --- /dev/null +++ b/CH5/CH5-3/BCD_adder_1D_G.qsf @@ -0,0 +1,68 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 20:23:21 September 09, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# BCD_adder_1D_G_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C16F484C6 +set_global_assignment -name TOP_LEVEL_ENTITY BCD_adder_1D_G +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:23:21 SEPTEMBER 09, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name BDF_FILE "../CH5-1/eight_bit_adder.bdf" +set_global_assignment -name BDF_FILE "../CH5-1/Full_adder_S.bdf" +set_global_assignment -name BDF_FILE "../CH5-1/Half_adder.bdf" +set_global_assignment -name BDF_FILE "../CH5-1/four_bir_adder.bdf" +set_global_assignment -name BDF_FILE BCD_adder_7483.bdf +set_global_assignment -name BDF_FILE BCD_adder_1D.bdf +set_global_assignment -name BDF_FILE BCD_adder_1D_G.bdf +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name VECTOR_WAVEFORM_FILE BCD_adder_1D_G.vwf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/qsim/" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation \ No newline at end of file diff --git a/CH5/CH5-3/BCD_adder_1D_G.qws b/CH5/CH5-3/BCD_adder_1D_G.qws new file mode 100644 index 00000000..646a1821 Binary files /dev/null and b/CH5/CH5-3/BCD_adder_1D_G.qws differ diff --git a/CH5/CH5-3/BCD_adder_1D_G.vwf b/CH5/CH5-3/BCD_adder_1D_G.vwf new file mode 100644 index 00000000..ec02478d --- /dev/null +++ b/CH5/CH5-3/BCD_adder_1D_G.vwf @@ -0,0 +1,809 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("A0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A5") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A6") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A7") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B5") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B6") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B7") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("C8") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S5") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S6") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S7") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +GROUP("A") +{ + MEMBERS = "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7"; +} + +GROUP("B") +{ + MEMBERS = "B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7"; +} + +GROUP("S") +{ + MEMBERS = "S0", "S1", "S2", "S3", "S4", "S5", "S6", "S7"; +} + +TRANSITION_LIST("A0") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("A1") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("A2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("A3") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("A4") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("A5") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("A6") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("A7") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("B0") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("B1") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("B2") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("B3") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("B4") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("B5") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("B6") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("B7") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("C8") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("S0") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("S1") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("S2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("S3") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("S4") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("S5") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("S6") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("S7") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "A"; + EXPAND_STATUS = EXPANDED; + RADIX = Unsigned; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8; +} + +DISPLAY_LINE +{ + CHANNEL = "A0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A5"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A6"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A7"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "B"; + EXPAND_STATUS = EXPANDED; + RADIX = Unsigned; + TREE_INDEX = 9; + TREE_LEVEL = 0; + CHILDREN = 10, 11, 12, 13, 14, 15, 16, 17; +} + +DISPLAY_LINE +{ + CHANNEL = "B0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B5"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B6"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B7"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "C8"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "S"; + EXPAND_STATUS = EXPANDED; + RADIX = Unsigned; + TREE_INDEX = 19; + TREE_LEVEL = 0; + CHILDREN = 20, 21, 22, 23, 24, 25, 26, 27; +} + +DISPLAY_LINE +{ + CHANNEL = "S0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 22; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 23; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 24; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S5"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 25; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S6"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 26; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S7"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 27; + TREE_LEVEL = 1; + PARENT = 19; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/CH5/CH5-3/BCD_adder_7483.bdf b/CH5/CH5-3/BCD_adder_7483.bdf new file mode 100644 index 00000000..b6788395 --- /dev/null +++ b/CH5/CH5-3/BCD_adder_7483.bdf @@ -0,0 +1,799 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 64 256 232 272) + (text "INPUT" (rect 125 0 154 9)(font "Arial" (font_size 6))) + (text "A0" (rect 5 0 20 10)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 16)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 64 272 232 288) + (text "INPUT" (rect 125 0 154 9)(font "Arial" (font_size 6))) + (text "B0" (rect 5 0 20 10)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 16)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 64 288 232 304) + (text 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(text "C4" (rect 84 131 102 143)(font "Arial" (font_size 8))) + (line (pt 104 136)(pt 120 136)) + ) + (port + (pt 120 56) + (output) + (text "S1" (rect 87 51 104 63)(font "Arial" (font_size 8))) + (text "S1" (rect 85 51 102 63)(font "Arial" (font_size 8))) + (line (pt 104 56)(pt 120 56)) + ) + (drawing + (text "FULL ADDER" (rect 29 179 111 191)(font "Arial" (font_size 8))) + (line (pt 16 16)(pt 104 16)) + (line (pt 16 176)(pt 16 16)) + (line (pt 16 176)(pt 104 176)) + (line (pt 104 176)(pt 104 16)) + ) +) +(symbol + (rect 232 408 264 440) + (text "GND" (rect 8 16 30 25)(font "Arial" (font_size 6))) + (text "inst2" (rect 3 21 26 31)(font "Arial" )(invisible)) + (port + (pt 16 0) + (output) + (text "1" (rect 18 0 27 11)(font "Courier New" (bold))(invisible)) + (text "1" (rect 18 0 27 11)(font "Courier New" (bold))(invisible)) + (line (pt 16 8)(pt 16 0)) + ) + (drawing + (line (pt 8 8)(pt 16 16)) + (line (pt 16 16)(pt 24 8)) + (line (pt 8 8)(pt 24 8)) + ) +) +(symbol + (rect 624 408 656 440) + (text "GND" (rect 8 16 30 25)(font "Arial" (font_size 6))) + (text "inst3" (rect 3 21 26 31)(font "Arial" )(invisible)) + (port + (pt 16 0) + (output) + (text "1" (rect 18 0 27 11)(font "Courier New" (bold))(invisible)) + (text "1" (rect 18 0 27 11)(font "Courier New" (bold))(invisible)) + (line (pt 16 8)(pt 16 0)) + ) + (drawing + (line (pt 8 8)(pt 16 16)) + (line (pt 16 16)(pt 24 8)) + (line (pt 8 8)(pt 24 8)) + ) +) +(symbol + (rect 448 392 512 440) + (text "AND2" (rect 1 0 29 9)(font "Arial" (font_size 6))) + (text "inst4" (rect 3 37 26 47)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN1" (rect 2 7 24 18)(font "Courier New" (bold))(invisible)) + (text "IN1" (rect 2 7 24 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 14 16)) + ) + (port + (pt 0 32) + (input) + (text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible)) + (text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible)) + (line (pt 0 32)(pt 14 32)) + ) + (port + (pt 64 24) + (output) + (text "OUT" (rect 48 15 70 26)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 15 70 26)(font "Courier New" (bold))(invisible)) + (line (pt 42 24)(pt 64 24)) + ) + (drawing + (line (pt 14 12)(pt 30 12)) + (line (pt 14 37)(pt 31 37)) + (line (pt 14 12)(pt 14 37)) + (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) + ) +) +(symbol + (rect 448 440 512 488) + (text "AND2" (rect 1 0 29 9)(font "Arial" (font_size 6))) + (text "inst5" (rect 3 37 26 47)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN1" (rect 2 7 24 18)(font "Courier New" (bold))(invisible)) + (text "IN1" (rect 2 7 24 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 14 16)) + ) + (port + (pt 0 32) + (input) + (text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible)) + (text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible)) + (line (pt 0 32)(pt 14 32)) + ) + (port + (pt 64 24) + (output) + (text "OUT" (rect 48 15 70 26)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 15 70 26)(font "Courier New" (bold))(invisible)) + (line (pt 42 24)(pt 64 24)) + ) + (drawing + (line (pt 14 12)(pt 30 12)) + (line (pt 14 37)(pt 31 37)) + (line (pt 14 12)(pt 14 37)) + (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) + ) +) +(symbol + (rect 544 440 608 488) + (text "OR3" (rect 1 0 23 9)(font "Arial" (font_size 6))) + (text "inst6" (rect 3 37 26 47)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "IN2" (rect 2 15 23 26)(font "Courier New" (bold))(invisible)) + (text "IN2" (rect 2 15 23 26)(font "Courier New" (bold))(invisible)) + (line (pt 0 24)(pt 18 24)) + ) + (port + (pt 0 32) + (input) + (text "IN3" (rect 2 24 23 35)(font "Courier New" (bold))(invisible)) + (text "IN3" (rect 2 24 23 35)(font "Courier New" (bold))(invisible)) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 16) + (input) + (text "IN1" (rect 2 7 24 18)(font "Courier New" (bold))(invisible)) + (text "IN1" (rect 2 7 24 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 16 16)) + ) + (port + (pt 64 24) + (output) + (text "OUT" (rect 47 15 69 26)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 47 15 69 26)(font "Courier New" (bold))(invisible)) + (line (pt 49 24)(pt 64 24)) + ) + (drawing + (line (pt 14 13)(pt 25 13)) + (line (pt 14 36)(pt 25 36)) + (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)) + (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)) + (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)) + ) +) +(connector + (pt 232 264) + (pt 264 264) +) +(connector + (pt 232 280) + (pt 264 280) +) +(connector + (pt 232 296) + (pt 264 296) +) +(connector + (pt 232 312) + (pt 264 312) +) +(connector + (pt 232 328) + (pt 264 328) +) +(connector + (pt 232 344) + (pt 264 344) +) +(connector + (pt 232 360) + (pt 264 360) +) +(connector + (pt 232 376) + (pt 264 376) +) +(connector + (pt 264 232) + (pt 248 232) +) +(connector + (pt 248 232) + (pt 248 408) +) +(connector + (pt 528 280) + (pt 528 296) +) +(connector + (pt 528 296) + (pt 656 296) +) +(connector + (pt 640 232) + (pt 656 232) +) +(connector + (pt 640 280) + (pt 656 280) +) +(connector + (pt 640 376) + (pt 656 376) +) +(connector + (pt 640 376) + (pt 640 408) +) +(connector + (pt 640 232) + (pt 640 280) +) +(connector + (pt 640 280) + (pt 640 376) +) +(connector + (pt 512 464) + (pt 544 464) +) +(connector + (pt 512 416) + (pt 528 416) +) +(connector + (pt 528 416) + (pt 528 456) +) +(connector + (pt 528 456) + (pt 544 456) +) +(connector + (pt 528 496) + (pt 528 472) +) +(connector + (pt 544 472) + (pt 528 472) +) +(connector + (pt 384 344) + (pt 408 344) +) +(connector + (pt 408 344) + (pt 408 496) +) +(connector + (pt 528 496) + (pt 408 496) +) +(connector + (pt 656 312) + (pt 616 312) +) +(connector + (pt 608 464) + (pt 616 464) +) +(connector + (pt 616 464) + (pt 776 464) +) +(connector + (pt 656 344) + (pt 616 344) +) +(connector + (pt 616 312) + (pt 616 344) +) +(connector + (pt 616 344) + (pt 616 464) +) +(connector + (pt 384 264) + (pt 656 264) +) +(connector + (pt 448 408) + (pt 440 408) +) +(connector + (pt 440 408) + (pt 440 280) +) +(connector + (pt 384 280) + (pt 440 280) +) +(connector + (pt 440 280) + (pt 528 280) +) +(connector + (pt 424 328) + (pt 656 328) +) +(connector + (pt 448 424) + (pt 432 424) +) +(connector + (pt 432 424) + (pt 432 360) +) +(connector + (pt 656 360) + (pt 432 360) +) +(connector + (pt 432 360) + (pt 416 360) +) +(connector + (pt 448 456) + (pt 424 456) +) +(connector + (pt 424 456) + (pt 424 328) +) +(connector + (pt 424 328) + (pt 424 296) +) +(connector + (pt 384 296) + (pt 424 296) +) +(connector + (pt 384 312) + (pt 416 312) +) +(connector + (pt 416 312) + (pt 416 360) +) +(connector + (pt 416 360) + (pt 416 472) +) +(connector + (pt 416 472) + (pt 448 472) +) +(junction (pt 640 280)) +(junction (pt 640 376)) +(junction (pt 616 464)) +(junction (pt 616 344)) +(junction (pt 440 280)) +(junction (pt 432 360)) +(junction (pt 424 328)) +(junction (pt 416 360)) diff --git a/CH5/CH5-3/BCD_adder_7483.qpf b/CH5/CH5-3/BCD_adder_7483.qpf new file mode 100644 index 00000000..8bee686d --- /dev/null +++ b/CH5/CH5-3/BCD_adder_7483.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.2 Build 153 07/15/2015 SJ Web Edition +# Date created = 22:30:50 August 26, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.0" +DATE = "22:30:50 August 26, 2019" + +# Revisions + +PROJECT_REVISION = "BCD_adder_7483" diff --git a/CH5/CH5-3/BCD_adder_7483.qsf b/CH5/CH5-3/BCD_adder_7483.qsf new file mode 100644 index 00000000..03399934 --- /dev/null +++ b/CH5/CH5-3/BCD_adder_7483.qsf @@ -0,0 +1,70 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.2 Build 153 07/15/2015 SJ Web Edition +# Date created = 22:30:50 August 26, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# BCD_adder_7483_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C16F484C6 +set_global_assignment -name TOP_LEVEL_ENTITY BCD_adder_7483 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:30:50 AUGUST 26, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name BDF_FILE BCD_adder_7483.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_location_assignment PIN_D2 -to A0 +set_location_assignment PIN_E4 -to A1 +set_location_assignment PIN_E3 -to A2 +set_location_assignment PIN_H7 -to A3 +set_location_assignment PIN_J7 -to B0 +set_location_assignment PIN_G5 -to B1 +set_location_assignment PIN_G4 -to B2 +set_location_assignment PIN_H6 -to B3 +set_location_assignment PIN_B1 -to C4 +set_location_assignment PIN_B2 -to S0 +set_location_assignment PIN_C2 -to S1 +set_location_assignment PIN_C1 -to S2 +set_location_assignment PIN_E1 -to S3 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/CH5/CH5-3/BCD_adder_7483.qws b/CH5/CH5-3/BCD_adder_7483.qws new file mode 100644 index 00000000..7764e5c8 Binary files /dev/null and b/CH5/CH5-3/BCD_adder_7483.qws differ diff --git a/CH5/CH5-3/c5_pin_model_dump.txt b/CH5/CH5-3/c5_pin_model_dump.txt new file mode 100644 index 00000000..31bb72c1 --- /dev/null +++ b/CH5/CH5-3/c5_pin_model_dump.txt @@ -0,0 +1,118 @@ +io_4iomodule_c5_index: 55gpio_index: 2 +io_4iomodule_c5_index: 54gpio_index: 465 +io_4iomodule_c5_index: 33gpio_index: 6 +io_4iomodule_c5_index: 51gpio_index: 461 +io_4iomodule_c5_index: 27gpio_index: 10 +io_4iomodule_c5_index: 57gpio_index: 457 +io_4iomodule_c5_index: 34gpio_index: 14 +io_4iomodule_c5_index: 28gpio_index: 453 +io_4iomodule_c5_index: 26gpio_index: 19 +io_4iomodule_c5_index: 47gpio_index: 449 +io_4iomodule_c5_index: 29gpio_index: 22 +io_4iomodule_c5_index: 3gpio_index: 445 +io_4iomodule_c5_index: 16gpio_index: 27 +io_4iomodule_c5_index: 6gpio_index: 441 +io_4iomodule_c5_index: 50gpio_index: 30 +io_4iomodule_c5_index: 35gpio_index: 437 +io_4iomodule_c5_index: 7gpio_index: 35 +io_4iomodule_c5_index: 53gpio_index: 433 +io_4iomodule_c5_index: 12gpio_index: 38 +io_4iomodule_c5_index: 1gpio_index: 429 +io_4iomodule_c5_index: 22gpio_index: 43 +io_4iomodule_c5_index: 8gpio_index: 425 +io_4iomodule_c5_index: 20gpio_index: 46 +io_4iomodule_c5_index: 30gpio_index: 421 +io_4iomodule_c5_index: 2gpio_index: 51 +io_4iomodule_c5_index: 31gpio_index: 417 +io_4iomodule_c5_index: 39gpio_index: 54 +io_4iomodule_c5_index: 18gpio_index: 413 +io_4iomodule_c5_index: 10gpio_index: 59 +io_4iomodule_c5_index: 42gpio_index: 409 +io_4iomodule_c5_index: 5gpio_index: 62 +io_4iomodule_c5_index: 24gpio_index: 405 +io_4iomodule_c5_index: 37gpio_index: 67 +io_4iomodule_c5_index: 13gpio_index: 401 +io_4iomodule_c5_index: 0gpio_index: 70 +io_4iomodule_c5_index: 44gpio_index: 397 +io_4iomodule_c5_index: 38gpio_index: 75 +io_4iomodule_c5_index: 52gpio_index: 393 +io_4iomodule_c5_index: 32gpio_index: 78 +io_4iomodule_c5_index: 56gpio_index: 389 +io_4iomodule_a_index: 13gpio_index: 385 +io_4iomodule_c5_index: 4gpio_index: 83 +io_4iomodule_c5_index: 23gpio_index: 86 +io_4iomodule_a_index: 15gpio_index: 381 +io_4iomodule_a_index: 8gpio_index: 377 +io_4iomodule_c5_index: 46gpio_index: 91 +io_4iomodule_a_index: 5gpio_index: 373 +io_4iomodule_a_index: 11gpio_index: 369 +io_4iomodule_c5_index: 41gpio_index: 94 +io_4iomodule_a_index: 3gpio_index: 365 +io_4iomodule_c5_index: 25gpio_index: 99 +io_4iomodule_a_index: 7gpio_index: 361 +io_4iomodule_c5_index: 9gpio_index: 102 +io_4iomodule_a_index: 0gpio_index: 357 +io_4iomodule_c5_index: 14gpio_index: 107 +io_4iomodule_a_index: 12gpio_index: 353 +io_4iomodule_c5_index: 45gpio_index: 110 +io_4iomodule_c5_index: 17gpio_index: 115 +io_4iomodule_a_index: 4gpio_index: 349 +io_4iomodule_c5_index: 36gpio_index: 118 +io_4iomodule_a_index: 10gpio_index: 345 +io_4iomodule_a_index: 16gpio_index: 341 +io_4iomodule_c5_index: 15gpio_index: 123 +io_4iomodule_a_index: 14gpio_index: 337 +io_4iomodule_c5_index: 43gpio_index: 126 +io_4iomodule_c5_index: 19gpio_index: 131 +io_4iomodule_a_index: 1gpio_index: 333 +io_4iomodule_c5_index: 59gpio_index: 134 +io_4iomodule_a_index: 2gpio_index: 329 +io_4iomodule_a_index: 9gpio_index: 325 +io_4iomodule_c5_index: 48gpio_index: 139 +io_4iomodule_a_index: 6gpio_index: 321 +io_4iomodule_a_index: 17gpio_index: 317 +io_4iomodule_c5_index: 40gpio_index: 142 +io_4iomodule_c5_index: 11gpio_index: 147 +io_4iomodule_c5_index: 58gpio_index: 150 +io_4iomodule_c5_index: 21gpio_index: 155 +io_4iomodule_c5_index: 49gpio_index: 158 +io_4iomodule_h_c5_index: 0gpio_index: 161 +io_4iomodule_h_c5_index: 6gpio_index: 165 +io_4iomodule_h_c5_index: 10gpio_index: 169 +io_4iomodule_h_c5_index: 3gpio_index: 173 +io_4iomodule_h_c5_index: 8gpio_index: 176 +io_4iomodule_h_c5_index: 11gpio_index: 180 +io_4iomodule_h_c5_index: 7gpio_index: 184 +io_4iomodule_h_c5_index: 5gpio_index: 188 +io_4iomodule_h_c5_index: 1gpio_index: 192 +io_4iomodule_h_c5_index: 2gpio_index: 196 +io_4iomodule_h_c5_index: 9gpio_index: 200 +io_4iomodule_h_c5_index: 4gpio_index: 204 +io_4iomodule_h_index: 15gpio_index: 208 +io_4iomodule_h_index: 1gpio_index: 212 +io_4iomodule_h_index: 3gpio_index: 216 +io_4iomodule_h_index: 2gpio_index: 220 +io_4iomodule_h_index: 11gpio_index: 224 +io_4iomodule_vref_h_index: 1gpio_index: 228 +io_4iomodule_h_index: 20gpio_index: 231 +io_4iomodule_h_index: 8gpio_index: 235 +io_4iomodule_h_index: 6gpio_index: 239 +io_4iomodule_h_index: 10gpio_index: 243 +io_4iomodule_h_index: 23gpio_index: 247 +io_4iomodule_h_index: 7gpio_index: 251 +io_4iomodule_h_index: 22gpio_index: 255 +io_4iomodule_h_index: 5gpio_index: 259 +io_4iomodule_h_index: 24gpio_index: 263 +io_4iomodule_h_index: 0gpio_index: 267 +io_4iomodule_h_index: 13gpio_index: 271 +io_4iomodule_h_index: 21gpio_index: 275 +io_4iomodule_h_index: 16gpio_index: 279 +io_4iomodule_vref_h_index: 0gpio_index: 283 +io_4iomodule_h_index: 12gpio_index: 286 +io_4iomodule_h_index: 4gpio_index: 290 +io_4iomodule_h_index: 19gpio_index: 294 +io_4iomodule_h_index: 18gpio_index: 298 +io_4iomodule_h_index: 17gpio_index: 302 +io_4iomodule_h_index: 25gpio_index: 306 +io_4iomodule_h_index: 14gpio_index: 310 +io_4iomodule_h_index: 9gpio_index: 314 diff --git a/CH5/CH5-3/db/.cmp.kpt b/CH5/CH5-3/db/.cmp.kpt new file mode 100644 index 00000000..948e0e22 Binary files /dev/null and b/CH5/CH5-3/db/.cmp.kpt differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.(0).cnf.cdb b/CH5/CH5-3/db/BCD_adder_1D.(0).cnf.cdb new file mode 100644 index 00000000..a598a3b7 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.(0).cnf.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.(0).cnf.hdb b/CH5/CH5-3/db/BCD_adder_1D.(0).cnf.hdb new file mode 100644 index 00000000..50e6d7ef Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.(0).cnf.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.(1).cnf.cdb b/CH5/CH5-3/db/BCD_adder_1D.(1).cnf.cdb new file mode 100644 index 00000000..b409cfc8 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.(1).cnf.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.(1).cnf.hdb b/CH5/CH5-3/db/BCD_adder_1D.(1).cnf.hdb new file mode 100644 index 00000000..4f0fcbc8 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.(1).cnf.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.(2).cnf.cdb b/CH5/CH5-3/db/BCD_adder_1D.(2).cnf.cdb new file mode 100644 index 00000000..ea866327 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.(2).cnf.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.(2).cnf.hdb b/CH5/CH5-3/db/BCD_adder_1D.(2).cnf.hdb new file mode 100644 index 00000000..1d65f6a0 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.(2).cnf.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.(3).cnf.cdb b/CH5/CH5-3/db/BCD_adder_1D.(3).cnf.cdb new file mode 100644 index 00000000..bd78515a Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.(3).cnf.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.(3).cnf.hdb b/CH5/CH5-3/db/BCD_adder_1D.(3).cnf.hdb new file mode 100644 index 00000000..8fca3769 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.(3).cnf.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.asm.qmsg b/CH5/CH5-3/db/BCD_adder_1D.asm.qmsg new file mode 100644 index 00000000..5a30f1b1 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567686542094 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567686542096 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 5 20:29:01 2019 " "Processing started: Thu Sep 5 20:29:01 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567686542096 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567686542096 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D " "Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567686542097 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1567686543602 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567686543646 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "378 " "Peak virtual memory: 378 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567686544107 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 5 20:29:04 2019 " "Processing ended: Thu Sep 5 20:29:04 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567686544107 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567686544107 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567686544107 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567686544107 ""} diff --git a/CH5/CH5-3/db/BCD_adder_1D.asm.rdb b/CH5/CH5-3/db/BCD_adder_1D.asm.rdb new file mode 100644 index 00000000..f2ee0625 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.asm.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.asm_labs.ddb b/CH5/CH5-3/db/BCD_adder_1D.asm_labs.ddb new file mode 100644 index 00000000..ed173e80 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.asm_labs.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.cbx.xml b/CH5/CH5-3/db/BCD_adder_1D.cbx.xml new file mode 100644 index 00000000..a6974564 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/CH5/CH5-3/db/BCD_adder_1D.cmp.bpm b/CH5/CH5-3/db/BCD_adder_1D.cmp.bpm new file mode 100644 index 00000000..99e75ccf Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.cmp.bpm differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.cmp.cdb b/CH5/CH5-3/db/BCD_adder_1D.cmp.cdb new file mode 100644 index 00000000..e5dbc9dd Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.cmp.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.cmp.hdb b/CH5/CH5-3/db/BCD_adder_1D.cmp.hdb new file mode 100644 index 00000000..c7ad68bb Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.cmp.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.cmp.idb b/CH5/CH5-3/db/BCD_adder_1D.cmp.idb new file mode 100644 index 00000000..65513dcd Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.cmp.idb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.cmp.logdb b/CH5/CH5-3/db/BCD_adder_1D.cmp.logdb new file mode 100644 index 00000000..96bcf8fb --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.cmp.logdb @@ -0,0 +1,55 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,13;0;13;0;0;13;13;0;13;13;0;5;0;0;8;0;5;8;0;0;0;5;0;0;0;0;0;13;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,0;13;0;13;13;0;0;13;0;0;13;8;13;13;5;13;8;5;13;13;13;8;13;13;13;13;13;0;13;13, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,S0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,C4,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/CH5/CH5-3/db/BCD_adder_1D.cmp.rdb b/CH5/CH5-3/db/BCD_adder_1D.cmp.rdb new file mode 100644 index 00000000..d0844b2d Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.cmp.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.cmp_merge.kpt b/CH5/CH5-3/db/BCD_adder_1D.cmp_merge.kpt new file mode 100644 index 00000000..064e5ebb Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.cmp_merge.kpt differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/CH5/CH5-3/db/BCD_adder_1D.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd new file mode 100644 index 00000000..d47667cb Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/CH5/CH5-3/db/BCD_adder_1D.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd new file mode 100644 index 00000000..fa762e05 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.db_info b/CH5/CH5-3/db/BCD_adder_1D.db_info new file mode 100644 index 00000000..c9b99606 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +Version_Index = 318808576 +Creation_Time = Mon Sep 9 20:51:52 2019 diff --git a/CH5/CH5-3/db/BCD_adder_1D.eda.qmsg b/CH5/CH5-3/db/BCD_adder_1D.eda.qmsg new file mode 100644 index 00000000..2ac8d512 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.eda.qmsg @@ -0,0 +1,12 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567686554053 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567686554055 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 5 20:29:13 2019 " "Processing started: Thu Sep 5 20:29:13 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567686554055 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567686554055 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D " "Command: quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567686554055 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_6_1200mv_85c_slow.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_6_1200mv_85c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686554677 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_6_1200mv_0c_slow.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_6_1200mv_0c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686554713 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_min_1200mv_0c_fast.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_min_1200mv_0c_fast.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686554749 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686554782 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_6_1200mv_85c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_6_1200mv_85c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686554822 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_6_1200mv_0c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_6_1200mv_0c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686554856 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_min_1200mv_0c_vhd_fast.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_min_1200mv_0c_vhd_fast.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686554887 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_vhd.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_vhd.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686554918 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "342 " "Peak virtual memory: 342 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567686554984 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 5 20:29:14 2019 " "Processing ended: Thu Sep 5 20:29:14 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567686554984 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567686554984 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567686554984 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567686554984 ""} diff --git a/CH5/CH5-3/db/BCD_adder_1D.fit.qmsg b/CH5/CH5-3/db/BCD_adder_1D.fit.qmsg new file mode 100644 index 00000000..51596528 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.fit.qmsg @@ -0,0 +1,45 @@ +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567686528241 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "BCD_adder_1D EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"BCD_adder_1D\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567686528249 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1567686528355 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1567686528357 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1567686528357 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1567686528514 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1567686528540 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1567686528923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1567686528923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1567686528923 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1567686528923 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 76 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1567686528935 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 78 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1567686528935 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 80 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1567686528935 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 82 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1567686528935 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 84 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1567686528935 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1567686528935 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1567686528941 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_1D.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_1D.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1567686530985 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1567686530986 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1567686530987 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1567686530988 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1567686530990 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1567686530990 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1567686530990 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1567686530996 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1567686530997 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1567686530997 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1567686530999 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1567686531000 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1567686531001 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1567686531001 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1567686531001 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1567686531002 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1567686531003 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1567686531003 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1567686531038 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1567686532474 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1567686532573 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1567686532587 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1567686532925 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1567686532925 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1567686533171 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" { } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1567686534102 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1567686534102 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1567686534196 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1567686534197 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1567686534197 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1567686534197 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.24 " "Total time spent on timing analysis during the Fitter is 0.24 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1567686534212 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1567686534277 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1567686534786 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1567686534843 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1567686535411 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1567686536037 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1567686537881 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567686538157 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 5 20:28:58 2019 " "Processing ended: Thu Sep 5 20:28:58 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567686538157 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567686538157 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567686538157 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567686538157 ""} diff --git a/CH5/CH5-3/db/BCD_adder_1D.hier_info b/CH5/CH5-3/db/BCD_adder_1D.hier_info new file mode 100644 index 00000000..9e387876 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.hier_info @@ -0,0 +1,258 @@ +|BCD_adder_1D +S0 <= four_bir_adder:inst2.S1 +A3 => four_bir_adder:inst.A4 +B3 => four_bir_adder:inst.B4 +A2 => four_bir_adder:inst.A3 +B2 => four_bir_adder:inst.B3 +A1 => four_bir_adder:inst.A2 +B1 => four_bir_adder:inst.B2 +A0 => four_bir_adder:inst.A1 +B0 => four_bir_adder:inst.B1 +S1 <= four_bir_adder:inst2.S2 +S2 <= four_bir_adder:inst2.S3 +S3 <= four_bir_adder:inst2.S4 +C4 <= inst6.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2 +S3 <= Full_adder_S:inst2.So +A3 => Full_adder_S:inst2.A +B3 => Full_adder_S:inst2.B +A2 => Full_adder_S:inst3.A +B2 => Full_adder_S:inst3.B +A1 => Full_adder_S:inst4.A +B1 => Full_adder_S:inst4.B +C0 => Full_adder_S:inst4.Ci +S4 <= Full_adder_S:inst.So +A4 => Full_adder_S:inst.A +B4 => Full_adder_S:inst.B +S1 <= Full_adder_S:inst4.So +C4 <= Full_adder_S:inst.Co +S2 <= Full_adder_S:inst3.So + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst2 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst3 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst4 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst4|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst4|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst +S3 <= Full_adder_S:inst2.So +A3 => Full_adder_S:inst2.A +B3 => Full_adder_S:inst2.B +A2 => Full_adder_S:inst3.A +B2 => Full_adder_S:inst3.B +A1 => Full_adder_S:inst4.A +B1 => Full_adder_S:inst4.B +C0 => Full_adder_S:inst4.Ci +S4 <= Full_adder_S:inst.So +A4 => Full_adder_S:inst.A +B4 => Full_adder_S:inst.B +S1 <= Full_adder_S:inst4.So +C4 <= Full_adder_S:inst.Co +S2 <= Full_adder_S:inst3.So + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst2 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst3 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst4 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/CH5/CH5-3/db/BCD_adder_1D.hif b/CH5/CH5-3/db/BCD_adder_1D.hif new file mode 100644 index 00000000..52345a95 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.hif differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.ipinfo b/CH5/CH5-3/db/BCD_adder_1D.ipinfo new file mode 100644 index 00000000..b19e3be1 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.ipinfo differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.lpc.html b/CH5/CH5-3/db/BCD_adder_1D.lpc.html new file mode 100644 index 00000000..8778b56a --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.lpc.html @@ -0,0 +1,434 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
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diff --git a/CH5/CH5-3/db/BCD_adder_1D.lpc.rdb b/CH5/CH5-3/db/BCD_adder_1D.lpc.rdb new file mode 100644 index 00000000..7725b794 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.lpc.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.lpc.txt b/CH5/CH5-3/db/BCD_adder_1D.lpc.txt new file mode 100644 index 00000000..bcd84d84 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.lpc.txt @@ -0,0 +1,32 @@ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; inst|inst|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst4|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst4|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst4 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst3|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst3|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst3 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst ; 9 ; 1 ; 0 ; 1 ; 5 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst4|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst4|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst4 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst3|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst3|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst3 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst2|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst2|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2|inst2 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst2 ; 9 ; 4 ; 0 ; 4 ; 5 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/CH5/CH5-3/db/BCD_adder_1D.map.ammdb b/CH5/CH5-3/db/BCD_adder_1D.map.ammdb new file mode 100644 index 00000000..e93ac1af Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.map.ammdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.map.bpm b/CH5/CH5-3/db/BCD_adder_1D.map.bpm new file mode 100644 index 00000000..8376c2cc Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.map.bpm differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.map.cdb b/CH5/CH5-3/db/BCD_adder_1D.map.cdb new file mode 100644 index 00000000..ef1d31e3 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.map.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.map.hdb b/CH5/CH5-3/db/BCD_adder_1D.map.hdb new file mode 100644 index 00000000..f3a0c2d8 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.map.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.map.kpt b/CH5/CH5-3/db/BCD_adder_1D.map.kpt new file mode 100644 index 00000000..e3e64e58 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.map.kpt differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.map.logdb b/CH5/CH5-3/db/BCD_adder_1D.map.logdb new file mode 100644 index 00000000..626799f0 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/CH5/CH5-3/db/BCD_adder_1D.map.qmsg b/CH5/CH5-3/db/BCD_adder_1D.map.qmsg new file mode 100644 index 00000000..129faa96 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.map.qmsg @@ -0,0 +1,18 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567686522465 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567686522468 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 5 20:28:42 2019 " "Processing started: Thu Sep 5 20:28:42 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567686522468 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567686522468 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D -c BCD_adder_1D " "Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D -c BCD_adder_1D" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567686522469 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567686522796 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_7483.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_7483.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_7483 " "Found entity 1: BCD_adder_7483" { } { { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686522948 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686522948 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Full_adder_S " "Found entity 1: Full_adder_S" { } { { "../CH5-1/Full_adder_S.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686522950 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686522950 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 four_bir_adder " "Found entity 1: four_bir_adder" { } { { "../CH5-1/four_bir_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686522951 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686522951 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 eight_bit_adder " "Found entity 1: eight_bit_adder" { } { { "../CH5-1/eight_bit_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686522952 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686522952 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Half_adder " "Found entity 1: Half_adder" { } { { "../CH5-1/Half_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686522953 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686522953 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_1D.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_1D.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_1D " "Found entity 1: BCD_adder_1D" { } { { "BCD_adder_1D.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686522954 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686522954 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "BCD_adder_1D " "Elaborating entity \"BCD_adder_1D\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567686523056 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "four_bir_adder four_bir_adder:inst2 " "Elaborating entity \"four_bir_adder\" for hierarchy \"four_bir_adder:inst2\"" { } { { "BCD_adder_1D.bdf" "inst2" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf" { { 224 888 984 416 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567686523061 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_adder_S four_bir_adder:inst2\|Full_adder_S:inst2 " "Elaborating entity \"Full_adder_S\" for hierarchy \"four_bir_adder:inst2\|Full_adder_S:inst2\"" { } { { "../CH5-1/four_bir_adder.bdf" "inst2" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { { 368 512 608 464 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567686523063 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Half_adder four_bir_adder:inst2\|Full_adder_S:inst2\|Half_adder:inst1 " "Elaborating entity \"Half_adder\" for hierarchy \"four_bir_adder:inst2\|Full_adder_S:inst2\|Half_adder:inst1\"" { } { { "../CH5-1/Full_adder_S.bdf" "inst1" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { { 248 456 552 344 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567686523064 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1567686524155 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1567686524565 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567686524565 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "23 " "Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567686524666 ""} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Implemented 5 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567686524666 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10 " "Implemented 10 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1567686524666 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567686524666 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567686524680 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 5 20:28:44 2019 " "Processing ended: Thu Sep 5 20:28:44 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567686524680 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567686524680 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567686524680 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567686524680 ""} diff --git a/CH5/CH5-3/db/BCD_adder_1D.map.rdb b/CH5/CH5-3/db/BCD_adder_1D.map.rdb new file mode 100644 index 00000000..4adad84d Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.map.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.map_bb.cdb b/CH5/CH5-3/db/BCD_adder_1D.map_bb.cdb new file mode 100644 index 00000000..8c4d3c69 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.map_bb.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.map_bb.hdb b/CH5/CH5-3/db/BCD_adder_1D.map_bb.hdb new file mode 100644 index 00000000..6858ab65 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.map_bb.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.map_bb.logdb b/CH5/CH5-3/db/BCD_adder_1D.map_bb.logdb new file mode 100644 index 00000000..626799f0 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/CH5/CH5-3/db/BCD_adder_1D.pplq.rdb b/CH5/CH5-3/db/BCD_adder_1D.pplq.rdb new file mode 100644 index 00000000..b9c4e156 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.pplq.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.pre_map.hdb b/CH5/CH5-3/db/BCD_adder_1D.pre_map.hdb new file mode 100644 index 00000000..ff2f860a Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.pre_map.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.pti_db_list.ddb b/CH5/CH5-3/db/BCD_adder_1D.pti_db_list.ddb new file mode 100644 index 00000000..6c4406c8 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.pti_db_list.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.root_partition.map.reg_db.cdb b/CH5/CH5-3/db/BCD_adder_1D.root_partition.map.reg_db.cdb new file mode 100644 index 00000000..e968df7f Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.root_partition.map.reg_db.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.routing.rdb b/CH5/CH5-3/db/BCD_adder_1D.routing.rdb new file mode 100644 index 00000000..0eead22b Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.routing.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.rtlv.hdb b/CH5/CH5-3/db/BCD_adder_1D.rtlv.hdb new file mode 100644 index 00000000..c8969dae Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.rtlv.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.rtlv_sg.cdb b/CH5/CH5-3/db/BCD_adder_1D.rtlv_sg.cdb new file mode 100644 index 00000000..3cdf12d0 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.rtlv_sg.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.rtlv_sg_swap.cdb b/CH5/CH5-3/db/BCD_adder_1D.rtlv_sg_swap.cdb new file mode 100644 index 00000000..6d295821 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.rtlv_sg_swap.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.sgdiff.cdb b/CH5/CH5-3/db/BCD_adder_1D.sgdiff.cdb new file mode 100644 index 00000000..b6b48d79 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.sgdiff.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.sgdiff.hdb b/CH5/CH5-3/db/BCD_adder_1D.sgdiff.hdb new file mode 100644 index 00000000..2ab6f4aa Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.sgdiff.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.sld_design_entry.sci b/CH5/CH5-3/db/BCD_adder_1D.sld_design_entry.sci new file mode 100644 index 00000000..7ef0f30b Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.sld_design_entry.sci differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.sld_design_entry_dsc.sci b/CH5/CH5-3/db/BCD_adder_1D.sld_design_entry_dsc.sci new file mode 100644 index 00000000..7ef0f30b Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.sld_design_entry_dsc.sci differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.smart_action.txt b/CH5/CH5-3/db/BCD_adder_1D.smart_action.txt new file mode 100644 index 00000000..c8e8a135 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/CH5/CH5-3/db/BCD_adder_1D.sta.qmsg b/CH5/CH5-3/db/BCD_adder_1D.sta.qmsg new file mode 100644 index 00000000..d465f33d --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.sta.qmsg @@ -0,0 +1,49 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567686547654 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567686547656 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 5 20:29:07 2019 " "Processing started: Thu Sep 5 20:29:07 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567686547656 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567686547656 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta BCD_adder_1D -c BCD_adder_1D " "Command: quartus_sta BCD_adder_1D -c BCD_adder_1D" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567686547656 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567686547717 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567686547925 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1567686547929 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1567686548039 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1567686548039 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_1D.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_1D.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567686548343 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567686548344 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1567686548345 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1567686548345 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1567686548346 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1567686548346 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567686548347 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1567686548355 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1567686548357 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686548358 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686548363 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686548364 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686548365 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686548366 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686548367 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1567686548377 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567686548424 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567686549351 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567686549382 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1567686549382 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1567686549382 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1567686549383 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686549383 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686549385 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686549387 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686549388 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686549389 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686549390 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1567686549400 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567686549536 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1567686549536 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1567686549536 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1567686549537 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686549539 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686549540 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686549541 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686549543 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686549544 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567686549740 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567686549740 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "369 " "Peak virtual memory: 369 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567686549782 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 5 20:29:09 2019 " "Processing ended: Thu Sep 5 20:29:09 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567686549782 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567686549782 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567686549782 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567686549782 ""} diff --git a/CH5/CH5-3/db/BCD_adder_1D.sta.rdb b/CH5/CH5-3/db/BCD_adder_1D.sta.rdb new file mode 100644 index 00000000..187b2bf7 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.sta.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.sta_cmp.6_slow_1200mv_85c.tdb b/CH5/CH5-3/db/BCD_adder_1D.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 00000000..08b243a4 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.tis_db_list.ddb b/CH5/CH5-3/db/BCD_adder_1D.tis_db_list.ddb new file mode 100644 index 00000000..33ec2f67 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.tis_db_list.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.tiscmp.fast_1200mv_0c.ddb b/CH5/CH5-3/db/BCD_adder_1D.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 00000000..a876e1c0 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.tiscmp.fast_1200mv_0c.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.tiscmp.slow_1200mv_0c.ddb b/CH5/CH5-3/db/BCD_adder_1D.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 00000000..20a8eeae Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.tiscmp.slow_1200mv_0c.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.tiscmp.slow_1200mv_85c.ddb b/CH5/CH5-3/db/BCD_adder_1D.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 00000000..89c10850 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.tiscmp.slow_1200mv_85c.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D.tmw_info b/CH5/CH5-3/db/BCD_adder_1D.tmw_info new file mode 100644 index 00000000..3d302b91 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D.tmw_info @@ -0,0 +1,5 @@ +start_analysis_synthesis:s +start_analysis_elaboration:s +start_fitter:s +start_timing_analyzer:s +start_eda_netlist_writer:s diff --git a/CH5/CH5-3/db/BCD_adder_1D.vpr.ammdb b/CH5/CH5-3/db/BCD_adder_1D.vpr.ammdb new file mode 100644 index 00000000..097e794c Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D.vpr.ammdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.(0).cnf.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.(0).cnf.cdb new file mode 100644 index 00000000..043f4cfb Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.(0).cnf.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.(0).cnf.hdb b/CH5/CH5-3/db/BCD_adder_1D_G.(0).cnf.hdb new file mode 100644 index 00000000..04cded5f Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.(0).cnf.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.(1).cnf.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.(1).cnf.cdb new file mode 100644 index 00000000..d803e87f Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.(1).cnf.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.(1).cnf.hdb b/CH5/CH5-3/db/BCD_adder_1D_G.(1).cnf.hdb new file mode 100644 index 00000000..3e622867 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.(1).cnf.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.(2).cnf.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.(2).cnf.cdb new file mode 100644 index 00000000..6863801d Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.(2).cnf.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.(2).cnf.hdb b/CH5/CH5-3/db/BCD_adder_1D_G.(2).cnf.hdb new file mode 100644 index 00000000..090e2215 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.(2).cnf.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.(3).cnf.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.(3).cnf.cdb new file mode 100644 index 00000000..3f166983 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.(3).cnf.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.(3).cnf.hdb b/CH5/CH5-3/db/BCD_adder_1D_G.(3).cnf.hdb new file mode 100644 index 00000000..8f1365f3 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.(3).cnf.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.(4).cnf.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.(4).cnf.cdb new file mode 100644 index 00000000..8f4cac50 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.(4).cnf.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.(4).cnf.hdb b/CH5/CH5-3/db/BCD_adder_1D_G.(4).cnf.hdb new file mode 100644 index 00000000..13efd8ba Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.(4).cnf.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.asm.qmsg b/CH5/CH5-3/db/BCD_adder_1D_G.asm.qmsg new file mode 100644 index 00000000..0a3b22d6 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1568034352221 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034352223 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 9 21:05:51 2019 " "Processing started: Mon Sep 9 21:05:51 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1568034352223 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1568034352223 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G " "Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1568034352224 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1568034353790 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1568034353832 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "378 " "Peak virtual memory: 378 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1568034354336 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 9 21:05:54 2019 " "Processing ended: Mon Sep 9 21:05:54 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1568034354336 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1568034354336 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1568034354336 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1568034354336 ""} diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.asm.rdb b/CH5/CH5-3/db/BCD_adder_1D_G.asm.rdb new file mode 100644 index 00000000..5bc00955 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.asm.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.asm_labs.ddb b/CH5/CH5-3/db/BCD_adder_1D_G.asm_labs.ddb new file mode 100644 index 00000000..c3fb0842 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.asm_labs.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.cbx.xml b/CH5/CH5-3/db/BCD_adder_1D_G.cbx.xml new file mode 100644 index 00000000..419f65c8 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.cmp.bpm b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.bpm new file mode 100644 index 00000000..a0095b30 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.bpm differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.cmp.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.cdb new file mode 100644 index 00000000..b907683f Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.cmp.hdb b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.hdb new file mode 100644 index 00000000..00302164 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.cmp.idb b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.idb new file mode 100644 index 00000000..a2797b76 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.idb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.cmp.logdb b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.logdb new file mode 100644 index 00000000..9b569b90 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.logdb @@ -0,0 +1,67 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;25;0;0;25;25;0;9;0;0;16;0;9;16;0;0;0;9;0;0;0;0;0;25;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,25;25;25;25;25;0;25;25;0;0;25;16;25;25;9;25;16;9;25;25;25;16;25;25;25;25;25;0;25;25, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,S3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S7,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S6,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S5,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S4,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,C8,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B7,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A4,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B4,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A5,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B5,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A6,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B6,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A7,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21, diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.cmp.rdb b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.rdb new file mode 100644 index 00000000..5d7908b2 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.cmp.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.cmp_merge.kpt b/CH5/CH5-3/db/BCD_adder_1D_G.cmp_merge.kpt new file mode 100644 index 00000000..f62bb0ba Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.cmp_merge.kpt differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/CH5/CH5-3/db/BCD_adder_1D_G.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd new file mode 100644 index 00000000..cd5d019e Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/CH5/CH5-3/db/BCD_adder_1D_G.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd new file mode 100644 index 00000000..a84d8e92 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.db_info b/CH5/CH5-3/db/BCD_adder_1D_G.db_info new file mode 100644 index 00000000..ddb80aa9 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +Version_Index = 318808576 +Creation_Time = Mon Sep 9 20:23:22 2019 diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.eda.qmsg b/CH5/CH5-3/db/BCD_adder_1D_G.eda.qmsg new file mode 100644 index 00000000..f095717b --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.eda.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1568034428796 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 1991-2013 Altera Corporation. All rights reserved. " "Copyright (C) 1991-2013 Altera Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Altera Corporation's design tools, logic functions " "Your use of Altera Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic " "and other software and tools, and its AMPP partner logic " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Altera Program License " "to the terms and conditions of the Altera Program License " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, Altera MegaCore Function License " "Subscription Agreement, Altera MegaCore Function License " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Agreement, or other applicable license agreement, including, " "Agreement, or other applicable license agreement, including, " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "without limitation, that your use is for the sole purpose of " "without limitation, that your use is for the sole purpose of " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "programming logic devices manufactured by Altera and sold by " "programming logic devices manufactured by Altera and sold by " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Altera or its authorized distributors. Please refer to the " "Altera or its authorized distributors. Please refer to the " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "applicable agreement for further details. " "applicable agreement for further details." { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 9 21:07:08 2019 " "Processing started: Mon Sep 9 21:07:08 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1568034428798 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/qsim/ BCD_adder_1D_G -c BCD_adder_1D_G " "Command: quartus_eda --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/qsim/ BCD_adder_1D_G -c BCD_adder_1D_G" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1568034428800 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_G.vo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/qsim// simulation " "Generated file BCD_adder_1D_G.vo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1568034429341 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "348 " "Peak virtual memory: 348 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1568034429393 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 9 21:07:09 2019 " "Processing ended: Mon Sep 9 21:07:09 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1568034429393 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1568034429393 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1568034429393 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1568034429393 ""} diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.fit.qmsg b/CH5/CH5-3/db/BCD_adder_1D_G.fit.qmsg new file mode 100644 index 00000000..d6c7581e --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.fit.qmsg @@ -0,0 +1,48 @@ +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1568034337771 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "BCD_adder_1D_G EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"BCD_adder_1D_G\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1568034337780 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1568034337895 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1568034337898 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1568034337898 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1568034338055 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1568034338079 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1568034338464 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1568034338464 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1568034338464 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1568034338464 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1568034338476 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1568034338476 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1568034338476 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1568034338476 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1568034338476 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1568034338476 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1568034338482 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "25 25 " "No exact pin location assignment(s) for 25 pins of 25 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S3 " "Pin S3 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S3 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 144 456 632 160 "S3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 57 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S2 " "Pin S2 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S2 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 160 456 632 176 "S2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 66 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S1 " "Pin S1 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S1 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 176 456 632 192 "S1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 67 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S0 " "Pin S0 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S0 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 192 456 632 208 "S0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 68 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S7 " "Pin S7 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S7 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 392 456 632 408 "S7" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 69 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S6 " "Pin S6 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S6 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 408 456 632 424 "S6" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 78 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S5 " "Pin S5 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S5 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 424 456 632 440 "S5" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 79 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S4 " "Pin S4 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S4 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 440 456 632 456 "S4" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 80 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C8 " "Pin C8 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { C8 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 456 456 632 472 "C8" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { C8 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 81 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B3 " "Pin B3 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B3 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 160 136 304 176 "B3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 59 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Pin A3 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A3 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 144 136 304 160 "A3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 58 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Pin A2 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A2 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 176 136 304 192 "A2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 60 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B2 " "Pin B2 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B2 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 192 136 304 208 "B2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 61 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B0 " "Pin B0 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B0 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 256 136 304 272 "B0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 65 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Pin A0 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A0 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 240 136 304 256 "A0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 64 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Pin A1 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A1 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 208 136 304 224 "A1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 62 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B1 " "Pin B1 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B1 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 224 136 304 240 "B1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 63 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B7 " "Pin B7 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B7 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 408 136 304 424 "B7" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 71 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Pin A4 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A4 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 488 136 304 504 "A4" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 76 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B4 " "Pin B4 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B4 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 504 136 304 520 "B4" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 77 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Pin A5 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A5 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 456 136 304 472 "A5" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 74 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B5 " "Pin B5 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B5 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 472 136 304 488 "B5" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 75 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Pin A6 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A6 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 424 136 304 440 "A6" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 72 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B6 " "Pin B6 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B6 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 440 136 304 456 "B6" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 73 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Pin A7 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A7 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 392 136 304 408 "A7" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 70 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568034340403 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1568034340403 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_1D_G.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_1D_G.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1568034340670 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1568034340671 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1568034340673 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1568034340674 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1568034340677 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1568034340677 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1568034340678 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1568034340684 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1568034340684 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1568034340685 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1568034340687 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1568034340687 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1568034340688 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1568034340688 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1568034340688 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1568034340688 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1568034340689 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1568034340689 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "25 unused 2.5V 16 9 0 " "Number of I/O pins in group: 25 (unused VREF, 2.5V VCCIO, 16 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1568034340693 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1568034340693 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1568034340693 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 29 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 29 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568034340696 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568034340696 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568034340696 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568034340696 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568034340696 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568034340696 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 47 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568034340696 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568034340696 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1568034340696 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1568034340696 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1568034340744 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1568034342263 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1568034342362 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1568034342379 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1568034342751 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1568034342751 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1568034343014 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X9_Y19 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19" { } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} 0 10 10 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1568034344001 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1568034344001 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1568034344114 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1568034344114 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1568034344114 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1568034344114 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.18 " "Total time spent on timing analysis during the Fitter is 0.18 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1568034344129 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1568034344201 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1568034344743 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1568034344800 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1568034345401 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1568034346064 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1568034347921 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1568034348194 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 9 21:05:48 2019 " "Processing ended: Mon Sep 9 21:05:48 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1568034348194 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1568034348194 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1568034348194 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1568034348194 ""} diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.hier_info b/CH5/CH5-3/db/BCD_adder_1D_G.hier_info new file mode 100644 index 00000000..00f08e3c --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.hier_info @@ -0,0 +1,552 @@ +|BCD_adder_1D_G +S3 <= BCD_adder_1D:inst.S3 +A3 => BCD_adder_1D:inst.A3 +B3 => BCD_adder_1D:inst.B3 +A2 => BCD_adder_1D:inst.A2 +B2 => BCD_adder_1D:inst.B2 +A1 => BCD_adder_1D:inst.A1 +B1 => BCD_adder_1D:inst.B1 +A0 => BCD_adder_1D:inst.A0 +B0 => BCD_adder_1D:inst.B0 +S2 <= BCD_adder_1D:inst.S2 +S1 <= BCD_adder_1D:inst.S1 +S0 <= BCD_adder_1D:inst.S0 +S7 <= BCD_adder_1D:inst4.S3 +A7 => BCD_adder_1D:inst4.A3 +B7 => BCD_adder_1D:inst4.B3 +A6 => BCD_adder_1D:inst4.A2 +B6 => BCD_adder_1D:inst4.B2 +A5 => BCD_adder_1D:inst4.A1 +B5 => BCD_adder_1D:inst4.B1 +A4 => BCD_adder_1D:inst4.A0 +B4 => BCD_adder_1D:inst4.B0 +S6 <= BCD_adder_1D:inst4.S2 +S5 <= BCD_adder_1D:inst4.S1 +S4 <= BCD_adder_1D:inst4.S0 +C8 <= BCD_adder_1D:inst4.C4 + + +|BCD_adder_1D_G|BCD_adder_1D:inst +S0 <= four_bir_adder:inst2.S1 +A3 => four_bir_adder:inst.A4 +B3 => four_bir_adder:inst.B4 +A2 => four_bir_adder:inst.A3 +B2 => four_bir_adder:inst.B3 +A1 => four_bir_adder:inst.A2 +B1 => four_bir_adder:inst.B2 +A0 => four_bir_adder:inst.A1 +B0 => four_bir_adder:inst.B1 +C0 => four_bir_adder:inst.C0 +C0 => four_bir_adder:inst2.B4 +C0 => four_bir_adder:inst2.B1 +C0 => four_bir_adder:inst2.C0 +S1 <= four_bir_adder:inst2.S2 +S2 <= four_bir_adder:inst2.S3 +S3 <= four_bir_adder:inst2.S4 +C4 <= inst6.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2 +S3 <= Full_adder_S:inst2.So +A3 => Full_adder_S:inst2.A +B3 => Full_adder_S:inst2.B +A2 => Full_adder_S:inst3.A +B2 => Full_adder_S:inst3.B +A1 => Full_adder_S:inst4.A +B1 => Full_adder_S:inst4.B +C0 => Full_adder_S:inst4.Ci +S4 <= Full_adder_S:inst.So +A4 => Full_adder_S:inst.A +B4 => Full_adder_S:inst.B +S1 <= Full_adder_S:inst4.So +C4 <= Full_adder_S:inst.Co +S2 <= Full_adder_S:inst3.So + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst2 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst3 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst4 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst4|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst4|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst +S3 <= Full_adder_S:inst2.So +A3 => Full_adder_S:inst2.A +B3 => Full_adder_S:inst2.B +A2 => Full_adder_S:inst3.A +B2 => Full_adder_S:inst3.B +A1 => Full_adder_S:inst4.A +B1 => Full_adder_S:inst4.B +C0 => Full_adder_S:inst4.Ci +S4 <= Full_adder_S:inst.So +A4 => Full_adder_S:inst.A +B4 => Full_adder_S:inst.B +S1 <= Full_adder_S:inst4.So +C4 <= Full_adder_S:inst.Co +S2 <= Full_adder_S:inst3.So + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst4 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4 +S0 <= four_bir_adder:inst2.S1 +A3 => four_bir_adder:inst.A4 +B3 => four_bir_adder:inst.B4 +A2 => four_bir_adder:inst.A3 +B2 => four_bir_adder:inst.B3 +A1 => four_bir_adder:inst.A2 +B1 => four_bir_adder:inst.B2 +A0 => four_bir_adder:inst.A1 +B0 => four_bir_adder:inst.B1 +C0 => four_bir_adder:inst.C0 +C0 => four_bir_adder:inst2.B4 +C0 => four_bir_adder:inst2.B1 +C0 => four_bir_adder:inst2.C0 +S1 <= four_bir_adder:inst2.S2 +S2 <= four_bir_adder:inst2.S3 +S3 <= four_bir_adder:inst2.S4 +C4 <= inst6.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2 +S3 <= Full_adder_S:inst2.So +A3 => Full_adder_S:inst2.A +B3 => Full_adder_S:inst2.B +A2 => Full_adder_S:inst3.A +B2 => Full_adder_S:inst3.B +A1 => Full_adder_S:inst4.A +B1 => Full_adder_S:inst4.B +C0 => Full_adder_S:inst4.Ci +S4 <= Full_adder_S:inst.So +A4 => Full_adder_S:inst.A +B4 => Full_adder_S:inst.B +S1 <= Full_adder_S:inst4.So +C4 <= Full_adder_S:inst.Co +S2 <= Full_adder_S:inst3.So + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst2 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst3 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst4 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst4|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst4|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst +S3 <= Full_adder_S:inst2.So +A3 => Full_adder_S:inst2.A +B3 => Full_adder_S:inst2.B +A2 => Full_adder_S:inst3.A +B2 => Full_adder_S:inst3.B +A1 => Full_adder_S:inst4.A +B1 => Full_adder_S:inst4.B +C0 => Full_adder_S:inst4.Ci +S4 <= Full_adder_S:inst.So +A4 => Full_adder_S:inst.A +B4 => Full_adder_S:inst.B +S1 <= Full_adder_S:inst4.So +C4 <= Full_adder_S:inst.Co +S2 <= Full_adder_S:inst3.So + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4 +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst +So <= Half_adder:inst1.S +A => Half_adder:inst.A +B => Half_adder:inst.B +Ci => Half_adder:inst1.B +Co <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst1 +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst +S <= inst.DB_MAX_OUTPUT_PORT_TYPE +A => inst.IN0 +A => inst2.IN0 +B => inst.IN1 +B => inst2.IN1 +C <= inst2.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.hif b/CH5/CH5-3/db/BCD_adder_1D_G.hif new file mode 100644 index 00000000..36c7d7aa Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.hif differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.ipinfo b/CH5/CH5-3/db/BCD_adder_1D_G.ipinfo new file mode 100644 index 00000000..b19e3be1 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.ipinfo differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.lpc.html b/CH5/CH5-3/db/BCD_adder_1D_G.lpc.html new file mode 100644 index 00000000..8dd3d380 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.lpc.html @@ -0,0 +1,882 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
inst4|inst|inst|inst2000200000000
inst4|inst|inst|inst12000200000000
inst4|inst|inst3000200000000
inst4|inst|inst4|inst2000200000000
inst4|inst|inst4|inst12000200000000
inst4|inst|inst43000200000000
inst4|inst|inst3|inst2000200000000
inst4|inst|inst3|inst12000200000000
inst4|inst|inst33000200000000
inst4|inst|inst2|inst2000200000000
inst4|inst|inst2|inst12000200000000
inst4|inst|inst23000200000000
inst4|inst9000500000000
inst4|inst2|inst|inst2000200000000
inst4|inst2|inst|inst12000200000000
inst4|inst2|inst3000200000000
inst4|inst2|inst4|inst2000200000000
inst4|inst2|inst4|inst12000200000000
inst4|inst2|inst43000200000000
inst4|inst2|inst3|inst2000200000000
inst4|inst2|inst3|inst12000200000000
inst4|inst2|inst33000200000000
inst4|inst2|inst2|inst2000200000000
inst4|inst2|inst2|inst12000200000000
inst4|inst2|inst23000200000000
inst4|inst29101511100000
inst49000500000000
inst|inst|inst|inst2000200000000
inst|inst|inst|inst12000200000000
inst|inst|inst3000200000000
inst|inst|inst4|inst2000200000000
inst|inst|inst4|inst12000200000000
inst|inst|inst43000200000000
inst|inst|inst3|inst2000200000000
inst|inst|inst3|inst12000200000000
inst|inst|inst33000200000000
inst|inst|inst2|inst2000200000000
inst|inst|inst2|inst12000200000000
inst|inst|inst23000200000000
inst|inst9000500000000
inst|inst2|inst|inst2000200000000
inst|inst2|inst|inst12000200000000
inst|inst2|inst3000200000000
inst|inst2|inst4|inst2000200000000
inst|inst2|inst4|inst12000200000000
inst|inst2|inst43000200000000
inst|inst2|inst3|inst2000200000000
inst|inst2|inst3|inst12000200000000
inst|inst2|inst33000200000000
inst|inst2|inst2|inst2000200000000
inst|inst2|inst2|inst12000200000000
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inst9101511100000
diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.lpc.rdb b/CH5/CH5-3/db/BCD_adder_1D_G.lpc.rdb new file mode 100644 index 00000000..ad74352c Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.lpc.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.lpc.txt b/CH5/CH5-3/db/BCD_adder_1D_G.lpc.txt new file mode 100644 index 00000000..bd6fe67e --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.lpc.txt @@ -0,0 +1,60 @@ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; inst4|inst|inst|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst|inst|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst|inst ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst|inst4|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst|inst4|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst|inst4 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst|inst3|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst|inst3|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst|inst3 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst|inst2|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst|inst2|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst|inst2 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst ; 9 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst4|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst4|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst4 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst3|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst3|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst3 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst2|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst2|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2|inst2 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4|inst2 ; 9 ; 1 ; 0 ; 1 ; 5 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst4 ; 9 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst4|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst4|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst4 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst3|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst3|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst3 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst2|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst2|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst|inst2 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst ; 9 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst4|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst4|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst4 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst3|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst3|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst3 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst2|inst ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst2|inst1 ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2|inst2 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|inst2 ; 9 ; 1 ; 0 ; 1 ; 5 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst ; 9 ; 1 ; 0 ; 1 ; 5 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.map.ammdb b/CH5/CH5-3/db/BCD_adder_1D_G.map.ammdb new file mode 100644 index 00000000..e93ac1af Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.map.ammdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.map.bpm b/CH5/CH5-3/db/BCD_adder_1D_G.map.bpm new file mode 100644 index 00000000..7e3e89be Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.map.bpm differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.map.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.map.cdb new file mode 100644 index 00000000..c4fa2571 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.map.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.map.hdb b/CH5/CH5-3/db/BCD_adder_1D_G.map.hdb new file mode 100644 index 00000000..bf1c269b Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.map.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.map.kpt b/CH5/CH5-3/db/BCD_adder_1D_G.map.kpt new file mode 100644 index 00000000..dc042ea8 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.map.kpt differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.map.logdb b/CH5/CH5-3/db/BCD_adder_1D_G.map.logdb new file mode 100644 index 00000000..626799f0 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.map.qmsg b/CH5/CH5-3/db/BCD_adder_1D_G.map.qmsg new file mode 100644 index 00000000..9fed2721 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.map.qmsg @@ -0,0 +1,20 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1568034331519 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034331521 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 9 21:05:31 2019 " "Processing started: Mon Sep 9 21:05:31 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1568034331521 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1568034331521 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G " "Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1568034331523 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1568034331876 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 eight_bit_adder " "Found entity 1: eight_bit_adder" { } { { "../CH5-1/eight_bit_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568034332025 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568034332025 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Full_adder_S " "Found entity 1: Full_adder_S" { } { { "../CH5-1/Full_adder_S.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568034332026 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568034332026 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Half_adder " "Found entity 1: Half_adder" { } { { "../CH5-1/Half_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568034332027 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568034332027 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 four_bir_adder " "Found entity 1: four_bir_adder" { } { { "../CH5-1/four_bir_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568034332028 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568034332028 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_7483.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_7483.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_7483 " "Found entity 1: BCD_adder_7483" { } { { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568034332029 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568034332029 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_1D.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_1D.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_1D " "Found entity 1: BCD_adder_1D" { } { { "BCD_adder_1D.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568034332030 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568034332030 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_1D_G.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_1D_G.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_1D_G " "Found entity 1: BCD_adder_1D_G" { } { { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568034332031 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568034332031 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "BCD_adder_1D_G " "Elaborating entity \"BCD_adder_1D_G\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1568034332140 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BCD_adder_1D BCD_adder_1D:inst " "Elaborating entity \"BCD_adder_1D\" for hierarchy \"BCD_adder_1D:inst\"" { } { { "BCD_adder_1D_G.bdf" "inst" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 120 336 432 312 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1568034332146 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "four_bir_adder BCD_adder_1D:inst\|four_bir_adder:inst2 " "Elaborating entity \"four_bir_adder\" for hierarchy \"BCD_adder_1D:inst\|four_bir_adder:inst2\"" { } { { "BCD_adder_1D.bdf" "inst2" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf" { { 224 888 984 416 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1568034332148 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_adder_S BCD_adder_1D:inst\|four_bir_adder:inst2\|Full_adder_S:inst2 " "Elaborating entity \"Full_adder_S\" for hierarchy \"BCD_adder_1D:inst\|four_bir_adder:inst2\|Full_adder_S:inst2\"" { } { { "../CH5-1/four_bir_adder.bdf" "inst2" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { { 368 512 608 464 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1568034332150 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Half_adder BCD_adder_1D:inst\|four_bir_adder:inst2\|Full_adder_S:inst2\|Half_adder:inst1 " "Elaborating entity \"Half_adder\" for hierarchy \"BCD_adder_1D:inst\|four_bir_adder:inst2\|Full_adder_S:inst2\|Half_adder:inst1\"" { } { { "../CH5-1/Full_adder_S.bdf" "inst1" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { { 248 456 552 344 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1568034332152 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1568034333484 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1568034334011 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1568034334011 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "50 " "Implemented 50 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Implemented 16 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1568034334118 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1568034334118 ""} { "Info" "ICUT_CUT_TM_LCELLS" "25 " "Implemented 25 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1568034334118 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1568034334118 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1568034334133 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 9 21:05:34 2019 " "Processing ended: Mon Sep 9 21:05:34 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1568034334133 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1568034334133 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1568034334133 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1568034334133 ""} diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.map.rdb b/CH5/CH5-3/db/BCD_adder_1D_G.map.rdb new file mode 100644 index 00000000..bbd38c29 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.map.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.map_bb.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.map_bb.cdb new file mode 100644 index 00000000..4e977824 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.map_bb.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.map_bb.hdb b/CH5/CH5-3/db/BCD_adder_1D_G.map_bb.hdb new file mode 100644 index 00000000..5108b3f2 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.map_bb.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.map_bb.logdb b/CH5/CH5-3/db/BCD_adder_1D_G.map_bb.logdb new file mode 100644 index 00000000..626799f0 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.pplq.rdb b/CH5/CH5-3/db/BCD_adder_1D_G.pplq.rdb new file mode 100644 index 00000000..b9c4e156 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.pplq.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.pre_map.hdb b/CH5/CH5-3/db/BCD_adder_1D_G.pre_map.hdb new file mode 100644 index 00000000..ee60efbd Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.pre_map.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.pti_db_list.ddb b/CH5/CH5-3/db/BCD_adder_1D_G.pti_db_list.ddb new file mode 100644 index 00000000..6c4406c8 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.pti_db_list.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.root_partition.map.reg_db.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.root_partition.map.reg_db.cdb new file mode 100644 index 00000000..ccae935a Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.root_partition.map.reg_db.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.routing.rdb b/CH5/CH5-3/db/BCD_adder_1D_G.routing.rdb new file mode 100644 index 00000000..7f251a5b Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.routing.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.rtlv.hdb b/CH5/CH5-3/db/BCD_adder_1D_G.rtlv.hdb new file mode 100644 index 00000000..a7d9f82c Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.rtlv.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.rtlv_sg.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.rtlv_sg.cdb new file mode 100644 index 00000000..424fff03 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.rtlv_sg.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.rtlv_sg_swap.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.rtlv_sg_swap.cdb new file mode 100644 index 00000000..17cf4e75 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.rtlv_sg_swap.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.sgdiff.cdb b/CH5/CH5-3/db/BCD_adder_1D_G.sgdiff.cdb new file mode 100644 index 00000000..167ed7f1 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.sgdiff.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.sgdiff.hdb b/CH5/CH5-3/db/BCD_adder_1D_G.sgdiff.hdb new file mode 100644 index 00000000..1a905a05 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.sgdiff.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.sld_design_entry.sci b/CH5/CH5-3/db/BCD_adder_1D_G.sld_design_entry.sci new file mode 100644 index 00000000..7ef0f30b Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.sld_design_entry.sci differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.sld_design_entry_dsc.sci b/CH5/CH5-3/db/BCD_adder_1D_G.sld_design_entry_dsc.sci new file mode 100644 index 00000000..7ef0f30b Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.sld_design_entry_dsc.sci differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.smart_action.txt b/CH5/CH5-3/db/BCD_adder_1D_G.smart_action.txt new file mode 100644 index 00000000..11b531f9 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.smart_action.txt @@ -0,0 +1 @@ +SOURCE diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.sta.qmsg b/CH5/CH5-3/db/BCD_adder_1D_G.sta.qmsg new file mode 100644 index 00000000..8dfba50d --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_1D_G.sta.qmsg @@ -0,0 +1,49 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1568034358055 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568034358057 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 9 21:05:57 2019 " "Processing started: Mon Sep 9 21:05:57 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1568034358057 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1568034358057 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta BCD_adder_1D_G -c BCD_adder_1D_G " "Command: quartus_sta BCD_adder_1D_G -c BCD_adder_1D_G" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1568034358058 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1568034358120 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1568034358336 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1568034358340 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1568034358455 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1568034358455 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_1D_G.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_1D_G.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1568034358768 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1568034358769 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1568034358770 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1568034358771 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1568034358772 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1568034358772 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1568034358773 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1568034358783 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1568034358784 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034358786 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034358791 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034358792 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034358793 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034358794 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034358795 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1568034358809 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1568034358858 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1568034359806 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1568034359840 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1568034359840 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1568034359841 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1568034359841 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034359842 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034359845 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034359847 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034359849 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034359850 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034359852 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1568034359862 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1568034360002 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1568034360003 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1568034360003 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1568034360003 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034360006 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034360008 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034360010 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034360012 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568034360015 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1568034360239 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1568034360240 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1568034360305 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 9 21:06:00 2019 " "Processing ended: Mon Sep 9 21:06:00 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1568034360305 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1568034360305 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1568034360305 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1568034360305 ""} diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.sta.rdb b/CH5/CH5-3/db/BCD_adder_1D_G.sta.rdb new file mode 100644 index 00000000..1bf6226f Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.sta.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.sta_cmp.6_slow_1200mv_85c.tdb b/CH5/CH5-3/db/BCD_adder_1D_G.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 00000000..d3b0383b Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.tis_db_list.ddb b/CH5/CH5-3/db/BCD_adder_1D_G.tis_db_list.ddb new file mode 100644 index 00000000..33ec2f67 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.tis_db_list.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.tiscmp.fast_1200mv_0c.ddb b/CH5/CH5-3/db/BCD_adder_1D_G.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 00000000..bf57a457 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.tiscmp.fast_1200mv_0c.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.tiscmp.slow_1200mv_0c.ddb b/CH5/CH5-3/db/BCD_adder_1D_G.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 00000000..c8f63ede Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.tiscmp.slow_1200mv_0c.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.tiscmp.slow_1200mv_85c.ddb b/CH5/CH5-3/db/BCD_adder_1D_G.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 00000000..c0b23e3c Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.tiscmp.slow_1200mv_85c.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_1D_G.vpr.ammdb b/CH5/CH5-3/db/BCD_adder_1D_G.vpr.ammdb new file mode 100644 index 00000000..dbe1f375 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_1D_G.vpr.ammdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.(0).cnf.cdb b/CH5/CH5-3/db/BCD_adder_7483.(0).cnf.cdb new file mode 100644 index 00000000..50540ecd Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.(0).cnf.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.(0).cnf.hdb b/CH5/CH5-3/db/BCD_adder_7483.(0).cnf.hdb new file mode 100644 index 00000000..6ee0fee2 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.(0).cnf.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.(1).cnf.cdb b/CH5/CH5-3/db/BCD_adder_7483.(1).cnf.cdb new file mode 100644 index 00000000..b0faea6e Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.(1).cnf.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.(1).cnf.hdb b/CH5/CH5-3/db/BCD_adder_7483.(1).cnf.hdb new file mode 100644 index 00000000..4b61bdb0 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.(1).cnf.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.asm.qmsg b/CH5/CH5-3/db/BCD_adder_7483.asm.qmsg new file mode 100644 index 00000000..5de4ed26 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1566832407488 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1566832407491 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 26 23:13:27 2019 " "Processing started: Mon Aug 26 23:13:27 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1566832407491 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1566832407491 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1566832407492 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1566832409617 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1566832409682 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566832410320 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 26 23:13:30 2019 " "Processing ended: Mon Aug 26 23:13:30 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566832410320 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566832410320 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566832410320 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1566832410320 ""} diff --git a/CH5/CH5-3/db/BCD_adder_7483.asm.rdb b/CH5/CH5-3/db/BCD_adder_7483.asm.rdb new file mode 100644 index 00000000..794a38c0 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.asm.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.asm_labs.ddb b/CH5/CH5-3/db/BCD_adder_7483.asm_labs.ddb new file mode 100644 index 00000000..f41c6667 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.asm_labs.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cbx.xml b/CH5/CH5-3/db/BCD_adder_7483.cbx.xml new file mode 100644 index 00000000..cf681320 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/CH5/CH5-3/db/BCD_adder_7483.cmp.bpm b/CH5/CH5-3/db/BCD_adder_7483.cmp.bpm new file mode 100644 index 00000000..b02451b1 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cmp.bpm differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cmp.cdb b/CH5/CH5-3/db/BCD_adder_7483.cmp.cdb new file mode 100644 index 00000000..c97f7edf Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cmp.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cmp.hdb b/CH5/CH5-3/db/BCD_adder_7483.cmp.hdb new file mode 100644 index 00000000..e3fa6aa4 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cmp.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cmp.idb b/CH5/CH5-3/db/BCD_adder_7483.cmp.idb new file mode 100644 index 00000000..0bc273d3 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cmp.idb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cmp.logdb b/CH5/CH5-3/db/BCD_adder_7483.cmp.logdb new file mode 100644 index 00000000..f2c4d9a2 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.cmp.logdb @@ -0,0 +1,55 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,13;0;13;0;0;13;13;0;13;13;0;5;0;0;8;0;5;8;0;0;0;5;0;0;0;0;0;13;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,0;13;0;13;13;0;0;13;0;0;13;8;13;13;5;13;8;5;13;13;13;8;13;13;13;13;13;0;13;13, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,S0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,S3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,C4,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/CH5/CH5-3/db/BCD_adder_7483.cmp.rdb b/CH5/CH5-3/db/BCD_adder_7483.cmp.rdb new file mode 100644 index 00000000..cf82ef71 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cmp.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cmp_merge.kpt b/CH5/CH5-3/db/BCD_adder_7483.cmp_merge.kpt new file mode 100644 index 00000000..fe9f097e Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cmp_merge.kpt differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/CH5/CH5-3/db/BCD_adder_7483.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd new file mode 100644 index 00000000..cd5d019e Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/CH5/CH5-3/db/BCD_adder_7483.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd new file mode 100644 index 00000000..a84d8e92 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ff_0c_fast.hsd b/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 00000000..bedbac68 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ff_85c_fast.hsd b/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ff_85c_fast.hsd new file mode 100644 index 00000000..3655b4fd Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ff_85c_fast.hsd differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ss_0c_slow.hsd b/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ss_0c_slow.hsd new file mode 100644 index 00000000..497655da Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ss_0c_slow.hsd differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ss_85c_slow.hsd b/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ss_85c_slow.hsd new file mode 100644 index 00000000..9b68c9e9 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.cyclonev_io_sim_cache.ss_85c_slow.hsd differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.db_info b/CH5/CH5-3/db/BCD_adder_7483.db_info new file mode 100644 index 00000000..70066b2b --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +Version_Index = 318808576 +Creation_Time = Mon Aug 26 22:33:43 2019 diff --git a/CH5/CH5-3/db/BCD_adder_7483.eda.qmsg b/CH5/CH5-3/db/BCD_adder_7483.eda.qmsg new file mode 100644 index 00000000..ee8cdf68 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.eda.qmsg @@ -0,0 +1,12 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1566832424929 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1566832424932 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 26 23:13:44 2019 " "Processing started: Mon Aug 26 23:13:44 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1566832424932 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1566832424932 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1566832424934 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_6_1200mv_85c_slow.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_6_1200mv_85c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832425788 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_6_1200mv_0c_slow.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_6_1200mv_0c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832425831 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_min_1200mv_0c_fast.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_min_1200mv_0c_fast.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832425881 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832425928 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_6_1200mv_85c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_6_1200mv_85c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832425980 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_6_1200mv_0c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_6_1200mv_0c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832426020 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_min_1200mv_0c_vhd_fast.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_min_1200mv_0c_vhd_fast.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832426067 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_vhd.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_vhd.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832426115 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "348 " "Peak virtual memory: 348 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566832426214 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 26 23:13:46 2019 " "Processing ended: Mon Aug 26 23:13:46 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566832426214 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566832426214 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566832426214 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1566832426214 ""} diff --git a/CH5/CH5-3/db/BCD_adder_7483.fit.qmsg b/CH5/CH5-3/db/BCD_adder_7483.fit.qmsg new file mode 100644 index 00000000..47f04259 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.fit.qmsg @@ -0,0 +1,44 @@ +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566832381921 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "BCD_adder_7483 EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"BCD_adder_7483\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566832381933 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1566832382073 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1566832382074 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1566832382282 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1566832382317 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1566832382896 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1566832382896 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1566832382896 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1566832382896 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 58 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1566832382913 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 60 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1566832382913 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 62 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1566832382913 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 64 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1566832382913 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 66 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1566832382913 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1566832382913 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1566832382920 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_7483.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_7483.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1566832386249 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1566832386251 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1566832386254 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1566832386255 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1566832386258 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1566832386258 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1566832386260 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1566832386269 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1566832386270 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1566832386271 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1566832386273 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1566832386275 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1566832386276 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1566832386276 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1566832386277 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1566832386277 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1566832386278 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1566832386278 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Fitter preparation operations ending: elapsed time is 00:00:04" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1566832386328 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1566832389803 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1566832389998 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1566832390020 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1566832390873 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1566832390874 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1566832391345 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" { } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1566832393293 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1566832393293 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1566832393479 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1566832393480 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1566832393480 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1566832393480 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.32 " "Total time spent on timing analysis during the Fitter is 0.32 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1566832393502 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1566832393596 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1566832394472 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1566832394603 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1566832395654 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1566832397045 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_7483.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_7483.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1566832399799 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566832400260 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 26 23:13:20 2019 " "Processing ended: Mon Aug 26 23:13:20 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566832400260 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Elapsed time: 00:00:21" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566832400260 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566832400260 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566832400260 ""} diff --git a/CH5/CH5-3/db/BCD_adder_7483.hier_info b/CH5/CH5-3/db/BCD_adder_7483.hier_info new file mode 100644 index 00000000..af641dc5 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.hier_info @@ -0,0 +1,66 @@ +|BCD_adder_7483 +S0 <= 7483:inst1.S1 +B3 => 7483:inst.B4 +A0 => 7483:inst.A1 +A1 => 7483:inst.A2 +B0 => 7483:inst.B1 +B1 => 7483:inst.B2 +A2 => 7483:inst.A3 +B2 => 7483:inst.B3 +A3 => 7483:inst.A4 +S1 <= 7483:inst1.S2 +S2 <= 7483:inst1.S3 +S3 <= 7483:inst1.S4 +C4 <= inst6.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_7483|7483:inst1 +C4 <= 83.DB_MAX_OUTPUT_PORT_TYPE +B4 => 22.IN0 +B4 => 26.IN0 +A4 => 22.IN1 +A4 => 26.IN1 +B3 => 21.IN0 +B3 => 25.IN0 +A3 => 21.IN1 +A3 => 25.IN1 +B2 => 20.IN0 +B2 => 24.IN0 +A2 => 20.IN1 +A2 => 24.IN1 +B1 => 19.IN0 +B1 => 23.IN0 +A1 => 19.IN1 +A1 => 23.IN1 +C0 => 17.IN0 +S4 <= 45.DB_MAX_OUTPUT_PORT_TYPE +S3 <= 44.DB_MAX_OUTPUT_PORT_TYPE +S2 <= 43.DB_MAX_OUTPUT_PORT_TYPE +S1 <= 42.DB_MAX_OUTPUT_PORT_TYPE + + +|BCD_adder_7483|7483:inst +C4 <= 83.DB_MAX_OUTPUT_PORT_TYPE +B4 => 22.IN0 +B4 => 26.IN0 +A4 => 22.IN1 +A4 => 26.IN1 +B3 => 21.IN0 +B3 => 25.IN0 +A3 => 21.IN1 +A3 => 25.IN1 +B2 => 20.IN0 +B2 => 24.IN0 +A2 => 20.IN1 +A2 => 24.IN1 +B1 => 19.IN0 +B1 => 23.IN0 +A1 => 19.IN1 +A1 => 23.IN1 +C0 => 17.IN0 +S4 <= 45.DB_MAX_OUTPUT_PORT_TYPE +S3 <= 44.DB_MAX_OUTPUT_PORT_TYPE +S2 <= 43.DB_MAX_OUTPUT_PORT_TYPE +S1 <= 42.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/CH5/CH5-3/db/BCD_adder_7483.hif b/CH5/CH5-3/db/BCD_adder_7483.hif new file mode 100644 index 00000000..6fd8f1d4 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.hif differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.ipinfo b/CH5/CH5-3/db/BCD_adder_7483.ipinfo new file mode 100644 index 00000000..b19e3be1 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.ipinfo differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.lpc.html b/CH5/CH5-3/db/BCD_adder_7483.lpc.html new file mode 100644 index 00000000..fbc5ab50 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/CH5/CH5-3/db/BCD_adder_7483.lpc.rdb b/CH5/CH5-3/db/BCD_adder_7483.lpc.rdb new file mode 100644 index 00000000..45b47e5f Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.lpc.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.lpc.txt b/CH5/CH5-3/db/BCD_adder_7483.lpc.txt new file mode 100644 index 00000000..a4638048 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/CH5/CH5-3/db/BCD_adder_7483.map.ammdb b/CH5/CH5-3/db/BCD_adder_7483.map.ammdb new file mode 100644 index 00000000..e93ac1af Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.map.ammdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.map.bpm b/CH5/CH5-3/db/BCD_adder_7483.map.bpm new file mode 100644 index 00000000..4a42332d Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.map.bpm differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.map.cdb b/CH5/CH5-3/db/BCD_adder_7483.map.cdb new file mode 100644 index 00000000..c12fbc9a Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.map.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.map.hdb b/CH5/CH5-3/db/BCD_adder_7483.map.hdb new file mode 100644 index 00000000..287b5c57 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.map.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.map.kpt b/CH5/CH5-3/db/BCD_adder_7483.map.kpt new file mode 100644 index 00000000..6ca99e9e Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.map.kpt differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.map.logdb b/CH5/CH5-3/db/BCD_adder_7483.map.logdb new file mode 100644 index 00000000..626799f0 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/CH5/CH5-3/db/BCD_adder_7483.map.qmsg b/CH5/CH5-3/db/BCD_adder_7483.map.qmsg new file mode 100644 index 00000000..be8a9b93 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.map.qmsg @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1566832373256 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1566832373261 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 26 23:12:52 2019 " "Processing started: Mon Aug 26 23:12:52 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1566832373261 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1566832373261 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 " "Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1566832373264 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1566832373774 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_7483.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_7483.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_7483 " "Found entity 1: BCD_adder_7483" { } { { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1566832373997 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1566832373997 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "BCD_adder_7483 " "Elaborating entity \"BCD_adder_7483\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1566832374148 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7483 7483:inst1 " "Elaborating entity \"7483\" for hierarchy \"7483:inst1\"" { } { { "BCD_adder_7483.bdf" "inst1" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 208 656 776 400 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1566832374165 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "7483:inst1 " "Elaborated megafunction instantiation \"7483:inst1\"" { } { { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 208 656 776 400 "inst1" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1566832374167 ""} +{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "1 " "Ignored 1 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "1 " "Ignored 1 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1566832374596 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1566832374596 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1566832375843 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1566832376388 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1566832376388 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "25 " "Implemented 25 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1566832376558 ""} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Implemented 5 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1566832376558 ""} { "Info" "ICUT_CUT_TM_LCELLS" "12 " "Implemented 12 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1566832376558 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1566832376558 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "371 " "Peak virtual memory: 371 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566832376577 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 26 23:12:56 2019 " "Processing ended: Mon Aug 26 23:12:56 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566832376577 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566832376577 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566832376577 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1566832376577 ""} diff --git a/CH5/CH5-3/db/BCD_adder_7483.map.rdb b/CH5/CH5-3/db/BCD_adder_7483.map.rdb new file mode 100644 index 00000000..7469a9f6 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.map.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.map_bb.cdb b/CH5/CH5-3/db/BCD_adder_7483.map_bb.cdb new file mode 100644 index 00000000..1de9495c Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.map_bb.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.map_bb.hdb b/CH5/CH5-3/db/BCD_adder_7483.map_bb.hdb new file mode 100644 index 00000000..c940380e Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.map_bb.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.map_bb.logdb b/CH5/CH5-3/db/BCD_adder_7483.map_bb.logdb new file mode 100644 index 00000000..626799f0 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/CH5/CH5-3/db/BCD_adder_7483.pplq.rdb b/CH5/CH5-3/db/BCD_adder_7483.pplq.rdb new file mode 100644 index 00000000..b9c4e156 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.pplq.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.pre_map.hdb b/CH5/CH5-3/db/BCD_adder_7483.pre_map.hdb new file mode 100644 index 00000000..63710c0a Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.pre_map.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.pti_db_list.ddb b/CH5/CH5-3/db/BCD_adder_7483.pti_db_list.ddb new file mode 100644 index 00000000..6c4406c8 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.pti_db_list.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.root_partition.map.reg_db.cdb b/CH5/CH5-3/db/BCD_adder_7483.root_partition.map.reg_db.cdb new file mode 100644 index 00000000..01cd44e8 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.root_partition.map.reg_db.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.routing.rdb b/CH5/CH5-3/db/BCD_adder_7483.routing.rdb new file mode 100644 index 00000000..74044f3a Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.routing.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.rtlv.hdb b/CH5/CH5-3/db/BCD_adder_7483.rtlv.hdb new file mode 100644 index 00000000..3c0f3a82 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.rtlv.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.rtlv_sg.cdb b/CH5/CH5-3/db/BCD_adder_7483.rtlv_sg.cdb new file mode 100644 index 00000000..ec08ca18 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.rtlv_sg.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.rtlv_sg_swap.cdb b/CH5/CH5-3/db/BCD_adder_7483.rtlv_sg_swap.cdb new file mode 100644 index 00000000..d5c1abbe Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.rtlv_sg_swap.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.sgdiff.cdb b/CH5/CH5-3/db/BCD_adder_7483.sgdiff.cdb new file mode 100644 index 00000000..5440d862 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.sgdiff.cdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.sgdiff.hdb b/CH5/CH5-3/db/BCD_adder_7483.sgdiff.hdb new file mode 100644 index 00000000..7d13b5af Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.sgdiff.hdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.sld_design_entry.sci b/CH5/CH5-3/db/BCD_adder_7483.sld_design_entry.sci new file mode 100644 index 00000000..7ef0f30b Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.sld_design_entry.sci differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.sld_design_entry_dsc.sci b/CH5/CH5-3/db/BCD_adder_7483.sld_design_entry_dsc.sci new file mode 100644 index 00000000..7ef0f30b Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.sld_design_entry_dsc.sci differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.smart_action.txt b/CH5/CH5-3/db/BCD_adder_7483.smart_action.txt new file mode 100644 index 00000000..c8e8a135 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/CH5/CH5-3/db/BCD_adder_7483.sta.qmsg b/CH5/CH5-3/db/BCD_adder_7483.sta.qmsg new file mode 100644 index 00000000..66b61a2d --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.sta.qmsg @@ -0,0 +1,48 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1566832415693 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1566832415695 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 26 23:13:35 2019 " "Processing started: Mon Aug 26 23:13:35 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1566832415695 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1566832415695 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta BCD_adder_7483 -c BCD_adder_7483 " "Command: quartus_sta BCD_adder_7483 -c BCD_adder_7483" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1566832415697 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1566832415787 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1566832416103 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1566832416247 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1566832416247 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_7483.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_7483.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1566832416644 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1566832416645 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1566832416646 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1566832416646 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1566832416647 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1566832416648 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1566832416649 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1566832416660 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1566832416662 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832416664 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832416670 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832416671 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832416673 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832416674 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832416676 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1566832416692 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1566832416757 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1566832417882 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1566832417923 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1566832417923 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1566832417924 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1566832417924 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832417925 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832417929 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832417932 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832417934 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832417936 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832417938 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1566832417948 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1566832418141 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1566832418142 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1566832418142 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1566832418142 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832418145 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832418147 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832418150 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832418152 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832418154 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1566832418400 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1566832418401 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566832418457 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 26 23:13:38 2019 " "Processing ended: Mon Aug 26 23:13:38 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566832418457 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566832418457 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566832418457 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1566832418457 ""} diff --git a/CH5/CH5-3/db/BCD_adder_7483.sta.rdb b/CH5/CH5-3/db/BCD_adder_7483.sta.rdb new file mode 100644 index 00000000..19901e37 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.sta.rdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.sta_cmp.6_slow_1200mv_85c.tdb b/CH5/CH5-3/db/BCD_adder_7483.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 00000000..a8ba4412 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.tis_db_list.ddb b/CH5/CH5-3/db/BCD_adder_7483.tis_db_list.ddb new file mode 100644 index 00000000..f326b985 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.tis_db_list.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.tiscmp.fast_1200mv_0c.ddb b/CH5/CH5-3/db/BCD_adder_7483.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 00000000..3c6e626e Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.tiscmp.fast_1200mv_0c.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.tiscmp.slow_1200mv_0c.ddb b/CH5/CH5-3/db/BCD_adder_7483.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 00000000..91240718 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.tiscmp.slow_1200mv_0c.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.tiscmp.slow_1200mv_85c.ddb b/CH5/CH5-3/db/BCD_adder_7483.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 00000000..1210c4b8 Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.tiscmp.slow_1200mv_85c.ddb differ diff --git a/CH5/CH5-3/db/BCD_adder_7483.tmw_info b/CH5/CH5-3/db/BCD_adder_7483.tmw_info new file mode 100644 index 00000000..024f2503 --- /dev/null +++ b/CH5/CH5-3/db/BCD_adder_7483.tmw_info @@ -0,0 +1,5 @@ +start_analysis_synthesis:s:00:00:11 +start_analysis_elaboration:s +start_fitter:s:00:00:24 +start_timing_analyzer:s:00:00:08 +start_eda_netlist_writer:s:00:00:08 diff --git a/CH5/CH5-3/db/BCD_adder_7483.vpr.ammdb b/CH5/CH5-3/db/BCD_adder_7483.vpr.ammdb new file mode 100644 index 00000000..2e7b066f Binary files /dev/null and b/CH5/CH5-3/db/BCD_adder_7483.vpr.ammdb differ diff --git a/CH5/CH5-3/db/logic_util_heursitic.dat b/CH5/CH5-3/db/logic_util_heursitic.dat new file mode 100644 index 00000000..66919ff0 Binary files /dev/null and b/CH5/CH5-3/db/logic_util_heursitic.dat differ diff --git a/CH5/CH5-3/db/prev_cmp_BCD_adder_1D.qmsg b/CH5/CH5-3/db/prev_cmp_BCD_adder_1D.qmsg new file mode 100644 index 00000000..b190bb8d --- /dev/null +++ b/CH5/CH5-3/db/prev_cmp_BCD_adder_1D.qmsg @@ -0,0 +1,138 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567686070254 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567686070257 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 5 20:21:09 2019 " "Processing started: Thu Sep 5 20:21:09 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567686070257 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567686070257 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D -c BCD_adder_1D " "Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D -c BCD_adder_1D" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567686070257 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567686070600 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_7483.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_7483.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_7483 " "Found entity 1: BCD_adder_7483" { } { { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686070747 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686070747 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Full_adder_S " "Found entity 1: Full_adder_S" { } { { "../CH5-1/Full_adder_S.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686070749 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686070749 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 four_bir_adder " "Found entity 1: four_bir_adder" { } { { "../CH5-1/four_bir_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686070750 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686070750 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 eight_bit_adder " "Found entity 1: eight_bit_adder" { } { { "../CH5-1/eight_bit_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686070751 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686070751 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Half_adder " "Found entity 1: Half_adder" { } { { "../CH5-1/Half_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686070752 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686070752 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_1D.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_1D.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_1D " "Found entity 1: BCD_adder_1D" { } { { "BCD_adder_1D.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567686070753 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567686070753 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "BCD_adder_1D " "Elaborating entity \"BCD_adder_1D\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567686070856 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "four_bir_adder four_bir_adder:inst2 " "Elaborating entity \"four_bir_adder\" for hierarchy \"four_bir_adder:inst2\"" { } { { "BCD_adder_1D.bdf" "inst2" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf" { { 224 888 984 416 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567686070862 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_adder_S four_bir_adder:inst2\|Full_adder_S:inst2 " "Elaborating entity \"Full_adder_S\" for hierarchy \"four_bir_adder:inst2\|Full_adder_S:inst2\"" { } { { "../CH5-1/four_bir_adder.bdf" "inst2" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { { 368 512 608 464 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567686070863 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Half_adder four_bir_adder:inst2\|Full_adder_S:inst2\|Half_adder:inst1 " "Elaborating entity \"Half_adder\" for hierarchy \"four_bir_adder:inst2\|Full_adder_S:inst2\|Half_adder:inst1\"" { } { { "../CH5-1/Full_adder_S.bdf" "inst1" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { { 248 456 552 344 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567686070865 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1567686071975 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1567686072387 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567686072387 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "23 " "Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567686072493 ""} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Implemented 5 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567686072493 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10 " "Implemented 10 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1567686072493 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567686072493 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "371 " "Peak virtual memory: 371 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567686072508 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 5 20:21:12 2019 " "Processing ended: Thu Sep 5 20:21:12 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567686072508 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567686072508 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567686072508 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567686072508 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567686075950 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567686075951 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 5 20:21:14 2019 " "Processing started: Thu Sep 5 20:21:14 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567686075951 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567686075951 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D " "Command: quartus_fit --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567686075952 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567686076013 ""} +{ "Info" "0" "" "Project = BCD_adder_1D" { } { } 0 0 "Project = BCD_adder_1D" 0 0 "Fitter" 0 0 1567686076014 ""} +{ "Info" "0" "" "Revision = BCD_adder_1D" { } { } 0 0 "Revision = BCD_adder_1D" 0 0 "Fitter" 0 0 1567686076015 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567686076123 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "BCD_adder_1D EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"BCD_adder_1D\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567686076130 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1567686076249 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1567686076251 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1567686076251 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1567686076414 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1567686076439 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1567686076847 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1567686076847 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1567686076847 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1567686076847 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 76 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1567686076860 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 78 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1567686076860 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 80 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1567686076860 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 82 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1567686076860 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 84 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1567686076860 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1567686076860 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1567686076865 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_1D.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_1D.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1567686078956 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1567686078957 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1567686078959 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1567686078959 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1567686078961 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1567686078961 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1567686078962 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1567686078967 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1567686078968 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1567686078968 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1567686078970 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1567686078971 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1567686078971 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1567686078971 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1567686078971 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1567686078972 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1567686078972 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1567686078972 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1567686079004 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1567686080443 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1567686080552 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1567686080567 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1567686080911 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1567686080911 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1567686081154 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" { } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1567686082118 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1567686082118 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1567686082203 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1567686082204 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1567686082204 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1567686082204 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.18 " "Total time spent on timing analysis during the Fitter is 0.18 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1567686082217 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1567686082283 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1567686082802 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1567686082855 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1567686083423 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1567686084049 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1567686085845 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567686086109 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 5 20:21:26 2019 " "Processing ended: Thu Sep 5 20:21:26 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567686086109 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567686086109 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567686086109 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567686086109 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567686090065 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567686090067 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 5 20:21:29 2019 " "Processing started: Thu Sep 5 20:21:29 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567686090067 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567686090067 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D " "Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567686090068 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1567686091577 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567686091626 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "378 " "Peak virtual memory: 378 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567686092083 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 5 20:21:32 2019 " "Processing ended: Thu Sep 5 20:21:32 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567686092083 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567686092083 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567686092083 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567686092083 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567686092224 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567686095674 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567686095675 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 5 20:21:35 2019 " "Processing started: Thu Sep 5 20:21:35 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567686095675 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567686095675 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta BCD_adder_1D -c BCD_adder_1D " "Command: quartus_sta BCD_adder_1D -c BCD_adder_1D" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567686095676 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567686095740 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567686095949 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1567686095953 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1567686096064 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1567686096064 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_1D.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_1D.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567686096365 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567686096366 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1567686096367 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1567686096368 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1567686096369 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1567686096369 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567686096370 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1567686096379 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1567686096381 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686096382 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686096387 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686096389 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686096390 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686096391 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686096392 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1567686096403 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567686096453 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567686097347 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567686097389 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1567686097389 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1567686097390 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1567686097390 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686097391 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686097394 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686097396 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686097397 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686097399 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686097401 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1567686097409 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567686097537 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1567686097537 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1567686097537 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1567686097538 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686097540 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686097541 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686097543 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686097545 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567686097546 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567686097743 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567686097744 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "369 " "Peak virtual memory: 369 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567686097785 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 5 20:21:37 2019 " "Processing ended: Thu Sep 5 20:21:37 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567686097785 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567686097785 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567686097785 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567686097785 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567686102039 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567686102040 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 5 20:21:41 2019 " "Processing started: Thu Sep 5 20:21:41 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567686102040 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567686102040 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D " "Command: quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567686102041 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_6_1200mv_85c_slow.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_6_1200mv_85c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686102680 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_6_1200mv_0c_slow.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_6_1200mv_0c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686102720 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_min_1200mv_0c_fast.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_min_1200mv_0c_fast.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686102758 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686102790 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_6_1200mv_85c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_6_1200mv_85c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686102833 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_6_1200mv_0c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_6_1200mv_0c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686102866 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_min_1200mv_0c_vhd_fast.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_min_1200mv_0c_vhd_fast.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686102896 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_vhd.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_vhd.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1567686102928 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "348 " "Peak virtual memory: 348 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567686102999 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 5 20:21:42 2019 " "Processing ended: Thu Sep 5 20:21:42 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567686102999 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567686102999 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567686102999 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567686102999 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 11 s " "Quartus II Full Compilation was successful. 0 errors, 11 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567686103148 ""} diff --git a/CH5/CH5-3/db/prev_cmp_BCD_adder_1D_G.qmsg b/CH5/CH5-3/db/prev_cmp_BCD_adder_1D_G.qmsg new file mode 100644 index 00000000..368274e9 --- /dev/null +++ b/CH5/CH5-3/db/prev_cmp_BCD_adder_1D_G.qmsg @@ -0,0 +1,143 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1568033885903 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568033885905 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 9 20:58:05 2019 " "Processing started: Mon Sep 9 20:58:05 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1568033885905 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1568033885905 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G " "Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1568033885906 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1568033886244 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 eight_bit_adder " "Found entity 1: eight_bit_adder" { } { { "../CH5-1/eight_bit_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568033886399 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568033886399 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Full_adder_S " "Found entity 1: Full_adder_S" { } { { "../CH5-1/Full_adder_S.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568033886400 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568033886400 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Half_adder " "Found entity 1: Half_adder" { } { { "../CH5-1/Half_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568033886401 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568033886401 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 four_bir_adder " "Found entity 1: four_bir_adder" { } { { "../CH5-1/four_bir_adder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568033886402 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568033886402 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_7483.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_7483.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_7483 " "Found entity 1: BCD_adder_7483" { } { { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568033886403 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568033886403 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_1D.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_1D.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_1D " "Found entity 1: BCD_adder_1D" { } { { "BCD_adder_1D.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568033886404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568033886404 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_1D_G.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_1D_G.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_1D_G " "Found entity 1: BCD_adder_1D_G" { } { { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1568033886404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1568033886404 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "BCD_adder_1D_G " "Elaborating entity \"BCD_adder_1D_G\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1568033886516 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BCD_adder_1D BCD_adder_1D:inst " "Elaborating entity \"BCD_adder_1D\" for hierarchy \"BCD_adder_1D:inst\"" { } { { "BCD_adder_1D_G.bdf" "inst" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 120 336 432 312 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1568033886521 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "four_bir_adder BCD_adder_1D:inst\|four_bir_adder:inst2 " "Elaborating entity \"four_bir_adder\" for hierarchy \"BCD_adder_1D:inst\|four_bir_adder:inst2\"" { } { { "BCD_adder_1D.bdf" "inst2" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf" { { 224 888 984 416 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1568033886523 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_adder_S BCD_adder_1D:inst\|four_bir_adder:inst2\|Full_adder_S:inst2 " "Elaborating entity \"Full_adder_S\" for hierarchy \"BCD_adder_1D:inst\|four_bir_adder:inst2\|Full_adder_S:inst2\"" { } { { "../CH5-1/four_bir_adder.bdf" "inst2" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf" { { 368 512 608 464 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1568033886525 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Half_adder BCD_adder_1D:inst\|four_bir_adder:inst2\|Full_adder_S:inst2\|Half_adder:inst1 " "Elaborating entity \"Half_adder\" for hierarchy \"BCD_adder_1D:inst\|four_bir_adder:inst2\|Full_adder_S:inst2\|Half_adder:inst1\"" { } { { "../CH5-1/Full_adder_S.bdf" "inst1" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf" { { 248 456 552 344 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1568033886527 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1568033887853 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1568033888358 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1568033888358 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "50 " "Implemented 50 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Implemented 16 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1568033888473 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1568033888473 ""} { "Info" "ICUT_CUT_TM_LCELLS" "25 " "Implemented 25 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1568033888473 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1568033888473 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "371 " "Peak virtual memory: 371 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1568033888489 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 9 20:58:08 2019 " "Processing ended: Mon Sep 9 20:58:08 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1568033888489 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1568033888489 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1568033888489 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1568033888489 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1568033892042 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568033892043 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 9 20:58:10 2019 " "Processing started: Mon Sep 9 20:58:10 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1568033892043 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1568033892043 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G " "Command: quartus_fit --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1568033892044 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1568033892101 ""} +{ "Info" "0" "" "Project = BCD_adder_1D_G" { } { } 0 0 "Project = BCD_adder_1D_G" 0 0 "Fitter" 0 0 1568033892103 ""} +{ "Info" "0" "" "Revision = BCD_adder_1D_G" { } { } 0 0 "Revision = BCD_adder_1D_G" 0 0 "Fitter" 0 0 1568033892104 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1568033892210 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "BCD_adder_1D_G EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"BCD_adder_1D_G\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1568033892217 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1568033892333 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1568033892335 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1568033892335 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1568033892486 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1568033892510 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1568033892906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1568033892906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1568033892906 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1568033892906 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1568033892918 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1568033892918 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1568033892918 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1568033892918 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1568033892918 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1568033892918 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1568033892924 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "25 25 " "No exact pin location assignment(s) for 25 pins of 25 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S3 " "Pin S3 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S3 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 144 456 632 160 "S3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 57 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S2 " "Pin S2 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S2 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 160 456 632 176 "S2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 66 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S1 " "Pin S1 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S1 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 176 456 632 192 "S1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 67 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S0 " "Pin S0 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S0 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 192 456 632 208 "S0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 68 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S7 " "Pin S7 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S7 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 392 456 632 408 "S7" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 69 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S6 " "Pin S6 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S6 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 408 456 632 424 "S6" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 78 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S5 " "Pin S5 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S5 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 424 456 632 440 "S5" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 79 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S4 " "Pin S4 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S4 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 440 456 632 456 "S4" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 80 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C8 " "Pin C8 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { C8 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 456 456 632 472 "C8" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { C8 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 81 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B3 " "Pin B3 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B3 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 160 136 304 176 "B3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 59 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Pin A3 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A3 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 144 136 304 160 "A3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 58 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Pin A2 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A2 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 176 136 304 192 "A2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 60 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B2 " "Pin B2 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B2 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 192 136 304 208 "B2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 61 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B0 " "Pin B0 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B0 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 256 136 304 272 "B0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 65 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Pin A0 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A0 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 240 136 304 256 "A0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 64 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Pin A1 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A1 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 208 136 304 224 "A1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 62 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B1 " "Pin B1 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B1 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 224 136 304 240 "B1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 63 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B7 " "Pin B7 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B7 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 408 136 304 424 "B7" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 71 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Pin A4 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A4 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 488 136 304 504 "A4" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 76 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B4 " "Pin B4 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B4 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 504 136 304 520 "B4" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 77 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Pin A5 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A5 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 456 136 304 472 "A5" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 74 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B5 " "Pin B5 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B5 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 472 136 304 488 "B5" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 75 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Pin A6 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A6 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 424 136 304 440 "A6" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 72 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B6 " "Pin B6 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B6 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 440 136 304 456 "B6" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 73 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Pin A7 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A7 } } } { "BCD_adder_1D_G.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf" { { 392 136 304 408 "A7" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 70 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1568033894854 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1568033894854 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_1D_G.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_1D_G.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1568033895137 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1568033895138 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1568033895139 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1568033895140 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1568033895142 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1568033895142 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1568033895143 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1568033895149 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1568033895149 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1568033895150 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1568033895152 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1568033895154 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1568033895155 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1568033895155 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1568033895155 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1568033895156 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1568033895157 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1568033895157 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "25 unused 2.5V 16 9 0 " "Number of I/O pins in group: 25 (unused VREF, 2.5V VCCIO, 16 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1568033895163 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1568033895163 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1568033895163 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 29 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 29 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568033895167 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568033895167 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568033895167 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568033895167 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568033895167 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568033895167 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 47 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568033895167 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1568033895167 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1568033895167 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1568033895167 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1568033895218 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1568033896712 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1568033896824 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1568033896838 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1568033897216 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1568033897216 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1568033897480 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X9_Y19 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19" { } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} 0 10 10 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1568033898465 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1568033898465 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1568033898567 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1568033898567 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1568033898567 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1568033898567 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.18 " "Total time spent on timing analysis during the Fitter is 0.18 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1568033898581 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1568033898644 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1568033899180 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1568033899234 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1568033899828 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1568033900471 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1568033902292 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1568033902567 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 9 20:58:22 2019 " "Processing ended: Mon Sep 9 20:58:22 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1568033902567 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1568033902567 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1568033902567 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1568033902567 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1568033906666 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568033906668 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 9 20:58:26 2019 " "Processing started: Mon Sep 9 20:58:26 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1568033906668 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1568033906668 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G " "Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1568033906668 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1568033908243 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1568033908292 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "378 " "Peak virtual memory: 378 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1568033908765 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 9 20:58:28 2019 " "Processing ended: Mon Sep 9 20:58:28 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1568033908765 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1568033908765 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1568033908765 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1568033908765 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1568033908900 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1568033912587 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568033912589 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 9 20:58:32 2019 " "Processing started: Mon Sep 9 20:58:32 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1568033912589 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1568033912589 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta BCD_adder_1D_G -c BCD_adder_1D_G " "Command: quartus_sta BCD_adder_1D_G -c BCD_adder_1D_G" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1568033912590 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1568033912647 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1568033912872 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1568033912876 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1568033912990 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1568033912990 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_1D_G.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_1D_G.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1568033913308 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1568033913309 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1568033913310 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1568033913310 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1568033913311 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1568033913311 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1568033913312 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1568033913322 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1568033913323 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033913325 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033913329 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033913330 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033913332 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033913333 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033913334 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1568033913348 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1568033913397 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1568033914366 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1568033914407 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1568033914407 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1568033914407 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1568033914408 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033914408 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033914411 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033914413 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033914415 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033914417 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033914418 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1568033914429 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1568033914560 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1568033914560 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1568033914561 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1568033914561 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033914564 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033914566 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033914568 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033914570 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1568033914572 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1568033914793 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1568033914794 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "372 " "Peak virtual memory: 372 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1568033914850 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 9 20:58:34 2019 " "Processing ended: Mon Sep 9 20:58:34 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1568033914850 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1568033914850 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1568033914850 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1568033914850 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1568033919386 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1568033919389 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 9 20:58:39 2019 " "Processing started: Mon Sep 9 20:58:39 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1568033919389 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1568033919389 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G " "Command: quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1568033919390 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_G_6_1200mv_85c_slow.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_G_6_1200mv_85c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1568033920061 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_G_6_1200mv_0c_slow.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_G_6_1200mv_0c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1568033920116 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_G_min_1200mv_0c_fast.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_G_min_1200mv_0c_fast.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1568033920162 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_G.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_G.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1568033920208 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_G_6_1200mv_85c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_G_6_1200mv_85c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1568033920251 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_G_6_1200mv_0c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_G_6_1200mv_0c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1568033920299 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_G_min_1200mv_0c_vhd_fast.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_G_min_1200mv_0c_vhd_fast.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1568033920338 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_1D_G_vhd.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_1D_G_vhd.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1568033920377 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "342 " "Peak virtual memory: 342 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1568033920446 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 9 20:58:40 2019 " "Processing ended: Mon Sep 9 20:58:40 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1568033920446 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1568033920446 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1568033920446 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1568033920446 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 12 s " "Quartus II Full Compilation was successful. 0 errors, 12 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1568033920607 ""} diff --git a/CH5/CH5-3/db/prev_cmp_BCD_adder_7483.qmsg b/CH5/CH5-3/db/prev_cmp_BCD_adder_7483.qmsg new file mode 100644 index 00000000..b21d51e3 --- /dev/null +++ b/CH5/CH5-3/db/prev_cmp_BCD_adder_7483.qmsg @@ -0,0 +1,134 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1566832036135 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1566832036138 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 26 23:07:15 2019 " "Processing started: Mon Aug 26 23:07:15 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1566832036138 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1566832036138 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 " "Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1566832036140 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1566832036678 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_adder_7483.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_adder_7483.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_adder_7483 " "Found entity 1: BCD_adder_7483" { } { { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1566832036906 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1566832036906 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "BCD_adder_7483 " "Elaborating entity \"BCD_adder_7483\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1566832037051 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7483 7483:inst1 " "Elaborating entity \"7483\" for hierarchy \"7483:inst1\"" { } { { "BCD_adder_7483.bdf" "inst1" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 208 656 776 400 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1566832037075 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "7483:inst1 " "Elaborated megafunction instantiation \"7483:inst1\"" { } { { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 208 656 776 400 "inst1" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1566832037094 ""} +{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "1 " "Ignored 1 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "1 " "Ignored 1 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1566832037509 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1566832037509 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1566832038648 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1566832039183 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1566832039183 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "25 " "Implemented 25 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1566832039331 ""} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Implemented 5 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1566832039331 ""} { "Info" "ICUT_CUT_TM_LCELLS" "12 " "Implemented 12 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1566832039331 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1566832039331 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "384 " "Peak virtual memory: 384 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566832039352 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 26 23:07:19 2019 " "Processing ended: Mon Aug 26 23:07:19 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566832039352 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566832039352 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566832039352 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1566832039352 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1566832044442 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1566832044444 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 26 23:07:22 2019 " "Processing started: Mon Aug 26 23:07:22 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1566832044444 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1566832044444 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1566832044445 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1566832044524 ""} +{ "Info" "0" "" "Project = BCD_adder_7483" { } { } 0 0 "Project = BCD_adder_7483" 0 0 "Fitter" 0 0 1566832044527 ""} +{ "Info" "0" "" "Revision = BCD_adder_7483" { } { } 0 0 "Revision = BCD_adder_7483" 0 0 "Fitter" 0 0 1566832044527 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566832044660 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "BCD_adder_7483 EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"BCD_adder_7483\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566832044670 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1566832044811 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1566832044811 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1566832045043 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1566832045077 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1566832045611 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1566832045611 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1566832045611 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1566832045611 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 58 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1566832045629 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 60 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1566832045629 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 62 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1566832045629 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 64 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1566832045629 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 66 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1566832045629 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1566832045629 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1566832045637 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "13 13 " "No exact pin location assignment(s) for 13 pins of 13 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S0 " "Pin S0 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S0 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 256 776 952 272 "S0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 5 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S1 " "Pin S1 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S1 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 272 776 952 288 "S1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 14 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S2 " "Pin S2 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S2 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 288 776 952 304 "S2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 15 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S3 " "Pin S3 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { S3 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 304 776 952 320 "S3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 16 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C4 " "Pin C4 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { C4 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 456 776 952 472 "C4" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { C4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 17 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Pin A0 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A0 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 256 64 232 272 "A0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 7 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B0 " "Pin B0 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B0 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 272 64 232 288 "B0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 9 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Pin A1 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A1 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 288 64 232 304 "A1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 8 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B1 " "Pin B1 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B1 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 304 64 232 320 "B1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 10 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Pin A3 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A3 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 352 64 232 368 "A3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 13 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B3 " "Pin B3 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B3 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 368 64 232 384 "B3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 6 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Pin A2 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A2 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 320 64 232 336 "A2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 11 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B2 " "Pin B2 not assigned to an exact location on the device" { } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B2 } } } { "BCD_adder_7483.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf" { { 336 64 232 352 "B2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 0 { 0 ""} 0 12 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1566832048045 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1566832048045 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_7483.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_7483.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1566832048440 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1566832048442 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1566832048444 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1566832048445 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1566832048448 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1566832048449 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1566832048449 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1566832048458 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1566832048459 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1566832048460 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1566832048463 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1566832048464 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1566832048465 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1566832048465 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1566832048466 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1566832048466 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1566832048467 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1566832048467 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "13 unused 2.5V 8 5 0 " "Number of I/O pins in group: 13 (unused VREF, 2.5V VCCIO, 8 input, 5 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1566832048474 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1566832048473 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1566832048473 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 29 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 29 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1566832048478 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1566832048478 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1566832048478 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1566832048478 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1566832048478 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1566832048478 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 47 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1566832048478 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1566832048478 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1566832048478 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1566832048478 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1566832048528 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1566832050834 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1566832050981 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1566832051003 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1566832051485 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1566832051486 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1566832052122 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X9_Y19 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19" { } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} 0 10 10 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1566832053532 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1566832053532 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1566832053737 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1566832053737 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1566832053737 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1566832053737 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.24 " "Total time spent on timing analysis during the Fitter is 0.24 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1566832053753 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1566832053838 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1566832054487 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1566832054560 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1566832055282 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1566832056057 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_7483.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_7483.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1566832058285 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566832058681 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 26 23:07:38 2019 " "Processing ended: Mon Aug 26 23:07:38 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566832058681 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566832058681 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566832058681 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566832058681 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1566832064806 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1566832064809 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 26 23:07:44 2019 " "Processing started: Mon Aug 26 23:07:44 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1566832064809 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1566832064809 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1566832064810 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1566832066787 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1566832066844 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566832067532 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 26 23:07:47 2019 " "Processing ended: Mon Aug 26 23:07:47 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566832067532 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566832067532 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566832067532 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1566832067532 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1566832067749 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1566832072975 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1566832072978 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 26 23:07:52 2019 " "Processing started: Mon Aug 26 23:07:52 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1566832072978 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1566832072978 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta BCD_adder_7483 -c BCD_adder_7483 " "Command: quartus_sta BCD_adder_7483 -c BCD_adder_7483" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1566832072979 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1566832073071 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1566832073392 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1566832073540 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1566832073540 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_adder_7483.sdc " "Synopsys Design Constraints File file not found: 'BCD_adder_7483.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1566832073935 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1566832073936 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1566832073938 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1566832073939 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1566832073940 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1566832073940 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1566832073942 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1566832073956 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1566832073958 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832073960 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832073967 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832073976 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832073978 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832073980 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832073982 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1566832073999 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1566832074067 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1566832075268 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1566832075309 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1566832075310 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1566832075310 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1566832075311 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832075311 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832075315 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832075317 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832075319 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832075325 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832075327 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1566832075339 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1566832075532 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1566832075532 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1566832075533 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1566832075533 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832075536 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832075539 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832075541 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832075544 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1566832075546 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1566832075807 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1566832075808 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "369 " "Peak virtual memory: 369 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566832075867 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 26 23:07:55 2019 " "Processing ended: Mon Aug 26 23:07:55 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566832075867 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566832075867 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566832075867 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1566832075867 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1566832082220 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1566832082224 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 26 23:08:01 2019 " "Processing started: Mon Aug 26 23:08:01 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1566832082224 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1566832082224 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1566832082225 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_6_1200mv_85c_slow.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_6_1200mv_85c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832083110 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_6_1200mv_0c_slow.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_6_1200mv_0c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832083162 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_min_1200mv_0c_fast.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_min_1200mv_0c_fast.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832083214 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483.vho /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483.vho in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832083267 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_6_1200mv_85c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_6_1200mv_85c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832083323 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_6_1200mv_0c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_6_1200mv_0c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832083380 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_min_1200mv_0c_vhd_fast.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_min_1200mv_0c_vhd_fast.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832083429 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_adder_7483_vhd.sdo /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/ simulation " "Generated file BCD_adder_7483_vhd.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1566832083479 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566832083581 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 26 23:08:03 2019 " "Processing ended: Mon Aug 26 23:08:03 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566832083581 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566832083581 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566832083581 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1566832083581 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 12 s " "Quartus II Full Compilation was successful. 0 errors, 12 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1566832083770 ""} diff --git a/CH5/CH5-3/hc_output/BCD_adder_7483.names_drv_tbl b/CH5/CH5-3/hc_output/BCD_adder_7483.names_drv_tbl new file mode 100644 index 00000000..25810508 --- /dev/null +++ b/CH5/CH5-3/hc_output/BCD_adder_7483.names_drv_tbl @@ -0,0 +1,7142 @@ +Source Name Derived Name +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_LOADEN_OUT_AB_n27 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_A_n28 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n29 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_B_n30 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_fref_n31 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_en_dskw_qd_bot_ch2_n32 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n33 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_D_n34 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_A_n35 +_4iomodule_h8_8 _4iomodule_h8_8~_INPUT_BUF_n36 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_C_n37 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n38 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_t_n39 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n40 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALP_R_n41 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_A_n42 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n43 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_t_n44 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n45 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n46 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_B_n47 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_A_n48 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALP_R_n49 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n50 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_LOADEN_OUT_CD_n51 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_align_det_sync_n52 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n53 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n54 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_iqtxrxclk_t_n55 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n56 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n57 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_LOADEN_OUT_AB_n58 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_cg_comp_rd_d_out_n59 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_INPUT_BUF_n60 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n61 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_LOADEN_OUT_AB_n62 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_B_n63 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_C_n64 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_INPUT_BUF_n65 +_4iomodule_c520_20 _4iomodule_c520_20~_BSDOUT_n66 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_D_n67 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n68 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_A_n69 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n70 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALP_L_n71 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_cg_comp_wr_out_n72 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_LOADEN_OUT_CD_n73 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_C_n74 +_4iomodule_c57_7 _4iomodule_c57_7~_BSDOUT_n75 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n76 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n77 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_A_n78 +_4iomodule_c516_16 _4iomodule_c516_16~_BSDOUT_n79 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_DPA_C_n80 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_A_n81 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n82 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_INPUT_BUF_n83 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n84 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n85 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch1_n86 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n87 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n88 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_pma_reserved_out_n89 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch1_n90 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n91 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n92 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_C_n93 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n94 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_DPA_A_n95 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n96 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_D_n97 +_4iomodule_c511_11 _4iomodule_c511_11~_INPUT_BUF_n98 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_align_det_sync_n99 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_INPUT_BUF_n100 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_D_n101 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n102 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n103 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_C_n104 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_D_n105 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_detect_valid_n106 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_tx_data_ts_bot_ch2_n107 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n108 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n109 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_pma_reserved_out_n110 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_FCLK_OUT_CD_n111 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n112 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n113 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n114 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n115 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQS_2X_CLK_R_n116 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n117 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALN_R_n118 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALP_R_n119 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch1_n120 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_rx_data_rs_bot_ch2_n121 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_FCLK_OUT_CD_n122 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_found_n123 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n124 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_fref_n125 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n126 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_DQS_IN_C_n127 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_C_n128 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n129 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch1_n130 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_align_status_sync_n131 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_rx_data_rs_bot_ch2_n132 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_FCLK_OUT_CD_n133 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_DPA_D_n134 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n135 +_4iomodule_c558_58 _4iomodule_c558_58~_INPUT_BUF_n136 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_FCLK_OUT_AB_n137 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n138 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQS1X_CLK_R_n139 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n140 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch1_n141 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_tx_data_ts_bot_ch2_n142 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n143 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n144 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_A_n145 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_FCLK_OUT_AB_n146 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n147 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQS1X_CLK_R_n148 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_DPA_D_n149 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_tx_data_ts_bot_ch2_n150 +_4iomodule_c558_58 _4iomodule_c558_58~_INPUT_BUF_n151 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n152 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_A_n153 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_L_OUT_CLK_n154 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_A_n155 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_DPA_D_n156 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_sigdet_n157 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n158 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n159 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n160 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rxpll_lock_n161 +_ir_lvl_top4_4 _ir_lvl_top4_4~_DQS_2X_CLK_R_n162 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n163 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_R_n164 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch0_n165 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n166 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n167 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_A_n168 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_A_n169 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_hclk_pcs_n170 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_LOADEN_OUT_CD_n171 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n172 +_ir_lvl_top4_4 _ir_lvl_top4_4~_DQS1X_CLK_R_n173 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n174 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n175 +_4iomodule_c558_58 _4iomodule_c558_58~_INPUT_BUF_n176 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_FCLK_OUT_CD_n177 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_reset_pc_ptrs_out_chnl_up_n178 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_A_n179 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_A_n180 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_pcie_sw_done_n181 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_FCLK_OUT_CD_n182 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n183 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_LOADEN_OUT_CD_n184 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n185 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n186 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n187 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_DQS_IN_C_n188 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_A_n189 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_clklow_n190 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_C_n191 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n192 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n193 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_LOADEN_OUT_CD_n194 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_DPA_A_n195 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_L_OUT_CLK_n196 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_config_sel_out_chnl_up_n197 +_4iomodule_h6_6 _4iomodule_h6_6~_BSDOUT_n198 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n199 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n200 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_b50_buf_out_n201 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_LOADEN_OUT_CD_n202 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_LOADEN_OUT_AB_n203 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n204 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_b50_buf_out_n205 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n206 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_D_n207 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_LOADEN_OUT_AB_n208 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_pma_reserved_out_n209 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n210 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_LOADEN_OUT_AB_n211 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_pfdmode_lock_n212 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_ATB1_FTRES_BIDIR_OUT_n213 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n214 +_ioreg16_h1_1 _ioreg16_h1_1~_REGSCANOUT_A_n215 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_LOADEN_OUT_CD_n216 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_fifo_select_out_chnl_up_n217 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n218 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_L_OUT_CLK_n219 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_ATB0_FTRES_BIDIR_OUT_n220 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n221 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_LOADEN_OUT_CD_n222 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n223 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_tx_clk_n224 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_A_n225 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_C_n226 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n227 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n228 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_pma_reserved_out_n229 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_write_n230 +_4iomodule_c511_11 _4iomodule_c511_11~_INPUT_BUF_n231 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_A_n232 +_4iomodule_c511_11 _4iomodule_c511_11~_INPUT_BUF_n233 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n234 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n235 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_rx_clk_out_n236 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_fifo_select_out_chnl_up_n237 +_4iomodule_c529_29 _4iomodule_c529_29~_BSDOUT_n238 +_ioreg16_c59_9 _ioreg16_c59_9~_REGSCANOUT_A_n239 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_ATB0_FTRES_BIDIR_OUT_n240 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_block_select_n241 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n242 +_4iomodule_c511_11 _4iomodule_c511_11~_INPUT_BUF_n243 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_C_n244 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_rxclkslip_n245 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n246 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_pma_reserved_out_n247 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_C_n248 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n249 +_4iomodule_c540_40 _4iomodule_c540_40~_INPUT_BUF_n250 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n251 +_ir_lvl_top4_4 _ir_lvl_top4_4~_DQS1X_CLK_R_n252 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_INPUT_BUF_n253 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_C_n254 +_4iomodule_c540_40 _4iomodule_c540_40~_INPUT_BUF_n255 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n256 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_D_n257 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n258 +_ir_lvl_top4_4 _ir_lvl_top4_4~_DQ_CLK_R_n259 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_pcie_sw_done_n260 +_4iomodule_c526_26 _4iomodule_c526_26~_BSDOUT_n261 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALN_R_n262 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n263 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_LOADEN_OUT_AB_n264 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_C_n265 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_fref_n266 +_ir_lvl_top4_4 _ir_lvl_top4_4~_DQS1X_CLK_R_n267 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_pfdmode_lock_n268 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n269 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALN_R_n270 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_cg_comp_rd_d_out_n271 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_D_n272 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n273 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_C_n274 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_fref_n275 +_4iomodule_c548_48 _4iomodule_c548_48~_INPUT_BUF_n276 +_4iomodule_c522_22 _4iomodule_c522_22~_BSDOUT_n277 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_en_dskw_rd_ptrs_top_ch1_n278 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n279 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_L_OUT_CLK_n280 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_INPUT_BUF_n281 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_ATB1_FTRES_BIDIR_OUT_n282 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_hclk_pcs_n283 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_clklow_n284 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_L_OUT_CLK_n285 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_INPUT_BUF_n286 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n287 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_INPUT_BUF_n288 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_A_n289 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_FCLK_OUT_AB_n290 +_4iomodule_c512_12 _4iomodule_c512_12~_BSDOUT_n291 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n292 +_ir_lvl_top6_6 _ir_lvl_top6_6~_PHYCT_TO_LVDS_FB_OUTR_n293 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n294 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_L_OUT_CLK_n295 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_INPUT_BUF_n296 +_ioreg16_c59_9 _ioreg16_c59_9~_REGSCANOUT_D_n297 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_FCLK_OUT_AB_n298 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_A_n299 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_D_n300 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n301 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_D_n302 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_DPA_A_n303 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_tx_ctl_ts_bot_ch2_n304 +_ioreg16_c52_2 _ioreg16_c52_2~_REGSCANOUT_C_n305 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_clk_out_n306 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_D_n307 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_DPA_A_n308 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_C_n309 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_D_n310 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_rx_wr_enable_out_chnl_up_n311 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n312 +_4iomodule_h24_24 _4iomodule_h24_24~_INPUT_BUF_n313 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_A_n314 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_SHORT_R_IN_CLK_n315 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n316 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_SHORT_R_IN_CLK_n317 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n318 +_ioreg16_c511_11 _ioreg16_c511_11~_REGSCANOUT_B_n319 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_A_n320 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_tx_b50_buf_out_n321 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n322 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n323 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n324 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n325 +_4iomodule_c51_1 _4iomodule_c51_1~_INPUT_BUF_n326 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_A_n327 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_tx_b50_buf_out_n328 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n329 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_DPA_B_n330 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n331 +_4iomodule_c51_1 _4iomodule_c51_1~_INPUT_BUF_n332 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n333 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_elec_idle_n334 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_DPA_B_n335 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_A_n336 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_R_OUT_CLK_n337 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_rx_we_out_chnl_up_n338 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_R_OUT_CLK_n339 +_4iomodule_c553_53 _4iomodule_c553_53~_INPUT_BUF_n340 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n341 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_txdetectrx_n342 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n343 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_rx_we_out_chnl_up_n344 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n345 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n346 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_tx_b50_buf_out_n347 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_A_n348 +_4iomodule_c51_1 _4iomodule_c51_1~_INPUT_BUF_n349 +_ioreg16_c50_n9 _ioreg16_c50_n9~_REGSCANOUT_A_n350 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n351 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_R_n352 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n353 +_4iomodule_c58_8 _4iomodule_c58_8~_INPUT_BUF_n354 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_FCLK_OUT_AB_n355 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_speed_change_out_chnl_up_n356 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n357 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_R_OUT_CLK_n358 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n359 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_FCLK_OUT_CD_n360 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_D_n361 +_ir_lvl_top6_6 _ir_lvl_top6_6~_HR_CLK_R_n362 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_R_n363 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n364 +_4iomodule_h24_24 _4iomodule_h24_24~_INPUT_BUF_n365 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_tx_div_sync_out_chnl_up_n366 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_A_n367 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n368 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_D_n369 +_4iomodule_c51_1 _4iomodule_c51_1~_INPUT_BUF_n370 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n371 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n372 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_tx_div_sync_out_chnl_up_n373 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_R_OUT_CLK_n374 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n375 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_R_n376 +_4iomodule_c58_8 _4iomodule_c58_8~_INPUT_BUF_n377 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_D_n378 +_ioreg16_h1_1 _ioreg16_h1_1~_REGSCANOUT_D_n379 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n380 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_D_n381 +_ioreg16_c54_4 _ioreg16_c54_4~_REGSCANOUT_C_n382 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_C_n383 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n384 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_L_OUT_CLK_n385 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n386 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_OCTRZQP_n387 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_D_n388 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n389 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_A_n390 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_D_n391 +_pm_aux0_n6 _pm_aux0_n6~_TX_50_n392 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_tx_b50_buf_out_n393 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n394 +_ioreg16_c50_n9 _ioreg16_c50_n9~_REGSCANOUT_D_n395 +_ioreg16_c58_8 _ioreg16_c58_8~_REGSCANOUT_D_n396 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_A_n397 +_ioreg16_h4_4 _ioreg16_h4_4~_REGSCANOUT_B_n398 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n399 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_A_n400 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_R_n401 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n402 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_A_n403 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_DPA_B_n404 +_ioreg16_c58_8 _ioreg16_c58_8~_REGSCANOUT_A_n405 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n406 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n407 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n408 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_R_n409 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_A_n410 +_4iomodule_c553_53 _4iomodule_c553_53~_INPUT_BUF_n411 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_block_select_n412 +_pm_aux0_n6 _pm_aux0_n6~_TX_50_n413 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_SHORT_R_IN_CLK_n414 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_B_n415 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n416 +_4iomodule_c553_53 _4iomodule_c553_53~_INPUT_BUF_n417 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n418 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n419 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n420 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_R_OUT_CLK_n421 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n422 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n423 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n424 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reserved_out_n425 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_R_OUT_CLK_n426 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_R_n427 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n428 +_4iomodule_c553_53 _4iomodule_c553_53~_INPUT_BUF_n429 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n430 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_b50_buf_out_n431 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_R_n432 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_B_n433 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_FCLK_OUT_CD_n434 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n435 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch0_n436 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n437 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_R_n438 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_LOADEN_OUT_AB_n439 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n440 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_FCLK_OUT_CD_n441 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_pcie_sw_done_n442 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n443 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch0_n444 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALN_R_n445 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALP_R_n446 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_R_n447 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n448 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_D_n449 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_FCLK_OUT_CD_n450 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n451 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n452 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_rxclkslip_n453 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_INPUT_BUF_n454 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALN_R_n455 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALP_R_n456 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_found_n457 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALN_R_n458 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_detect_valid_n459 +_4iomodule_h13_13 _4iomodule_h13_13~_INPUT_BUF_n460 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n461 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_tx_data_ts_bot_ch2_n462 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_hclk_pcs_n463 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_INPUT_BUF_n464 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reserved_out_n465 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_tx_data_tc_n466 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_tx_data_ts_bot_ch2_n467 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n468 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n469 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_rxpma_rstb_n470 +_4iomodule_c549_49 _4iomodule_c549_49~_INPUT_BUF_n471 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_INPUT_BUF_n472 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n473 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_D_n474 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_tx_data_ts_bot_ch2_n475 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_INPUT_BUF_n476 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_rx_clk_out_n477 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n478 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n479 +_ioreg16_c58_8 _ioreg16_c58_8~_REGSCANOUT_C_n480 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_tx_b50_buf_out_n481 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALN_R_n482 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALP_R_n483 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n484 +_4iomodule6_6 _4iomodule6_6~_BSDOUT_n485 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_tx_b50_buf_out_n486 +_pm_aux0_n6 _pm_aux0_n6~_RX_50_n487 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n488 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n489 +_pm_aux0_n6 _pm_aux0_n6~_TX_50_n490 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_clk_n491 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_LOADEN_OUT_AB_n492 +_pm_aux0_n6 _pm_aux0_n6~_RX_50_n493 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_b50_buf_out_n494 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_D_n495 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n496 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALN_L_n497 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n498 +_pm_aux0_n6 _pm_aux0_n6~_RX_50_n499 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n500 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_b50_buf_out_n501 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_D_n502 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n503 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_A_n504 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALN_L_n505 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_D_n506 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALN_L_n507 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_D_n508 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n509 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n510 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_DPA_B_n511 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_FCLK_OUT_AB_n512 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_D_n513 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_A_n514 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_D_n515 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALN_L_n516 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n517 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n518 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_ibp50u_bgrx_n519 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_A_n520 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n521 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n522 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALN_L_n523 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reg_addr_n524 +_pm_aux0_n6 _pm_aux0_n6~_RX_50_n525 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_b50_buf_out_n526 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_FCLK_OUT_CD_n527 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_FCLK_OUT_AB_n528 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_D_n529 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n530 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALN_L_n531 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n532 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reserved_out_n533 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n534 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_FCLK_OUT_CD_n535 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_b50_buf_out_n536 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n537 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n538 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_byte_en_n539 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n540 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_DPA_A_n541 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_D_n542 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reg_addr_n543 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_FCLK_OUT_AB_n544 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALP_R_n545 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n546 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n547 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_dec_data_n548 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_DPA_A_n549 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_DPA_C_n550 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n551 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n552 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_dec_data_n553 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALP_R_n554 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n555 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n556 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_b50_buf_out_n557 +_pm_aux0_n6 _pm_aux0_n6~_TX_50_n558 +_ir_lvl_top2_2 _ir_lvl_top2_2~_PHYCT_TO_LVDS_FB_OUTL_n559 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_FCLK_OUT_AB_n560 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_byte_en_n561 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALN_R_n562 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_A_n563 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n564 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n565 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n566 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_dec_data_n567 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_DPA_C_n568 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_LOADEN_OUT_AB_n569 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reg_addr_n570 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n571 +_ir_lvl_top2_2 _ir_lvl_top2_2~_PHYCT_TO_LVDS_FB_OUTL_n572 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_rx_we_out_chnl_down_n573 +_4iomodule_h15_15 _4iomodule_h15_15~_BUF_IOREG_n574 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reg_addr_n575 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n576 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n577 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_rx_wr_enable_out_chnl_down_n578 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n579 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_cpulse_xn_up_out_n580 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n581 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALP_L_n582 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n583 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n584 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reg_addr_n585 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_C_n586 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_reset_ppm_cntrs_out_chnl_down_n587 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n588 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_FCLK_OUT_AB_n589 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALP_L_n590 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reg_addr_n591 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n592 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_C_n593 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_LOADEN_OUT_AB_n594 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_C_n595 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALN_L_n596 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALP_L_n597 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_FCLK_OUT_AB_n598 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n599 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_FCLK_OUT_CD_n600 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_A_n601 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_LOADEN_OUT_AB_n602 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n603 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_A_n604 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_rx_rd_enable_out_chnl_down_n605 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_C_n606 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reg_addr_n607 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_LOADEN_OUT_AB_n608 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_C_n609 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n610 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reg_addr_n611 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_FCLK_OUT_CD_n612 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_rx_we_out_chnl_down_n613 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_fbclk_ffpll_n614 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_C_n615 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n616 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n617 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ffpll_ref_iqclk_t_n618 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n619 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n620 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_C_n621 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n622 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reg_addr_n623 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_C_n624 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n625 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n626 +_4iomodule_h11_11 _4iomodule_h11_11~_INPUT_BUF_n627 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_A_n628 +_pm_aux0_n6 _pm_aux0_n6~_RX_50_n629 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_dprio_scan_mode_n_n630 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n631 +_4iomodule_h11_11 _4iomodule_h11_11~_INPUT_BUF_n632 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_rx_div_sync_out_chnl_down_n633 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_DPA_A_n634 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_rx_div_sync_out_chnl_down_n635 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_DPA_A_n636 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reg_addr_n637 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_FCLK_OUT_CD_n638 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_FCLK_OUT_AB_n639 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_C_n640 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_FCLK_OUT_CD_n641 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_DPA_A_n642 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n643 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_FCLK_OUT_AB_n644 +_4iomodule_c55_5 _4iomodule_c55_5~_BSDOUT_n645 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rxpll_lock_n646 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n647 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALN_R_n648 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_DPA_D_n649 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_A_n650 +_4iomodule_c536_36 _4iomodule_c536_36~_INPUT_BUF_n651 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_FCLK_OUT_AB_n652 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_C_n653 +_4iomodule_c510_10 _4iomodule_c510_10~_BSDOUT_n654 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_sigdet_n655 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n656 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_A_n657 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_L_n658 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_ibp50u_bgrx_n659 +_4iomodule_h15_15 _4iomodule_h15_15~_IOBUF_DPA_n660 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_C_n661 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n662 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BSDOUT_n663 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n664 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n665 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_L_n666 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n667 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_C_n668 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_tx_b50_buf_out_n669 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_FCLK_OUT_AB_n670 +_4iomodule_c537_37 _4iomodule_c537_37~_BSDOUT_n671 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n672 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_DPA_D_n673 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_L_n674 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n675 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n676 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALP_L_n677 +_ioreg16_c59_9 _ioreg16_c59_9~_REGSCANOUT_C_n678 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n679 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n680 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n681 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n682 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_tx_b50_buf_out_n683 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_D_n684 +_4iomodule_h10_10 _4iomodule_h10_10~_BSDOUT_n685 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n686 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_L_n687 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_C_n688 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n689 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n690 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n691 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n692 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_A_n693 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_L_n694 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n695 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALP_L_n696 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n697 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n698 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_FCLK_OUT_AB_n699 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_D_n700 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n701 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_DPA_D_n702 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n703 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n704 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n705 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_C_n706 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n707 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n708 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_LOADEN_OUT_CD_n709 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_DPA_D_n710 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n711 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALP_L_n712 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n713 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n714 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_rd_enable_sync_n715 +_4iomodule_h14_14 _4iomodule_h14_14~_IOBUF_DPA_n716 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n717 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_FCLK_OUT_AB_n718 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n719 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n720 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALN_L_n721 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_rd_align_n722 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_C_n723 +_4iomodule_h25_25 _4iomodule_h25_25~_IOBUF_DPA_n724 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n725 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_B_n726 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n727 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n728 +_4iomodule_c536_36 _4iomodule_c536_36~_INPUT_BUF_n729 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_rx_data_n730 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n731 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n732 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_LOADEN_OUT_CD_n733 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n734 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_latency_comp_out_n735 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALP_L_n736 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n737 +_ir_lvl_top4_4 _ir_lvl_top4_4~_DQS1X_CLK_R_n738 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n739 +_4iomodule_h12_12 _4iomodule_h12_12~_INPUT_BUF_n740 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n741 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_D_n742 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n743 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rxpll_lock_n744 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n745 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALP_L_n746 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n747 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_rx_we_out_chnl_up_n748 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n749 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n750 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_FCLK_OUT_AB_n751 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n752 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_sigdet_n753 +_ir_lvl_top7_7 _ir_lvl_top7_7~_CSRDOUT_n754 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_D_n755 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_speed_change_out_chnl_up_n756 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n757 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_A_n758 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n759 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n760 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_detect_valid_n761 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_C_n762 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n763 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_running_disp_n764 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_D_n765 +_4iomodule_h1_1 _4iomodule_h1_1~_BUF_IOREG_n766 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_FCLK_OUT_CD_n767 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_C_n768 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_found_n769 +_4iomodule_h21_21 _4iomodule_h21_21~_BSDOUT_n770 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_D_n771 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALN_L_n772 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALN_R_n773 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n774 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n775 +_4iomodule_h12_12 _4iomodule_h12_12~_INPUT_BUF_n776 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n777 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_DPA_C_n778 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_L_n779 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_D_n780 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALN_R_n781 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n782 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n783 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reg_addr_n784 +_4iomodule_h12_12 _4iomodule_h12_12~_INPUT_BUF_n785 +_4iomodule_c536_36 _4iomodule_c536_36~_INPUT_BUF_n786 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_DPA_C_n787 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_tx_clk_n788 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_A_n789 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALN_L_n790 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_FCLK_OUT_CD_n791 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n792 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_clk_n793 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reg_addr_n794 +_4iomodule_c517_17 _4iomodule_c517_17~_INPUT_BUF_n795 +_4iomodule_h12_12 _4iomodule_h12_12~_INPUT_BUF_n796 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_A_n797 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n798 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALN_R_n799 +_hmcphy_int_t0_n2 _hmcphy_int_t0_n2~_hmc_csr_dout_n800 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n801 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reg_addr_n802 +_4iomodule_c517_17 _4iomodule_c517_17~_INPUT_BUF_n803 +_4iomodule_h1_1 _4iomodule_h1_1~_IOBUF_DPA_n804 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n805 +_ioreg16_c514_14 _ioreg16_c514_14~_CSR_DOUT_2_n806 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_b50_buf_out_n807 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_FCLK_OUT_CD_n808 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n809 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n810 +_ioreg16_c514_14 _ioreg16_c514_14~_CSRDATAOUT_D_n811 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALN_L_n812 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_b50_buf_out_n813 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n814 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n815 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n816 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n817 +_ioreg16_c514_14 _ioreg16_c514_14~_CSRDATAOUT_C_n818 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_elec_idle_n819 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n820 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n821 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n822 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n823 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n824 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n825 +_4iomodule_c539_39 _4iomodule_c539_39~_BSDOUT_n826 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n827 +_ioreg16_c510_10 _ioreg16_c510_10~_CSRDATAOUT_D_n828 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n829 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n830 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n831 +_4iomodule_c52_2 _4iomodule_c52_2~_BSDOUT_n832 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n833 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n834 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n835 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_D_n836 +_ioreg16_c510_10 _ioreg16_c510_10~_CSRDATAOUT_C_n837 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_rx_we_out_chnl_up_n838 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n839 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n840 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n841 +_4iomodule_c545_45 _4iomodule_c545_45~_INPUT_BUF_n842 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n843 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_FCLK_OUT_CD_n844 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n845 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n846 +_4iomodule_h23_23 _4iomodule_h23_23~_INPUT_BUF_n847 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n848 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_rx_rd_enable_out_chnl_up_n849 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_rd_align_n850 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n851 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n852 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_rx_wr_enable_out_chnl_up_n853 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n854 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n855 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_A_n856 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n857 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n858 +_4iomodule_c517_17 _4iomodule_c517_17~_INPUT_BUF_n859 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_A_n860 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_D_n861 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n862 +_4iomodule_c517_17 _4iomodule_c517_17~_INPUT_BUF_n863 +_4iomodule_c538_38 _4iomodule_c538_38~_BSDOUT_n864 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_b50_buf_out_n865 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_A_n866 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n867 +_4iomodule_h20_20 _4iomodule_h20_20~_BSDOUT_n868 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_tx_b50_buf_out_n869 +_ioreg16_c514_14 _ioreg16_c514_14~_CSRDATAOUT_B_n870 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_D_n871 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_A_n872 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_A_n873 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_C_n874 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_D_n875 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n876 +_4iomodule_c545_45 _4iomodule_c545_45~_INPUT_BUF_n877 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reg_addr_n878 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n879 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_D_n880 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_rd_align_n881 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_C_n882 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_INPUT_BUF_n883 +_4iomodule_c512_12 _4iomodule_c512_12~_INPUT_BUF_n884 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n885 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_DPA_D_n886 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reserved_out_n887 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n888 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_D_n889 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_latency_comp_out_n890 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_INPUT_BUF_n891 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_C_n892 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_SHORT_R_IN_CLK_n893 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n894 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_fbclk_ffpll_n895 +_4iomodule_c522_22 _4iomodule_c522_22~_INPUT_BUF_n896 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_D_n897 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n898 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n899 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_speed_change_out_chnl_down_n900 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_sync_status_n901 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQS1X_CLK_R_n902 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_INPUT_BUF_n903 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_DPA_D_n904 +_4iomodule_c512_12 _4iomodule_c512_12~_INPUT_BUF_n905 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_SHORT_R_IN_CLK_n906 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_running_disp_n907 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_LOADEN_OUT_AB_n908 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_running_disp_n909 +_4iomodule15_15 _4iomodule15_15~_INPUT_BUF_n910 +_ioreg16_c513_13 _ioreg16_c513_13~_REGSCANOUT_B_n911 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_INPUT_BUF_n912 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_ctl_ts_top_ch1_n913 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_LOADEN_OUT_AB_n914 +_4iomodule15_15 _4iomodule15_15~_INPUT_BUF_n915 +_4iomodule_h20_20 _4iomodule_h20_20~_INPUT_BUF_n916 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_INPUT_BUF_n917 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_B_n918 +_4iomodule_c522_22 _4iomodule_c522_22~_INPUT_BUF_n919 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n920 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_B_n921 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_INPUT_BUF_n922 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_B_n923 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_DPA_B_n924 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_cpulse_xn_dn_out_n925 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n926 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_FCLK_OUT_AB_n927 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_dec_data_n928 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_A_n929 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_IOCSRDOUT_n930 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_B_n931 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_LOADEN_OUT_CD_n932 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n933 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_csrdout_n934 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_dec_data_n935 +_4iomodule_c57_7 _4iomodule_c57_7~_INPUT_BUF_n936 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n937 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_LOADEN_OUT_CD_n938 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_dec_data_n939 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_A_n940 +_4iomodule_c57_7 _4iomodule_c57_7~_INPUT_BUF_n941 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_DPA_D_n942 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n943 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n944 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_LOADEN_OUT_CD_n945 +_ioreg16_c59_9 _ioreg16_c59_9~_PHYCT_SHORT_R_IN_CLK_n946 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n947 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_DPA_C_n948 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_INPUT_BUF_n949 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_dec_data_n950 +_4iomodule15_15 _4iomodule15_15~_BSDOUT_n951 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n952 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_B_n953 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n954 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_clkb_seg_dn_out_n955 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n956 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_DPA_C_n957 +_4iomodule_c512_12 _4iomodule_c512_12~_INPUT_BUF_n958 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_B_n959 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_dec_data_n960 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_FCLK_OUT_CD_n961 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_SHORT_R_IN_CLK_n962 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_csr_dout_n963 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n964 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_B_n965 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_A_n966 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n967 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_rd_enable_sync_n968 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_B_n969 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_B_n970 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_A_n971 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n972 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_FCLK_OUT_AB_n973 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_rd_align_n974 +_4iomodule_c57_7 _4iomodule_c57_7~_INPUT_BUF_n975 +_4iomodule15_15 _4iomodule15_15~_INPUT_BUF_n976 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_DPA_A_n977 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n978 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_A_n979 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_B_n980 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n981 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_B_n982 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_A_n983 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n984 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_B_n985 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_LOADEN_OUT_AB_n986 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_dec_data_n987 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n988 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_dec_data_n989 +_4iomodule_c534_34 _4iomodule_c534_34~_BSDOUT_n990 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_LOADEN_OUT_AB_n991 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_dec_data_valid_n992 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_DPA_B_n993 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n994 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n995 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_FCLK_OUT_CD_n996 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_DPA_C_n997 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n998 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_B_n999 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALN_L_n1000 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_fifo_ovr_out_n1001 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n1002 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n1003 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALN_L_n1004 +_4iomodule_h1_1 _4iomodule_h1_1~_INPUT_BUF_n1005 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_dec_data_n1006 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n1007 +_4iomodule_h1_1 _4iomodule_h1_1~_INPUT_BUF_n1008 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_dec_data_n1009 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQ_CLK_R_n1010 +_4iomodule15_15 _4iomodule15_15~_INPUT_BUF_n1011 +_4iomodule_h2_2 _4iomodule_h2_2~_IOBUF_DPA_n1012 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_byte_en_n1013 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_insert_incomplete_out_n1014 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n1015 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_n1016 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_dec_data_n1017 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n1018 +_4iomodule_h3_3 _4iomodule_h3_3~_IOBUF_DPA_n1019 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_del_cond_met_out_n1020 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n1021 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_n1022 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_DPA_C_n1023 +_4iomodule_c556_56 _4iomodule_c556_56~_BSDOUT_n1024 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n1025 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_DPA_C_n1026 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_B_n1027 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_tx_div_sync_out_chnl_down_n1028 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_B_n1029 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_elec_idle_n1030 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_fifo_rd_out_comp_n1031 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n1032 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n1033 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_DPA_C_n1034 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n1035 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_B_n1036 +_4iomodule_c512_12 _4iomodule_c512_12~_INPUT_BUF_n1037 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_dec_data_n1038 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_C_n1039 +_4iomodule17_17 _4iomodule17_17~_IOBUF_DPA_n1040 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n1041 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_B_n1042 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_B_n1043 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n1044 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQS1X_CLK_R_n1045 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n1046 +_4iomodule_h20_20 _4iomodule_h20_20~_INPUT_BUF_n1047 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_txdetectrx_n1048 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_FCLK_OUT_AB_n1049 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_B_n1050 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n1051 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_B_n1052 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALP_L_n1053 +_ioreg16_h5_5 _ioreg16_h5_5~_CSRDATAOUT_B_n1054 +_4iomodule_h20_20 _4iomodule_h20_20~_INPUT_BUF_n1055 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_byte_en_n1056 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_FCLK_OUT_AB_n1057 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CORECLK_LO0_n1058 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_tx_div_sync_out_chnl_down_n1059 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALP_L_n1060 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n1061 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALP_L_n1062 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_write_n1063 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n1064 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n1065 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_tx_data_tc_n1066 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n1067 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_b50_buf_out_n1068 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALP_R_n1069 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n1070 +_ioreg16_c512_12 _ioreg16_c512_12~_PHYCT_SHORT_R_IN_CLK_n1071 +_ioreg16_h1_1 _ioreg16_h1_1~_CSRDATAOUT_C_n1072 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_tx_data_tc_n1073 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n1074 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALP_R_n1075 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALN_L_n1076 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_cg_comp_wr_out_n1077 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_tx_data_tc_n1078 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALN_L_n1079 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_b50_buf_out_n1080 +_ioreg16_h5_5 _ioreg16_h5_5~_CSRDATAOUT_C_n1081 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n1082 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n1083 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_tx_data_tc_n1084 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reg_addr_n1085 +_ioreg16_c511_11 _ioreg16_c511_11~_PHYCT_SHORT_R_IN_CLK_n1086 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n1087 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_b50_buf_out_n1088 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n1089 +_ioreg16_h1_1 _ioreg16_h1_1~_CSRDATAOUT_D_n1090 +_4iomodule_c555_55 _4iomodule_c555_55~_BSDOUT_n1091 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n1092 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALP_R_n1093 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n1094 +_ioreg16_c512_12 _ioreg16_c512_12~_PHYCT_SHORT_R_IN_CLK_n1095 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n1096 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n1097 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALP_R_n1098 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n1099 +_ioreg16_h0_n7 _ioreg16_h0_n7~_CSRDATAOUT_A_n1100 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n1101 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_SHORT_R_IN_CLK_n1102 +_ioreg16_c512_12 _ioreg16_c512_12~_PHYCT_SHORT_R_IN_CLK_n1103 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_ctl_rs_top_ch0_n1104 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n1105 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n1106 +_ioreg16_c511_11 _ioreg16_c511_11~_PHYCT_SHORT_R_IN_CLK_n1107 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_R_FB_OUT_CLK_n1108 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n1109 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n1110 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_SHORT_R_IN_CLK_n1111 +_ioreg16_c512_12 _ioreg16_c512_12~_PHYCT_SHORT_R_IN_CLK_n1112 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_L_OUT_CLK_n1113 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_C_n1114 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n1115 +_4iomodule_c533_33 _4iomodule_c533_33~_BSDOUT_n1116 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n1117 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n1118 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_C_n1119 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n1120 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n1121 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n1122 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_latency_comp_0_bot_ch2_n1123 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_C_n1124 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n1125 +_4iomodule2_2 _4iomodule2_2~_INPUT_BUF_n1126 +_pm_aux0_n6 _pm_aux0_n6~_TX_50_n1127 +_ioreg16_c511_11 _ioreg16_c511_11~_REGSCANOUT_C_n1128 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n1129 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_insert_incomplete_out_n1130 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALP_R_n1131 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n1132 +_ioreg16_c57_7 _ioreg16_c57_7~_REGSCANOUT_B_n1133 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n1134 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_fifo_rd_out_comp_n1135 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALP_R_n1136 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n1137 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_dec_data_n1138 +_ioreg16_c512_12 _ioreg16_c512_12~_PHYCT_SHORT_R_IN_CLK_n1139 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n1140 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n1141 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_fifo_ovr_out_n1142 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1143 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_EXTCLK_n1144 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n1145 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n1146 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n1147 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_n1148 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n1149 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1150 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_n1151 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_pma_reserved_out_n1152 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_tx_data_tc_n1153 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_n1154 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALP_R_n1155 +_4iomodule_h24_24 _4iomodule_h24_24~_INPUT_BUF_n1156 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1157 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALN_L_n1158 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n1159 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALP_R_n1160 +_4iomodule_h22_22 _4iomodule_h22_22~_BSDOUT_n1161 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n1162 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n1163 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n1164 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_rx_data_rs_bot_ch2_n1165 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_B_n1166 +_io_oct_serpar1_1 _io_oct_serpar1_1~_IOCSRDOUT_n1167 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n1168 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n1169 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n1170 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_B_n1171 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n1172 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch0_n1173 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_cg_comp_wr_out_n1174 +_ioreg16_c511_11 _ioreg16_c511_11~_CSRDATAOUT_D_n1175 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n1176 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n1177 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n1178 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n1179 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n1180 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_rx_data_rs_bot_ch2_n1181 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_C_n1182 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n1183 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n1184 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_R_FB_OUT_CLK_n1185 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_L_OUT_CLK_n1186 +_ioreg16_c512_12 _ioreg16_c512_12~_REGSCANOUT_D_n1187 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_n1188 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_hfclkn_x6_b_dn_out_n1189 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n1190 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTCALN_L_n1191 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_C_n1192 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch0_n1193 +_im_sysclk0_n17 _im_sysclk0_n17~_CSRDOUT_n1194 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_C_n1195 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_dec_data_n1196 +_ioreg16_c56_6 _ioreg16_c56_6~_REGSCANOUT_C_n1197 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reg_addr_n1198 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reg_addr_n1199 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_DPA_A_n1200 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n1201 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n1202 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch0_n1203 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_C_n1204 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reg_addr_n1205 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_dec_ctl_n1206 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n1207 +_ioreg16_c52_2 _ioreg16_c52_2~_REGSCANOUT_B_n1208 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n1209 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n1210 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n1211 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_dec_data_n1212 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_DPA_B_n1213 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_C_n1214 +_ioreg16_c512_12 _ioreg16_c512_12~_REGSCANOUT_A_n1215 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_B_n1216 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch0_n1217 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n1218 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_dec_data_n1219 +_4iomodule_c556_56 _4iomodule_c556_56~_BUF_IOREG_n1220 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reg_addr_n1221 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_C_n1222 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n1223 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_L_n1224 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n1225 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n1226 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_C_n1227 +_ioreg16_h2_2 _ioreg16_h2_2~_CSRDATAOUT_A_n1228 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n1229 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_C_n1230 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_CSRDOUT_n1231 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_L_OUT_CLK_n1232 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_ctl_rs_top_ch1_n1233 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_rx_data_rs_bot_ch2_n1234 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_L_n1235 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_CORECLK_RO0_n1236 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1237 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_L_OUT_CLK_n1238 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_C_n1239 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_C_n1240 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_C_n1241 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_DPA_B_n1242 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1243 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_write_n1244 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_cg_comp_wr_out_n1245 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_DPA_B_n1246 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_R_FB_OUT_CLK_n1247 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_C_n1248 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n1249 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n1250 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_txdetectrx_n1251 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_b50_buf_out_n1252 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rcvd_clk_out_top_n1253 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_dec_ctl_n1254 +_ioreg16_h1_1 _ioreg16_h1_1~_CSRDATAOUT_A_n1255 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_C_n1256 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_L_n1257 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n1258 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_b50_buf_out_n1259 +_ir_lvl_top6_6 _ir_lvl_top6_6~_PHYCT_TO_LVDS_FB_OUTR_n1260 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_C_n1261 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_C_n1262 +_ioreg16_c51_1 _ioreg16_c51_1~_DQS_IN_C_n1263 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n1264 +_ioreg16_h2_2 _ioreg16_h2_2~_CSRDATAOUT_D_n1265 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n1266 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_C_n1267 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n1268 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_L_n1269 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n1270 +_ioreg16_h2_2 _ioreg16_h2_2~_CSRDATAOUT_C_n1271 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_clk_n1272 +_ioreg16_h1_1 _ioreg16_h1_1~_CSRDATAOUT_B_n1273 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n1274 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n1275 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_L_OUT_CLK_n1276 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_B_n1277 +_ioreg16_h2_2 _ioreg16_h2_2~_CSRDATAOUT_B_n1278 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n1279 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_L_OUT_CLK_n1280 +_4iomodule2_2 _4iomodule2_2~_INPUT_BUF_n1281 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_SHORT_R_IN_CLK_n1282 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_B_n1283 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n1284 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n1285 +_ioreg16_c57_7 _ioreg16_c57_7~_REGSCANOUT_A_n1286 +_4iomodule2_2 _4iomodule2_2~_INPUT_BUF_n1287 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reg_addr_n1288 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_reset_ppm_cntrs_out_chnl_up_n1289 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALN_L_n1290 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_L_OUT_CLK_n1291 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n1292 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1293 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_SHORT_R_IN_CLK_n1294 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reg_addr_n1295 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_rx_rd_enable_out_chnl_up_n1296 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n1297 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1298 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1299 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_IOBUF_DPA_n1300 +_ioreg16_c58_8 _ioreg16_c58_8~_CSRDATAOUT_D_n1301 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n1302 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALN_L_n1303 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n1304 +_4iomodule1_1 _4iomodule1_1~_INPUT_BUF_n1305 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_rx_div_sync_out_chnl_up_n1306 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_SHORT_R_IN_CLK_n1307 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_A_n1308 +_4iomodule_c541_41 _4iomodule_c541_41~_IOBUF_DPA_n1309 +_4iomodule1_1 _4iomodule1_1~_INPUT_BUF_n1310 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_LOADEN_OUT_AB_n1311 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_A_n1312 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n1313 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n1314 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_B_n1315 +_4iomodule_c525_25 _4iomodule_c525_25~_IOBUF_DPA_n1316 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALN_L_n1317 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_LOADEN_OUT_CD_n1318 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n1319 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reserved_out_n1320 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_b50_buf_out_n1321 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n1322 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_B_n1323 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n1324 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_C_n1325 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_rx_div_sync_out_chnl_up_n1326 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n1327 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reserved_out_n1328 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_A_n1329 +_4iomodule_c546_46 _4iomodule_c546_46~_IOBUF_DPA_n1330 +_ioreg16_c57_7 _ioreg16_c57_7~_REGSCANOUT_D_n1331 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_L_OUT_CLK_n1332 +_4iomodule_c510_10 _4iomodule_c510_10~_INPUT_BUF_n1333 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n1334 +_ioreg16_c50_n9 _ioreg16_c50_n9~_REGSCANOUT_B_n1335 +_4iomodule9_9 _4iomodule9_9~_BSDOUT_n1336 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n1337 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n1338 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_FCLK_OUT_CD_n1339 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_R_OUT_CLK_n1340 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_DPA_A_n1341 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_ser_shift_load_n1342 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_clk_n1343 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_LOADEN_OUT_AB_n1344 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_C_n1345 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_rxpma_rstb_n1346 +_4iomodule_c523_23 _4iomodule_c523_23~_IOBUF_DPA_n1347 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_SHORT_R_IN_CLK_n1348 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_C_n1349 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1350 +_4iomodule_c539_39 _4iomodule_c539_39~_INPUT_BUF_n1351 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_rxclkslip_n1352 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_LOADEN_OUT_CD_n1353 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_b50_buf_out_n1354 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_A_n1355 +_4iomodule_c557_57 _4iomodule_c557_57~_INPUT_BUF_n1356 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n1357 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_C_n1358 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_SHORT_R_IN_CLK_n1359 +_4iomodule_c510_10 _4iomodule_c510_10~_INPUT_BUF_n1360 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n1361 +_4iomodule_c545_45 _4iomodule_c545_45~_IOBUF_DPA_n1362 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_A_n1363 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n1364 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_C_n1365 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_rx_data_rs_bot_ch2_n1366 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_SHORT_R_IN_CLK_n1367 +_4iomodule1_1 _4iomodule1_1~_INPUT_BUF_n1368 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1369 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n1370 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_DPA_A_n1371 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n1372 +_4iomodule_c557_57 _4iomodule_c557_57~_INPUT_BUF_n1373 +_4iomodule_c539_39 _4iomodule_c539_39~_INPUT_BUF_n1374 +_4iomodule_c514_14 _4iomodule_c514_14~_IOBUF_DPA_n1375 +_ioreg16_c50_n9 _ioreg16_c50_n9~_CSRDATAOUT_A_n1376 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_C_n1377 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_C_n1378 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n1379 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_SHORT_R_IN_CLK_n1380 +_ioreg16_c50_n9 _ioreg16_c50_n9~_CSRDATAOUT_B_n1381 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1382 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_R_FB_OUT_CLK_n1383 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n1384 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_C_n1385 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_OCTRZQP_n1386 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_IOCSRDOUT_n1387 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n1388 +_4iomodule_c539_39 _4iomodule_c539_39~_INPUT_BUF_n1389 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n1390 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n1391 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQ_CLK_L_n1392 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n1393 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_rx_data_rs_bot_ch2_n1394 +_4iomodule_c539_39 _4iomodule_c539_39~_INPUT_BUF_n1395 +_ir_lvl_top2_2 _ir_lvl_top2_2~_CSRDOUT_n1396 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n1397 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n1398 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_B_n1399 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n1400 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQS1X_CLK_L_n1401 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_csrdout_mux_n1402 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1403 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_rx_data_rs_bot_ch2_n1404 +_ioreg16_c511_11 _ioreg16_c511_11~_CSRDATAOUT_A_n1405 +_4iomodule_c59_9 _4iomodule_c59_9~_IOBUF_DPA_n1406 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n1407 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_D_n1408 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n1409 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n1410 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n1411 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_DPA_B_n1412 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_D_n1413 +_ioreg16_c50_n9 _ioreg16_c50_n9~_CSRDATAOUT_C_n1414 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n1415 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n1416 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n1417 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n1418 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_C_n1419 +_ioreg16_c50_n9 _ioreg16_c50_n9~_CSRDATAOUT_D_n1420 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1421 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n1422 +_4iomodule_h24_24 _4iomodule_h24_24~_INPUT_BUF_n1423 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n1424 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_OCTRZQP_n1425 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reg_addr_n1426 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1427 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n1428 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n1429 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_byte_en_n1430 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n1431 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQS_2X_CLK_L_n1432 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reg_addr_n1433 +_ioreg16_h0_n7 _ioreg16_h0_n7~_CSRDATAOUT_B_n1434 +_ioreg16_c55_5 _ioreg16_c55_5~_REGSCANOUT_D_n1435 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n1436 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_dec_data_n1437 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n1438 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_byte_en_n1439 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reg_addr_n1440 +_ioreg16_h0_n7 _ioreg16_h0_n7~_CSRDATAOUT_C_n1441 +_ioreg16_c512_12 _ioreg16_c512_12~_PHYCT_SHORT_R_IN_CLK_n1442 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1443 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n1444 +_ioreg16_c57_7 _ioreg16_c57_7~_REGSCANOUT_C_n1445 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n1446 +_4iomodule_h5_5 _4iomodule_h5_5~_INPUT_BUF_n1447 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n1448 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_EXTCLK_n1449 +_4iomodule_h5_5 _4iomodule_h5_5~_INPUT_BUF_n1450 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reg_addr_n1451 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_C_n1452 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n1453 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_del_cond_met_out_n1454 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_rx_ctl_rs_bot_ch2_n1455 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_C_n1456 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reserved_out_n1457 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1458 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_dec_data_valid_n1459 +_ioreg16_c52_2 _ioreg16_c52_2~_OUT_STAGE_A1L_n1460 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_PHYCT_R_OUT_CLK_n1461 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQS1X_CLK_L_n1462 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n1463 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_B_n1464 +_ioreg16_h4_4 _ioreg16_h4_4~_CSRDATAOUT_C_n1465 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_D_n1466 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_C_n1467 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1468 +_4iomodule_h5_5 _4iomodule_h5_5~_INPUT_BUF_n1469 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQS1X_CLK_L_n1470 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_OCTRZQP_n1471 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch0_n1472 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_C_n1473 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reserved_out_n1474 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BUF_IOREG_n1475 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_C_n1476 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_B_n1477 +_ir_lvl_top6_6 _ir_lvl_top6_6~_DQS1X_CLK_L_n1478 +_ioreg16_h4_4 _ioreg16_h4_4~_CSRDATAOUT_A_n1479 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_OCTRZQP_n1480 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_C_n1481 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch0_n1482 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n1483 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reserved_out_n1484 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1485 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_B_n1486 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_LOADEN_OUT_AB_n1487 +_ioreg16_h4_4 _ioreg16_h4_4~_CSRDATAOUT_B_n1488 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_R_OUT_CLK_n1489 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n1490 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_L_OUT_CLK_n1491 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_DPA_B_n1492 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALN_R_n1493 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_R_OUT_CLK_n1494 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_C_n1495 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_LOADEN_OUT_AB_n1496 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_B_n1497 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1498 +_4iomodule_c520_20 _4iomodule_c520_20~_BUF_IOREG_n1499 +_4iomodule_c549_49 _4iomodule_c549_49~_INPUT_BUF_n1500 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n1501 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_R_OUT_CLK_n1502 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_A_n1503 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1504 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_B_n1505 +_4iomodule6_6 _4iomodule6_6~_INPUT_BUF_n1506 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1507 +_4iomodule6_6 _4iomodule6_6~_INPUT_BUF_n1508 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch1_n1509 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_R_OUT_CLK_n1510 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n1511 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n1512 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n1513 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_C_n1514 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_R_OUT_CLK_n1515 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_A_n1516 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n1517 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n1518 +_4iomodule6_6 _4iomodule6_6~_INPUT_BUF_n1519 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n1520 +_4iomodule1_1 _4iomodule1_1~_INPUT_BUF_n1521 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_A_n1522 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_B_n1523 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n1524 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_LOADEN_OUT_AB_n1525 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_B_n1526 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch0_n1527 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n1528 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_A_n1529 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_ATB0_BIDIR_OUT_n1530 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_A_n1531 +_4iomodule_h15_15 _4iomodule_h15_15~_INPUT_BUF_n1532 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n1533 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_LOADEN_OUT_AB_n1534 +_4iomodule_c527_27 _4iomodule_c527_27~_BSDOUT_n1535 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1536 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch0_n1537 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n1538 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n1539 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_A_n1540 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_atb1_n1541 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_dprio_clk_n1542 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_FCLK_OUT_CD_n1543 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch0_n1544 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_DPA_C_n1545 +_4iomodule_h1_1 _4iomodule_h1_1~_INPUT_BUF_n1546 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_ATB1_BIDIR_OUT_n1547 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_LOADEN_OUT_CD_n1548 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_LOADEN_OUT_AB_n1549 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch0_n1550 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQS1X_CLK_R_n1551 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n1552 +_4iomodule_c554_54 _4iomodule_c554_54~_INPUT_BUF_n1553 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n1554 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n1555 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_C_n1556 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n1557 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n1558 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_A_n1559 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n1560 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQ_CLK_R_n1561 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_DPA_C_n1562 +_4iomodule10_10 _4iomodule10_10~_INPUT_BUF_n1563 +_ioreg16_c51_1 _ioreg16_c51_1~_PHYCT_R_OUT_CLK_n1564 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_A_n1565 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_atb0_n1566 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n1567 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_B_n1568 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_A_n1569 +_ir_lvl_top8_8 _ir_lvl_top8_8~_HR_CLK_R_n1570 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n1571 +_4iomodule_h1_1 _4iomodule_h1_1~_INPUT_BUF_n1572 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_DPA_C_n1573 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n1574 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n1575 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_align_det_sync_n1576 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reg_addr_n1577 +_ioreg16_c54_4 _ioreg16_c54_4~_CSRDATAOUT_A_n1578 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n1579 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_DPA_C_n1580 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_cg_comp_rd_d_out_n1581 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n1582 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reg_addr_n1583 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_read_n1584 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_LOADEN_OUT_CD_n1585 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_LOADEN_OUT_CD_n1586 +_4iomodule_c551_51 _4iomodule_c551_51~_INPUT_BUF_n1587 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n1588 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n1589 +_4iomodule6_6 _4iomodule6_6~_INPUT_BUF_n1590 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reg_addr_n1591 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_cg_comp_rd_d_out_n1592 +_ioreg16_c54_4 _ioreg16_c54_4~_CSRDATAOUT_D_n1593 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n1594 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n1595 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n1596 +_4iomodule_c557_57 _4iomodule_c557_57~_INPUT_BUF_n1597 +_ioreg16_c513_13 _ioreg16_c513_13~_CSRDATAOUT_D_n1598 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_B_n1599 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQS1X_CLK_R_n1600 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_C_n1601 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_tx_rd_enable_out_chnl_down_n1602 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_DPA_D_n1603 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n1604 +_4iomodule_c557_57 _4iomodule_c557_57~_INPUT_BUF_n1605 +_ioreg16_c54_4 _ioreg16_c54_4~_CSRDATAOUT_B_n1606 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_B_n1607 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n1608 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n1609 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_B_n1610 +_4iomodule_h8_8 _4iomodule_h8_8~_BSDOUT_n1611 +_4iomodule_c521_21 _4iomodule_c521_21~_INPUT_BUF_n1612 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALN_L_n1613 +_4iomodule_c554_54 _4iomodule_c554_54~_INPUT_BUF_n1614 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n1615 +_ioreg16_c58_8 _ioreg16_c58_8~_CSRDATAOUT_A_n1616 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n1617 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_align_det_sync_n1618 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_FCLK_OUT_CD_n1619 +_4iomodule_c549_49 _4iomodule_c549_49~_INPUT_BUF_n1620 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_A_n1621 +_4iomodule_c551_51 _4iomodule_c551_51~_INPUT_BUF_n1622 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_B_n1623 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_A_n1624 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_tx_wr_enable_out_chnl_down_n1625 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch1_n1626 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_rx_clk_out_n1627 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1628 +_4iomodule_c521_21 _4iomodule_c521_21~_INPUT_BUF_n1629 +_4iomodule_h15_15 _4iomodule_h15_15~_INPUT_BUF_n1630 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1631 +_4iomodule_c551_51 _4iomodule_c551_51~_INPUT_BUF_n1632 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_DPA_C_n1633 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_DPA_D_n1634 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n1635 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n1636 +_ioreg16_c54_4 _ioreg16_c54_4~_CSRDATAOUT_C_n1637 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reserved_out_n1638 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_DPA_D_n1639 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_A_n1640 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch1_n1641 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1642 +_4iomodule_c521_21 _4iomodule_c521_21~_INPUT_BUF_n1643 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_clk_out_n1644 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_ppm_lock_n1645 +_4iomodule_c551_51 _4iomodule_c551_51~_INPUT_BUF_n1646 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_C_n1647 +_ioreg16_c58_8 _ioreg16_c58_8~_CSRDATAOUT_B_n1648 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_A_n1649 +_4iomodule_h4_4 _4iomodule_h4_4~_INPUT_BUF_n1650 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_clk_n1651 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1652 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n1653 +_4iomodule_h4_4 _4iomodule_h4_4~_BSDOUT_n1654 +_4iomodule5_5 _4iomodule5_5~_BSDOUT_n1655 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_B_n1656 +_4iomodule_c554_54 _4iomodule_c554_54~_INPUT_BUF_n1657 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1658 +_4iomodule_c521_21 _4iomodule_c521_21~_INPUT_BUF_n1659 +_4iomodule_h15_15 _4iomodule_h15_15~_INPUT_BUF_n1660 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n1661 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reg_addr_n1662 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1663 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_ser_shift_load_n1664 +_4iomodule_h15_15 _4iomodule_h15_15~_INPUT_BUF_n1665 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1666 +_4iomodule5_5 _4iomodule5_5~_INPUT_BUF_n1667 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_DPA_D_n1668 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n1669 +_4iomodule5_5 _4iomodule5_5~_INPUT_BUF_n1670 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_pcie_switch_n1671 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1672 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_A_n1673 +_ioreg16_c58_8 _ioreg16_c58_8~_CSRDATAOUT_C_n1674 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1675 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALN_L_n1676 +_4iomodule5_5 _4iomodule5_5~_INPUT_BUF_n1677 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n1678 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1679 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_A_n1680 +_ir_lvl_top3_3 _ir_lvl_top3_3~_CSRDOUT_n1681 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_A_n1682 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n1683 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1684 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1685 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_B_n1686 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_LOADEN_OUT_CD_n1687 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_current_coeff_n1688 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_nfrzdrv_n1689 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n1690 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALN_L_n1691 +_4iomodule_c558_58 _4iomodule_c558_58~_INPUT_BUF_n1692 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_DPA_C_n1693 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n1694 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTCALN_R_n1695 +_ioreg16_c513_13 _ioreg16_c513_13~_LVDS_LOADEN_OUT_AB_n1696 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALP_L_n1697 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALN_L_n1698 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_B_n1699 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_C_n1700 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_D_n1701 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLMOUT0_n1702 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_A_n1703 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_B_n1704 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_IC50UA_FT_BIDIR_OUT_n1705 +_4iomodule_c541_41 _4iomodule_c541_41~_BSDOUT_n1706 +_4iomodule_h25_25 _4iomodule_h25_25~_BUF_IOREG_n1707 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_SHORT_L_IN_CLK_n1708 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n1709 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQ_CLK_L_n1710 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_A_n1711 +_4iomodule_c557_57 _4iomodule_c557_57~_BSDOUT_n1712 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n1713 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQS1X_CLK_R_n1714 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n1715 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n1716 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_A_n1717 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_ltr_n1718 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_A_n1719 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALN_L_n1720 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQS1X_CLK_R_n1721 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_A_n1722 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n1723 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_SHORT_L_IN_CLK_n1724 +_4iomodule5_5 _4iomodule5_5~_INPUT_BUF_n1725 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n1726 +_4iomodule_c523_23 _4iomodule_c523_23~_BSDOUT_n1727 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_A_n1728 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALP_L_n1729 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_D_n1730 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_SHORT_L_IN_CLK_n1731 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQS_2X_CLK_R_n1732 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n1733 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n1734 +_4iomodule_c525_25 _4iomodule_c525_25~_BSDOUT_n1735 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_csr_dout_n1736 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_R_n1737 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_L_n1738 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_CSRDOUT_n1739 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQS_2X_CLK_L_n1740 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n1741 +_4iomodule_c551_51 _4iomodule_c551_51~_BSDOUT_n1742 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n1743 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQS1X_CLK_R_n1744 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_Q_n1745 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_A_n1746 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_LOADEN_OUT_CD_n1747 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_L_n1748 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_detect_valid_n1749 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_out_n1750 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_D_n1751 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_pcie_switch_n1752 +_ioreg16_h5_5 _ioreg16_h5_5~_PHYCT_SHORT_R_IN_CLK_n1753 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_L_n1754 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_found_n1755 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_t_a_n1756 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_D_n1757 +_4iomodule3_3 _4iomodule3_3~_INPUT_BUF_n1758 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n1759 +_ioreg16_c53_3 _ioreg16_c53_3~_DQS_IN_C_n1760 +_4iomodule_c535_35 _4iomodule_c535_35~_BSDOUT_n1761 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_n1762 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_mdio_dis_n1763 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n1764 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_L_n1765 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_out_n1766 +_4iomodule3_3 _4iomodule3_3~_INPUT_BUF_n1767 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_n1768 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n1769 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_A_n1770 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_out_n1771 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_nfrzdrv_n1772 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_A_n1773 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n1774 +_ioreg16_h1_1 _ioreg16_h1_1~_DQS_IN_C_n1775 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_tx_b50_buf_out_n1776 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQS1X_CLK_R_n1777 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_n1778 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n1779 +_4iomodule_c531_31 _4iomodule_c531_31~_INPUT_BUF_n1780 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_TC_BO_BIDIR_OUT_n1781 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_A_n1782 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_L_n1783 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n1784 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_QN_n1785 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_tx_b50_buf_out_n1786 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_n1787 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQS_2X_CLK_R_n1788 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_A_n1789 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n1790 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n1791 +_4iomodule_c531_31 _4iomodule_c531_31~_INPUT_BUF_n1792 +_4iomodule_c528_28 _4iomodule_c528_28~_BSDOUT_n1793 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_SHORT_L_IN_CLK_n1794 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n1795 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_n1796 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_A_n1797 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_out_n1798 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_TC_BO_BIDIR_OUT_n1799 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQS1X_CLK_L_n1800 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n1801 +_4iomodule_c547_47 _4iomodule_c547_47~_BSDOUT_n1802 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_B_n1803 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_n1804 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n1805 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n1806 +_ir_lvl_top1_1 _ir_lvl_top1_1~_HR_CLK_L_n1807 +_4iomodule_c531_31 _4iomodule_c531_31~_INPUT_BUF_n1808 +_4iomodule_c53_3 _4iomodule_c53_3~_BSDOUT_n1809 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_IOBUF_DPA_n1810 +_4iomodule_c530_30 _4iomodule_c530_30~_INPUT_BUF_n1811 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_D_n1812 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_IOBUF_DPA_n1813 +_4iomodule_h11_11 _4iomodule_h11_11~_BSDOUT_n1814 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_SHORT_L_IN_CLK_n1815 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n1816 +_4iomodule_c56_6 _4iomodule_c56_6~_BSDOUT_n1817 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_B_n1818 +_4iomodule_c546_46 _4iomodule_c546_46~_BSDOUT_n1819 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_IOBUF_DPA_n1820 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_SHORT_L_IN_CLK_n1821 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQS1X_CLK_L_n1822 +_4iomodule_c530_30 _4iomodule_c530_30~_INPUT_BUF_n1823 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n1824 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_B_n1825 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n1826 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_n1827 +_4iomodule_c531_31 _4iomodule_c531_31~_INPUT_BUF_n1828 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n1829 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_n1830 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n1831 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_pclk_xn_up_out_n1832 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_align_status_sync_n1833 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n1834 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n1835 +_4iomodule_c530_30 _4iomodule_c530_30~_INPUT_BUF_n1836 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_SHORT_L_IN_CLK_n1837 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_n1838 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_DPA_B_n1839 +_4iomodule_c58_8 _4iomodule_c58_8~_INPUT_BUF_n1840 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_n1841 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n1842 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_TC_BO_BIDIR_OUT_n1843 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_found_n1844 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n1845 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n1846 +_4iomodule_c530_30 _4iomodule_c530_30~_INPUT_BUF_n1847 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_dprio_clk_n1848 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_detect_valid_n1849 +_4iomodule_h11_11 _4iomodule_h11_11~_INPUT_BUF_n1850 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_clkb_seg_dn_out_n1851 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_LOADEN_OUT_AB_n1852 +_4iomodule_c528_28 _4iomodule_c528_28~_IOBUF_DPA_n1853 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n1854 +_4iomodule_c58_8 _4iomodule_c58_8~_INPUT_BUF_n1855 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_A_n1856 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n1857 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_LOADEN_OUT_CD_n1858 +_4iomodule_h11_11 _4iomodule_h11_11~_INPUT_BUF_n1859 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n1860 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_sigdet_n1861 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_A_n1862 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n1863 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_A_n1864 +_ioreg16_c55_5 _ioreg16_c55_5~_CSRDATAOUT_D_n1865 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_A_n1866 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_A_n1867 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_LOADEN_OUT_CD_n1868 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n1869 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n1870 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n1871 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ffpll_ref_iqclk_t_n1872 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_L_n1873 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n1874 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n1875 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_L_n1876 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n1877 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n1878 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_A_n1879 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n1880 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_LOADEN_OUT_AB_n1881 +_ir_lvl_top4_4 _ir_lvl_top4_4~_CSRDOUT_n1882 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n1883 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_tx_b50_buf_out_n1884 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_TC_BO_BIDIR_OUT_n1885 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n1886 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_CSRDATAOUT_D_n1887 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_LOADEN_OUT_CD_n1888 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n1889 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_L_n1890 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n1891 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n1892 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n1893 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_D_n1894 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n1895 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_D_n1896 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_FCLK_OUT_CD_n1897 +_4iomodule_c532_32 _4iomodule_c532_32~_INPUT_BUF_n1898 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_D_n1899 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_B_n1900 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n1901 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_dprio_rst_n_n1902 +_ioreg16_c514_14 _ioreg16_c514_14~_CSRDATAOUT_A_n1903 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_n1904 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_B_n1905 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_clk_seg_up_out_n1906 +_4iomodule_h6_6 _4iomodule_h6_6~_INPUT_BUF_n1907 +_4iomodule11_11 _4iomodule11_11~_INPUT_BUF_n1908 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n1909 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_clkb_seg_up_out_n1910 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALN_R_n1911 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n1912 +_4iomodule_h6_6 _4iomodule_h6_6~_INPUT_BUF_n1913 +_4iomodule11_11 _4iomodule11_11~_INPUT_BUF_n1914 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rxpll_lock_n1915 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_cpulse_x6_dn_out_n1916 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n1917 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_A_n1918 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_D_n1919 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_n1920 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n1921 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_CSRDATAOUT_C_n1922 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_clk_seg_dn_out_n1923 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_A_n1924 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_D_n1925 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_LOADEN_OUT_CD_n1926 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_cpulse_xn_up_out_n1927 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_CSRDATAOUT_B_n1928 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n1929 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_sigdet_n1930 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_D_n1931 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n1932 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_CSRDATAOUT_A_n1933 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_dprio_clk_n1934 +_ioreg16_c55_5 _ioreg16_c55_5~_REGSCANOUT_B_n1935 +_4iomodule_c550_50 _4iomodule_c550_50~_INPUT_BUF_n1936 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_L_n1937 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_A_n1938 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQS1X_CLK_R_n1939 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQS1X_CLK_R_n1940 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_DPACLK0_I_n1941 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n1942 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_D_n1943 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_SHORT_R_IN_CLK_n1944 +_ioreg16_c57_7 _ioreg16_c57_7~_CSRDATAOUT_B_n1945 +_4iomodule_h6_6 _4iomodule_h6_6~_INPUT_BUF_n1946 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_DPACLK0_I_n1947 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_csrdout_n1948 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_CLKIN_TC_BO_BIDIR_OUT_n1949 +_4iomodule11_11 _4iomodule11_11~_INPUT_BUF_n1950 +_ioreg16_c56_6 _ioreg16_c56_6~_DQS_IN_C_n1951 +_4iomodule_c523_23 _4iomodule_c523_23~_INPUT_BUF_n1952 +_4iomodule_c511_11 _4iomodule_c511_11~_IOBUF_DPA_n1953 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_DPA_A_n1954 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_IOCSR_DATAOUT_n1955 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_CLKIN_TC_BO_BIDIR_OUT_n1956 +_4iomodule11_11 _4iomodule11_11~_INPUT_BUF_n1957 +_4iomodule_c54_4 _4iomodule_c54_4~_INPUT_BUF_n1958 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n1959 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_CLKIN_TC_BO_BIDIR_OUT_n1960 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n1961 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_reset_pc_ptrs_out_chnl_down_n1962 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_D_n1963 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_D_n1964 +_4iomodule_c523_23 _4iomodule_c523_23~_INPUT_BUF_n1965 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_CLKIN_TC_BO_BIDIR_OUT_n1966 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_DPACLK0_I_n1967 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n1968 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_sigdet_n1969 +_4iomodule_c523_23 _4iomodule_c523_23~_INPUT_BUF_n1970 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n1971 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n1972 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n1973 +_4iomodule_c54_4 _4iomodule_c54_4~_INPUT_BUF_n1974 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_cpulse_xn_dn_out_n1975 +_4iomodule_h3_3 _4iomodule_h3_3~_BSDOUT_n1976 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n1977 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_LVDS_CLK0_n1978 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n1979 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n1980 +_ioreg16_c514_14 _ioreg16_c514_14~_REGSCANOUT_B_n1981 +_4iomodule_c549_49 _4iomodule_c549_49~_IOBUF_DPA_n1982 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_DPA_A_n1983 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_DPACLK0_I_n1984 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n1985 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_fbclk_ffpll_n1986 +_ioreg16_c55_5 _ioreg16_c55_5~_REGSCANOUT_A_n1987 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IC50UA_FT_BIDIR_OUT_n1988 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n1989 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n1990 +_4iomodule_c516_16 _4iomodule_c516_16~_INPUT_BUF_n1991 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_D_n1992 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n1993 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n1994 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_IT50UA_FT_BIDIR_OUT_n1995 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reg_addr_n1996 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n1997 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_D_n1998 +_4iomodule_c550_50 _4iomodule_c550_50~_INPUT_BUF_n1999 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n2000 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQS1X_CLK_R_n2001 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_L_n2002 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ffpll_ref_iqclk_t_n2003 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n2004 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_D_n2005 +_4iomodule_c558_58 _4iomodule_c558_58~_IOBUF_DPA_n2006 +_4iomodule_c550_50 _4iomodule_c550_50~_INPUT_BUF_n2007 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IT50UA_FT_BIDIR_OUT_n2008 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n2009 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_D_n2010 +_4iomodule_c516_16 _4iomodule_c516_16~_INPUT_BUF_n2011 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_L_n2012 +_4iomodule_c521_21 _4iomodule_c521_21~_IOBUF_DPA_n2013 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_A_n2014 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n2015 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_DPA_B_n2016 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQS1X_CLK_R_n2017 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_L_n2018 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n2019 +_4iomodule_c516_16 _4iomodule_c516_16~_INPUT_BUF_n2020 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQ_CLK_R_n2021 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n2022 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_A_n2023 +_4iomodule_h18_18 _4iomodule_h18_18~_BSDOUT_n2024 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQS_2X_CLK_R_n2025 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n2026 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n2027 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_D_n2028 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n2029 +_4iomodule_c529_29 _4iomodule_c529_29~_INPUT_BUF_n2030 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQS_2X_CLK_R_n2031 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQS1X_CLK_R_n2032 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQS1X_CLK_R_n2033 +_4iomodule_c536_36 _4iomodule_c536_36~_BUF_IOREG_n2034 +_4iomodule_c523_23 _4iomodule_c523_23~_INPUT_BUF_n2035 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_B_n2036 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n2037 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_rxpma_rstb_n2038 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_DPA_C_n2039 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n2040 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n2041 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n2042 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_ffpll_n2043 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_D_n2044 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_DPA_C_n2045 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_B_n2046 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_ser_shift_load_n2047 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n2048 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n2049 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n2050 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reg_addr_n2051 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_b_a_n2052 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_D_n2053 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_DPA_B_n2054 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_B_n2055 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n2056 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n2057 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n2058 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_DPA_A_n2059 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_B_n2060 +_ioreg16_c511_11 _ioreg16_c511_11~_CSRDATAOUT_B_n2061 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_t_a_n2062 +_4iomodule_c516_16 _4iomodule_c516_16~_INPUT_BUF_n2063 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reserved_out_n2064 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_t_a_n2065 +_4iomodule_c57_7 _4iomodule_c57_7~_INPUT_BUF_n2066 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_A_n2067 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_reserved_out_n2068 +_4iomodule_c550_50 _4iomodule_c550_50~_INPUT_BUF_n2069 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n2070 +_ioreg16_c511_11 _ioreg16_c511_11~_CSRDATAOUT_C_n2071 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_DPACLK0_I_n2072 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n2073 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n2074 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_rxclkslip_n2075 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_byte_en_n2076 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n2077 +_4iomodule_c54_4 _4iomodule_c54_4~_INPUT_BUF_n2078 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n2079 +_ir_lvl_top6_6 _ir_lvl_top6_6~_CSRDOUT_n2080 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_CSRDATAOUT_C_n2081 +_4iomodule_c54_4 _4iomodule_c54_4~_INPUT_BUF_n2082 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n2083 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_clk_out_n2084 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_A_n2085 +_4iomodule_c546_46 _4iomodule_c546_46~_INPUT_BUF_n2086 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_CSRDATAOUT_D_n2087 +_im_sysclk1_1 _im_sysclk1_1~_CSRDOUT_n2088 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n2089 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_CSRDATAOUT_D_n2090 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n2091 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n2092 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n2093 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n2094 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_DPA_D_n2095 +_4iomodule_c546_46 _4iomodule_c546_46~_INPUT_BUF_n2096 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n2097 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_rx_clk_out_n2098 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_DPA_D_n2099 +_ioreg16_c58_8 _ioreg16_c58_8~_CSR_DOUT_2_n2100 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_A_n2101 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n2102 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_CSRDATAOUT_A_n2103 +_4iomodule_c527_27 _4iomodule_c527_27~_BUF_IOREG_n2104 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_DPA_A_n2105 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_CSRDATAOUT_B_n2106 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLDOUT0_n2107 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n2108 +_4iomodule_c526_26 _4iomodule_c526_26~_INPUT_BUF_n2109 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_enscan_o_n2110 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_tx_data_tc_n2111 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n2112 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_tx_data_tc_n2113 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_ltr_n2114 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n2115 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n2116 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_R_OUT_CLK_n2117 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n2118 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_A_n2119 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_csren_o_n2120 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_C_n2121 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n2122 +_4iomodule_h8_8 _4iomodule_h8_8~_IOBUF_DPA_n2123 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n2124 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n2125 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_C_n2126 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_A_n2127 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_C_n2128 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n2129 +_4iomodule_c513_13 _4iomodule_c513_13~_IOBUF_DPA_n2130 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_C_n2131 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_enscan_o_n2132 +_pl_aux0_n21 _pl_aux0_n21~_ATBSEL_n2133 +_4iomodule_c544_44 _4iomodule_c544_44~_IOBUF_DPA_n2134 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n2135 +_pl_aux0_n21 _pl_aux0_n21~_VPCAS_IREF_FIXED_n2136 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_B_n2137 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_A_n2138 +_pl_aux0_n21 _pl_aux0_n21~_VP_IREF_PPOLY_n2139 +_4iomodule_c526_26 _4iomodule_c526_26~_INPUT_BUF_n2140 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_C_n2141 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_B_n2142 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n2143 +_pl_aux0_n21 _pl_aux0_n21~_VP_IREF_FIXED_n2144 +_4iomodule_c529_29 _4iomodule_c529_29~_INPUT_BUF_n2145 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_B_n2146 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n2147 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_A_n2148 +_ioreg16_h0_n7 _ioreg16_h0_n7~_CSRDATAOUT_D_n2149 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_D_n2150 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n2151 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_B_n2152 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_tx_data_tc_n2153 +_ioreg16_c56_6 _ioreg16_c56_6~_OUT_STAGE_A1R_n2154 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n2155 +_ioreg16_h3_3 _ioreg16_h3_3~_CSRDATAOUT_A_n2156 +_pl_aux0_n21 _pl_aux0_n21~_ATBSEL_n2157 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_B_n2158 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_tx_data_tc_n2159 +_4iomodule_c526_26 _4iomodule_c526_26~_INPUT_BUF_n2160 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_elec_idle_n2161 +_pl_aux0_n21 _pl_aux0_n21~_ATBSEL_n2162 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reg_addr_n2163 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_B_n2164 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_A_n2165 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_A_n2166 +_4iomodule7_7 _4iomodule7_7~_INPUT_BUF_n2167 +_pl_aux0_n21 _pl_aux0_n21~_ATBSEL_n2168 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reg_addr_n2169 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQS1X_CLK_L_n2170 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_B_n2171 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQS1X_CLK_L_n2172 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_A_n2173 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n2174 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_DPA_B_n2175 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n2176 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_tx_data_tc_n2177 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n2178 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_C_n2179 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n2180 +_ioreg16_h6_6 _ioreg16_h6_6~_CSRDATAOUT_B_n2181 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_SHORT_L_IN_CLK_n2182 +_4iomodule_c529_29 _4iomodule_c529_29~_INPUT_BUF_n2183 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_pcie_switch_n2184 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQS1X_CLK_L_n2185 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n2186 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_DPA_B_n2187 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_SHORT_L_IN_CLK_n2188 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_mdio_dis_n2189 +_ioreg16_h6_6 _ioreg16_h6_6~_CSRDATAOUT_C_n2190 +_4iomodule_c529_29 _4iomodule_c529_29~_INPUT_BUF_n2191 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n2192 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQS1X_CLK_L_n2193 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_B_n2194 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n2195 +_ioreg16_h6_6 _ioreg16_h6_6~_DQS_IN_C_n2196 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n2197 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_SHORT_L_IN_CLK_n2198 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n2199 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n2200 +_4iomodule_h17_17 _4iomodule_h17_17~_BSDOUT_n2201 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n2202 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reg_addr_n2203 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n2204 +_ioreg16_c55_5 _ioreg16_c55_5~_CSRDATAOUT_A_n2205 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n2206 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_fifo_select_out_chnl_up_n2207 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n2208 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n2209 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reg_addr_n2210 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n2211 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_fifo_select_out_chnl_up_n2212 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n2213 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_config_sel_out_chnl_up_n2214 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n2215 +_ioreg16_c55_5 _ioreg16_c55_5~_CSRDATAOUT_B_n2216 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reg_addr_n2217 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n2218 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n2219 +_ioreg16_c57_7 _ioreg16_c57_7~_CSRDATAOUT_D_n2220 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n2221 +_ioreg16_c55_5 _ioreg16_c55_5~_CSRDATAOUT_C_n2222 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reg_addr_n2223 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n2224 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_R_n2225 +_4iomodule_c526_26 _4iomodule_c526_26~_INPUT_BUF_n2226 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n2227 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_n2228 +_ioreg16_h4_4 _ioreg16_h4_4~_REGSCANOUT_A_n2229 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reserved_out_n2230 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n2231 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n2232 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_R_n2233 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_DPA_C_n2234 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n2235 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_n2236 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BSDOUT_n2237 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BUF_IOREG_n2238 +_ioreg16_c57_7 _ioreg16_c57_7~_CSRDATAOUT_A_n2239 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_C_n2240 +_ioreg16_h4_4 _ioreg16_h4_4~_REGSCANOUT_D_n2241 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_ZDB_IN_RO0_n2242 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reserved_out_n2243 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n2244 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_R_n2245 +_ioreg16_h1_1 _ioreg16_h1_1~_REGSCANOUT_C_n2246 +_ioreg16_c57_7 _ioreg16_c57_7~_CSRDATAOUT_C_n2247 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n2248 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n2249 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_R_n2250 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_A_n2251 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n2252 +_4iomodule_c52_2 _4iomodule_c52_2~_INPUT_BUF_n2253 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_R_n2254 +_4iomodule_c51_1 _4iomodule_c51_1~_BSDOUT_n2255 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n2256 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_LOADEN0_n2257 +_4iomodule_c559_59 _4iomodule_c559_59~_BUF_IOREG_n2258 +_4iomodule_c52_2 _4iomodule_c52_2~_INPUT_BUF_n2259 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_R_n2260 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n2261 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_DPA_B_n2262 +_4iomodule_c52_2 _4iomodule_c52_2~_INPUT_BUF_n2263 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n2264 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n2265 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n2266 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_load_csr_o_n2267 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n2268 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_load_csr_o_n2269 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_A_n2270 +_ioreg16_h6_6 _ioreg16_h6_6~_CSRDATAOUT_D_n2271 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n2272 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_byte_en_n2273 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2274 +_4iomodule_c552_52 _4iomodule_c552_52~_BSDOUT_n2275 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_n2276 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_D_n2277 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n2278 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_D_n2279 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_L_OUT_CLK_n2280 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_C_n2281 +_ioreg16_c50_n9 _ioreg16_c50_n9~_REGSCANOUT_C_n2282 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n2283 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_D_n2284 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_C_n2285 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_D_n2286 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rxpll_lock_n2287 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_QN_n2288 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n2289 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2290 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_DPA_B_n2291 +_4iomodule6_6 _4iomodule6_6~_IOBUF_DPA_n2292 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_found_n2293 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_CLKIN_TC_BO_BIDIR_OUT_n2294 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n2295 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_QN_n2296 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_detect_valid_n2297 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_LOADEN_OUT_AB_n2298 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_C_n2299 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_CLKIN_TC_BO_BIDIR_OUT_n2300 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_QN_n2301 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n2302 +_4iomodule_c52_2 _4iomodule_c52_2~_INPUT_BUF_n2303 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2304 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_DPA_D_n2305 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_LOADEN0_n2306 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_LOADEN_OUT_AB_n2307 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_CLKIN_TC_BO_BIDIR_OUT_n2308 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_DPA_B_n2309 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_DPA_D_n2310 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2311 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_Q_n2312 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_CLKIN_TC_BO_BIDIR_OUT_n2313 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n2314 +_4iomodule_c520_20 _4iomodule_c520_20~_INPUT_BUF_n2315 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n2316 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_D_n2317 +_4iomodule_c524_24 _4iomodule_c524_24~_BSDOUT_n2318 +_4iomodule_c520_20 _4iomodule_c520_20~_INPUT_BUF_n2319 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2320 +_4iomodule_h23_23 _4iomodule_h23_23~_BSDOUT_n2321 +_ioreg16_c59_9 _ioreg16_c59_9~_REGSCANOUT_B_n2322 +_4iomodule_c542_42 _4iomodule_c542_42~_BSDOUT_n2323 +_4iomodule_c518_18 _4iomodule_c518_18~_BSDOUT_n2324 +_4iomodule_c540_40 _4iomodule_c540_40~_IOBUF_DPA_n2325 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n2326 +_ioreg16_c52_2 _ioreg16_c52_2~_REGSCANOUT_D_n2327 +_4iomodule_c531_31 _4iomodule_c531_31~_BSDOUT_n2328 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n2329 +_ioreg16_h0_n7 _ioreg16_h0_n7~_DQS_IN_C_n2330 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_DPA_A_n2331 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_D_n2332 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n2333 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n2334 +_ioreg16_h5_5 _ioreg16_h5_5~_CSRDATAOUT_A_n2335 +_ioreg16_c52_2 _ioreg16_c52_2~_REGSCANOUT_A_n2336 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_DPA_C_n2337 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_byte_en_n2338 +_4iomodule_h20_20 _4iomodule_h20_20~_IOBUF_DPA_n2339 +_4iomodule_c530_30 _4iomodule_c530_30~_BSDOUT_n2340 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n2341 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_writedata_n2342 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_FCLK_OUT_AB_n2343 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_D_n2344 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rxpll_lock_n2345 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n2346 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2347 +_4iomodule_c58_8 _4iomodule_c58_8~_BSDOUT_n2348 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_FCLK_OUT_AB_n2349 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_D_n2350 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n2351 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n2352 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_FCLK_OUT_AB_n2353 +_pl_aux0_n21 _pl_aux0_n21~_VPCAS_IREF_PPOLY_n2354 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2355 +_ir_lvl_top7_7 _ir_lvl_top7_7~_HR_CLK_R_n2356 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_FCLK_OUT_AB_n2357 +_ir_lvl_top1_1 _ir_lvl_top1_1~_HR_CLK_R_n2358 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2359 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_D_n2360 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n2361 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_LVDS_CLK0_n2362 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_B_n2363 +_4iomodule_c520_20 _4iomodule_c520_20~_INPUT_BUF_n2364 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_dprio_rst_n_n2365 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_FCLK_OUT_CD_n2366 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n2367 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_dprio_scan_mode_n_n2368 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_n2369 +_4iomodule_c522_22 _4iomodule_c522_22~_INPUT_BUF_n2370 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_FCLK_OUT_CD_n2371 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_tx_b50_buf_out_n2372 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_n2373 +_4iomodule_c522_22 _4iomodule_c522_22~_INPUT_BUF_n2374 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_FCLK_OUT_AB_n2375 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_tx_data_tc_n2376 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_B_n2377 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_IOBUF_DPA_n2378 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_write_n2379 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_running_disp_n2380 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_C_n2381 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_D_n2382 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_B_n2383 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n2384 +_4iomodule_h8_8 _4iomodule_h8_8~_BUF_IOREG_n2385 +_4iomodule_c544_44 _4iomodule_c544_44~_BSDOUT_n2386 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_txdetectrx_n2387 +_ioreg16_h3_3 _ioreg16_h3_3~_CSRDATAOUT_D_n2388 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_C_n2389 +_4iomodule_h11_11 _4iomodule_h11_11~_IOBUF_DPA_n2390 +_4iomodule_c551_51 _4iomodule_c551_51~_IOBUF_DPA_n2391 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_sync_status_n2392 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_D_n2393 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n2394 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n2395 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_R_OUT_CLK_n2396 +_4iomodule_c513_13 _4iomodule_c513_13~_BSDOUT_n2397 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n2398 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_LVDS_CLK0_n2399 +_4iomodule_c554_54 _4iomodule_c554_54~_IOBUF_DPA_n2400 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_C_n2401 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_D_n2402 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_dprio_scan_shift_n_n2403 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n2404 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_R_OUT_CLK_n2405 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n2406 +_ioreg16_h6_6 _ioreg16_h6_6~_CSRDATAOUT_A_n2407 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_C_n2408 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_C_n2409 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n2410 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_D_n2411 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_tx_data_tc_n2412 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_early_eios_n2413 +_4iomodule_c540_40 _4iomodule_c540_40~_BUF_IOREG_n2414 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n2415 +_4iomodule_c520_20 _4iomodule_c520_20~_INPUT_BUF_n2416 +_ir_lvl_top1_1 _ir_lvl_top1_1~_CSRDOUT_n2417 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_C_n2418 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_tx_data_tc_n2419 +_4iomodule_c557_57 _4iomodule_c557_57~_IOBUF_DPA_n2420 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_C_n2421 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_R_OUT_CLK_n2422 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_CSR_DOUT_1_n2423 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_LOADEN_OUT_AB_n2424 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_tx_b50_buf_out_n2425 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n2426 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_R_n2427 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_n2428 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_FCLK_OUT_CD_n2429 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n2430 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_C_n2431 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_SHORT_R_IN_CLK_n2432 +_ioreg16_h3_3 _ioreg16_h3_3~_CSRDATAOUT_C_n2433 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_R_n2434 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n2435 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_R_n2436 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_rx_data_n2437 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_C_n2438 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_tx_ctl_tc_n2439 +_ioreg16_h3_3 _ioreg16_h3_3~_CSRDATAOUT_B_n2440 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_C_n2441 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n2442 +_4iomodule_h14_14 _4iomodule_h14_14~_INPUT_BUF_n2443 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_R_n2444 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_rxpma_rstb_n2445 +_4iomodule_h14_14 _4iomodule_h14_14~_INPUT_BUF_n2446 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_DPA_B_n2447 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_IOCSRDOUT_n2448 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_n2449 +_4iomodule_h14_14 _4iomodule_h14_14~_INPUT_BUF_n2450 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n2451 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_R_n2452 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_FCLK_OUT_AB_n2453 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_B_n2454 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reg_addr_n2455 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_R_n2456 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_DPA_B_n2457 +_4iomodule_c540_40 _4iomodule_c540_40~_BSDOUT_n2458 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_DPA_C_n2459 +_4iomodule_h14_14 _4iomodule_h14_14~_INPUT_BUF_n2460 +_ioreg16_c512_12 _ioreg16_c512_12~_REGSCANOUT_C_n2461 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_n2462 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n2463 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n2464 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n2465 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n2466 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_LOADEN_OUT_AB_n2467 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_FCLK_OUT_CD_n2468 +_4iomodule_c511_11 _4iomodule_c511_11~_BSDOUT_n2469 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_D_n2470 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_C_n2471 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_C_n2472 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_ser_shift_load_n2473 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_n2474 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n2475 +_4iomodule_h22_22 _4iomodule_h22_22~_VREF_BIDIR_OUT_n2476 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n2477 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_FCLK_OUT_CD_n2478 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_FCLK_OUT_CD_n2479 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_D_n2480 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n2481 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_n2482 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n2483 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_FCLK_OUT_CD_n2484 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_FCLK_OUT_CD_n2485 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n2486 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n2487 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reg_addr_n2488 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reserved_out_n2489 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_C_n2490 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2491 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n2492 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_FCLK_OUT_CD_n2493 +_4iomodule_c50_n12 _4iomodule_c50_n12~_INPUT_BUF_n2494 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n2495 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reg_addr_n2496 +_4iomodule_c538_38 _4iomodule_c538_38~_INPUT_BUF_n2497 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reg_addr_n2498 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n2499 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reg_addr_n2500 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_LVDS_FCLK_OUT_CD_n2501 +_ioreg16_c54_4 _ioreg16_c54_4~_OUT_STAGE_A1R_n2502 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n2503 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n2504 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reg_addr_n2505 +_4iomodule_c543_43 _4iomodule_c543_43~_BUF_IOREG_n2506 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n2507 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2508 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n2509 +_4iomodule_c538_38 _4iomodule_c538_38~_INPUT_BUF_n2510 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n2511 +_4iomodule_c532_32 _4iomodule_c532_32~_INPUT_BUF_n2512 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reg_addr_n2513 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_C_n2514 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_A_n2515 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_ibc50u_bgtx_n2516 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n2517 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reg_addr_n2518 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_C_n2519 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_nfrzdrv_n2520 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_del_cond_met_0_top_ch0_n2521 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n2522 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_LOADEN_OUT_AB_n2523 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n2524 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_A_n2525 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_read_n2526 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n2527 +_4iomodule_c542_42 _4iomodule_c542_42~_BUF_IOREG_n2528 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_pcie_switch_n2529 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2530 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_del_cond_met_0_top_ch1_n2531 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_C_n2532 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n2533 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n2534 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_ibc50u_bgtx_n2535 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reg_addr_n2536 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reg_addr_n2537 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_DPA_B_n2538 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_ibc50u_bgrx_n2539 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_C_n2540 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n2541 +_4iomodule_c521_21 _4iomodule_c521_21~_BSDOUT_n2542 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n2543 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_ibp50u_bgrx_n2544 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reg_addr_n2545 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_B_n2546 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n2547 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_reg_addr_n2548 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_mdio_dis_n2549 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_read_n2550 +_ioreg16_c57_7 _ioreg16_c57_7~_PHYCT_SHORT_L_IN_CLK_n2551 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_del_cond_met_0_top_ch1_n2552 +_io_oct_serpar1_1 _io_oct_serpar1_1~_OCTRTCALN_R_n2553 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n2554 +_4iomodule_c558_58 _4iomodule_c558_58~_BSDOUT_n2555 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_LOADEN_OUT_CD_n2556 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_A_n2557 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_B_n2558 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_en_dskw_qd_top_ch1_n2559 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_ppm_lock_n2560 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_dprio_rst_n_n2561 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_en_dskw_qd_top_ch0_n2562 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_byte_en_n2563 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_SHORT_L_IN_CLK_n2564 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n2565 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_LOADEN_OUT_CD_n2566 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reg_addr_n2567 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_DPA_B_n2568 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_en_dskw_rd_ptrs_bot_ch2_n2569 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_SHORT_L_IN_CLK_n2570 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reg_addr_n2571 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_DPA_C_n2572 +_ioreg16_c55_5 _ioreg16_c55_5~_DQS_IN_C_n2573 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_B_n2574 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_SHORT_L_IN_CLK_n2575 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n2576 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_LOADEN_OUT_AB_n2577 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_OCTRZQP_n2578 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reg_addr_n2579 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_B_n2580 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_A_n2581 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_HR_CLK_R_n2582 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n2583 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n2584 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_FCLK_OUT_CD_n2585 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_OCTRZQP_n2586 +_4iomodule_c518_18 _4iomodule_c518_18~_BUF_IOREG_n2587 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_LOADEN_OUT_CD_n2588 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_SHORT_R_IN_CLK_n2589 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_B_n2590 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_A_n2591 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_en_dskw_qd_bot_ch2_n2592 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_FCLK_OUT_CD_n2593 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_running_disp_n2594 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_IOBUF_DPA_n2595 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_LOADEN_OUT_AB_n2596 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_n2597 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_LOADEN_OUT_CD_n2598 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_SHORT_R_IN_CLK_n2599 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n2600 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n2601 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_LOADEN_OUT_AB_n2602 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n2603 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n2604 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n2605 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_LOADEN_OUT_CD_n2606 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_INPUT_BUF_n2607 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n2608 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_SHORT_R_IN_CLK_n2609 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n2610 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n2611 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_D_n2612 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_INPUT_BUF_n2613 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n2614 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n2615 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n2616 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_dprio_clk_n2617 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_OCTRZQP_n2618 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_FCLK_OUT_AB_n2619 +_4iomodule_c50_n12 _4iomodule_c50_n12~_INPUT_BUF_n2620 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_read_n2621 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n2622 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n2623 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_FCLK_OUT_CD_n2624 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_OCTRZQP_n2625 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n2626 +_4iomodule_c50_n12 _4iomodule_c50_n12~_INPUT_BUF_n2627 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n2628 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_C_n2629 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_LOADEN_OUT_AB_n2630 +_4iomodule_c538_38 _4iomodule_c538_38~_INPUT_BUF_n2631 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_C_n2632 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_ibc50u_bgrx_n2633 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_dprio_scan_shift_n_n2634 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_C_n2635 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n2636 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_C_n2637 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_D_n2638 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_B_n2639 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n2640 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_FCLK_OUT_AB_n2641 +_4iomodule_h17_17 _4iomodule_h17_17~_IOBUF_DPA_n2642 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n2643 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n2644 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_B_n2645 +_4iomodule_h23_23 _4iomodule_h23_23~_INPUT_BUF_n2646 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n2647 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_LOADEN_OUT_AB_n2648 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_FCLK_OUT_AB_n2649 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n2650 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n2651 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n2652 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_DPA_A_n2653 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_R_n2654 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_B_n2655 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_FCLK_OUT_CD_n2656 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n2657 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n2658 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_C_n2659 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_tx_data_tc_n2660 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n2661 +_ioreg16_h6_6 _ioreg16_h6_6~_REGSCANOUT_C_n2662 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n2663 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_B_n2664 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_DPA_A_n2665 +_4iomodule_h23_23 _4iomodule_h23_23~_INPUT_BUF_n2666 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n2667 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_FCLK_OUT_CD_n2668 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n2669 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_R_n2670 +_4iomodule_c552_52 _4iomodule_c552_52~_INPUT_BUF_n2671 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_FCLK_OUT_AB_n2672 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_tx_data_tc_n2673 +_4iomodule_c515_15 _4iomodule_c515_15~_BUF_IOREG_n2674 +_ioreg16_h5_5 _ioreg16_h5_5~_REGSCANOUT_D_n2675 +_4iomodule_h23_23 _4iomodule_h23_23~_INPUT_BUF_n2676 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n2677 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_R_n2678 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_R_n2679 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_fifo_rst_rd_qd_top_ch1_n2680 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_tx_data_tc_n2681 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_nfrzdrv_n2682 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_lfclkp_xn_dn_out_n2683 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n2684 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n2685 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_SHORT_R_IN_CLK_n2686 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_tx_data_tc_n2687 +_4iomodule_h9_9 _4iomodule_h9_9~_IOBUF_DPA_n2688 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_mdio_dis_n2689 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_cpulse_x6_up_out_n2690 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_C_n2691 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_SHORT_R_IN_CLK_n2692 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_C_n2693 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_lfclkp_x6_b_dn_out_n2694 +_4iomodule17_17 _4iomodule17_17~_INPUT_BUF_n2695 +_ioreg16_h5_5 _ioreg16_h5_5~_PHYCT_SHORT_R_IN_CLK_n2696 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n2697 +_4iomodule_c532_32 _4iomodule_c532_32~_IOBUF_DPA_n2698 +_4iomodule17_17 _4iomodule17_17~_INPUT_BUF_n2699 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_lfclkp_x6_t_dn_out_n2700 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_L_FB_OUT_CLK_n2701 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n2702 +_ioreg16_h5_5 _ioreg16_h5_5~_PHYCT_SHORT_R_IN_CLK_n2703 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_C_n2704 +_4iomodule_c538_38 _4iomodule_c538_38~_IOBUF_DPA_n2705 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLMOUT0_n2706 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_byte_en_n2707 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_DATX3_n2708 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n2709 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n2710 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n2711 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_ppm_lock_n2712 +_4iomodule17_17 _4iomodule17_17~_INPUT_BUF_n2713 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_LOADEN_OUT_CD_n2714 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n2715 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_SHORT_R_IN_CLK_n2716 +_4iomodule_c537_37 _4iomodule_c537_37~_IOBUF_DPA_n2717 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_FCLK_OUT_AB_n2718 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n2719 +_4iomodule_c536_36 _4iomodule_c536_36~_BSDOUT_n2720 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n2721 +_4iomodule_c542_42 _4iomodule_c542_42~_IOBUF_DPA_n2722 +_ioreg16_h5_5 _ioreg16_h5_5~_PHYCT_SHORT_R_IN_CLK_n2723 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQS1X_CLK_L_n2724 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_LOADEN_OUT_CD_n2725 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_LOADEN_OUT_CD_n2726 +_4iomodule_c515_15 _4iomodule_c515_15~_BSDOUT_n2727 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_INPUT_BUF_n2728 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_running_disp_n2729 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n2730 +_ioreg16_h5_5 _ioreg16_h5_5~_PHYCT_SHORT_R_IN_CLK_n2731 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_align_status_top_ch0_n2732 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_FCLK_OUT_AB_n2733 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n2734 +_4iomodule_c548_48 _4iomodule_c548_48~_BSDOUT_n2735 +_4iomodule_c531_31 _4iomodule_c531_31~_IOBUF_DPA_n2736 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n2737 +_ioreg16_h5_5 _ioreg16_h5_5~_PHYCT_SHORT_R_IN_CLK_n2738 +_4iomodule_c50_n12 _4iomodule_c50_n12~_IOBUF_DPA_n2739 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n2740 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_align_status_sync_0_top_ch1_n2741 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_byte_en_n2742 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_LOADEN_OUT_AB_n2743 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n2744 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n2745 +_4iomodule_c518_18 _4iomodule_c518_18~_IOBUF_DPA_n2746 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_LOADEN_OUT_CD_n2747 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n2748 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n2749 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_ppm_lock_n2750 +_4iomodule_c519_19 _4iomodule_c519_19~_BSDOUT_n2751 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n2752 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n2753 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n2754 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_pclk_x6_b_dn_out_n2755 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_align_status_top_ch1_n2756 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_clkb_seg_up_out_n2757 +_4iomodule_h1_1 _4iomodule_h1_1~_BSDOUT_n2758 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n2759 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_LOADEN_OUT_AB_n2760 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n2761 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_LOADEN_OUT_AB_n2762 +_4iomodule_c559_59 _4iomodule_c559_59~_BSDOUT_n2763 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n2764 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n2765 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n2766 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_pclk_x6_t_dn_out_n2767 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_LOADEN_OUT_AB_n2768 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_A_n2769 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_D_n2770 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_LOADEN_OUT_AB_n2771 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_LOADEN_OUT_CD_n2772 +_ioreg16_c57_7 _ioreg16_c57_7~_OUT_STAGE_A1L_n2773 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_sync_status_n2774 +_ioreg16_h5_5 _ioreg16_h5_5~_PHYCT_SHORT_R_IN_CLK_n2775 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_clk_seg_up_out_n2776 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_FCLK_OUT_CD_n2777 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_ibp50u_bgrx_n2778 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_C_n2779 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n2780 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_D_n2781 +_ioreg16_c53_3 _ioreg16_c53_3~_LVDS_LOADEN_OUT_CD_n2782 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_FCLK_OUT_AB_n2783 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_DPA_C_n2784 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_C_n2785 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_dprio_scan_shift_n_n2786 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_L_FB_OUT_CLK_n2787 +_4iomodule_c552_52 _4iomodule_c552_52~_INPUT_BUF_n2788 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n2789 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_C_n2790 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLMOUT0_n2791 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_dprio_scan_mode_n_n2792 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_B_n2793 +_4iomodule_c524_24 _4iomodule_c524_24~_IOBUF_DPA_n2794 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_LOADEN_OUT_CD_n2795 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_SCHMITT_n2796 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_DPA_D_n2797 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_C_n2798 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n2799 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_ltr_n2800 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n2801 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_FCLK_OUT_AB_n2802 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_LOADEN_OUT_CD_n2803 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_C_n2804 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_INPUT_BUF_n2805 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_FCLK_OUT_AB_n2806 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_ibc50u_bgrx_n2807 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n2808 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_early_eios_n2809 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n2810 +_4iomodule_c556_56 _4iomodule_c556_56~_INPUT_BUF_n2811 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_FCLK_OUT_AB_n2812 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_FCLK_OUT_AB_n2813 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_ibp50u_bgrx_n2814 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n2815 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n2816 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_LOADEN_OUT_CD_n2817 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_LOADEN_OUT_CD_n2818 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_D_n2819 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_R_OUT_CLK_n2820 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_FCLK_OUT_AB_n2821 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n2822 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_ibp50u_bgrx_n2823 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_C_n2824 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_cg_comp_wr_all_top_ch1_n2825 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_FCLK_OUT_CD_n2826 +_ioreg16_c510_10 _ioreg16_c510_10~_LVDS_FCLK_OUT_AB_n2827 +_4iomodule_c556_56 _4iomodule_c556_56~_INPUT_BUF_n2828 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reg_addr_n2829 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_D_n2830 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_FCLK_OUT_AB_n2831 +_4iomodule_c552_52 _4iomodule_c552_52~_INPUT_BUF_n2832 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_FCLK_OUT_CD_n2833 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_DATX3_n2834 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_cg_comp_rd_d_all_top_ch1_n2835 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_FCLK_OUT_AB_n2836 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n2837 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_SCHMITT_n2838 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_cg_comp_rd_d_all_top_ch0_n2839 +_4iomodule_h9_9 _4iomodule_h9_9~_BUF_IOREG_n2840 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reg_addr_n2841 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_SHORT_R_IN_CLK_n2842 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_cg_comp_wr_all_top_ch0_n2843 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n2844 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_SHORT_R_IN_CLK_n2845 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n2846 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_D_n2847 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_tx_data_tc_n2848 +_ioreg16_c511_11 _ioreg16_c511_11~_REGSCANOUT_A_n2849 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_clk_out_n2850 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_fifo_rst_rd_qd_top_ch0_n2851 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_tx_data_tc_n2852 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n2853 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reg_addr_n2854 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_D_n2855 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_SCHMITT_n2856 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n2857 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_DPA_B_n2858 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n2859 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_fifo_rd_out_comp_0_top_ch1_n2860 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_D_n2861 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_tx_ctl_tc_n2862 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n2863 +_4iomodule_c552_52 _4iomodule_c552_52~_IOBUF_DPA_n2864 +_ioreg16_c511_11 _ioreg16_c511_11~_REGSCANOUT_D_n2865 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reg_addr_n2866 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_DPA_B_n2867 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n2868 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n2869 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_LOADEN_OUT_AB_n2870 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_DATX0_n2871 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reg_addr_n2872 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n2873 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n2874 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n2875 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n2876 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_D_n2877 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_D_n2878 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_C_n2879 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_D_n2880 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n2881 +_4iomodule_c555_55 _4iomodule_c555_55~_IOBUF_DPA_n2882 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_LOADEN_OUT_CD_n2883 +_ioreg16_c514_14 _ioreg16_c514_14~_PHYCT_SHORT_L_IN_CLK_n2884 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_C_n2885 +_4iomodule17_17 _4iomodule17_17~_INPUT_BUF_n2886 +_4iomodule_h17_17 _4iomodule_h17_17~_INPUT_BUF_n2887 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_D_n2888 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_D_n2889 +_4iomodule_c556_56 _4iomodule_c556_56~_IOBUF_DPA_n2890 +_4iomodule_c525_25 _4iomodule_c525_25~_INPUT_BUF_n2891 +_ioreg16_h5_5 _ioreg16_h5_5~_LVDS_LOADEN_OUT_CD_n2892 +_4iomodule_h19_19 _4iomodule_h19_19~_BSDOUT_n2893 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_L_n2894 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_L_n2895 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_Q_n2896 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n2897 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n2898 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_L_n2899 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n2900 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_L_n2901 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_R_OUT_CLK_n2902 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_tx_data_n2903 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_C_n2904 +_ioreg16_c514_14 _ioreg16_c514_14~_PHYCT_SHORT_L_IN_CLK_n2905 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n2906 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_IOBUF_DPA_n2907 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQ_CLK_R_n2908 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_L_n2909 +_ir_lvl_top5_5 _ir_lvl_top5_5~_PHYCT_TO_LVDS_FB_OUTL_n2910 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_SHORT_R_IN_CLK_n2911 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_en_dskw_qd_top_ch1_n2912 +_4iomodule_c525_25 _4iomodule_c525_25~_INPUT_BUF_n2913 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_LOADEN_OUT_AB_n2914 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_Q_n2915 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n2916 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n2917 +_ioreg16_h4_4 _ioreg16_h4_4~_PHYCT_SHORT_R_IN_CLK_n2918 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_cdr_t_clkb_dn_out_n2919 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_csren_o_n2920 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n2921 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n2922 +_4iomodule17_17 _4iomodule17_17~_BSDOUT_n2923 +_ioreg16_c514_14 _ioreg16_c514_14~_PHYCT_SHORT_L_IN_CLK_n2924 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_SHORT_R_IN_CLK_n2925 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n2926 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_SHORT_R_IN_CLK_n2927 +_4iomodule_c541_41 _4iomodule_c541_41~_INPUT_BUF_n2928 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_C_n2929 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_FCLK_OUT_CD_n2930 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n2931 +_ir_lvl_top5_5 _ir_lvl_top5_5~_PHYCT_TO_LVDS_FB_OUTL_n2932 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_LOADEN_OUT_AB_n2933 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_D_n2934 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n2935 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n2936 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_LOADEN_OUT_CD_n2937 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_L_n2938 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_HR_CLK_L_n2939 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_C_n2940 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_D_n2941 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_DPA_D_n2942 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_LOADEN_OUT_AB_n2943 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n2944 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n2945 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_D_n2946 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_LOADEN_OUT_AB_n2947 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n2948 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_LOADEN_OUT_CD_n2949 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_SHORT_R_IN_CLK_n2950 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n2951 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_latency_comp_0_top_ch0_n2952 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n2953 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_B_n2954 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_SHORT_R_IN_CLK_n2955 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_D_n2956 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n2957 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n2958 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_latency_comp_0_top_ch1_n2959 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_D_n2960 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_B_n2961 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_SHORT_R_IN_CLK_n2962 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_D_n2963 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_dec_data_valid_n2964 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_insert_incomplete_0_top_ch1_n2965 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_B_n2966 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_LOADEN_OUT_CD_n2967 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n2968 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_SHORT_R_IN_CLK_n2969 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_B_n2970 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_D_n2971 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n2972 +_4iomodule_c541_41 _4iomodule_c541_41~_INPUT_BUF_n2973 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_SHORT_R_IN_CLK_n2974 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n2975 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n2976 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQS1X_CLK_R_n2977 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_L_n2978 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_D_n2979 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n2980 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_C_n2981 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_A_n2982 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n2983 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_D_n2984 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_D_n2985 +_im_sysclk2_2 _im_sysclk2_2~_CSRDOUT_n2986 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n2987 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n2988 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_A_n2989 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n2990 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_FCLK_OUT_CD_n2991 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n2992 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n2993 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n2994 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_C_n2995 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_A_n2996 +_4iomodule_h3_3 _4iomodule_h3_3~_INPUT_BUF_n2997 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n2998 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n2999 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n3000 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_FCLK_OUT_CD_n3001 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_C_n3002 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_IOCSRDOUT_n3003 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n3004 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_FCLK_OUT_CD_n3005 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_LOADEN_OUT_CD_n3006 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_FCLK_OUT_CD_n3007 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_rd_align_n3008 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n3009 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_B_n3010 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_FCLK_OUT_CD_n3011 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_A_n3012 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_LOADEN_OUT_AB_n3013 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BUF_IOREG_n3014 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_LOADEN_OUT_CD_n3015 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_C_n3016 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_latency_comp_out_n3017 +_4iomodule_c534_34 _4iomodule_c534_34~_SCHMITT_n3018 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_writedata_n3019 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n3020 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_tx_data_n3021 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n3022 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_LOADEN_OUT_CD_n3023 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_C_n3024 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_rd_enable_sync_n3025 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_FCLK_OUT_CD_n3026 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_LOADEN_OUT_CD_n3027 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_rd_align_n3028 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_LOADEN_OUT_AB_n3029 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_align_status_sync_0_top_ch0_n3030 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_FCLK_OUT_CD_n3031 +_4iomodule_c534_34 _4iomodule_c534_34~_SCHMITT_n3032 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_B_n3033 +_4iomodule_c534_34 _4iomodule_c534_34~_SCHMITT_n3034 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_en_dskw_rd_ptrs_top_ch0_n3035 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n3036 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_tx_b50_buf_out_n3037 +_ioreg16_c511_11 _ioreg16_c511_11~_LVDS_LOADEN_OUT_AB_n3038 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_fifo_ovr_out_n3039 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_LOADEN_OUT_CD_n3040 +_4iomodule_c546_46 _4iomodule_c546_46~_INPUT_BUF_n3041 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_B_n3042 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n3043 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_block_select_n3044 +_4iomodule_h14_14 _4iomodule_h14_14~_BUF_IOREG_n3045 +_4iomodule_c510_10 _4iomodule_c510_10~_INPUT_BUF_n3046 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_LOADEN_OUT_CD_n3047 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_del_cond_met_out_n3048 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_B_n3049 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_B_n3050 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_SHORT_R_IN_CLK_n3051 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_en_dskw_qd_top_ch0_n3052 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_LOADEN_OUT_CD_n3053 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n3054 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_insert_incomplete_out_n3055 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_R_OUT_CLK_n3056 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_B_n3057 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_B_n3058 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_B_n3059 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_cdr_t_clk_dn_out_n3060 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_fifo_rd_out_comp_n3061 +_ioreg16_c510_10 _ioreg16_c510_10~_PHYCT_R_OUT_CLK_n3062 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_FCLK_OUT_CD_n3063 +_4iomodule_c546_46 _4iomodule_c546_46~_INPUT_BUF_n3064 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n3065 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n3066 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_FCLK_OUT_AB_n3067 +_4iomodule_h16_16 _4iomodule_h16_16~_IOBUF_DPA_n3068 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_FCLK_OUT_CD_n3069 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_FCLK_OUT_CD_n3070 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n3071 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n3072 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_CSRDATAOUT_A_n3073 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_B_n3074 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_D_n3075 +_4iomodule_h13_13 _4iomodule_h13_13~_IOBUF_DPA_n3076 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_FCLK_OUT_AB_n3077 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_LOADEN_OUT_CD_n3078 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_A_n3079 +_4iomodule_c527_27 _4iomodule_c527_27~_DATX1_n3080 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_B_n3081 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_FCLK_OUT_AB_n3082 +_ioreg16_h2_2 _ioreg16_h2_2~_LVDS_FCLK_OUT_AB_n3083 +_4iomodule_c534_34 _4iomodule_c534_34~_BUF_IOREG_n3084 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CORECLK_LO0_n3085 +_4iomodule_c537_37 _4iomodule_c537_37~_INPUT_BUF_n3086 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_current_coeff_n3087 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_INPUT_BUF_n3088 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_C_n3089 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_B_n3090 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_FPLL0_COUT_n3091 +_4iomodule_h21_21 _4iomodule_h21_21~_IOBUF_DPA_n3092 +_ioreg16_c510_10 _ioreg16_c510_10~_DQS_IN_C_n3093 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_C_n3094 +_4iomodule7_7 _4iomodule7_7~_BSDOUT_n3095 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_SHORT_L_IN_CLK_n3096 +_4iomodule_c537_37 _4iomodule_c537_37~_INPUT_BUF_n3097 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_pma_so_n3098 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_C_n3099 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_dprio_rst_n_n3100 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_A_n3101 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_INPUT_BUF_n3102 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reserved_out_n3103 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n3104 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_CSRDATAOUT_B_n3105 +_4iomodule_h13_13 _4iomodule_h13_13~_INPUT_BUF_n3106 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n3107 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_C_n3108 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_dprio_scan_mode_n_n3109 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_A_n3110 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_INPUT_BUF_n3111 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_DPA_D_n3112 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n3113 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_B_n3114 +_4iomodule_c55_5 _4iomodule_c55_5~_INPUT_BUF_n3115 +_ioreg16_c514_14 _ioreg16_c514_14~_OUT_STAGE_A1L_n3116 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_early_eios_n3117 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reserved_out_n3118 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_B_n3119 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_A_n3120 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BUF_IOREG_n3121 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_pma_so_n3122 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_INPUT_BUF_n3123 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_SHORT_L_IN_CLK_n3124 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_tx_clk_n3125 +_4iomodule_c537_37 _4iomodule_c537_37~_INPUT_BUF_n3126 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_FPLL0_COUT_n3127 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_ibp50u_bgrx_n3128 +_4iomodule_c537_37 _4iomodule_c537_37~_INPUT_BUF_n3129 +_ioreg16_h5_5 _ioreg16_h5_5~_DQS_IN_C_n3130 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_ibp50u_bgrx_n3131 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_R_OUT_CLK_n3132 +_4iomodule_h17_17 _4iomodule_h17_17~_INPUT_BUF_n3133 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_rx_clk_out_n3134 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n3135 +_4iomodule_c534_34 _4iomodule_c534_34~_DATX2_n3136 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n3137 +_4iomodule_c534_34 _4iomodule_c534_34~_DATX3_n3138 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_LOADEN_OUT_AB_n3139 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n3140 +_4iomodule_h17_17 _4iomodule_h17_17~_INPUT_BUF_n3141 +_4iomodule_h3_3 _4iomodule_h3_3~_INPUT_BUF_n3142 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_LOADEN_OUT_AB_n3143 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_DPA_D_n3144 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_DPA_A_n3145 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_FCLK_OUT_CD_n3146 +_4iomodule13_13 _4iomodule13_13~_INPUT_BUF_n3147 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n3148 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_fifo_rd_out_comp_0_top_ch0_n3149 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n3150 +_ir_lvl_top4_4 _ir_lvl_top4_4~_HR_CLK_R_n3151 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_LOADEN_OUT_AB_n3152 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_reg_addr_n3153 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n3154 +_4iomodule_h3_3 _4iomodule_h3_3~_INPUT_BUF_n3155 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_C_n3156 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_FCLK_OUT_CD_n3157 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_R_OUT_CLK_n3158 +_4iomodule_h17_17 _4iomodule_h17_17~_INPUT_BUF_n3159 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_fifo_ovr_0_top_ch1_n3160 +_4iomodule13_13 _4iomodule13_13~_INPUT_BUF_n3161 +_4iomodule_h3_3 _4iomodule_h3_3~_INPUT_BUF_n3162 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_pfdmode_lock_n3163 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_LOADEN_OUT_AB_n3164 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_R_OUT_CLK_n3165 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_fifo_ovr_0_top_ch0_n3166 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_LOADEN_OUT_CD_n3167 +_4iomodule13_13 _4iomodule13_13~_INPUT_BUF_n3168 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALP_L_n3169 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_R_OUT_CLK_n3170 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_FCLK_OUT_CD_n3171 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_C_n3172 +_ioreg16_c57_7 _ioreg16_c57_7~_PHYCT_SHORT_L_IN_CLK_n3173 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_L_n3174 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_pma_so_n3175 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_FPLL0_COUT_n3176 +_ioreg16_c514_14 _ioreg16_c514_14~_PHYCT_SHORT_L_IN_CLK_n3177 +_ioreg16_c57_7 _ioreg16_c57_7~_PHYCT_SHORT_L_IN_CLK_n3178 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_rcvd_clk_out_bot_n3179 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTCALN_L_n3180 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_LOADEN_OUT_AB_n3181 +_4iomodule_h15_15 _4iomodule_h15_15~_BSDOUT_n3182 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n3183 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_LOADEN_OUT_AB_n3184 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_LOADEN_OUT_AB_n3185 +_ioreg16_c57_7 _ioreg16_c57_7~_PHYCT_SHORT_L_IN_CLK_n3186 +_ioreg16_c514_14 _ioreg16_c514_14~_PHYCT_SHORT_L_IN_CLK_n3187 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n3188 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_LOADEN_OUT_CD_n3189 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n3190 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_LOADEN_OUT_CD_n3191 +_ioreg16_c57_7 _ioreg16_c57_7~_PHYCT_SHORT_L_IN_CLK_n3192 +_4iomodule_c513_13 _4iomodule_c513_13~_BUF_IOREG_n3193 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_B_n3194 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_IOCSRDOUT_n3195 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n3196 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n3197 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n3198 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_FCLK_OUT_AB_n3199 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BUF_IOREG_n3200 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_B_n3201 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_LOADEN_OUT_AB_n3202 +_ioreg16_c514_14 _ioreg16_c514_14~_PHYCT_SHORT_L_IN_CLK_n3203 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_FCLK_OUT_CD_n3204 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_FCLK_OUT_AB_n3205 +_4iomodule_c557_57 _4iomodule_c557_57~_BUF_IOREG_n3206 +_ioreg16_c57_7 _ioreg16_c57_7~_PHYCT_SHORT_L_IN_CLK_n3207 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n3208 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_FBLVDS_IN_RO0_n3209 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_C_n3210 +_ioreg16_h5_5 _ioreg16_h5_5~_REGSCANOUT_C_n3211 +_4iomodule13_13 _4iomodule13_13~_INPUT_BUF_n3212 +_ioreg16_c57_7 _ioreg16_c57_7~_PHYCT_SHORT_L_IN_CLK_n3213 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n3214 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n3215 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_LOADEN_OUT_CD_n3216 +_4iomodule_c514_14 _4iomodule_c514_14~_BSDOUT_n3217 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_insert_incomplete_0_top_ch0_n3218 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_LOADEN_OUT_CD_n3219 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_CSRDATAOUT_C_n3220 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_FBLVDS_OUT0_n3221 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_LOADEN_OUT_AB_n3222 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n3223 +_4iomodule_c510_10 _4iomodule_c510_10~_INPUT_BUF_n3224 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch0_n3225 +_ioreg16_h4_4 _ioreg16_h4_4~_PHYCT_SHORT_R_IN_CLK_n3226 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n3227 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n3228 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_DPA_A_n3229 +_4iomodule_c534_34 _4iomodule_c534_34~_IOBUF_DPA_n3230 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BUF_IOREG_n3231 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_B_n3232 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_R_OUT_CLK_n3233 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch0_n3234 +_4iomodule_h6_6 _4iomodule_h6_6~_INPUT_BUF_n3235 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n3236 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n3237 +_4iomodule_c55_5 _4iomodule_c55_5~_INPUT_BUF_n3238 +_4iomodule_c549_49 _4iomodule_c549_49~_INPUT_BUF_n3239 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n3240 +_4iomodule_c527_27 _4iomodule_c527_27~_IOBUF_DPA_n3241 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_LOADEN_OUT_AB_n3242 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n3243 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_R_OUT_CLK_n3244 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n3245 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_LOADEN_OUT_AB_n3246 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_D_n3247 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_CSR_DOUT_1_n3248 +_4iomodule3_3 _4iomodule3_3~_INPUT_BUF_n3249 +_ioreg16_h4_4 _ioreg16_h4_4~_PHYCT_SHORT_R_IN_CLK_n3250 +_ioreg16_c55_5 _ioreg16_c55_5~_PHYCT_SHORT_R_IN_CLK_n3251 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_FPLL0_COUT_n3252 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n3253 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_D_n3254 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_LOADEN_OUT_AB_n3255 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n3256 +_4iomodule3_3 _4iomodule3_3~_INPUT_BUF_n3257 +_4iomodule_c545_45 _4iomodule_c545_45~_BSDOUT_n3258 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_LOADEN_OUT_CD_n3259 +_ioreg16_h2_2 _ioreg16_h2_2~_REGSCANOUT_B_n3260 +_4iomodule_c517_17 _4iomodule_c517_17~_BSDOUT_n3261 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_C_n3262 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n3263 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_LOADEN_OUT_CD_n3264 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n3265 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n3266 +_4iomodule_c50_n12 _4iomodule_c50_n12~_INPUT_BUF_n3267 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_R_OUT_CLK_n3268 +_4iomodule_c59_9 _4iomodule_c59_9~_BSDOUT_n3269 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n3270 +_4iomodule_c533_33 _4iomodule_c533_33~_IOBUF_DPA_n3271 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n3272 +_ioreg16_c514_14 _ioreg16_c514_14~_PHYCT_SHORT_L_IN_CLK_n3273 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n3274 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n3275 +_4iomodule_c528_28 _4iomodule_c528_28~_BUF_IOREG_n3276 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_SHORT_R_IN_CLK_n3277 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_LOADEN_OUT_AB_n3278 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_FBLVDS_OUT0_n3279 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_LOADEN_OUT_AB_n3280 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_ltr_n3281 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_LOADEN_OUT_AB_n3282 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_C_n3283 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_LOADEN_OUT_AB_n3284 +_ioreg16_c513_13 _ioreg16_c513_13~_CSRDATAOUT_B_n3285 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_OCTRZQP_n3286 +_4iomodule_h2_2 _4iomodule_h2_2~_INPUT_BUF_n3287 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLDOUT0_n3288 +_ioreg16_c513_13 _ioreg16_c513_13~_CSRDATAOUT_A_n3289 +_4iomodule_h21_21 _4iomodule_h21_21~_INPUT_BUF_n3290 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_SHORT_R_IN_CLK_n3291 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_D_n3292 +_4iomodule16_16 _4iomodule16_16~_BSDOUT_n3293 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IC50UA_FT_BIDIR_OUT_n3294 +_4iomodule_h2_2 _4iomodule_h2_2~_INPUT_BUF_n3295 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_DPA_D_n3296 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_R_OUT_CLK_n3297 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_D_n3298 +_4iomodule4_4 _4iomodule4_4~_INPUT_BUF_n3299 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_ZDB_IN_RO0_n3300 +_ioreg16_h6_6 _ioreg16_h6_6~_REGSCANOUT_D_n3301 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_pma_reserved_out_n3302 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reg_addr_n3303 +_4iomodule_h16_16 _4iomodule_h16_16~_BSDOUT_n3304 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_R_n3305 +_ioreg16_c513_13 _ioreg16_c513_13~_CSRDATAOUT_C_n3306 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n3307 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_R_OUT_CLK_n3308 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_pma_reserved_out_n3309 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n3310 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n3311 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_R_n3312 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_SHORT_R_IN_CLK_n3313 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n3314 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reg_addr_n3315 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_pma_reserved_out_n3316 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_cg_comp_rd_d_all_bot_ch2_n3317 +_ioreg16_h4_4 _ioreg16_h4_4~_PHYCT_SHORT_R_IN_CLK_n3318 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_R_OUT_CLK_n3319 +_4iomodule_h19_19 _4iomodule_h19_19~_INPUT_BUF_n3320 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_R_n3321 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3322 +_4iomodule_h0_n8 _4iomodule_h0_n8~_INPUT_BUF_n3323 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_hclk_pcs_n3324 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_dprio_scan_shift_n_n3325 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_read_n3326 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_R_n3327 +_4iomodule_h0_n8 _4iomodule_h0_n8~_INPUT_BUF_n3328 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_R_n3329 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IC50UA_FT_BIDIR_OUT_n3330 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_pcie_sw_done_n3331 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_R_OUT_CLK_n3332 +_cc_clkmuxf_tb0_n15 _cc_clkmuxf_tb0_n15~_CSRDOUT_n3333 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_align_status_top_ch0_n3334 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n3335 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_early_eios_n3336 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_R_n3337 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IC50UA_FT_BIDIR_OUT_n3338 +_4iomodule_c57_7 _4iomodule_c57_7~_IOBUF_DPA_n3339 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_align_status_top_ch1_n3340 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_dprio_rst_n_n3341 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_pfdmode_lock_n3342 +_ioreg16_c53_3 _ioreg16_c53_3~_CSR_DOUT_2_n3343 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reg_addr_n3344 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_dec_ctl_n3345 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_R_OUT_CLK_n3346 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_C_n3347 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n3348 +_ioreg16_h6_6 _ioreg16_h6_6~_REGSCANOUT_A_n3349 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_dprio_scan_mode_n_n3350 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_R_OUT_CLK_n3351 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reg_addr_n3352 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n3353 +_ioreg16_h4_4 _ioreg16_h4_4~_LVDS_LOADEN_OUT_AB_n3354 +_4iomodule_c522_22 _4iomodule_c522_22~_IOBUF_DPA_n3355 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reg_addr_n3356 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_A_n3357 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_C_n3358 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n3359 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n3360 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_R_OUT_CLK_n3361 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_R_n3362 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_dprio_clk_n3363 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reg_addr_n3364 +_4iomodule_c512_12 _4iomodule_c512_12~_IOBUF_DPA_n3365 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_SCHMITT_n3366 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_dec_data_n3367 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n3368 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_DPA_D_n3369 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_elec_idle_n3370 +_ioreg16_h5_5 _ioreg16_h5_5~_REGSCANOUT_B_n3371 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_n3372 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_dec_data_n3373 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n3374 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n3375 +_4iomodule_h15_15 _4iomodule_h15_15~_VREF_BIDIR_OUT_n3376 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_ppm_lock_n3377 +_4iomodule_h5_5 _4iomodule_h5_5~_BSDOUT_n3378 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n3379 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_R_OUT_CLK_n3380 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_Q_n3381 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_R_n3382 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_LOADEN_OUT_CD_n3383 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n3384 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n3385 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_t_n3386 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_dec_data_n3387 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_A_n3388 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_tx_ctl_tc_n3389 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_DPA_A_n3390 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_R_n3391 +_4iomodule_h10_10 _4iomodule_h10_10~_INPUT_BUF_n3392 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_B_n3393 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reg_addr_n3394 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_pcie_switch_n3395 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_tx_data_tc_n3396 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_R_n3397 +_4iomodule_h2_2 _4iomodule_h2_2~_INPUT_BUF_n3398 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_LOADEN_OUT_CD_n3399 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_read_n3400 +_4iomodule4_4 _4iomodule4_4~_IOBUF_DPA_n3401 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_LOADEN_OUT_CD_n3402 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_R_n3403 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n3404 +_4iomodule12_12 _4iomodule12_12~_IOBUF_DPA_n3405 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n3406 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_QN_n3407 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_sync_status_n3408 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_Q_n3409 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_A_n3410 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n3411 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_ltr_n3412 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_D_n3413 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_rx_iqclk_b_a_n3414 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_cg_comp_wr_out_n3415 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_D_n3416 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_early_eios_n3417 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_refclk_ffpll_n3418 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n3419 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_D_n3420 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_cg_comp_wr_out_n3421 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_tx_data_tc_n3422 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_t_n3423 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_nfrzdrv_n3424 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n3425 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_R_OUT_CLK_n3426 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_ibp50u_bgrx_n3427 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n3428 +_4iomodule_h24_24 _4iomodule_h24_24~_IOBUF_DPA_n3429 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n3430 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n3431 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n3432 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reg_addr_n3433 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_mdio_dis_n3434 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_LOADEN_OUT_AB_n3435 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_t_n3436 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n3437 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_QN_n3438 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reg_addr_n3439 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n3440 +_ioreg16_c50_n9 _ioreg16_c50_n9~_OUT_STAGE_A1L_n3441 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n3442 +_4iomodule0_n13 _4iomodule0_n13~_IOBUF_DPA_n3443 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_D_n3444 +_4iomodule2_2 _4iomodule2_2~_IOBUF_DPA_n3445 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_R_OUT_CLK_n3446 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n3447 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n3448 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n3449 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n3450 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_LOADEN_OUT_AB_n3451 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n3452 +_4iomodule_h0_n8 _4iomodule_h0_n8~_IOBUF_DPA_n3453 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n3454 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_tx_data_tc_n3455 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_R_OUT_CLK_n3456 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n3457 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n3458 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n3459 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_running_disp_n3460 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_cg_comp_wr_all_top_ch0_n3461 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n3462 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n3463 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_R_n3464 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n3465 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n3466 +_4iomodule9_9 _4iomodule9_9~_IOBUF_DPA_n3467 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n3468 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n3469 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n3470 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_A_n3471 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_R_n3472 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_L_OUT_CLK_n3473 +_4iomodule4_4 _4iomodule4_4~_INPUT_BUF_n3474 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n3475 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_tx_data_tc_n3476 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n3477 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_cg_comp_rd_d_all_top_ch1_n3478 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n3479 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n3480 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n3481 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_tx_data_tc_n3482 +_4iomodule_h19_19 _4iomodule_h19_19~_INPUT_BUF_n3483 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_tx_data_tc_n3484 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n3485 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_cg_comp_wr_all_bot_ch2_n3486 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_OCTRZQP_n3487 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_LOADEN_OUT_CD_n3488 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n3489 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n3490 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_D_n3491 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n3492 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_L_OUT_CLK_n3493 +_4iomodule_h19_19 _4iomodule_h19_19~_INPUT_BUF_n3494 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_R_OUT_CLK_n3495 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_LOADEN_OUT_CD_n3496 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALN_L_n3497 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n3498 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n3499 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_L_OUT_CLK_n3500 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_FCLK_OUT_CD_n3501 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_tx_b50_buf_out_n3502 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_n3503 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n3504 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n3505 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQS1X_CLK_L_n3506 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQS1X_CLK_L_n3507 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n3508 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n3509 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_n3510 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_csr_out_n3511 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_fifo_select_out_chnl_down_n3512 +_4iomodule_h5_5 _4iomodule_h5_5~_IOBUF_DPA_n3513 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n3514 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_FCLK_OUT_AB_n3515 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_n3516 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n3517 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_LOADEN_OUT_CD_n3518 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_R_n3519 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_A_n3520 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_LOADEN_OUT_AB_n3521 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n3522 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_tx_b50_buf_out_n3523 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_FCLK_OUT_AB_n3524 +_ioreg16_c511_11 _ioreg16_c511_11~_DQS_IN_C_n3525 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_LOADEN_OUT_CD_n3526 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_hfclkp_x6_dn_out_n3527 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_R_n3528 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_SHORT_L_IN_CLK_n3529 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_A_n3530 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_LOADEN_OUT_AB_n3531 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n3532 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_A_n3533 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_B_n3534 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_SHORT_L_IN_CLK_n3535 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_LOADEN_OUT_CD_n3536 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_SHORT_L_IN_CLK_n3537 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n3538 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_A_n3539 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_R_n3540 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_SHORT_L_IN_CLK_n3541 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_L_n3542 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_csr_dout_n3543 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n3544 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQS_2X_CLK_L_n3545 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_write_n3546 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_R_n3547 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_A_n3548 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_SHORT_L_IN_CLK_n3549 +_4iomodule_h7_7 _4iomodule_h7_7~_INPUT_BUF_n3550 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_A_n3551 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_R_n3552 +_4iomodule4_4 _4iomodule4_4~_INPUT_BUF_n3553 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_L_OUT_CLK_n3554 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_A_n3555 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_L_OUT_CLK_n3556 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n3557 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_hfclkn_xn_up_out_n3558 +_4iomodule4_4 _4iomodule4_4~_INPUT_BUF_n3559 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_DPA_A_n3560 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_L_OUT_CLK_n3561 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n3562 +_4iomodule_h19_19 _4iomodule_h19_19~_INPUT_BUF_n3563 +_4iomodule_h10_10 _4iomodule_h10_10~_INPUT_BUF_n3564 +_ioreg16_h4_4 _ioreg16_h4_4~_PHYCT_SHORT_R_IN_CLK_n3565 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_D_n3566 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n3567 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n3568 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reg_addr_n3569 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n3570 +_ioreg16_h4_4 _ioreg16_h4_4~_PHYCT_SHORT_R_IN_CLK_n3571 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3572 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n3573 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n3574 +_ir_lvl_top3_3 _ir_lvl_top3_3~_HR_CLK_L_n3575 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_B_n3576 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reg_addr_n3577 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_R_n3578 +_ir_lvl_top5_5 _ir_lvl_top5_5~_CSRDOUT_n3579 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n3580 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BUF_IOREG_n3581 +_ioreg16_c52_2 _ioreg16_c52_2~_CSRDATAOUT_A_n3582 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_block_select_n3583 +_ioreg16_c512_12 _ioreg16_c512_12~_CSRDATAOUT_D_n3584 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_R_n3585 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_A_n3586 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_A_n3587 +_4iomodule_h10_10 _4iomodule_h10_10~_INPUT_BUF_n3588 +_ioreg16_c52_2 _ioreg16_c52_2~_CSR_DOUT_1_n3589 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_R_n3590 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQ_CLK_L_n3591 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_B_n3592 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n3593 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reg_addr_n3594 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_B_n3595 +_ioreg16_c52_2 _ioreg16_c52_2~_CSRDATAOUT_C_n3596 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_R_n3597 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n3598 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_SHORT_L_IN_CLK_n3599 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n3600 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_FCLK_OUT_CD_n3601 +_ioreg16_c52_2 _ioreg16_c52_2~_CSRDATAOUT_B_n3602 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3603 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n3604 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_A_n3605 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_LOADEN_OUT_AB_n3606 +_4iomodule_h22_22 _4iomodule_h22_22~_IOBUF_DPA_n3607 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQS1X_CLK_L_n3608 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n3609 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_R_n3610 +_ioreg16_c59_9 _ioreg16_c59_9~_CSRDATAOUT_A_n3611 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n3612 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n3613 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_D_n3614 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3615 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n3616 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_LOADEN_OUT_AB_n3617 +_ioreg16_c52_2 _ioreg16_c52_2~_CSRDATAOUT_D_n3618 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_QN_n3619 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_tx_b50_buf_out_n3620 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3621 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3622 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reg_addr_n3623 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_B_n3624 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_QN_n3625 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_LOADEN_OUT_AB_n3626 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3627 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reg_addr_n3628 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n3629 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_D_n3630 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_A_n3631 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_block_select_n3632 +_ioreg16_h4_4 _ioreg16_h4_4~_PHYCT_SHORT_R_IN_CLK_n3633 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_D_n3634 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n3635 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n3636 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n3637 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_D_n3638 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_A_n3639 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_cdr_b_clkb_up_out_n3640 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_tx_data_tc_n3641 +_4iomodule_h12_12 _4iomodule_h12_12~_BSDOUT_n3642 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n3643 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3644 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n3645 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n3646 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQS1X_CLK_L_n3647 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reg_addr_n3648 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n3649 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_A_n3650 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_FCLK_OUT_CD_n3651 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n3652 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reg_addr_n3653 +_4iomodule_h10_10 _4iomodule_h10_10~_INPUT_BUF_n3654 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n3655 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_D_n3656 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_D_n3657 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_A_n3658 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3659 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n3660 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_txdetectrx_n3661 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n3662 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_D_n3663 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_tx_b50_buf_out_n3664 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_A_n3665 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n3666 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reg_addr_n3667 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_L_OUT_CLK_n3668 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n3669 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_LOADEN_OUT_AB_n3670 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_L_OUT_CLK_n3671 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_tx_b50_buf_out_n3672 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n3673 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_FCLK_OUT_CD_n3674 +_4iomodule2_2 _4iomodule2_2~_INPUT_BUF_n3675 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n3676 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_fifo_select_out_chnl_down_n3677 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_L_n3678 +_4iomodule_c532_32 _4iomodule_c532_32~_BUF_IOREG_n3679 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_cg_comp_rd_d_out_n3680 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n3681 +_ir_lvl_top5_5 _ir_lvl_top5_5~_DQ_CLK_L_n3682 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_L_OUT_CLK_n3683 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n3684 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_DPA_A_n3685 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n3686 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_tx_data_tc_n3687 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_L_n3688 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3689 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n3690 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_cg_comp_wr_out_n3691 +_ioreg16_h2_2 _ioreg16_h2_2~_REGSCANOUT_D_n3692 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n3693 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_out_n3694 +_ir_lvl_top5_5 _ir_lvl_top5_5~_DQS1X_CLK_L_n3695 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_L_OUT_CLK_n3696 +_ioreg16_h2_2 _ioreg16_h2_2~_REGSCANOUT_A_n3697 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_D_n3698 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_align_status_sync_n3699 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3700 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_L_n3701 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n3702 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_FCLK_OUT_CD_n3703 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_QN_n3704 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_L_OUT_CLK_n3705 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_D_n3706 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_pma_so_n3707 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_cg_comp_rd_d_out_n3708 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BUF_IOREG_n3709 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3710 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n3711 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n3712 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_lfclkp_x6_up_out_n3713 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_QN_n3714 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n3715 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n3716 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n3717 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_config_sel_out_chnl_down_n3718 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_FCLK_OUT_AB_n3719 +_4iomodule_h7_7 _4iomodule_h7_7~_INPUT_BUF_n3720 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n3721 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_pma_so_n3722 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n3723 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_latency_comp_out_n3724 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n3725 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_FCLK_OUT_CD_n3726 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BUF_IOREG_n3727 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n3728 +_4iomodule_h7_7 _4iomodule_h7_7~_INPUT_BUF_n3729 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_CLKIN_TC_BO_BIDIR_OUT_n3730 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n3731 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n3732 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n3733 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n3734 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_align_status_sync_0_top_ch1_n3735 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_CLKIN_TC_BO_BIDIR_OUT_n3736 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_CLKIN_TC_BO_BIDIR_OUT_n3737 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n3738 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n3739 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n3740 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n3741 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n3742 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_fifo_rd_out_comp_n3743 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_align_status_sync_0_top_ch0_n3744 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n3745 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_L_OUT_CLK_n3746 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n3747 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_fifo_ovr_out_n3748 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_out_n3749 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_L_n3750 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n3751 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_align_status_sync_0_bot_ch2_n3752 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_tx_b50_buf_out_n3753 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n3754 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_DPA_D_n3755 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_R_n3756 +_4iomodule_h10_10 _4iomodule_h10_10~_IOBUF_DPA_n3757 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_tx_b50_buf_out_n3758 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_b50_buf_out_n3759 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n3760 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_rd_enable_sync_n3761 +_4iomodule_h6_6 _4iomodule_h6_6~_IOBUF_DPA_n3762 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_B_n3763 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_L_n3764 +_ioreg16_c512_12 _ioreg16_c512_12~_LVDS_FCLK_OUT_CD_n3765 +_4iomodule_c527_27 _4iomodule_c527_27~_SCHMITT_n3766 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n3767 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_out_n3768 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_b50_buf_out_n3769 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_tx_b50_buf_out_n3770 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n3771 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n3772 +_ioreg16_c59_9 _ioreg16_c59_9~_DQS_IN_C_n3773 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n3774 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_tx_b50_buf_out_n3775 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_R_n3776 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n3777 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_DPA_D_n3778 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n3779 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n3780 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_FCLK_OUT_AB_n3781 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch1_n3782 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_R_n3783 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3784 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n3785 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_D_n3786 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALP_L_n3787 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n3788 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_out_n3789 +_ir_lvl_top5_5 _ir_lvl_top5_5~_DQS1X_CLK_L_n3790 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n3791 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_ctl_ts_top_ch0_n3792 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_FCLK_OUT_AB_n3793 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_tx_b50_buf_out_n3794 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_R_n3795 +_4iomodule_c521_21 _4iomodule_c521_21~_BUF_IOREG_n3796 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n3797 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n3798 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_insert_incomplete_out_n3799 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_FCLK_OUT_CD_n3800 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_TC_BO_BIDIR_OUT_n3801 +_ioreg16_c59_9 _ioreg16_c59_9~_CSRDATAOUT_B_n3802 +_4iomodule_h7_7 _4iomodule_h7_7~_IOBUF_DPA_n3803 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n3804 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n3805 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_C_n3806 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_L_n3807 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_B_n3808 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n3809 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n3810 +_ioreg16_c59_9 _ioreg16_c59_9~_CSRDATAOUT_C_n3811 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch1_n3812 +_4iomodule_h23_23 _4iomodule_h23_23~_IOBUF_DPA_n3813 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_clk_out_n3814 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_C_n3815 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_C_n3816 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_t_n3817 +_ir_lvl_top5_5 _ir_lvl_top5_5~_DQS_2X_CLK_L_n3818 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_D_n3819 +_ir_lvl_top5_5 _ir_lvl_top5_5~_DQS1X_CLK_L_n3820 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_R_n3821 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n3822 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_C_n3823 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_ser_shift_load_n3824 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_ser_shift_load_n3825 +_4iomodule_h0_n8 _4iomodule_h0_n8~_INPUT_BUF_n3826 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch1_n3827 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3828 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_L_n3829 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_D_n3830 +_ir_lvl_top5_5 _ir_lvl_top5_5~_DQS1X_CLK_L_n3831 +_4iomodule_h0_n8 _4iomodule_h0_n8~_INPUT_BUF_n3832 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_C_n3833 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_R_n3834 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_L_n3835 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_t_n3836 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_C_n3837 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n3838 +_4iomodule16_16 _4iomodule16_16~_INPUT_BUF_n3839 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n3840 +_4iomodule8_8 _4iomodule8_8~_BSDOUT_n3841 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_FCLK_OUT_AB_n3842 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_DPA_D_n3843 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_B_n3844 +_ioreg16_h2_2 _ioreg16_h2_2~_IOREG_BUF_C_n3845 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3846 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_L_n3847 +_4iomodule16_16 _4iomodule16_16~_INPUT_BUF_n3848 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n3849 +_ioreg16_c51_1 _ioreg16_c51_1~_LVDS_FCLK_OUT_AB_n3850 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_B_n3851 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_DPA_C_n3852 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_LOADEN_OUT_CD_n3853 +_4iomodule_h24_24 _4iomodule_h24_24~_BSDOUT_n3854 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_D_n3855 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_B_n3856 +_4iomodule_h13_13 _4iomodule_h13_13~_BSDOUT_n3857 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_QN_n3858 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n3859 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_B_n3860 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_TC_BO_BIDIR_OUT_n3861 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_LOADEN_OUT_AB_n3862 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_DPA_C_n3863 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_LOADEN_OUT_CD_n3864 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_tx_data_ts_top_ch0_n3865 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_Q_n3866 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3867 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_B_n3868 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_B_n3869 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_R_n3870 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_block_select_n3871 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_B_n3872 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_FCLK_OUT_CD_n3873 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_rxpma_rstb_n3874 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_SCHMITT_n3875 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3876 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IT50UA_FT_BIDIR_OUT_n3877 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_B_n3878 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3879 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_rxclkslip_n3880 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_B_n3881 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IT50UA_FT_BIDIR_OUT_n3882 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_B_n3883 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_rx_clk_out_n3884 +_4iomodule_h7_7 _4iomodule_h7_7~_INPUT_BUF_n3885 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n3886 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_B_n3887 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_C_n3888 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_SCHMITT_n3889 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_D_n3890 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_B_n3891 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_OUT_STAGE_A1R_n3892 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n3893 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reserved_out_n3894 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_C_n3895 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_B_n3896 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IT50UA_FT_BIDIR_OUT_n3897 +_4iomodule_c53_3 _4iomodule_c53_3~_BUF_IOREG_n3898 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3899 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n3900 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_reserved_out_n3901 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_D_n3902 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IC50UA_FTRES_BIDIR_OUT_n3903 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_B_n3904 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_DPA_D_n3905 +_ioreg16_c57_7 _ioreg16_c57_7~_DQS_IN_C_n3906 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_QN_n3907 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_BSDOUT_n3908 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IC50UA_FTRES_BIDIR_OUT_n3909 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_B_n3910 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_B_n3911 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_D_n3912 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_DPA_A_n3913 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_L_n3914 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_BSDOUT_n3915 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3916 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_B_n3917 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n3918 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_D_n3919 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_D_n3920 +_4iomodule16_16 _4iomodule16_16~_INPUT_BUF_n3921 +_4iomodule3_3 _4iomodule3_3~_BSDOUT_n3922 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n3923 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_DATX2_n3924 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_DPA_D_n3925 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_DPA_B_n3926 +_4iomodule16_16 _4iomodule16_16~_INPUT_BUF_n3927 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_B_n3928 +_4iomodule_h21_21 _4iomodule_h21_21~_BUF_IOREG_n3929 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n3930 +_ioreg16_c57_7 _ioreg16_c57_7~_OUT_STAGE_A1R_n3931 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n3932 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3933 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_B_n3934 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_byte_en_n3935 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n3936 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_D_n3937 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_byte_en_n3938 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_CLKIN_TC_BO_BIDIR_OUT_n3939 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3940 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_B_n3941 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_FCLK_OUT_CD_n3942 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n3943 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_D_n3944 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n3945 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_current_coeff_n3946 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n3947 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n3948 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n3949 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_Q_n3950 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n3951 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_B_n3952 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n3953 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_D_n3954 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_B_n3955 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n3956 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n3957 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_B_n3958 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_B_n3959 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_TC_BO_BIDIR_OUT_n3960 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n3961 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_cg_comp_rd_d_all_top_ch0_n3962 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n3963 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch1_n3964 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n3965 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_DATX1_n3966 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_hfclkn_xn_dn_out_n3967 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_del_cond_met_0_bot_ch2_n3968 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IT50UA_FT_BIDIR_OUT_n3969 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n3970 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_PHYCT_SHORT_L_IN_CLK_n3971 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch1_n3972 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n3973 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n3974 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n3975 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n3976 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_del_cond_met_0_top_ch0_n3977 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n3978 +_4iomodule_c518_18 _4iomodule_c518_18~_INPUT_BUF_n3979 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_dec_data_n3980 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_hfclkp_x6_b_dn_out_n3981 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_dec_data_n3982 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_tx_data_tc_n3983 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n3984 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_D_n3985 +_4iomodule_c538_38 _4iomodule_c538_38~_BUF_IOREG_n3986 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_L_n3987 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_hfclkp_x6_t_dn_out_n3988 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_L_n3989 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n3990 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_cg_comp_wr_all_top_ch1_n3991 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_PHYCT_SHORT_L_IN_CLK_n3992 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_L_n3993 +_ioreg16_c514_14 _ioreg16_c514_14~_DQS_IN_C_n3994 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_TC_BO_BIDIR_OUT_n3995 +_4iomodule10_10 _4iomodule10_10~_IOBUF_DPA_n3996 +_4iomodule_c542_42 _4iomodule_c542_42~_INPUT_BUF_n3997 +_4iomodule12_12 _4iomodule12_12~_INPUT_BUF_n3998 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_dec_data_n3999 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n4000 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n4001 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_hfclkp_xn_dn_out_n4002 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_t_n4003 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_D_n4004 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n4005 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch1_n4006 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n4007 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_sigdet_n4008 +_4iomodule_c542_42 _4iomodule_c542_42~_INPUT_BUF_n4009 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_L_n4010 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_TC_BO_BIDIR_OUT_n4011 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_D_n4012 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_t_n4013 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_L_n4014 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n4015 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_D_n4016 +_4iomodule14_14 _4iomodule14_14~_IOBUF_DPA_n4017 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_iqtxrxclk_ffpll_n4018 +_4iomodule_c524_24 _4iomodule_c524_24~_INPUT_BUF_n4019 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n4020 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n4021 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_tx_wr_enable_out_chnl_up_n4022 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_R_OUT_CLK_n4023 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n4024 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n4025 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_dec_data_n4026 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n4027 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_dprio_scan_shift_n_n4028 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n4029 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n4030 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_cg_comp_wr_out_n4031 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_D_n4032 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_D_n4033 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTCALN_L_n4034 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_D_n4035 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_found_n4036 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n4037 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_dprio_clk_n4038 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_A_n4039 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n4040 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_cg_comp_rd_d_out_n4041 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_pma_so_n4042 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_dprio_rst_n_n4043 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_D_n4044 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_D_n4045 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IC50UA_FTRES_BIDIR_OUT_n4046 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_C_n4047 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n4048 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rxpll_lock_n4049 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch1_n4050 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_cg_comp_rd_d_out_n4051 +_4iomodule12_12 _4iomodule12_12~_INPUT_BUF_n4052 +_4iomodule16_16 _4iomodule16_16~_IOBUF_DPA_n4053 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_A_n4054 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_tx_rd_enable_out_chnl_up_n4055 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_D_n4056 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n4057 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_detect_valid_n4058 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_A_n4059 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_D_n4060 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_dec_data_valid_n4061 +_ioreg16_h6_6 _ioreg16_h6_6~_PHYCT_L_OUT_CLK_n4062 +_4iomodule_c517_17 _4iomodule_c517_17~_BUF_IOREG_n4063 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_B_n4064 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n4065 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_agg_rx_data_rs_top_ch1_n4066 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_DATX3_n4067 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_rd_align_n4068 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_D_n4069 +_4iomodule12_12 _4iomodule12_12~_INPUT_BUF_n4070 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_B_n4071 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n4072 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_FCLK_OUT_AB_n4073 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n4074 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_rd_align_n4075 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_SHORT_L_IN_CLK_n4076 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_D_n4077 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n4078 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_dprio_scan_mode_n_n4079 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n4080 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_FCLK_OUT_AB_n4081 +_4iomodule_h16_16 _4iomodule_h16_16~_BUF_IOREG_n4082 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_SHORT_L_IN_CLK_n4083 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n4084 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_FCLK_OUT_CD_n4085 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_D_n4086 +_4iomodule_c517_17 _4iomodule_c517_17~_IOBUF_DPA_n4087 +_4iomodule10_10 _4iomodule10_10~_BSDOUT_n4088 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n4089 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n4090 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n4091 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_DATX1_n4092 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n4093 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_A_n4094 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n4095 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_writedata_n4096 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_tx_clk_n4097 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BUF_IOREG_n4098 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n4099 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IC50UA_FT_BIDIR_OUT_n4100 +_4iomodule_c515_15 _4iomodule_c515_15~_IOBUF_DPA_n4101 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_C_n4102 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n4103 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_FCLK_OUT_CD_n4104 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n4105 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n4106 +_4iomodule_h21_21 _4iomodule_h21_21~_INPUT_BUF_n4107 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n4108 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_del_cond_met_out_n4109 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n4110 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n4111 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n4112 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_n4113 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n4114 +_4iomodule_h2_2 _4iomodule_h2_2~_INPUT_BUF_n4115 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n4116 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n4117 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_DATX2_n4118 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_dec_data_n4119 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_C_n4120 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_FCLK_OUT_CD_n4121 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_Q_n4122 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_R_n4123 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4124 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BUF_IOREG_n4125 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_n4126 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n4127 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4128 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n4129 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_D_n4130 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_CSRDOUT_n4131 +_4iomodule_h17_17 _4iomodule_h17_17~_BUF_IOREG_n4132 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_R_n4133 +_4iomodule_c54_4 _4iomodule_c54_4~_BSDOUT_n4134 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4135 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n4136 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IC50UA_FT_BIDIR_OUT_n4137 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4138 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_n4139 +_4iomodule_c536_36 _4iomodule_c536_36~_IOBUF_DPA_n4140 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_running_disp_n4141 +_ioreg16_c53_3 _ioreg16_c53_3~_CSRDATAOUT_D_n4142 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_Q_n4143 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_B_n4144 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_DATX0_n4145 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BSDOUT_n4146 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n4147 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_PHYCT_SHORT_L_IN_CLK_n4148 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n4149 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n4150 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_n4151 +_4iomodule_h21_21 _4iomodule_h21_21~_INPUT_BUF_n4152 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_SCHMITT_n4153 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_BSDOUT_n4154 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n4155 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n4156 +_4iomodule_h21_21 _4iomodule_h21_21~_INPUT_BUF_n4157 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_BSDOUT_n4158 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_data_n4159 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_n4160 +_ioreg16_c53_3 _ioreg16_c53_3~_CSRDATAOUT_A_n4161 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n4162 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n4163 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n4164 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BSDOUT_n4165 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_tx_clk_out_n4166 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_SCHMITT_n4167 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n4168 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_L_n4169 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n4170 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n4171 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_latency_comp_out_n4172 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n4173 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_FCLK_OUT_CD_n4174 +_4iomodule_c510_10 _4iomodule_c510_10~_BUF_IOREG_n4175 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_PHYCT_SHORT_L_IN_CLK_n4176 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_LOADEN_OUT_AB_n4177 +_4iomodule_c549_49 _4iomodule_c549_49~_BUF_IOREG_n4178 +_ioreg16_c53_3 _ioreg16_c53_3~_CSRDATAOUT_C_n4179 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n4180 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n4181 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_align_status_bot_ch2_n4182 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_rd_align_n4183 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_FCLK_OUT_CD_n4184 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n4185 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_PHYCT_SHORT_L_IN_CLK_n4186 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_LOADEN_OUT_AB_n4187 +_ioreg16_c53_3 _ioreg16_c53_3~_CSRDATAOUT_B_n4188 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n4189 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n4190 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n4191 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_rd_align_n4192 +_4iomodule_c518_18 _4iomodule_c518_18~_INPUT_BUF_n4193 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_LOADEN_OUT_AB_n4194 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_rd_enable_sync_n4195 +_ioreg16_c512_12 _ioreg16_c512_12~_REGSCANOUT_B_n4196 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n4197 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n4198 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_L_n4199 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_PHYCT_SHORT_L_IN_CLK_n4200 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_lfclkn_xn_up_out_n4201 +_ioreg16_c56_6 _ioreg16_c56_6~_REGSCANOUT_A_n4202 +_4iomodule_c526_26 _4iomodule_c526_26~_BUF_IOREG_n4203 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n4204 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_SCHMITT_n4205 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_L_n4206 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_lfclkp_xn_up_out_n4207 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4208 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4209 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_DPA_B_n4210 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_pclk_xn_dn_out_n4211 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_DPACLK0_I_n4212 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n4213 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_lfclkp_xn_dn_out_n4214 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4215 +_4iomodule12_12 _4iomodule12_12~_INPUT_BUF_n4216 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_DPA_B_n4217 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n4218 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_b_a_n4219 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n4220 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4221 +_4iomodule_c524_24 _4iomodule_c524_24~_INPUT_BUF_n4222 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALN_L_n4223 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_b50_buf_out_n4224 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_b_a_n4225 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n4226 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n4227 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_DPACLK0_I_n4228 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n4229 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n4230 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4231 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n4232 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n4233 +_4iomodule_c529_29 _4iomodule_c529_29~_BUF_IOREG_n4234 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n4235 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_DPA_D_n4236 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_C_n4237 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_ffpll_n4238 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n4239 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_DPACLK0_I_n4240 +_4iomodule_h9_9 _4iomodule_h9_9~_INPUT_BUF_n4241 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_IOBUF_DPA_n4242 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_SHORT_L_IN_CLK_n4243 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_pma_reserved_out_n4244 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_B_n4245 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n4246 +_4iomodule_c544_44 _4iomodule_c544_44~_INPUT_BUF_n4247 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n4248 +_4iomodule_c544_44 _4iomodule_c544_44~_INPUT_BUF_n4249 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_b_a_n4250 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_D_n4251 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n4252 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n4253 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_EXTCLK_n4254 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLMOUT0_n4255 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_A_n4256 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_EXTCLK_n4257 +_4iomodule_h9_9 _4iomodule_h9_9~_INPUT_BUF_n4258 +_4iomodule_h20_20 _4iomodule_h20_20~_INPUT_BUF_n4259 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_lfclkp_x6_dn_out_n4260 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n4261 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_t_a_n4262 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_iqtxrxclk_ffpll_n4263 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_A_n4264 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_n4265 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_B_n4266 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_out_n4267 +_4iomodule_c544_44 _4iomodule_c544_44~_INPUT_BUF_n4268 +_4iomodule8_8 _4iomodule8_8~_INPUT_BUF_n4269 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_DPA_B_n4270 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_out_n4271 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_C_n4272 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4273 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_A_n4274 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_IOBUF_DPA_n4275 +_4iomodule_h9_9 _4iomodule_h9_9~_INPUT_BUF_n4276 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_B_n4277 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4278 +_4iomodule_c544_44 _4iomodule_c544_44~_INPUT_BUF_n4279 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_A_n4280 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_running_disp_n4281 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_hclk_pcs_n4282 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_rd_enable_sync_n4283 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_pcie_sw_done_n4284 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n4285 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_B_n4286 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_BSDOUT_n4287 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQS1X_CLK_L_n4288 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_ctl_ts_top_ch0_n4289 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_B_n4290 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_clklow_n4291 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_B_n4292 +_4iomodule_h_c58_8 _4iomodule_h_c58_8~_BSDOUT_n4293 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4294 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQ_CLK_L_n4295 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_B_n4296 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n4297 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_ctl_ts_bot_ch2_n4298 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_fref_n4299 +_4iomodule_h_c511_11 _4iomodule_h_c511_11~_BSDOUT_n4300 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4301 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQS1X_CLK_L_n4302 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_insert_incomplete_out_n4303 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n4304 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_B_n4305 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_latency_comp_out_n4306 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_bot_ch2_n4307 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQS1X_CLK_L_n4308 +_4iomodule_h9_9 _4iomodule_h9_9~_INPUT_BUF_n4309 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_fifo_rd_out_comp_n4310 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_cg_comp_rd_d_out_n4311 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_rx_rd_enable_out_chnl_down_n4312 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_ctl_ts_top_ch1_n4313 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_A_n4314 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_bot_ch2_n4315 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_rd_align_n4316 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_A_n4317 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n4318 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_B_n4319 +_4iomodule_c518_18 _4iomodule_c518_18~_INPUT_BUF_n4320 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_rd_align_n4321 +_ioreg16_c52_2 _ioreg16_c52_2~_OUT_STAGE_A1R_n4322 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_A_n4323 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_bot_ch2_n4324 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_D_n4325 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_OCTRZQP_n4326 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_C_n4327 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch1_n4328 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_rx_div_sync_out_chnl_down_n4329 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_TC_BO_BIDIR_OUT_n4330 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_bot_ch2_n4331 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_dec_data_valid_n4332 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_OCTRZQP_n4333 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_A_n4334 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_rx_div_sync_out_chnl_down_n4335 +_4iomodule_c542_42 _4iomodule_c542_42~_INPUT_BUF_n4336 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_TC_BO_BIDIR_OUT_n4337 +_4iomodule7_7 _4iomodule7_7~_INPUT_BUF_n4338 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_bot_ch2_n4339 +_4iomodule_c518_18 _4iomodule_c518_18~_INPUT_BUF_n4340 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_A_n4341 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_A_n4342 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n4343 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_bot_ch2_n4344 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ffpll_ref_iqclk_t_n4345 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_fifo_ovr_out_n4346 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n4347 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_C_n4348 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_A_n4349 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_cg_comp_rd_d_out_n4350 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4351 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALP_L_n4352 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_reset_ppm_cntrs_out_chnl_down_n4353 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4354 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_pma_reserved_out_n4355 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_bot_ch2_n4356 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_DPACLK0_I_n4357 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_del_cond_met_out_n4358 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_A_n4359 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_align_status_sync_n4360 +_4iomodule_c542_42 _4iomodule_c542_42~_INPUT_BUF_n4361 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n4362 +_4iomodule7_7 _4iomodule7_7~_INPUT_BUF_n4363 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n4364 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_A_n4365 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_hclk_top_n4366 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_DPACLK0_I_n4367 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_A_n4368 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4369 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_C_n4370 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_rx_we_out_chnl_down_n4371 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n4372 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQS1X_CLK_L_n4373 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n4374 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_DPACLK0_I_n4375 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_DPA_A_n4376 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n4377 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n4378 +_4iomodule7_7 _4iomodule7_7~_INPUT_BUF_n4379 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_D_n4380 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_iqtxrxclk_t_n4381 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n4382 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_C_n4383 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_SHORT_L_IN_CLK_n4384 +_4iomodule8_8 _4iomodule8_8~_INPUT_BUF_n4385 +_ir_lvl_top7_7 _ir_lvl_top7_7~_DQS_2X_CLK_L_n4386 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_pma_reserved_out_n4387 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_D_n4388 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_DPA_B_n4389 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n4390 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n4391 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_lfclkn_xn_dn_out_n4392 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_align_det_sync_n4393 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_D_n4394 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_FBLVDS_OUT0_n4395 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_DPACLK0_I_n4396 +_ioreg16_c51_1 _ioreg16_c51_1~_REGSCANOUT_D_n4397 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n4398 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_lfclkn_x6_dn_out_n4399 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_align_det_sync_n4400 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_SHORT_L_IN_CLK_n4401 +_ir_lvl_top5_5 _ir_lvl_top5_5~_HR_CLK_L_n4402 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_DPA_D_n4403 +_ioreg16_c51_1 _ioreg16_c51_1~_REGSCANOUT_A_n4404 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_C_n4405 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n4406 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_C_n4407 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4408 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALN_L_n4409 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n4410 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n4411 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_DPA_B_n4412 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n4413 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALN_L_n4414 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_FBLVDS_IN_RO0_n4415 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4416 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_ffpll_n4417 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_A_n4418 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n4419 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_dec_data_n4420 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_t_a_n4421 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4422 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4423 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n4424 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALN_L_n4425 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_hfclkn_xn_up_out_n4426 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n4427 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_t_a_n4428 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n4429 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n4430 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_DPA_B_n4431 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_n4432 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n4433 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_B_n4434 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n4435 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_out_n4436 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n4437 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n4438 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_dec_data_n4439 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_pclk_xn_up_out_n4440 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_clklow_n4441 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n4442 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4443 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_D_n4444 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4445 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_D_n4446 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n4447 +_4iomodule_h13_13 _4iomodule_h13_13~_INPUT_BUF_n4448 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_DPA_B_n4449 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4450 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n4451 +_4iomodule_h13_13 _4iomodule_h13_13~_INPUT_BUF_n4452 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_mdio_dis_n4453 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_fref_n4454 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_pclk_xn_dn_out_n4455 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_BSDOUT_n4456 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_D_n4457 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_ppm_lock_n4458 +_ioreg16_c53_3 _ioreg16_c53_3~_PHYCT_SHORT_L_IN_CLK_n4459 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_hfclkn_x6_up_out_n4460 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_D_n4461 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n4462 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_C_n4463 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_nfrzdrv_n4464 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n4465 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_D_n4466 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_pclk_x6_dn_out_n4467 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_SHORT_L_IN_CLK_n4468 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_B_n4469 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4470 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_D_n4471 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n4472 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch0_n4473 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_clk_n4474 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n4475 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_D_n4476 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch0_n4477 +_ioreg16_c56_6 _ioreg16_c56_6~_REGSCANOUT_B_n4478 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_pcie_switch_n4479 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_D_n4480 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_B_n4481 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n4482 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_b50_buf_out_n4483 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_C_n4484 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n4485 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_D_n4486 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch1_n4487 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_C_n4488 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_b50_buf_out_n4489 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_data_n4490 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch1_n4491 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CORECLK_LO0_n4492 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_C_n4493 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n4494 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_D_n4495 +_4iomodule_c513_13 _4iomodule_c513_13~_INPUT_BUF_n4496 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_C_n4497 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_SHORT_R_IN_CLK_n4498 +_ioreg16_h0_n7 _ioreg16_h0_n7~_PHYCT_SHORT_L_IN_CLK_n4499 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch1_n4500 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_B_n4501 +_4iomodule_c513_13 _4iomodule_c513_13~_INPUT_BUF_n4502 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n4503 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n4504 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_D_n4505 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_tx_div_sync_out_chnl_down_n4506 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_L_n4507 +_4iomodule_c524_24 _4iomodule_c524_24~_BUF_IOREG_n4508 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n4509 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch1_n4510 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n4511 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_D_n4512 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQS_2X_CLK_L_n4513 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_R_OUT_CLK_n4514 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch1_n4515 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_ltr_n4516 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_L_n4517 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_DPA_D_n4518 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_tx_div_sync_out_chnl_down_n4519 +_4iomodule_c513_13 _4iomodule_c513_13~_INPUT_BUF_n4520 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_R_OUT_CLK_n4521 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_n4522 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_L_n4523 +_4iomodule0_n13 _4iomodule0_n13~_INPUT_BUF_n4524 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch1_n4525 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_SHORT_R_IN_CLK_n4526 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_tx_wr_enable_out_chnl_down_n4527 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n4528 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQ_CLK_R_n4529 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n4530 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALP_L_n4531 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALP_L_n4532 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_SHORT_R_IN_CLK_n4533 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch1_n4534 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_DPA_D_n4535 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALP_L_n4536 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n4537 +_ioreg16_c51_1 _ioreg16_c51_1~_REGSCANOUT_C_n4538 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_SHORT_R_IN_CLK_n4539 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_align_det_sync_n4540 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch1_n4541 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ref_iqclk_out_n4542 +_4iomodule_c513_13 _4iomodule_c513_13~_INPUT_BUF_n4543 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_L_n4544 +_4iomodule0_n13 _4iomodule0_n13~_INPUT_BUF_n4545 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_SHORT_R_IN_CLK_n4546 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_align_det_sync_n4547 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_early_eios_n4548 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_SHORT_L_IN_CLK_n4549 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n4550 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_A_n4551 +_4iomodule0_n13 _4iomodule0_n13~_INPUT_BUF_n4552 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_n4553 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_A_n4554 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_B_n4555 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_SHORT_L_IN_CLK_n4556 +_4iomodule0_n13 _4iomodule0_n13~_INPUT_BUF_n4557 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTCALP_L_n4558 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_dprio_scan_shift_n_n4559 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQS1X_CLK_R_n4560 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALP_L_n4561 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_LOADEN_OUT_CD_n4562 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n4563 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_SHORT_R_IN_CLK_n4564 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_dprio_clk_n4565 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n4566 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4567 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_reset_pc_ptrs_out_chnl_down_n4568 +_ioreg16_c56_6 _ioreg16_c56_6~_LVDS_LOADEN_OUT_CD_n4569 +_4iomodule_c56_6 _4iomodule_c56_6~_IOBUF_DPA_n4570 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n4571 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_tx_rd_enable_out_chnl_down_n4572 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n4573 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_DPA_A_n4574 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_b_a_n4575 +_4iomodule_c530_30 _4iomodule_c530_30~_BUF_IOREG_n4576 +_4iomodule_c547_47 _4iomodule_c547_47~_IOBUF_DPA_n4577 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n4578 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_hfclkp_x6_up_out_n4579 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n4580 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_D_n4581 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQS1X_CLK_R_n4582 +_ioreg16_h3_3 _ioreg16_h3_3~_PHYCT_SHORT_R_IN_CLK_n4583 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_b_a_n4584 +_4iomodule_c535_35 _4iomodule_c535_35~_IOBUF_DPA_n4585 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_SHORT_L_IN_CLK_n4586 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_D_n4587 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_DPA_A_n4588 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n4589 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_dprio_rst_n_n4590 +_4iomodule_c555_55 _4iomodule_c555_55~_SCHMITT_n4591 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_b50_buf_out_n4592 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_OCTRTCALN_L_n4593 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n4594 +_4iomodule_c53_3 _4iomodule_c53_3~_IOBUF_DPA_n4595 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_n4596 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_SHORT_L_IN_CLK_n4597 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALP_L_n4598 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_B_n4599 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_A_n4600 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_pclk_x6_up_out_n4601 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n4602 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_D_n4603 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_DPA_D_n4604 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reserved_out_n4605 +_ioreg16_c56_6 _ioreg16_c56_6~_REGSCANOUT_D_n4606 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_b50_buf_out_n4607 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_A_n4608 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n4609 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_B_n4610 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_SHORT_L_IN_CLK_n4611 +_ir_lvl_top7_7 _ir_lvl_top7_7~_HR_CLK_L_n4612 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_A_n4613 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n4614 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n4615 +_ir_lvl_top6_6 _ir_lvl_top6_6~_HR_CLK_L_n4616 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_rxclkslip_n4617 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_clk_n4618 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n4619 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_EXTCLK_n4620 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_B_n4621 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_LOADEN_OUT_AB_n4622 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n4623 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n4624 +_4iomodule_h14_14 _4iomodule_h14_14~_BSDOUT_n4625 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n4626 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_lfclkp_xn_up_out_n4627 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_DPA_A_n4628 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reserved_out_n4629 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_B_n4630 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n4631 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_LOADEN_OUT_AB_n4632 +_4iomodule_c533_33 _4iomodule_c533_33~_SCHMITT_n4633 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n4634 +_4iomodule_h18_18 _4iomodule_h18_18~_INPUT_BUF_n4635 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n4636 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reg_addr_n4637 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_DPA_A_n4638 +_ioreg16_c513_13 _ioreg16_c513_13~_REGSCANOUT_C_n4639 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_FCLK_OUT_CD_n4640 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n4641 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_DPA_D_n4642 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n4643 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_rx_clk_out_n4644 +_4iomodule_c555_55 _4iomodule_c555_55~_DATX1_n4645 +_ioreg16_c58_8 _ioreg16_c58_8~_REGSCANOUT_B_n4646 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n4647 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4648 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_C_n4649 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_FCLK_OUT_CD_n4650 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n4651 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n4652 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n4653 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n4654 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n4655 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_B_n4656 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_B_n4657 +_ioreg16_c54_4 _ioreg16_c54_4~_REGSCANOUT_A_n4658 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_FCLK_OUT_CD_n4659 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n4660 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_A_n4661 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n4662 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n4663 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n4664 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_C_n4665 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_FCLK_OUT_CD_n4666 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_EXTCLK_n4667 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n4668 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_hclk_pcs_n4669 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_INPUT_BUF_n4670 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_A_n4671 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n4672 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4673 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n4674 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n4675 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_A_n4676 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_FBLVDS_IN_RO0_n4677 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_C_n4678 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_B_n4679 +_ir_lvl_top2_2 _ir_lvl_top2_2~_HR_CLK_L_n4680 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n4681 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_D_n4682 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n4683 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n4684 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n4685 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n4686 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n4687 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n4688 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n4689 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_pfdmode_lock_n4690 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_b50_buf_out_n4691 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n4692 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_C_n4693 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n4694 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_A_n4695 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_fref_n4696 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_FCLK_OUT_AB_n4697 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n4698 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n4699 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4700 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_SHORT_L_IN_CLK_n4701 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n4702 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_dprio_scan_mode_n_n4703 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_b50_buf_out_n4704 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_A_n4705 +_ioreg16_h0_n7 _ioreg16_h0_n7~_PHYCT_SHORT_L_IN_CLK_n4706 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_A_n4707 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n4708 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_A_n4709 +_ioreg16_c54_4 _ioreg16_c54_4~_REGSCANOUT_D_n4710 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_INPUT_BUF_n4711 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n4712 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n4713 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4714 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_DPA_B_n4715 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n4716 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n4717 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_A_n4718 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n4719 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_D_n4720 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_INPUT_BUF_n4721 +_4iomodule_c533_33 _4iomodule_c533_33~_BUF_IOREG_n4722 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n4723 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_dec_data_n4724 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n4725 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n4726 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_INPUT_BUF_n4727 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_DPA_D_n4728 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_A_n4729 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n4730 +_ioreg16_c50_n9 _ioreg16_c50_n9~_DQS_IN_C_n4731 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_byte_en_n4732 +_ir_lvl_top2_2 _ir_lvl_top2_2~_DQS1X_CLK_L_n4733 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_dec_ctl_n4734 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_clklow_n4735 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQS1X_CLK_R_n4736 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n4737 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_clklow_n4738 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_SHORT_L_IN_CLK_n4739 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n4740 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n4741 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_DPA_C_n4742 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n4743 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_iqtxrxclk_t_n4744 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n4745 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_D_n4746 +_ioreg16_h0_n7 _ioreg16_h0_n7~_PHYCT_SHORT_L_IN_CLK_n4747 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_rxpma_rstb_n4748 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_SHORT_L_IN_CLK_n4749 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_dec_data_n4750 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n4751 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_SHORT_L_IN_CLK_n4752 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n4753 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_iqtxrxclk_t_n4754 +_ir_lvl_top4_4 _ir_lvl_top4_4~_PHYCT_TO_LVDS_FB_OUTR_n4755 +_4iomodule_h23_23 _4iomodule_h23_23~_BUF_IOREG_n4756 +_pl_aux0_n21 _pl_aux0_n21~_IT50U_BIDIR_OUT_n4757 +_ir_lvl_top2_2 _ir_lvl_top2_2~_DQS1X_CLK_L_n4758 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n4759 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_B_n4760 +_4iomodule_c555_55 _4iomodule_c555_55~_BUF_IOREG_n4761 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_D_n4762 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_A_n4763 +_ir_lvl_top4_4 _ir_lvl_top4_4~_PHYCT_TO_LVDS_FB_OUTR_n4764 +_4iomodule_h11_11 _4iomodule_h11_11~_BUF_IOREG_n4765 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_dec_data_n4766 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_D_n4767 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_DPA_C_n4768 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n4769 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQS1X_CLK_R_n4770 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_FCLK_OUT_AB_n4771 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_dec_data_n4772 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_SHORT_L_IN_CLK_n4773 +_pl_aux0_n21 _pl_aux0_n21~_IT50U_BIDIR_OUT_n4774 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n4775 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_D_n4776 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n4777 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_D_n4778 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_IC50UA_FT_BIDIR_OUT_n4779 +_4iomodule_h_c57_7 _4iomodule_h_c57_7~_INPUT_BUF_n4780 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_D_n4781 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_SHORT_L_IN_CLK_n4782 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_B_n4783 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reserved_out_n4784 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_PHYCT_SHORT_L_IN_CLK_n4785 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_INPUT_BUF_n4786 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_DPA_A_n4787 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n4788 +_pl_aux0_n21 _pl_aux0_n21~_IC50U_BIDIR_OUT_n4789 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_D_n4790 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_reg_addr_n4791 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_byte_en_n4792 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_dec_data_n4793 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n4794 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_DPA_A_n4795 +_4iomodule_c555_55 _4iomodule_c555_55~_DATX0_n4796 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_FCLK_OUT_AB_n4797 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_dec_data_n4798 +_4iomodule12_12 _4iomodule12_12~_BSDOUT_n4799 +_ir_lvl_top2_2 _ir_lvl_top2_2~_DQS1X_CLK_L_n4800 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_LOADEN0_n4801 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_FCLK_OUT_AB_n4802 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_current_coeff_n4803 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_cg_comp_wr_out_n4804 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_ZDB_IN_RO0_n4805 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQ_CLK_L_n4806 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_DATX0_n4807 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_A_n4808 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_D_n4809 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_iqtxrxclk_t_n4810 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_C_n4811 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_block_select_n4812 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_SCHMITT_n4813 +_ir_lvl_top2_2 _ir_lvl_top2_2~_DQ_CLK_L_n4814 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_C_n4815 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_D_n4816 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_A_n4817 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_A_n4818 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_align_det_sync_n4819 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_LOADEN0_n4820 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_C_n4821 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_C_n4822 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_C_n4823 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_C_n4824 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_D_n4825 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_D_n4826 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_C_n4827 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_D_n4828 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_B_n4829 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n4830 +_ioreg16_c54_4 _ioreg16_c54_4~_OUT_STAGE_A1L_n4831 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_align_det_sync_n4832 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_lfclkn_x6_up_out_n4833 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_B_n4834 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n4835 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_D_n4836 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n4837 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4838 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_tx_data_tc_n4839 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n4840 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_B_n4841 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_pma_reserved_out_n4842 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_D_n4843 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n4844 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4845 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n4846 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_DPA_C_n4847 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_B_n4848 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n4849 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n4850 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n4851 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n4852 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4853 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_D_n4854 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_A_n4855 +_4iomodule_c554_54 _4iomodule_c554_54~_BUF_IOREG_n4856 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_pma_reserved_out_n4857 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_iqtxrxclk_t_n4858 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_LOADEN0_n4859 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_OCTRZQP_n4860 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4861 +_4iomodule_h18_18 _4iomodule_h18_18~_INPUT_BUF_n4862 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_n4863 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4864 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_LOADEN0_n4865 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n4866 +_4iomodule_h18_18 _4iomodule_h18_18~_INPUT_BUF_n4867 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_pcie_sw_done_n4868 +_4iomodule_c59_9 _4iomodule_c59_9~_BUF_IOREG_n4869 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_D_n4870 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4871 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n4872 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n4873 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4874 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_A_n4875 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_LVDS_CLK0_n4876 +_ir_lvl_top2_2 _ir_lvl_top2_2~_DQS1X_CLK_L_n4877 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n4878 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_B_n4879 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_A_n4880 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n4881 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_B_n4882 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_OCTRZQP_n4883 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_n4884 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch0_n4885 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_OCTRZQP_n4886 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_D_n4887 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4888 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_C_n4889 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_B_n4890 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_align_status_sync_n4891 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n4892 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_A_n4893 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_OCTRZQP_n4894 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch0_n4895 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_A_n4896 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n4897 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_B_n4898 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_OCTRZQP_n4899 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_SHORT_L_IN_CLK_n4900 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_OCTRZQP_n4901 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_DPA_C_n4902 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_IC50UA_FT_BIDIR_OUT_n4903 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_B_n4904 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n4905 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_B_n4906 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_B_n4907 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n4908 +_ioreg16_h1_1 _ioreg16_h1_1~_REGSCANOUT_B_n4909 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n4910 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4911 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_QN_n4912 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLL_CAS_OUT1_n4913 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n4914 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_B_n4915 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n4916 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_B_n4917 +_4iomodule_c555_55 _4iomodule_c555_55~_DATX3_n4918 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n4919 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_OCTRZQP_n4920 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_pma_reserved_out_n4921 +_pl_aux0_n21 _pl_aux0_n21~_IC50U_BIDIR_OUT_n4922 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_readdata_n4923 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch0_n4924 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n4925 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_readdata_n4926 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n4927 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_SHORT_L_IN_CLK_n4928 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_lfclkn_xn_up_out_n4929 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_current_coeff_n4930 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n4931 +_ir_lvl_top3_3 _ir_lvl_top3_3~_HR_CLK_R_n4932 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n4933 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_B_n4934 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch0_n4935 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_B_n4936 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_OCTRZQP_n4937 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_n4938 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n4939 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_fifo_rd_out_comp_n4940 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n4941 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_B_n4942 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n4943 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n4944 +_4iomodule_h_c56_6 _4iomodule_h_c56_6~_BUF_IOREG_n4945 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_D_n4946 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n4947 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_B_n4948 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_A_n4949 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_DPA_A_n4950 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_fifo_ovr_out_n4951 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_QN_n4952 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_n4953 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_ltr_n4954 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n4955 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_bot_ch2_n4956 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_hfclkp_xn_up_out_n4957 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n4958 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_D_n4959 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reg_addr_n4960 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_B_n4961 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_B_n4962 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_del_cond_met_out_n4963 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n4964 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_mdio_dis_n4965 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch0_n4966 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n4967 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_bot_ch2_n4968 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_A_n4969 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_B_n4970 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reg_addr_n4971 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_dprio_scan_shift_n_n4972 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n4973 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n4974 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_B_n4975 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n4976 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQS1X_CLK_R_n4977 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n4978 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_DPA_A_n4979 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_early_eios_n4980 +_4iomodule_h22_22 _4iomodule_h22_22~_BUF_IOREG_n4981 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQ_CLK_R_n4982 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n4983 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n4984 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_A_n4985 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n4986 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch0_n4987 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n4988 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_ppm_lock_n4989 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_INPUT_BUF_n4990 +_ioreg16_h0_n7 _ioreg16_h0_n7~_PHYCT_SHORT_L_IN_CLK_n4991 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_DPA_B_n4992 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQS1X_CLK_R_n4993 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_bot_ch2_n4994 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_clklow_n4995 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_C_n4996 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n4997 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_INPUT_BUF_n4998 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_A_n4999 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_QN_n5000 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch0_n5001 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_B_n5002 +_ir_lvl_top3_3 _ir_lvl_top3_3~_DQS1X_CLK_R_n5003 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_bot_ch2_n5004 +_ir_lvl_top2_2 _ir_lvl_top2_2~_DQS_2X_CLK_L_n5005 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_bot_ch2_n5006 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_C_n5007 +_ioreg16_c54_4 _ioreg16_c54_4~_DQS_IN_C_n5008 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_nfrzdrv_n5009 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_INPUT_BUF_n5010 +_4iomodule_c551_51 _4iomodule_c551_51~_BUF_IOREG_n5011 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_QN_n5012 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_insert_incomplete_out_n5013 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_B_n5014 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_B_n5015 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reg_addr_n5016 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_B_n5017 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n5018 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_QN_n5019 +_ioreg16_h0_n7 _ioreg16_h0_n7~_PHYCT_SHORT_L_IN_CLK_n5020 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch0_n5021 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_A_n5022 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_hclk_pcs_n5023 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_B_n5024 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_pma_reserved_out_n5025 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_pcie_switch_n5026 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_pfdmode_lock_n5027 +_ioreg16_h0_n7 _ioreg16_h0_n7~_PHYCT_SHORT_L_IN_CLK_n5028 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_reserved_out_n5029 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_B_n5030 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n5031 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_QN_n5032 +_ioreg16_h0_n7 _ioreg16_h0_n7~_PHYCT_SHORT_L_IN_CLK_n5033 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_ctl_rs_top_ch1_n5034 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_iqtxrxclk_t_n5035 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_fref_n5036 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_B_n5037 +_4iomodule_c555_55 _4iomodule_c555_55~_SCHMITT_n5038 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n5039 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_B_n5040 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n5041 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n5042 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_pfdmode_lock_n5043 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_A_n5044 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch1_n5045 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch0_n5046 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_B_n5047 +_ioreg16_c50_n9 _ioreg16_c50_n9~_OUT_STAGE_A1R_n5048 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n5049 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_pcie_sw_done_n5050 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_bot_ch2_n5051 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_B_n5052 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch0_pma_read_n5053 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_agg_dec_data_valid_n5054 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n5055 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n5056 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_IT50UA_FT_BIDIR_OUT_n5057 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_bot_ch2_n5058 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_A_n5059 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n5060 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_LOADEN_OUT_CD_n5061 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_B_n5062 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_bot_ch2_n5063 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_B_n5064 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_B_n5065 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n5066 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_C_n5067 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n5068 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_A_n5069 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n5070 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_B_n5071 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_bot_ch2_n5072 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n5073 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_C_n5074 +_ioreg16_c514_14 _ioreg16_c514_14~_OUT_STAGE_A1R_n5075 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_B_n5076 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_A_n5077 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n5078 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n5079 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n5080 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_cdr_b_clk_up_out_n5081 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_B_n5082 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n5083 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_B_n5084 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_current_coeff_n5085 +_4iomodule_c531_31 _4iomodule_c531_31~_BUF_IOREG_n5086 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_rx_data_n5087 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_pma_reserved_out_n5088 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_A_n5089 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_A_n5090 +_4iomodule_c547_47 _4iomodule_c547_47~_BUF_IOREG_n5091 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_B_n5092 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_readdata_n5093 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_pma_reserved_out_n5094 +_4iomodule_h18_18 _4iomodule_h18_18~_INPUT_BUF_n5095 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reg_addr_n5096 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n5097 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_B_n5098 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_early_eios_n5099 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_FCLK_OUT_AB_n5100 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reg_addr_n5101 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_rxpma_rstb_n5102 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_tx_data_tc_n5103 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_B_n5104 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_tx_data_tc_n5105 +_4iomodule_h10_10 _4iomodule_h10_10~_BUF_IOREG_n5106 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n5107 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_dprio_scan_shift_n_n5108 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reg_addr_n5109 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n5110 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_rxclkslip_n5111 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_C_n5112 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_pcie_sw_done_n5113 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n5114 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n5115 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_DATX3_n5116 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_config_sel_out_chnl_down_n5117 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5118 +_4iomodule_h_c510_10 _4iomodule_h_c510_10~_BUF_IOREG_n5119 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_B_n5120 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_tx_data_tc_n5121 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_C_n5122 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reg_addr_n5123 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n5124 +_4iomodule_h6_6 _4iomodule_h6_6~_BUF_IOREG_n5125 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_B_n5126 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_A_n5127 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_D_n5128 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5129 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_FCLK_OUT_AB_n5130 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_DQS_IN_C_n5131 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_D_n5132 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALP_L_n5133 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_fifo_select_out_chnl_down_n5134 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_tx_data_tc_n5135 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_D_n5136 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IOCSR_DATAOUT_n5137 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_SHORT_L_IN_CLK_n5138 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_C_n5139 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALP_L_n5140 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n5141 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_C_n5142 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_C_n5143 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_fifo_select_out_chnl_down_n5144 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_B_n5145 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_D_n5146 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reg_addr_n5147 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_D_n5148 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALP_L_n5149 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_FCLK_OUT_AB_n5150 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_C_n5151 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_A_n5152 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IC50UA_FTRES_BIDIR_OUT_n5153 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_FPLL0_COUT_n5154 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_LOADEN_OUT_CD_n5155 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_D_n5156 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_D_n5157 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALN_L_n5158 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_csrdout_n5159 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_FCLK_OUT_AB_n5160 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_B_n5161 +_4iomodule8_8 _4iomodule8_8~_IOBUF_DPA_n5162 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_tx_data_tc_n5163 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALP_L_n5164 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_A_n5165 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_LOADEN_OUT_CD_n5166 +_4iomodule15_15 _4iomodule15_15~_IOBUF_DPA_n5167 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_DATX0_n5168 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_FCLK_OUT_AB_n5169 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IC50UA_FTRES_BIDIR_OUT_n5170 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_tx_clk_n5171 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_LOADEN_OUT_CD_n5172 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_L_OUT_CLK_n5173 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_read_n5174 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_DPA_C_n5175 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_mdio_dis_n5176 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_L_OUT_CLK_n5177 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_A_n5178 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_C_n5179 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_B_n5180 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reg_addr_n5181 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_B_n5182 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5183 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_A_n5184 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALP_L_n5185 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_ltr_n5186 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IC50UA_FTRES_BIDIR_OUT_n5187 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_D_n5188 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALN_L_n5189 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLMOUT0_n5190 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_B_n5191 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_C_n5192 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_tx_data_tc_n5193 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_DATX2_n5194 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_pcie_switch_n5195 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALN_L_n5196 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_running_disp_n5197 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_B_n5198 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_D_n5199 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_LOADEN_OUT_AB_n5200 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_nfrzdrv_n5201 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_tx_data_tc_n5202 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_SCHMITT_n5203 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_B_n5204 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n5205 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5206 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_LOADEN_OUT_AB_n5207 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_A_n5208 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_D_n5209 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_SCHMITT_n5210 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_C_n5211 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_tx_clk_n5212 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_C_n5213 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_tx_ctl_tc_n5214 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_pma_reserved_out_n5215 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch0_n5216 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n5217 +_4iomodule10_10 _4iomodule10_10~_INPUT_BUF_n5218 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_C_n5219 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALP_L_n5220 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_L_OUT_CLK_n5221 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_C_n5222 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_D_n5223 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch0_n5224 +_4iomodule_h7_7 _4iomodule_h7_7~_BUF_IOREG_n5225 +_4iomodule10_10 _4iomodule10_10~_INPUT_BUF_n5226 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_DPA_D_n5227 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_C_n5228 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_L_OUT_CLK_n5229 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_D_n5230 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALP_L_n5231 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_DPA_C_n5232 +_4iomodule14_14 _4iomodule14_14~_BSDOUT_n5233 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_DPA_A_n5234 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_D_n5235 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_D_n5236 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_D_n5237 +_4iomodule10_10 _4iomodule10_10~_INPUT_BUF_n5238 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n5239 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_DPA_A_n5240 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_C_n5241 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_D_n5242 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_A_n5243 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_DPA_B_n5244 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_D_n5245 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_B_n5246 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_elec_idle_n5247 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_FPLL0_COUT_n5248 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_pfdmode_lock_n5249 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_agg_sync_status_n5250 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_D_n5251 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_D_n5252 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n5253 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_D_n5254 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_C_n5255 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_FPLL0_COUT_n5256 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_dprio_clk_n5257 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_DPA_D_n5258 +_ioreg16_c53_3 _ioreg16_c53_3~_REGSCANOUT_D_n5259 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n5260 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_D_n5261 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n5262 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_DPA_D_n5263 +_4iomodule_h_c52_2 _4iomodule_h_c52_2~_IOBUF_DPA_n5264 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5265 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_insert_incomplete_0_bot_ch2_n5266 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_DPA_D_n5267 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n5268 +_ioreg16_h3_3 _ioreg16_h3_3~_REGSCANOUT_C_n5269 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_clklow_n5270 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n5271 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_B_n5272 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5273 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5274 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_IOBUF_DPA_n5275 +_4iomodule_c554_54 _4iomodule_c554_54~_INPUT_BUF_n5276 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch1_pma_reserved_out_n5277 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_ppm_lock_n5278 +_ioreg16_c53_3 _ioreg16_c53_3~_REGSCANOUT_A_n5279 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_DPA_B_n5280 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5281 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_LOADEN_OUT_CD_n5282 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_mdio_dis_n5283 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_D_n5284 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_txdetectrx_n5285 +_4iomodule_h_c51_1 _4iomodule_h_c51_1~_IOBUF_DPA_n5286 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_FCLK_OUT_CD_n5287 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5288 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n5289 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch0_n5290 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_D_n5291 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_DPA_D_n5292 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_write_n5293 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_SHORT_L_IN_CLK_n5294 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_detect_valid_n5295 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_B_n5296 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch0_n5297 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n5298 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_LOADEN_OUT_AB_n5299 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n5300 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_B_n5301 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_nfrzdrv_n5302 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BUF_IOREG_n5303 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_FCLK_OUT_AB_n5304 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_LOADEN_OUT_AB_n5305 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_A_n5306 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_t_n5307 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_FCLK_OUT_AB_n5308 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n5309 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_A_n5310 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_D_n5311 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n5312 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_found_n5313 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_data_rs_top_ch0_n5314 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_ppm_lock_n5315 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_A_n5316 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_D_n5317 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n5318 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_detect_valid_n5319 +_ioreg16_c513_13 _ioreg16_c513_13~_REGSCANOUT_D_n5320 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_FCLK_OUT_CD_n5321 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_D_n5322 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_SHORT_L_IN_CLK_n5323 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n5324 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_DPA_C_n5325 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_dprio_scan_mode_n_n5326 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_D_n5327 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_D_n5328 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_D_n5329 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_SHORT_L_IN_CLK_n5330 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_sigdet_n5331 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rxpll_lock_n5332 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_FPLL0_COUT_n5333 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_dprio_rst_n_n5334 +_4iomodule_c55_5 _4iomodule_c55_5~_BUF_IOREG_n5335 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_tx_data_tc_n5336 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_LOADEN_OUT_CD_n5337 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_D_n5338 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_tx_b50_buf_out_n5339 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n5340 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_FPLL0_COUT_n5341 +_4iomodule_h25_25 _4iomodule_h25_25~_INPUT_BUF_n5342 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_OCT_PLLBIASEN_n5343 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n5344 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_DPA_D_n5345 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_tx_data_tc_n5346 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5347 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_D_n5348 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_L_FB_OUT_CLK_n5349 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_D_n5350 +_4iomodule_h25_25 _4iomodule_h25_25~_INPUT_BUF_n5351 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_tx_data_tc_n5352 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n5353 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_L_FB_OUT_CLK_n5354 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_D_n5355 +_4iomodule_h25_25 _4iomodule_h25_25~_INPUT_BUF_n5356 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_D_n5357 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_tx_b50_buf_out_n5358 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5359 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_FCLK_OUT_AB_n5360 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n5361 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_tx_data_tc_n5362 +_4iomodule_h25_25 _4iomodule_h25_25~_INPUT_BUF_n5363 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5364 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n5365 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_DPA_B_n5366 +_4iomodule_c545_45 _4iomodule_c545_45~_BUF_IOREG_n5367 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_sync_status_n5368 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_B_n5369 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_B_n5370 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_C_n5371 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n5372 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5373 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5374 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_tx_ctl_tc_n5375 +_ioreg16_c50_n9 _ioreg16_c50_n9~_LVDS_LOADEN_OUT_CD_n5376 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_DPA_C_n5377 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5378 +_4iomodule9_9 _4iomodule9_9~_INPUT_BUF_n5379 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_tx_b50_buf_out_n5380 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_LOADEN_OUT_CD_n5381 +_4iomodule_c525_25 _4iomodule_c525_25~_INPUT_BUF_n5382 +_ioreg16_c56_6 _ioreg16_c56_6~_CSRDATAOUT_B_n5383 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_FCLK_OUT_AB_n5384 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_DPA_C_n5385 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5386 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_tx_data_tc_n5387 +_4iomodule9_9 _4iomodule9_9~_INPUT_BUF_n5388 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_DPA_C_n5389 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_C_n5390 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5391 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_tx_data_tc_n5392 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_B_n5393 +_4iomodule9_9 _4iomodule9_9~_INPUT_BUF_n5394 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5395 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_C_n5396 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_C_n5397 +_4iomodule9_9 _4iomodule9_9~_INPUT_BUF_n5398 +_4iomodule_c534_34 _4iomodule_c534_34~_INPUT_BUF_n5399 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_C_n5400 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_C_n5401 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5402 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_DPA_C_n5403 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_LOADEN_OUT_AB_n5404 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_tx_data_tc_n5405 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5406 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_C_n5407 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5408 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_B_n5409 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_C_n5410 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_DPA_B_n5411 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_B_n5412 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_ibc50u_bgtx_n5413 +_ioreg16_h6_6 _ioreg16_h6_6~_REGSCANOUT_B_n5414 +_ioreg16_c56_6 _ioreg16_c56_6~_CSRDATAOUT_A_n5415 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_DPA_D_n5416 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_C_n5417 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5418 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_INPUT_BUF_n5419 +_ir_lvl_top8_8 _ir_lvl_top8_8~_CSRDOUT_n5420 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_C_n5421 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5422 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_LOADEN_OUT_CD_n5423 +_ioreg16_c55_5 _ioreg16_c55_5~_REGSCANOUT_C_n5424 +_ioreg16_c513_13 _ioreg16_c513_13~_REGSCANOUT_A_n5425 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5426 +_4iomodule_c54_4 _4iomodule_c54_4~_DATX2_n5427 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_C_n5428 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_tx_data_tc_n5429 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_LOADEN_OUT_CD_n5430 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_D_n5431 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n5432 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_B_n5433 +_4iomodule2_2 _4iomodule2_2~_BSDOUT_n5434 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_B_n5435 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_C_n5436 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_LOADEN_OUT_CD_n5437 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_clk_out_n5438 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_tx_clk_n5439 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_C_n5440 +_ioreg16_c514_14 _ioreg16_c514_14~_REGSCANOUT_A_n5441 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_fifo_ovr_0_top_ch1_n5442 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_C_n5443 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5444 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_DATX1_n5445 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_FBCLK_IN_RO0_n5446 +_ioreg16_h6_6 _ioreg16_h6_6~_LVDS_LOADEN_OUT_CD_n5447 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_ser_shift_load_n5448 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_B_n5449 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_tx_b50_buf_out_n5450 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_D_n5451 +_ioreg16_c510_10 _ioreg16_c510_10~_REGSCANOUT_B_n5452 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_FCLK_OUT_CD_n5453 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_IOREG_BUF_C_n5454 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_C_n5455 +_4iomodule_vref_h1_1 _4iomodule_vref_h1_1~_BSDOUT_n5456 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_B_n5457 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n5458 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_B_n5459 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_CORECLK_RO0_n5460 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_fifo_ovr_0_bot_ch2_n5461 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_pma_reserved_out_n5462 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_en_dskw_rd_ptrs_bot_ch2_n5463 +_4iomodule_h5_5 _4iomodule_h5_5~_INPUT_BUF_n5464 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n5465 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_en_dskw_rd_ptrs_top_ch1_n5466 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_C_n5467 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_en_dskw_rd_ptrs_top_ch0_n5468 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_FCLK_OUT_CD_n5469 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_DPA_B_n5470 +_io_oct_serpar_h0_n24 _io_oct_serpar_h0_n24~_OCTRTCALP_L_n5471 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_C_n5472 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n5473 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_A_n5474 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5475 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n5476 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5477 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_C_n5478 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_IC50UA_FTRES_BIDIR_OUT_n5479 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_DPA_A_n5480 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_pma_reserved_out_n5481 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_C_n5482 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_ibc50u_bgrx_n5483 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5484 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n5485 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_fifo_ovr_0_bot_ch2_n5486 +_ioreg16_c510_10 _ioreg16_c510_10~_REGSCANOUT_C_n5487 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_IT50UA_FTRES_BIDIR_OUT_n5488 +_ioreg16_c51_1 _ioreg16_c51_1~_CSR_DOUT_1_n5489 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n5490 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_DPA_A_n5491 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5492 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_A_n5493 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n5494 +_4iomodule5_5 _4iomodule5_5~_IOBUF_DPA_n5495 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_fifo_rd_out_comp_0_top_ch1_n5496 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_hfclkn_x6_t_dn_out_n5497 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reg_addr_n5498 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n5499 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_B_n5500 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_FCLK_OUT_AB_n5501 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_fifo_ovr_0_top_ch0_n5502 +_cc_clkmuxf_tb1_1 _cc_clkmuxf_tb1_1~_CSRDOUT_n5503 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_SCHMITT_n5504 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_A_n5505 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n5506 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_D_n5507 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n5508 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_C_n5509 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_A_n5510 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n5511 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_tx_b50_buf_out_n5512 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_B_n5513 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_OCT_PLLBIASEN_n5514 +_ioreg16_h3_3 _ioreg16_h3_3~_REGSCANOUT_A_n5515 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_A_n5516 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_A_n5517 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n5518 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n5519 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n5520 +_ioreg16_h0_n7 _ioreg16_h0_n7~_REGSCANOUT_C_n5521 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n5522 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_tx_rd_enable_out_chnl_up_n5523 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_C_n5524 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_A_n5525 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_rx_clk_out_n5526 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n5527 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_LOADEN_OUT_CD_n5528 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_fifo_rst_rd_qd_bot_ch2_n5529 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_C_n5530 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_B_n5531 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n5532 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_tx_div_sync_out_chnl_up_n5533 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_A_n5534 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reg_addr_n5535 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_B_n5536 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_fref_n5537 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n5538 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_A_n5539 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_B_n5540 +_ioreg16_h3_3 _ioreg16_h3_3~_REGSCANOUT_B_n5541 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_A_n5542 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reg_addr_n5543 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_B_n5544 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n5545 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_hclk_pcs_n5546 +_4iomodule7_7 _4iomodule7_7~_IOBUF_DPA_n5547 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_elec_idle_n5548 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_tx_wr_enable_out_chnl_up_n5549 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_A_n5550 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n5551 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_C_n5552 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_FCLK_OUT_AB_n5553 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_ibc50u_bgtx_n5554 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_C_n5555 +_4iomodule_h13_13 _4iomodule_h13_13~_BUF_IOREG_n5556 +_ioreg16_h0_n7 _ioreg16_h0_n7~_REGSCANOUT_D_n5557 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_B_n5558 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_tx_b50_buf_out_n5559 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n5560 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_DPA_B_n5561 +_ioreg16_c54_4 _ioreg16_c54_4~_LVDS_FCLK_OUT_AB_n5562 +_ioreg16_h3_3 _ioreg16_h3_3~_REGSCANOUT_D_n5563 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n5564 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_block_select_n5565 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_C_n5566 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_LOADEN_OUT_AB_n5567 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n5568 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_DPA_B_n5569 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_C_n5570 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n5571 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_writedata_n5572 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_tx_clk_n5573 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_BUF_B_n5574 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_A_n5575 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5576 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n5577 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_DPA_C_n5578 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_SHORT_L_IN_CLK_n5579 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_L_OUT_CLK_n5580 +_4iomodule_c56_6 _4iomodule_c56_6~_INPUT_BUF_n5581 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQS1X_CLK_L_n5582 +_4iomodule3_3 _4iomodule3_3~_IOBUF_DPA_n5583 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n5584 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_B_n5585 +_ioreg16_h0_n7 _ioreg16_h0_n7~_REGSCANOUT_A_n5586 +_4iomodule_h4_4 _4iomodule_h4_4~_INPUT_BUF_n5587 +_4iomodule_h2_2 _4iomodule_h2_2~_BUF_IOREG_n5588 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_C_n5589 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n5590 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_DPA_D_n5591 +_ioreg16_c511_11 _ioreg16_c511_11~_PHYCT_SHORT_R_IN_CLK_n5592 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_b50_buf_out_n5593 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_L_OUT_CLK_n5594 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n5595 +_4iomodule_h4_4 _4iomodule_h4_4~_INPUT_BUF_n5596 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_C_n5597 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5598 +_4iomodule_c53_3 _4iomodule_c53_3~_INPUT_BUF_n5599 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_L_OUT_CLK_n5600 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_L_OUT_CLK_n5601 +_4iomodule_h20_20 _4iomodule_h20_20~_BUF_IOREG_n5602 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_cpulse_x6_t_dn_out_n5603 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_write_n5604 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_C_n5605 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_SHORT_L_IN_CLK_n5606 +_ioreg16_c511_11 _ioreg16_c511_11~_PHYCT_SHORT_R_IN_CLK_n5607 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n5608 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_LOADEN_OUT_AB_n5609 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_L_OUT_CLK_n5610 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_txdetectrx_n5611 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_out_n5612 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n5613 +_ioreg16_h1_1 _ioreg16_h1_1~_PHYCT_L_OUT_CLK_n5614 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5615 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_LOADEN_OUT_AB_n5616 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_L_OUT_CLK_n5617 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_clk_n5618 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n5619 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n5620 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n5621 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_fifo_rd_out_comp_0_bot_ch2_n5622 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5623 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n5624 +_ioreg16_h4_4 _ioreg16_h4_4~_DQS_IN_C_n5625 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_LOADEN_OUT_AB_n5626 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_L_OUT_CLK_n5627 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_out_n5628 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_cpulse_x6_b_dn_out_n5629 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n5630 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_dprio_clk_n5631 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_L_OUT_CLK_n5632 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch1_n5633 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_LOADEN_OUT_AB_n5634 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_L_OUT_CLK_n5635 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_SHORT_L_IN_CLK_n5636 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n5637 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_D_n5638 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n5639 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch1_n5640 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_current_coeff_n5641 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALP_L_n5642 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_L_OUT_CLK_n5643 +_ioreg16_c511_11 _ioreg16_c511_11~_PHYCT_SHORT_R_IN_CLK_n5644 +_4iomodule_c535_35 _4iomodule_c535_35~_INPUT_BUF_n5645 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_C_n5646 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n5647 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_FCLK_OUT_CD_n5648 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALP_L_n5649 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5650 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_B_n5651 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n5652 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_L_OUT_CLK_n5653 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5654 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n5655 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_LOADEN_OUT_AB_n5656 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_B_n5657 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_FCLK_OUT_CD_n5658 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch2_pma_writedata_n5659 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch1_n5660 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_L_OUT_CLK_n5661 +_4iomodule_c56_6 _4iomodule_c56_6~_INPUT_BUF_n5662 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_tx_ctl_tc_n5663 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n5664 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_DPA_D_n5665 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_FCLK_OUT_CD_n5666 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_b50_buf_out_n5667 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch1_n5668 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_DPA_A_n5669 +_4iomodule_c535_35 _4iomodule_c535_35~_INPUT_BUF_n5670 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_L_OUT_CLK_n5671 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5672 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_B_n5673 +_4iomodule_h24_24 _4iomodule_h24_24~_BUF_IOREG_n5674 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_B_n5675 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_FCLK_OUT_CD_n5676 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n5677 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_DPA_A_n5678 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_A_n5679 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_sigdet_n5680 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_tx_data_tc_n5681 +_4iomodule_c56_6 _4iomodule_c56_6~_INPUT_BUF_n5682 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_D_n5683 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_byte_en_n5684 +_ioreg16_c511_11 _ioreg16_c511_11~_PHYCT_SHORT_R_IN_CLK_n5685 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n5686 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_FCLK_OUT_CD_n5687 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rxpll_lock_n5688 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_SHORT_L_IN_CLK_n5689 +_4iomodule_c535_35 _4iomodule_c535_35~_INPUT_BUF_n5690 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_D_n5691 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_FBCLK_IN_LO0_n5692 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch1_n5693 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n5694 +_4iomodule_c53_3 _4iomodule_c53_3~_INPUT_BUF_n5695 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_fifo_rst_rd_qd_top_ch1_n5696 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_b50_buf_out_n5697 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_FCLK_OUT_AB_n5698 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_A_n5699 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_found_n5700 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5701 +_4iomodule_h0_n8 _4iomodule_h0_n8~_BUF_IOREG_n5702 +_4iomodule4_4 _4iomodule4_4~_BSDOUT_n5703 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_A_n5704 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_B_n5705 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_C_n5706 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_C_n5707 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_tx_data_tc_n5708 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n5709 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n5710 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5711 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n5712 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_align_status_bot_ch2_n5713 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_LOADEN_OUT_CD_n5714 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_LOADEN_OUT_CD_n5715 +_4iomodule_c553_53 _4iomodule_c553_53~_BUF_IOREG_n5716 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_C_n5717 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_R_OUT_CLK_n5718 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_B_n5719 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n5720 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_align_status_sync_0_bot_ch2_n5721 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_LOADEN_OUT_CD_n5722 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_tx_data_ts_top_ch1_n5723 +_4iomodule_h4_4 _4iomodule_h4_4~_BUF_IOREG_n5724 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_DPA_A_n5725 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5726 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n5727 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_LVDS_CLK0_n5728 +_ioreg16_c58_8 _ioreg16_c58_8~_LVDS_LOADEN_OUT_CD_n5729 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5730 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_A_n5731 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_R_OUT_CLK_n5732 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5733 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n5734 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_del_cond_met_0_bot_ch2_n5735 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n5736 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_rxclkslip_n5737 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_insert_incomplete_0_bot_ch2_n5738 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_FCLK_OUT_CD_n5739 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n5740 +_ioreg16_c56_6 _ioreg16_c56_6~_CSRDATAOUT_C_n5741 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_B_n5742 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_LOADEN_OUT_CD_n5743 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n5744 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_cg_comp_rd_d_all_bot_ch2_n5745 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_ser_shift_load_n5746 +_ioreg16_c514_14 _ioreg16_c514_14~_REGSCANOUT_D_n5747 +_ioreg16_c51_1 _ioreg16_c51_1~_CSRDATAOUT_A_n5748 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_insert_incomplete_0_top_ch1_n5749 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n5750 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5751 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_B_n5752 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_rxpma_rstb_n5753 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n5754 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_cg_comp_wr_all_bot_ch2_n5755 +_ioreg16_c51_1 _ioreg16_c51_1~_CSRDATAOUT_B_n5756 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n5757 +_4iomodule_c535_35 _4iomodule_c535_35~_INPUT_BUF_n5758 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_tx_data_n5759 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_latency_comp_0_top_ch0_n5760 +_ioreg16_c51_1 _ioreg16_c51_1~_CSRDATAOUT_C_n5761 +_4iomodule_c55_5 _4iomodule_c55_5~_IOBUF_DPA_n5762 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n5763 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_ser_shift_load_n5764 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_ctl_rs_bot_ch2_n5765 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_D_n5766 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_rxpma_rstb_n5767 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n5768 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_insert_incomplete_0_top_ch0_n5769 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5770 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_B_n5771 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_FBCLK_IN_LO0_n5772 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_rx_b50_buf_out_n5773 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n5774 +_4iomodule_c539_39 _4iomodule_c539_39~_IOBUF_DPA_n5775 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_latency_comp_0_top_ch1_n5776 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_B_n5777 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_latency_comp_0_bot_ch2_n5778 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_C_n5779 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n5780 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n5781 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5782 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5783 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n5784 +_4iomodule_c510_10 _4iomodule_c510_10~_IOBUF_DPA_n5785 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALP_L_n5786 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rcvd_clk_out_top_n5787 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_R_OUT_CLK_n5788 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n5789 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n5790 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_OCTRTCALP_L_n5791 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_data_n5792 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_LVDS_CLK0_n5793 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_A_n5794 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5795 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_readdata_n5796 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_agg_tx_data_tc_n5797 +_4iomodule_h12_12 _4iomodule_h12_12~_BUF_IOREG_n5798 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5799 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_ibc50u_bgrx_n5800 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_b50_buf_out_n5801 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_R_OUT_CLK_n5802 +_4iomodule_c56_6 _4iomodule_c56_6~_INPUT_BUF_n5803 +_ioreg16_h2_2 _ioreg16_h2_2~_PHYCT_R_OUT_CLK_n5804 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5805 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_dprio_rst_n_n5806 +_ioreg16_c51_1 _ioreg16_c51_1~_CSRDATAOUT_D_n5807 +_ioreg16_h3_3 _ioreg16_h3_3~_DQS_IN_C_n5808 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_b_a_n5809 +_4iomodule_c528_28 _4iomodule_c528_28~_INPUT_BUF_n5810 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5811 +_ioreg16_c59_9 _ioreg16_c59_9~_PHYCT_SHORT_R_IN_CLK_n5812 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reg_addr_n5813 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQS1X_CLK_L_n5814 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_D_n5815 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_pcie_switch_n5816 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5817 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_LOADEN_OUT_CD_n5818 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reg_addr_n5819 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_dprio_scan_shift_n_n5820 +_4iomodule_c527_27 _4iomodule_c527_27~_DATX3_n5821 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_b50_buf_out_n5822 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQS_2X_CLK_L_n5823 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_SHORT_R_IN_CLK_n5824 +_ioreg16_c513_13 _ioreg16_c513_13~_IOREG_BUF_D_n5825 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_LOADEN_OUT_AB_n5826 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_rx_ctl_rs_top_ch0_n5827 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_C_n5828 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_b50_buf_out_n5829 +_4iomodule_h5_5 _4iomodule_h5_5~_BUF_IOREG_n5830 +_4iomodule_c528_28 _4iomodule_c528_28~_INPUT_BUF_n5831 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_DPACLK0_I_n5832 +_4iomodule_c527_27 _4iomodule_c527_27~_SCHMITT_n5833 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_B_n5834 +_ioreg16_c59_9 _ioreg16_c59_9~_PHYCT_SHORT_R_IN_CLK_n5835 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_A_n5836 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5837 +_ir_lvl_top0_n20 _ir_lvl_top0_n20~_DQS1X_CLK_L_n5838 +_4iomodule_h_c53_3 _4iomodule_h_c53_3~_IOBUF_DPA_n5839 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_t_n5840 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_DPACLK0_I_n5841 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_LOADEN_OUT_CD_n5842 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_early_eios_n5843 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_speed_change_out_chnl_down_n5844 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5845 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_D_n5846 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_rx_wr_enable_out_chnl_down_n5847 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_t_n5848 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_DPACLK0_I_n5849 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_DPA_A_n5850 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_LOADEN_OUT_AB_n5851 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ref_iqclk_t_n5852 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_rx_we_out_chnl_down_n5853 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_DPA_C_n5854 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_DPA_B_n5855 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_DPA_C_n5856 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_refclk_ffpll_n5857 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reg_addr_n5858 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_clk_out_n5859 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_LOADEN_OUT_AB_n5860 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_ibc50u_bgtx_n5861 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_byte_en_n5862 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_DPA_C_n5863 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_A_n5864 +_4iomodule_c547_47 _4iomodule_c547_47~_INPUT_BUF_n5865 +_4iomodule_c516_16 _4iomodule_c516_16~_IOBUF_DPA_n5866 +_ioreg16_h5_5 _ioreg16_h5_5~_REGSCANOUT_A_n5867 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_A_n5868 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5869 +_4iomodule_c547_47 _4iomodule_c547_47~_INPUT_BUF_n5870 +_4iomodule_c550_50 _4iomodule_c550_50~_IOBUF_DPA_n5871 +_4iomodule_h25_25 _4iomodule_h25_25~_BSDOUT_n5872 +_4iomodule_h3_3 _4iomodule_h3_3~_BUF_IOREG_n5873 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_ibc50u_bgtx_n5874 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_B_n5875 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_C_n5876 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5877 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_elec_idle_n5878 +_4iomodule_c53_3 _4iomodule_c53_3~_INPUT_BUF_n5879 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_B_n5880 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_ibc50u_bgrx_n5881 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_dprio_scan_mode_n_n5882 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_current_coeff_n5883 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_dec_data_n5884 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_A_n5885 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_A_n5886 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_L_OUT_CLK_n5887 +_4iomodule_c53_3 _4iomodule_c53_3~_INPUT_BUF_n5888 +_4iomodule_c553_53 _4iomodule_c553_53~_IOBUF_DPA_n5889 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_ibc50u_bgtx_n5890 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_dec_data_n5891 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_ltr_n5892 +_ioreg16_c59_9 _ioreg16_c59_9~_PHYCT_SHORT_R_IN_CLK_n5893 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_B_n5894 +_4iomodule_c51_1 _4iomodule_c51_1~_IOBUF_DPA_n5895 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_ibc50u_bgrx_n5896 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reg_addr_n5897 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5898 +_ioreg16_c56_6 _ioreg16_c56_6~_CSRDATAOUT_D_n5899 +_4iomodule_c58_8 _4iomodule_c58_8~_IOBUF_DPA_n5900 +_4iomodule_c528_28 _4iomodule_c528_28~_INPUT_BUF_n5901 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reg_addr_n5902 +_4iomodule_c530_30 _4iomodule_c530_30~_IOBUF_DPA_n5903 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5904 +_ioreg16_c512_12 _ioreg16_c512_12~_CSRDATAOUT_A_n5905 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_OUT_STAGE_A1L_n5906 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_DPA_C_n5907 +_4iomodule_c52_2 _4iomodule_c52_2~_IOBUF_DPA_n5908 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_DPA_D_n5909 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reg_addr_n5910 +_4iomodule_c547_47 _4iomodule_c547_47~_INPUT_BUF_n5911 +_4iomodule_c527_27 _4iomodule_c527_27~_SCHMITT_n5912 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5913 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_dec_data_n5914 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_C_n5915 +_ioreg16_c59_9 _ioreg16_c59_9~_PHYCT_SHORT_R_IN_CLK_n5916 +_4iomodule_c547_47 _4iomodule_c547_47~_INPUT_BUF_n5917 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n5918 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_B_n5919 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_C_n5920 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_dec_data_n5921 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n5922 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_DPA_A_n5923 +_4iomodule_h_c50_n11 _4iomodule_h_c50_n11~_IOBUF_DPA_n5924 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5925 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_dec_data_n5926 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_C_n5927 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_ibc50u_bgrx_n5928 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_DPACLK0_I_n5929 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_DPA_D_n5930 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_SHORT_R_IN_CLK_n5931 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_D_n5932 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n5933 +_ioreg16_c59_9 _ioreg16_c59_9~_PHYCT_SHORT_R_IN_CLK_n5934 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n5935 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n5936 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_dec_data_n5937 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_D_n5938 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_DPACLK0_I_n5939 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n5940 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n5941 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_D_n5942 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_cg_comp_wr_out_n5943 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5944 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_DPA_C_n5945 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_D_n5946 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_SHORT_R_IN_CLK_n5947 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_B_n5948 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n5949 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_txdetectrx_n5950 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_pma_so_n5951 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_dec_ctl_n5952 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5953 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_C_n5954 +_ioreg16_h2_2 _ioreg16_h2_2~_DQS_IN_C_n5955 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_D_n5956 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_C_n5957 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_D_n5958 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_write_n5959 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_pma_so_n5960 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_dec_data_n5961 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5962 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n5963 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_L_OUT_CLK_n5964 +_ioreg16_c59_9 _ioreg16_c59_9~_PHYCT_SHORT_R_IN_CLK_n5965 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n5966 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_C_n5967 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n5968 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_pma_so_n5969 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5970 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_agg_dec_data_n5971 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_C_n5972 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_A_n5973 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_FCLK_OUT_AB_n5974 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_ibc50u_bgrx_n5975 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n5976 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_rcvd_clk_out_bot_n5977 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_BUF_C_n5978 +_ir_lvl_top1_1 _ir_lvl_top1_1~_DQS_2X_CLK_R_n5979 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_FCLK_OUT_AB_n5980 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_LOADEN_OUT_CD_n5981 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_rx_data_n5982 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n5983 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_tx_b50_buf_out_n5984 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_FCLK_OUT_AB_n5985 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n5986 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_L_OUT_CLK_n5987 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_t_a_n5988 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_out_n5989 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_FCLK_OUT_AB_n5990 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n5991 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_C_n5992 +_ioreg16_c512_12 _ioreg16_c512_12~_PHYCT_SHORT_R_IN_CLK_n5993 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_t_a_n5994 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_out_n5995 +_ioreg16_c52_2 _ioreg16_c52_2~_LVDS_FCLK_OUT_AB_n5996 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_C_n5997 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n5998 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n5999 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_L_OUT_CLK_n6000 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_read_n6001 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_DPA_B_n6002 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_readdata_n6003 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n6004 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reg_addr_n6005 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_FCLK_OUT_CD_n6006 +_4iomodule_c528_28 _4iomodule_c528_28~_INPUT_BUF_n6007 +_ioreg16_c56_6 _ioreg16_c56_6~_PHYCT_L_OUT_CLK_n6008 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_t_a_n6009 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_D_n6010 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_ibc50u_bgtx_n6011 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_FCLK_OUT_CD_n6012 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_FCLK_OUT_AB_n6013 +_ioreg16_c511_11 _ioreg16_c511_11~_PHYCT_SHORT_R_IN_CLK_n6014 +_4iomodule_c526_26 _4iomodule_c526_26~_IOBUF_DPA_n6015 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_readdata_n6016 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n6017 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_pma_writedata_n6018 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_tx_b50_buf_out_n6019 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_tx_b50_buf_out_n6020 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_D_n6021 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_DPACLK0_I_n6022 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_FCLK_OUT_AB_n6023 +_4iomodule_c529_29 _4iomodule_c529_29~_IOBUF_DPA_n6024 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch1_pma_tx_data_n6025 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_FCLK_OUT_AB_n6026 +_ioreg16_c57_7 _ioreg16_c57_7~_IOREG_DPA_C_n6027 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n6028 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_rx_iqclk_ffpll_n6029 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_DPA_C_n6030 +_4iomodule_c514_14 _4iomodule_c514_14~_INPUT_BUF_n6031 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n6032 +_ioreg16_h_c52_2 _ioreg16_h_c52_2~_LVDS_FCLK_OUT_AB_n6033 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_align_det_sync_n6034 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_B_n6035 +_4iomodule_c527_27 _4iomodule_c527_27~_SCHMITT_n6036 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n6037 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_DPA_C_n6038 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_FCLK_OUT_AB_n6039 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_D_n6040 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_clk_n6041 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_LOADEN_OUT_CD_n6042 +_4iomodule_c533_33 _4iomodule_c533_33~_SCHMITT_n6043 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6044 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLMOUT0_n6045 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_TC_BO_BIDIR_OUT_n6046 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n6047 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_PHYCT_SHORT_L_IN_CLK_n6048 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n6049 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_LVDS_LOADEN_OUT_CD_n6050 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_FCLK_OUT_AB_n6051 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6052 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_txdetectrx_n6053 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_align_status_sync_n6054 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQ_CLK_L_n6055 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_C_n6056 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n6057 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_elec_idle_n6058 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_CORECLK_RO0_n6059 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n6060 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n6061 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_C_n6062 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n6063 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6064 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_A_n6065 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_FCLK_OUT_CD_n6066 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n6067 +_ioreg16_c510_10 _ioreg16_c510_10~_REGSCANOUT_D_n6068 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n6069 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_align_det_sync_n6070 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_C_n6071 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n6072 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n6073 +_ioreg16_c59_9 _ioreg16_c59_9~_LVDS_FCLK_OUT_AB_n6074 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6075 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_b50_buf_out_n6076 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_write_n6077 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n6078 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6079 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n6080 +_4iomodule_c527_27 _4iomodule_c527_27~_DATX2_n6081 +_4iomodule_c533_33 _4iomodule_c533_33~_DATX2_n6082 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n6083 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n6084 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_OUT_STAGE_A1R_n6085 +_4iomodule_c57_7 _4iomodule_c57_7~_BUF_IOREG_n6086 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n6087 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_A_n6088 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_A_n6089 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6090 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_A_n6091 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6092 +_ioreg16_c510_10 _ioreg16_c510_10~_CSRDATAOUT_B_n6093 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_A_n6094 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6095 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_tx_data_ts_bot_ch2_n6096 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_writedata_n6097 +_ioreg16_c510_10 _ioreg16_c510_10~_CSRDATAOUT_A_n6098 +_4iomodule_c543_43 _4iomodule_c543_43~_IOBUF_DPA_n6099 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_A_n6100 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n6101 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_A_n6102 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_tx_data_ts_bot_ch2_n6103 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_A_n6104 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_reg_addr_n6105 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_C_n6106 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6107 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_IT50UA_FTRES_BIDIR_OUT_n6108 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n6109 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6110 +_ir_lvl_top8_8 _ir_lvl_top8_8~_HR_CLK_L_n6111 +_ioreg16_c53_3 _ioreg16_c53_3~_REGSCANOUT_B_n6112 +_ioreg16_c59_9 _ioreg16_c59_9~_CSRDATAOUT_D_n6113 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n6114 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6115 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQS1X_CLK_L_n6116 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6117 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n6118 +_im_sysclk3_3 _im_sysclk3_3~_CSRDOUT_n6119 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n6120 +_ir_lvl_top8_8 _ir_lvl_top8_8~_DQS1X_CLK_L_n6121 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n6122 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_ibc50u_bgtx_n6123 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_A_n6124 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n6125 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n6126 +_ioreg16_c510_10 _ioreg16_c510_10~_REGSCANOUT_A_n6127 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_C_n6128 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_A_n6129 +_4iomodule14_14 _4iomodule14_14~_INPUT_BUF_n6130 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_tx_b50_buf_out_n6131 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n6132 +_ioreg16_c514_14 _ioreg16_c514_14~_REGSCANOUT_C_n6133 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_tx_div_sync_out_chnl_up_n6134 +_4iomodule_c514_14 _4iomodule_c514_14~_INPUT_BUF_n6135 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_t_n6136 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_C_n6137 +_4iomodule14_14 _4iomodule14_14~_INPUT_BUF_n6138 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n6139 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_b_a_n6140 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_C_n6141 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_A_n6142 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6143 +_4iomodule_c514_14 _4iomodule_c514_14~_INPUT_BUF_n6144 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n6145 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_b_a_n6146 +_4iomodule_h22_22 _4iomodule_h22_22~_INPUT_BUF_n6147 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n6148 +_4iomodule_c514_14 _4iomodule_c514_14~_INPUT_BUF_n6149 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_t_n6150 +_4iomodule_h22_22 _4iomodule_h22_22~_INPUT_BUF_n6151 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_refclk_ffpll_n6152 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6153 +_4iomodule_c535_35 _4iomodule_c535_35~_BUF_IOREG_n6154 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_B_n6155 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_A_n6156 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_BUF_B_n6157 +_ioreg16_c58_8 _ioreg16_c58_8~_PHYCT_SHORT_R_IN_CLK_n6158 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n6159 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n6160 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_n6161 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_B_n6162 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n6163 +_ioreg16_c52_2 _ioreg16_c52_2~_IOREG_BUF_C_n6164 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_n6165 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_tx_b50_buf_out_n6166 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n6167 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_IC50UA_FTRES_BIDIR_OUT_n6168 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_B_n6169 +_4iomodule_c548_48 _4iomodule_c548_48~_BUF_IOREG_n6170 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6171 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n6172 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_A_n6173 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_b50_buf_out_n6174 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_ibc200u_bgtx_n6175 +_4iomodule_c525_25 _4iomodule_c525_25~_INPUT_BUF_n6176 +_ioreg16_c50_n9 _ioreg16_c50_n9~_IOREG_BUF_D_n6177 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_B_n6178 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_rx_data_n6179 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_A_n6180 +_4iomodule_c59_9 _4iomodule_c59_9~_INPUT_BUF_n6181 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n6182 +_4iomodule_c539_39 _4iomodule_c539_39~_BUF_IOREG_n6183 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_tx_b50_buf_out_n6184 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n6185 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6186 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_QN_n6187 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n6188 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6189 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6190 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_A_n6191 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_A_n6192 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n6193 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_DPA_A_n6194 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n6195 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6196 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n6197 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_A_n6198 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n6199 +_ioreg16_h6_6 _ioreg16_h6_6~_IOREG_DPA_A_n6200 +_4iomodule_c527_27 _4iomodule_c527_27~_DATX0_n6201 +_4iomodule_c533_33 _4iomodule_c533_33~_DATX3_n6202 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n6203 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n6204 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_A_n6205 +_ioreg16_c513_13 _ioreg16_c513_13~_PHYCT_SHORT_R_IN_CLK_n6206 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n6207 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_QN_n6208 +_4iomodule_c52_2 _4iomodule_c52_2~_BUF_IOREG_n6209 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n6210 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_DPA_A_n6211 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6212 +_4iomodule_h16_16 _4iomodule_h16_16~_INPUT_BUF_n6213 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n6214 +_4iomodule_h22_22 _4iomodule_h22_22~_INPUT_BUF_n6215 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_t_n6216 +_4iomodule_c59_9 _4iomodule_c59_9~_INPUT_BUF_n6217 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6218 +_4iomodule_c59_9 _4iomodule_c59_9~_INPUT_BUF_n6219 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_QN_n6220 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n6221 +_4iomodule_h22_22 _4iomodule_h22_22~_INPUT_BUF_n6222 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ref_iqclk_t_n6223 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n6224 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reg_addr_n6225 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6226 +_4iomodule_c59_9 _4iomodule_c59_9~_INPUT_BUF_n6227 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_b50_buf_out_n6228 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n6229 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n6230 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6231 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6232 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_b50_buf_out_n6233 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6234 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n6235 +_4iomodule_h16_16 _4iomodule_h16_16~_INPUT_BUF_n6236 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_dec_data_n6237 +_4iomodule_h19_19 _4iomodule_h19_19~_BUF_IOREG_n6238 +_4iomodule_c555_55 _4iomodule_c555_55~_SCHMITT_n6239 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n6240 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n6241 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6242 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_b50_buf_out_n6243 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_A_n6244 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n6245 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_dec_data_n6246 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_rxclkslip_n6247 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_A_n6248 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_ibc200u_bgtx_n6249 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_SHORT_L_IN_CLK_n6250 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_A_n6251 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n6252 +_4iomodule_c555_55 _4iomodule_c555_55~_SCHMITT_n6253 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_pma_reserved_out_n6254 +_ioreg16_h0_n7 _ioreg16_h0_n7~_IOREG_BUF_A_n6255 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6256 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_rx_clk_out_n6257 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_dec_data_n6258 +_4iomodule_c533_33 _4iomodule_c533_33~_SCHMITT_n6259 +_4iomodule_c550_50 _4iomodule_c550_50~_BUF_IOREG_n6260 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reserved_out_n6261 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_SHORT_L_IN_CLK_n6262 +_4iomodule_c548_48 _4iomodule_c548_48~_INPUT_BUF_n6263 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_B_n6264 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_pma_reserved_out_n6265 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6266 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6267 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_rx_b50_buf_out_n6268 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_dec_data_n6269 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n6270 +_ioreg16_c58_8 _ioreg16_c58_8~_PHYCT_SHORT_R_IN_CLK_n6271 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IOCSR_DATAOUT_n6272 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reserved_out_n6273 +_4iomodule_c548_48 _4iomodule_c548_48~_INPUT_BUF_n6274 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_B_n6275 +_4iomodule_c533_33 _4iomodule_c533_33~_SCHMITT_n6276 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_dec_ctl_n6277 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n6278 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n6279 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_SHORT_L_IN_CLK_n6280 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_ibc200u_bgtx_n6281 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n6282 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_A_n6283 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_pma_reserved_out_n6284 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n6285 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_ibc200u_bgtx_n6286 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_clk_out_n6287 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6288 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_B_n6289 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_dec_data_n6290 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n6291 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n6292 +_ioreg16_c52_2 _ioreg16_c52_2~_DQS_IN_C_n6293 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_C_n6294 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6295 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n6296 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_cg_comp_wr_out_n6297 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_A_n6298 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n6299 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n6300 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n6301 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n6302 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_C_n6303 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n6304 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6305 +_ioreg16_c58_8 _ioreg16_c58_8~_PHYCT_SHORT_R_IN_CLK_n6306 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_DPA_B_n6307 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_SHORT_L_IN_CLK_n6308 +_ioreg16_c56_6 _ioreg16_c56_6~_IOREG_BUF_A_n6309 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n6310 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_A_n6311 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6312 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n6313 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6314 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_IOREG_DPA_B_n6315 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n6316 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n6317 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n6318 +_4iomodule_c56_6 _4iomodule_c56_6~_BUF_IOREG_n6319 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_A_n6320 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n6321 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6322 +_4iomodule_c540_40 _4iomodule_c540_40~_INPUT_BUF_n6323 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_FCLK_OUT_CD_n6324 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n6325 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_DPA_A_n6326 +_4iomodule_c548_48 _4iomodule_c548_48~_INPUT_BUF_n6327 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6328 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6329 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_cg_comp_wr_out_n6330 +_ioreg16_h4_4 _ioreg16_h4_4~_IOREG_BUF_A_n6331 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n6332 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_n6333 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IT50UA_FT_BIDIR_OUT_n6334 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6335 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reserved_out_n6336 +_4iomodule_c533_33 _4iomodule_c533_33~_DATX0_n6337 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6338 +_ioreg16_c58_8 _ioreg16_c58_8~_PHYCT_SHORT_R_IN_CLK_n6339 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n6340 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n6341 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_C_n6342 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IC50UA_FT_BIDIR_OUT_n6343 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_B_n6344 +_4iomodule_c540_40 _4iomodule_c540_40~_INPUT_BUF_n6345 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6346 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6347 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_reg_addr_n6348 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_cg_comp_rd_d_out_n6349 +_ioreg16_c58_8 _ioreg16_c58_8~_PHYCT_SHORT_R_IN_CLK_n6350 +_ioreg16_c57_7 _ioreg16_c57_7~_LVDS_FCLK_OUT_CD_n6351 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_tx_b50_buf_out_n6352 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_C_n6353 +_ioreg16_c58_8 _ioreg16_c58_8~_PHYCT_SHORT_R_IN_CLK_n6354 +_4iomodule_c533_33 _4iomodule_c533_33~_DATX1_n6355 +_4iomodule_c520_20 _4iomodule_c520_20~_IOBUF_DPA_n6356 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_IT50UA_FT_BIDIR_OUT_n6357 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_B_n6358 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_SHORT_L_IN_CLK_n6359 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6360 +_ioreg16_c58_8 _ioreg16_c58_8~_PHYCT_SHORT_R_IN_CLK_n6361 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6362 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_n6363 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_B_n6364 +_4iomodule_c559_59 _4iomodule_c559_59~_INPUT_BUF_n6365 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n6366 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_B_n6367 +_4iomodule_c54_4 _4iomodule_c54_4~_BUF_IOREG_n6368 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6369 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_agg_cg_comp_rd_d_out_n6370 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6371 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_B_n6372 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_FBCLK_IN_LO0_n6373 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_n6374 +_4iomodule_c559_59 _4iomodule_c559_59~_INPUT_BUF_n6375 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_L_OUT_CLK_n6376 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_C_n6377 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_FBCLK_IN_RO0_n6378 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n6379 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_out_n6380 +_ioreg16_h3_3 _ioreg16_h3_3~_IOREG_BUF_B_n6381 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_out_n6382 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6383 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_n6384 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_B_n6385 +_4iomodule_c541_41 _4iomodule_c541_41~_BUF_IOREG_n6386 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n6387 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_n6388 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_writedata_n6389 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_t_a_n6390 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_IC50UA_FTRES_BIDIR_OUT_n6391 +_4iomodule14_14 _4iomodule14_14~_INPUT_BUF_n6392 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_C_n6393 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_out_n6394 +_4iomodule_c525_25 _4iomodule_c525_25~_BUF_IOREG_n6395 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_C_n6396 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_block_select_n6397 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_C_n6398 +_ioreg16_c54_4 _ioreg16_c54_4~_PHYCT_L_OUT_CLK_n6399 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_IT50UA_FTRES_BIDIR_OUT_n6400 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_C_n6401 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_C_n6402 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n6403 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_IT50UA_FT_BIDIR_OUT_n6404 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_IT50UA_FTRES_BIDIR_OUT_n6405 +_4iomodule14_14 _4iomodule14_14~_INPUT_BUF_n6406 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n6407 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_D_n6408 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n6409 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_IT50UA_FTRES_BIDIR_OUT_n6410 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_tx_clk_n6411 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_D_n6412 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch0_ibc200u_bgtx_n6413 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6414 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n6415 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n6416 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch1_ibc200u_bgtx_n6417 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_D_n6418 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n6419 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6420 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_FBCLK_IN_RO0_n6421 +_4iomodule_c519_19 _4iomodule_c519_19~_INPUT_BUF_n6422 +_4iomodule_c559_59 _4iomodule_c559_59~_IOBUF_DPA_n6423 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n6424 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch1_ibc200u_bgtx_n6425 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6426 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_D_n6427 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n6428 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n6429 +_4iomodule_c519_19 _4iomodule_c519_19~_IOBUF_DPA_n6430 +_ioreg16_c52_2 _ioreg16_c52_2~_PHYCT_SHORT_L_IN_CLK_n6431 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_D_n6432 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6433 +_4iomodule_c555_55 _4iomodule_c555_55~_DATX2_n6434 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n6435 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch2_ibc200u_bgtx_n6436 +_4iomodule_c519_19 _4iomodule_c519_19~_INPUT_BUF_n6437 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_out_n6438 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6439 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n6440 +_4iomodule_c519_19 _4iomodule_c519_19~_INPUT_BUF_n6441 +_4iomodule_c548_48 _4iomodule_c548_48~_IOBUF_DPA_n6442 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_rx_data_n6443 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_C_n6444 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6445 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_A_n6446 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n6447 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_C_n6448 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_tx_b50_buf_out_n6449 +_4iomodule_c559_59 _4iomodule_c559_59~_INPUT_BUF_n6450 +_4iomodule8_8 _4iomodule8_8~_INPUT_BUF_n6451 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6452 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_A_n6453 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_R_n6454 +_pm_pma3_bot_c51_1 _pm_pma3_bot_c51_1~_ch0_readdata_n6455 +_4iomodule_c559_59 _4iomodule_c559_59~_INPUT_BUF_n6456 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch0_ibc200u_bgtx_n6457 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_D_n6458 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_R_n6459 +_4iomodule_c54_4 _4iomodule_c54_4~_IOBUF_DPA_n6460 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_fifo_rd_out_comp_0_bot_ch2_n6461 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6462 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_hfclkp_xn_dn_out_n6463 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLDOUT0_n6464 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_D_n6465 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6466 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_hclk_top_n6467 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n6468 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_D_n6469 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6470 +_4iomodule8_8 _4iomodule8_8~_INPUT_BUF_n6471 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6472 +_ioreg16_c511_11 _ioreg16_c511_11~_IOREG_BUF_D_n6473 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_R_n6474 +_4iomodule_c543_43 _4iomodule_c543_43~_INPUT_BUF_n6475 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_OCTRZQP_n6476 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_lfclkn_x6_t_dn_out_n6477 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_BUF_D_n6478 +_4iomodule_c58_8 _4iomodule_c58_8~_BUF_IOREG_n6479 +_4iomodule_c516_16 _4iomodule_c516_16~_BUF_IOREG_n6480 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_FCLK_OUT_AB_n6481 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_hfclkp_xn_up_out_n6482 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_D_n6483 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_OCTRZQP_n6484 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_lfclkn_x6_b_dn_out_n6485 +_ioreg16_c55_5 _ioreg16_c55_5~_IOREG_BUF_D_n6486 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_FCLK_OUT_AB_n6487 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_FCLK_OUT_AB_n6488 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_D_n6489 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n6490 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_fifo_rst_rd_qd_top_ch0_n6491 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_D_n6492 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n6493 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n6494 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_iqtxrxclk_t_n6495 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_agg_fifo_rd_out_comp_0_top_ch0_n6496 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_L_n6497 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n6498 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_DPA_D_n6499 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n6500 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_OCT_PLLBIASEN_n6501 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n6502 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_L_n6503 +_ioreg16_c514_14 _ioreg16_c514_14~_IOREG_DPA_D_n6504 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_LOADEN_OUT_CD_n6505 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n6506 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_FCLK_OUT_CD_n6507 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_L_n6508 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n6509 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n6510 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n6511 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_B_n6512 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_OCTRZQP_n6513 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_L_n6514 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_DPA_B_n6515 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n6516 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_C_n6517 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n6518 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_FCLK_OUT_AB_n6519 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_FCLK_OUT_AB_n6520 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_B_n6521 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n6522 +_4iomodule_c519_19 _4iomodule_c519_19~_INPUT_BUF_n6523 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_B_n6524 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_C_n6525 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n6526 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_DPA_B_n6527 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_FCLK_OUT_CD_n6528 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_C_n6529 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_LOADEN_OUT_CD_n6530 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_DPA_D_n6531 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_running_disp_n6532 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_B_n6533 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_D_n6534 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_C_n6535 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_ch0_agg_running_disp_n6536 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_LOADEN_OUT_AB_n6537 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n6538 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_C_n6539 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_DATX2_n6540 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6541 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n6542 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n6543 +_4iomodule_h18_18 _4iomodule_h18_18~_BUF_IOREG_n6544 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_B_n6545 +_4iomodule_c514_14 _4iomodule_c514_14~_BUF_IOREG_n6546 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n6547 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n6548 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_D_n6549 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n6550 +_ioreg16_c58_8 _ioreg16_c58_8~_IOREG_BUF_B_n6551 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_BUF_B_n6552 +_ioreg16_c512_12 _ioreg16_c512_12~_DQS_IN_C_n6553 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_tx_data_n6554 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n6555 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_LOADEN_OUT_CD_n6556 +_4iomodule_c522_22 _4iomodule_c522_22~_BUF_IOREG_n6557 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_pma_reserved_out_n6558 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IT50UA_FTRES_BIDIR_OUT_n6559 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_LOADEN_OUT_AB_n6560 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n6561 +_4iomodule_c543_43 _4iomodule_c543_43~_INPUT_BUF_n6562 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IT50UA_FTRES_BIDIR_OUT_n6563 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n6564 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_writedata_n6565 +_4iomodule_c543_43 _4iomodule_c543_43~_INPUT_BUF_n6566 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n6567 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n6568 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IT50UA_FTRES_BIDIR_OUT_n6569 +_4iomodule_c543_43 _4iomodule_c543_43~_INPUT_BUF_n6570 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n6571 +_4iomodule_h16_16 _4iomodule_h16_16~_INPUT_BUF_n6572 +_smrt_smrtpack0_n5 _smrt_smrtpack0_n5~_ch2_pma_tx_data_n6573 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_DPA_A_n6574 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_LOADEN_OUT_AB_n6575 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_B_n6576 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n6577 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n6578 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_reset_pc_ptrs_out_chnl_up_n6579 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_DPA_B_n6580 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_FCLK_OUT_CD_n6581 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n6582 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_LOADEN_OUT_CD_n6583 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_LOADEN_OUT_AB_n6584 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n6585 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_rx_div_sync_out_chnl_up_n6586 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IT50UA_FTRES_BIDIR_OUT_n6587 +_ioreg16_c514_14 _ioreg16_c514_14~_LVDS_LOADEN_OUT_AB_n6588 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_t_n6589 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_D_n6590 +_4iomodule_c519_19 _4iomodule_c519_19~_BUF_IOREG_n6591 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n6592 +_4iomodule_c534_34 _4iomodule_c534_34~_DATX0_n6593 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IT50UA_FTRES_BIDIR_OUT_n6594 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_A_n6595 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_IT50UA_FTRES_BIDIR_OUT_n6596 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_t_a_n6597 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n6598 +_ioreg16_c53_3 _ioreg16_c53_3~_IOREG_BUF_B_n6599 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_DPA_A_n6600 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n6601 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_ffpll_n6602 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n6603 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_reset_ppm_cntrs_out_chnl_up_n6604 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_clk_seg_dn_out_n6605 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n6606 +_ioreg16_h5_5 _ioreg16_h5_5~_IOREG_DPA_B_n6607 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_D_n6608 +_4iomodule_c536_36 _4iomodule_c536_36~_INPUT_BUF_n6609 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_rx_div_sync_out_chnl_up_n6610 +_4iomodule_c515_15 _4iomodule_c515_15~_INPUT_BUF_n6611 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_rx_iqclk_t_n6612 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_hfclkn_x6_dn_out_n6613 +_4iomodule_c515_15 _4iomodule_c515_15~_INPUT_BUF_n6614 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_pcie_sw_done_n6615 +_4iomodule_c515_15 _4iomodule_c515_15~_INPUT_BUF_n6616 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_hclk_pcs_n6617 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_iqtxrxclk_ffpll_n6618 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_FCLK_OUT_AB_n6619 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_D_n6620 +_ioreg16_c513_13 _ioreg16_c513_13~_DQS_IN_C_n6621 +_ioreg16_h0_n7 _ioreg16_h0_n7~_LVDS_FCLK_OUT_CD_n6622 +_4iomodule_h19_19 _4iomodule_h19_19~_IOBUF_DPA_n6623 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_hfclkn_xn_dn_out_n6624 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n6625 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_B_n6626 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_pfdmode_lock_n6627 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_FCLK_OUT_CD_n6628 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_D_n6629 +_4iomodule_h4_4 _4iomodule_h4_4~_IOBUF_DPA_n6630 +_4iomodule_c515_15 _4iomodule_c515_15~_INPUT_BUF_n6631 +_ioreg16_c59_9 _ioreg16_c59_9~_IOREG_BUF_B_n6632 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6633 +_4iomodule_h12_12 _4iomodule_h12_12~_IOBUF_DPA_n6634 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_iqtxrxclk_t_n6635 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n6636 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n6637 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_iqtxrxclk_t_n6638 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n6639 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6640 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch2_readdata_n6641 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_IC50UA_FTRES_BIDIR_OUT_n6642 +_4iomodule_h8_8 _4iomodule_h8_8~_INPUT_BUF_n6643 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_FCLK_OUT_CD_n6644 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n6645 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_A_n6646 +_4iomodule_h8_8 _4iomodule_h8_8~_INPUT_BUF_n6647 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n6648 +_ioreg16_c55_5 _ioreg16_c55_5~_LVDS_FCLK_OUT_AB_n6649 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_rx_iqclk_out_n6650 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_DPA_C_n6651 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_A_n6652 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_rx_iqclk_ffpll_n6653 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n6654 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n6655 +_4iomodule_h18_18 _4iomodule_h18_18~_IOBUF_DPA_n6656 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_rx_iqclk_t_a_n6657 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch0_pma_tx_data_n6658 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6659 +_4iomodule_c511_11 _4iomodule_c511_11~_BUF_IOREG_n6660 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n6661 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_A_n6662 +_ioreg16_c50_n9 _ioreg16_c50_n9~_PHYCT_L_OUT_CLK_n6663 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n6664 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6665 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n6666 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6667 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_FCLK_OUT_AB_n6668 +_ioreg16_h2_2 _ioreg16_h2_2~_REGSCANOUT_C_n6669 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_BUF_C_n6670 +_ioreg16_c512_12 _ioreg16_c512_12~_CSRDATAOUT_C_n6671 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_A_n6672 +_ioreg16_c54_4 _ioreg16_c54_4~_REGSCANOUT_B_n6673 +_4iomodule_h8_8 _4iomodule_h8_8~_INPUT_BUF_n6674 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_FCLK_OUT_CD_n6675 +_smrt_smrtpack2_2 _smrt_smrtpack2_2~_agg_fifo_rst_rd_qd_bot_ch2_n6676 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_A_n6677 +_ioreg16_c512_12 _ioreg16_c512_12~_CSRDATAOUT_B_n6678 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n6679 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_FCLK_OUT_CD_n6680 +_4iomodule_h4_4 _4iomodule_h4_4~_INPUT_BUF_n6681 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_A_n6682 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_A_n6683 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_FCLK_OUT_AB_n6684 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_tx_b50_buf_out_n6685 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_A_n6686 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_A_n6687 +_4iomodule_c546_46 _4iomodule_c546_46~_BUF_IOREG_n6688 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_A_n6689 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_C_n6690 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_ch2_rx_data_n6691 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_R_n6692 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n6693 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6694 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_FCLK_OUT_AB_n6695 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_IC50UA_FTRES_BIDIR_OUT_n6696 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n6697 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n6698 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n6699 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n6700 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_FCLK_OUT_AB_n6701 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_A_n6702 +_4iomodule_c512_12 _4iomodule_c512_12~_BUF_IOREG_n6703 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_A_n6704 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch1_pma_current_coeff_n6705 +_ioreg16_c54_4 _ioreg16_c54_4~_IOREG_DPA_C_n6706 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n6707 +_io_oct_serpar_h1_1 _io_oct_serpar_h1_1~_OCTRTCALP_R_n6708 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_C_n6709 +_4iomodule_h16_16 _4iomodule_h16_16~_INPUT_BUF_n6710 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n6711 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n6712 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n6713 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n6714 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_C_n6715 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_A_n6716 +_ioreg16_c58_8 _ioreg16_c58_8~_DQS_IN_C_n6717 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6718 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n6719 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_DPA_C_n6720 +_4iomodule_c51_1 _4iomodule_c51_1~_BUF_IOREG_n6721 +_smrt_smrtpack1_1 _smrt_smrtpack1_1~_ch2_pma_tx_data_n6722 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n6723 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6724 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_LOADEN_OUT_CD_n6725 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_C_n6726 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_DPA_C_n6727 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n6728 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n6729 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_D_n6730 +_4iomodule_c523_23 _4iomodule_c523_23~_BUF_IOREG_n6731 +_ioreg16_c56_6 _ioreg16_c56_6~_OUT_STAGE_A1L_n6732 +_ioreg16_h1_1 _ioreg16_h1_1~_LVDS_LOADEN_OUT_CD_n6733 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n6734 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n6735 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_C_n6736 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_iqtxrxclk_t_n6737 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n6738 +_ioreg16_c51_1 _ioreg16_c51_1~_IOREG_BUF_C_n6739 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_D_n6740 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_FCLK_OUT_AB_n6741 +_ioreg16_h3_3 _ioreg16_h3_3~_LVDS_FCLK_OUT_AB_n6742 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_rx_iqclk_b_a_n6743 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_C_n6744 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_readdata_n6745 +_4iomodule_c50_n12 _4iomodule_c50_n12~_BUF_IOREG_n6746 +_4iomodule_c552_52 _4iomodule_c552_52~_BUF_IOREG_n6747 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_rx_iqclk_b_a_n6748 +_ioreg16_c510_10 _ioreg16_c510_10~_IOREG_BUF_C_n6749 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_A_n6750 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_D_n6751 +_4iomodule_c537_37 _4iomodule_c537_37~_BUF_IOREG_n6752 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n6753 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_iqtxrxclk_t_n6754 +_ioreg16_h_c50_n10 _ioreg16_h_c50_n10~_IOREG_BUF_A_n6755 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_pma_reserved_out_n6756 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_clklow_n6757 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_D_n6758 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_rx_iqclk_out_n6759 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_lfclkn_xn_dn_out_n6760 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_D_n6761 +_ioreg16_h1_1 _ioreg16_h1_1~_IOREG_BUF_D_n6762 +_pm_pma3_top_c50_n3 _pm_pma3_top_c50_n3~_ch1_pma_reserved_out_n6763 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_rx_iqclk_out_n6764 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n6765 +_4iomodule_c558_58 _4iomodule_c558_58~_BUF_IOREG_n6766 +_ioreg16_c512_12 _ioreg16_c512_12~_IOREG_BUF_D_n6767 +_4iomodule_c544_44 _4iomodule_c544_44~_BUF_IOREG_n6768 +_pm_pma3_bot_c50_n4 _pm_pma3_bot_c50_n4~_rx_iqclk_out_n6769 +_ir_dll_top1_1 _ir_dll_top1_1~_CTL_A_n6770 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALP_L_n6771 +_4iomodule_c541_41 _4iomodule_c541_41~_INPUT_BUF_n6772 +_ioreg16_c511_11 _ioreg16_c511_11~_PHYCT_SHORT_R_FB_IN_CLK_n6773 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_CLKIN_TM_RO_n6774 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALN_L_n6775 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALP_L_n6776 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_TX_IMPCTRL_n6777 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_FBLVDS_OUT_R0_n6778 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_TM_BO_BIDIR_OUT_n6779 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALN_R_n6780 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_L_n6781 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RATBEN1_n6782 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_CLKIN_TM_RO_n6783 +_ir_lvl_top7_7 _ir_lvl_top7_7~_PLL_AFI_CLK_n6784 +_ir_dll_top3_3 _ir_dll_top3_3~_CTL_A_n6785 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_L_n6786 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_R_n6787 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_CLKOUT_n6788 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_A_n6789 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_LOADEN_R0_n6790 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_CLKIN_TM_RO_n6791 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RBG_LST_n6792 +_4iomodule_c552_52 _4iomodule_c552_52~_INPUT_BUF_n6793 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_R_n6794 +_4iomodule_c545_45 _4iomodule_c545_45~_INPUT_BUF_n6795 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALN_L_n6796 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALP_R_n6797 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_BIT_TX_n6798 +_4iomodule_c549_49 _4iomodule_c549_49~_BSDOUT_n6799 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RREXT_BYPASS_n6800 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_A_n6801 +_4iomodule_c524_24 _4iomodule_c524_24~_INPUT_BUF_n6802 +_ir_dll_top1_1 _ir_dll_top1_1~_CTL_A_n6803 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_PHYCT_SHORT_L_FB_IN_CLK_n6804 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_TX_IMPCTRL_n6805 +_im_sysclk3_3 _im_sysclk3_3~_FBCLKOUTB_n6806 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_BIT_TX_n6807 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALP_R_n6808 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALP_R_n6809 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_LVDS_CLK_R0_n6810 +_im_sysclk0_n17 _im_sysclk0_n17~_CLKOUTO_n6811 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_TM_BO_BIDIR_OUT_n6812 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_L_n6813 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALP_R_n6814 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_R_n6815 +_im_sysclk0_n17 _im_sysclk0_n17~_FBCLKOUTB_n6816 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_CLKOUT_n6817 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_R_n6818 +_im_sysclk3_3 _im_sysclk3_3~_LVDSCLKB_n6819 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_ENSEROUT_n6820 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RCOMP_PLUS_n6821 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALN_R_n6822 +_cc_clkmuxf_lr1_1 _cc_clkmuxf_lr1_1~_CSRDOUT_n6823 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_BSDOUT_n6824 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_TM_BO_BIDIR_OUT_n6825 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_T_BO_BIDIR_OUT_n6826 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALP_R_n6827 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_TM_BO_BIDIR_OUT_n6828 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLDOUT_R0_n6829 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_CSRDOUT_n6830 +_ir_dll_top1_1 _ir_dll_top1_1~_CTL_A_n6831 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RATBEN0_n6832 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_R_n6833 +_cc_clkmuxf_lr1_1 _cc_clkmuxf_lr1_1~_FBCLKTOUT_n6834 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_INPUT_BUF_n6835 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RZ50_SELECT_n6836 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALN_R_n6837 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_R_n6838 +_ir_dll_top2_2 _ir_dll_top2_2~_CTL_B_n6839 +_ioreg16_c511_11 _ioreg16_c511_11~_CSR_DOUT_2_n6840 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_SER_DATA_OUT_n6841 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_L_n6842 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALN_R_n6843 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALP_L_n6844 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLMOUT_R0_n6845 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_SCANOUT_n6846 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_EXTCLK_R_n6847 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLMOUT_L0_n6848 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALN_R_n6849 +_4iomodule11_11 _4iomodule11_11~_BSDOUT_n6850 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_B_n6851 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALN_R_n6852 +_im_sysclk0_n17 _im_sysclk0_n17~_LVDSCLKB_n6853 +_ioreg16_c57_7 _ioreg16_c57_7~_PHYCT_SHORT_L_FB_IN_CLK_n6854 +_im_sysclk2_2 _im_sysclk2_2~_CLKOUTO_n6855 +_im_sysclk0_n17 _im_sysclk0_n17~_FBIN_n6856 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_TM_BO_BIDIR_OUT_n6857 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_CLKIN_TM_RO_n6858 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_LVDS_CLK_R0_n6859 +_ir_dll_top2_2 _ir_dll_top2_2~_CSRDATAOUT_n6860 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_T_BO_BIDIR_OUT_n6861 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_L_n6862 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_FPLL0_COUT_n6863 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_INPUT_BUF_n6864 +_ir_lvl_top7_7 _ir_lvl_top7_7~_PLL_AVL_CLK_n6865 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALP_R_n6866 +_im_sysclk3_3 _im_sysclk3_3~_CLKOUTO_n6867 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALN_R_n6868 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_IOCSR_DATAOUT_n6869 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_T_BO_BIDIR_OUT_n6870 +_im_sysclk3_3 _im_sysclk3_3~_FBIN_n6871 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_FBLVDS_OUT_R0_n6872 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RBG_LST_n6873 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RPWR_DN_n6874 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALN_R_n6875 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RBG_KS_n6876 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_L_n6877 +_4iomodule_c55_5 _4iomodule_c55_5~_INPUT_BUF_n6878 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_T_BO_BIDIR_OUT_n6879 +_im_sysclk0_n17 _im_sysclk0_n17~_LVDSCLKB_n6880 +_im_sysclk2_2 _im_sysclk2_2~_LVDSCLKA_n6881 +_ir_dll_top3_3 _ir_dll_top3_3~_CTL_A_n6882 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_A_n6883 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALN_R_n6884 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALN_R_n6885 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALN_R_n6886 +_io_oct_serpar_h2_2 _io_oct_serpar_h2_2~_SCANOUT_n6887 +_ir_dll_top2_2 _ir_dll_top2_2~_CTL_B_n6888 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALN_R_n6889 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALP_R_n6890 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLMOUT_R0_n6891 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_EXTCLK_R_n6892 +_ir_dll_top1_1 _ir_dll_top1_1~_CTL_A_n6893 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALN_R_n6894 +_ir_dll_top1_1 _ir_dll_top1_1~_CTL_A_n6895 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_R_n6896 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALN_L_n6897 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_BIT_RX_n6898 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALN_R_n6899 +_im_sysclk1_1 _im_sysclk1_1~_LVDSCLKA_n6900 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALN_R_n6901 +_im_sysclk2_2 _im_sysclk2_2~_LVDSCLKA_n6902 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALP_L_n6903 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_LOADEN_R0_n6904 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_CLKIN_TM_RO_n6905 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_LVDS_CLK_R0_n6906 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALN_R_n6907 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_R_n6908 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_R_n6909 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_R_n6910 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_T_BO_BIDIR_OUT_n6911 +_4iomodule_c532_32 _4iomodule_c532_32~_INPUT_BUF_n6912 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALN_R_n6913 +_im_sysclk0_n17 _im_sysclk0_n17~_CLKOUTO_n6914 +_4iomodule_h_c55_5 _4iomodule_h_c55_5~_BSDOUT_n6915 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_EXTCLK_R_n6916 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_TM_BO_BIDIR_OUT_n6917 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_FPLL0_COUT_n6918 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALP_R_n6919 +_ir_dll_top0_n19 _ir_dll_top0_n19~_UPDATEN_B_n6920 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALP_L_n6921 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALP_L_n6922 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_R_n6923 +_4iomodule_c524_24 _4iomodule_c524_24~_INPUT_BUF_n6924 +_im_sysclk2_2 _im_sysclk2_2~_CLKOUTO_n6925 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_DPACLK0_I_n6926 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CSRDATAOUT_n6927 +_io_oct_serpar2_2 _io_oct_serpar2_2~_IOCSRDOUT_n6928 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RBG_LST_n6929 +_4iomodule_c532_32 _4iomodule_c532_32~_BSDOUT_n6930 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_LVDS_CLK_R0_n6931 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_CLKIN_TM_RO_n6932 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_IOCSR_DATAOUT_n6933 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RZTXWR_n6934 +_ir_dll_top1_1 _ir_dll_top1_1~_CTL_A_n6935 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_R_n6936 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALP_R_n6937 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_T_BO_BIDIR_OUT_n6938 +_cc_clkmuxf_corne2_2 _cc_clkmuxf_corne2_2~_CSRDOUT_n6939 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALP_L_n6940 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_BIT_RX_n6941 +_4iomodule13_13 _4iomodule13_13~_IOBUF_DPA_n6942 +_im_sysclk1_1 _im_sysclk1_1~_LVDSCLKA_n6943 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_R_n6944 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_R_n6945 +_ir_dll_top3_3 _ir_dll_top3_3~_UPDATEN_A_n6946 +_im_sysclk0_n17 _im_sysclk0_n17~_LVDSCLKB_n6947 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALN_R_n6948 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALN_R_n6949 +_4iomodule_c538_38 _4iomodule_c538_38~_INPUT_BUF_n6950 +_ir_dll_top2_2 _ir_dll_top2_2~_CTL_B_n6951 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_BIT_RX_n6952 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLMOUT_R0_n6953 +_4iomodule13_13 _4iomodule13_13~_BSDOUT_n6954 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_TM_BO_BIDIR_OUT_n6955 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_L_n6956 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALP_R_n6957 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLMOUT_L0_n6958 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_CLKIN_TM_RO_n6959 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RMUXCLKSEL_n6960 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_R_n6961 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_R_n6962 +_cc_clkmuxf_corne0_n14 _cc_clkmuxf_corne0_n14~_CSRDOUT_n6963 +_4iomodule_c550_50 _4iomodule_c550_50~_BSDOUT_n6964 +_im_sysclk1_1 _im_sysclk1_1~_FBCLKOUTA_n6965 +_io_oct_serpar_h3_3 _io_oct_serpar_h3_3~_SCANOUT_n6966 +_im_sysclk1_1 _im_sysclk1_1~_LVDSCLKA_n6967 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALN_L_n6968 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_LOADEN_R0_n6969 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_SER_DATA_OUT_n6970 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RZCAL_n6971 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_T_BO_BIDIR_OUT_n6972 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_B_n6973 +_im_sysclk3_3 _im_sysclk3_3~_FBCLKIN_n6974 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALP_L_n6975 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_FPLL0_COUT_n6976 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_TM_BO_BIDIR_OUT_n6977 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALP_R_n6978 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_T_BO_BIDIR_OUT_n6979 +_ioreg16_c59_9 _ioreg16_c59_9~_PHYCT_SHORT_R_FB_IN_CLK_n6980 +_ir_dll_top3_3 _ir_dll_top3_3~_CTL_A_n6981 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_A_n6982 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_EXTCLK_R_n6983 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_B_n6984 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALN_L_n6985 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALP_L_n6986 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_A_n6987 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALN_R_n6988 +_4iomodule_c541_41 _4iomodule_c541_41~_INPUT_BUF_n6989 +_ioreg16_c59_9 _ioreg16_c59_9~_PHYCT_SHORT_R_FB_IN_CLK_n6990 +_ir_dll_top3_3 _ir_dll_top3_3~_CTL_A_n6991 +_4iomodule_c545_45 _4iomodule_c545_45~_INPUT_BUF_n6992 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_DPACLK0_I_n6993 +_4iomodule_h2_2 _4iomodule_h2_2~_BSDOUT_n6994 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_R_n6995 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_L_n6996 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALN_L_n6997 +_4iomodule_vref_h0_n25 _4iomodule_vref_h0_n25~_BSDOUT_n6998 +_ir_dll_top3_3 _ir_dll_top3_3~_CTL_A_n6999 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_DPACLK0_I_n7000 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_T_BO_BIDIR_OUT_n7001 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_T_BO_BIDIR_OUT_n7002 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALN_L_n7003 +_ir_dll_top1_1 _ir_dll_top1_1~_CTL_A_n7004 +_4iomodule_h_c54_4 _4iomodule_h_c54_4~_INPUT_BUF_n7005 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALN_R_n7006 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RBG_LST_n7007 +_im_sysclk1_1 _im_sysclk1_1~_LVDSCLKA_n7008 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_EXTCLK_R_n7009 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_R_n7010 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_T_BO_BIDIR_OUT_n7011 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RTEST_n7012 +_ir_dll_top2_2 _ir_dll_top2_2~_CTL_B_n7013 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_PLLCOUT_L_n7014 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_INPUT_BUF_n7015 +_ir_dll_top1_1 _ir_dll_top1_1~_UPDATEN_A_n7016 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALP_R_n7017 +_ir_lvl_top7_7 _ir_lvl_top7_7~_PLL_ADDR_CMD_CLK_n7018 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_CLKIN_TM_BO_BIDIR_OUT_n7019 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_B_n7020 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_EXTCLK_R_n7021 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALP_L_n7022 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_CLKIN_TM_RO_n7023 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RBG_LST_n7024 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_R_n7025 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALP_L_n7026 +_4iomodule_c553_53 _4iomodule_c553_53~_BSDOUT_n7027 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_L_n7028 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALP_R_n7029 +_im_sysclk3_3 _im_sysclk3_3~_CLKOUTO_n7030 +_ir_dll_top3_3 _ir_dll_top3_3~_CSRDATAOUT_n7031 +_4iomodule0_n13 _4iomodule0_n13~_BSDOUT_n7032 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_CLKIN_TM_RO_n7033 +_im_sysclk3_3 _im_sysclk3_3~_LVDSCLKB_n7034 +_im_sysclk0_n17 _im_sysclk0_n17~_FBCLKIN_n7035 +_ioreg16_c57_7 _ioreg16_c57_7~_PHYCT_SHORT_L_FB_IN_CLK_n7036 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALP_L_n7037 +_ioreg16_h_c51_1 _ioreg16_h_c51_1~_PHYCT_SHORT_L_FB_IN_CLK_n7038 +_im_sysclk0_n17 _im_sysclk0_n17~_LVDSCLKB_n7039 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_IOCSR_DATAOUT_n7040 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RCAL_CLK_TEST_SEL_n7041 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_R_n7042 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_CLKIN_TM_RO_n7043 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_L_n7044 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALN_R_n7045 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALP_R_n7046 +_ioreg16_c511_11 _ioreg16_c511_11~_PHYCT_SHORT_R_FB_IN_CLK_n7047 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALN_L_n7048 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALN_L_n7049 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_L_n7050 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALN_R_n7051 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALN_L_n7052 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALP_R_n7053 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALN_R_n7054 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALP_R_n7055 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_R_n7056 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RMUXCLKSEL_n7057 +_4iomodule_c532_32 _4iomodule_c532_32~_INPUT_BUF_n7058 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALN_R_n7059 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALP_R_n7060 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALN_L_n7061 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_LVDS_CLK_R0_n7062 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_R_n7063 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RBG_BYPASS_n7064 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_FBLVDS_OUT_R0_n7065 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALN_L_n7066 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLDOUT_R0_n7067 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RCOMP_MINUS_n7068 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_L_n7069 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RATBEN1_PRECOMP_n7070 +_cc_clkmuxf_corne1_1 _cc_clkmuxf_corne1_1~_CSRDOUT_n7071 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALP_R_n7072 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALN_R_n7073 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_A_n7074 +_4iomodule_c556_56 _4iomodule_c556_56~_INPUT_BUF_n7075 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_R_n7076 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALN_R_n7077 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_RX_IMPCTRL_n7078 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RVBG_FLAG_PD_n7079 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_T_BO_BIDIR_OUT_n7080 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RMUXCLKSEL_n7081 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_CLKIN_TM_RO_n7082 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALP_R_n7083 +_4iomodule_c556_56 _4iomodule_c556_56~_INPUT_BUF_n7084 +_io_oct_serpar3_3 _io_oct_serpar3_3~_IOCSRDOUT_n7085 +_4iomodule_c543_43 _4iomodule_c543_43~_BSDOUT_n7086 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLMOUT_L0_n7087 +_ir_dll_top3_3 _ir_dll_top3_3~_CTL_A_n7088 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALP_R_n7089 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RZRXWR_n7090 +_ir_dll_top2_2 _ir_dll_top2_2~_CTL_B_n7091 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALP_L_n7092 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALP_R_n7093 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RATBEN0_PRECOMP_n7094 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALN_R_n7095 +_im_sysclk2_2 _im_sysclk2_2~_LVDSCLKA_n7096 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_ENSEROUT_n7097 +_4iomodule1_1 _4iomodule1_1~_BSDOUT_n7098 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_BIT_RX_n7099 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALP_R_n7100 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALP_R_n7101 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALP_R_n7102 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALP_L_n7103 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTCALP_R_n7104 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_LOADEN_R0_n7105 +_4iomodule_h7_7 _4iomodule_h7_7~_BSDOUT_n7106 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLDOUT_R0_n7107 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RBG_PDB_n7108 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALP_L_n7109 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALP_R_n7110 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALN_R_n7111 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_BIT_TX_n7112 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_CLKIN_TM_RO_n7113 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALN_L_n7114 +_im_sysclk3_3 _im_sysclk3_3~_LVDSCLKB_n7115 +_pl_fpll_ip0_n22 _pl_fpll_ip0_n22~_PLLCOUT_R_n7116 +_im_sysclk2_2 _im_sysclk2_2~_FBCLKOUTA_n7117 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALP_R_n7118 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_A_n7119 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_RATB_EN_n7120 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_PLLCOUT_L_n7121 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_BIT_TX_n7122 +_io_oc_rsrtcal2_2 _io_oc_rsrtcal2_2~_CLKOUT_n7123 +_ir_dll_top2_2 _ir_dll_top2_2~_UPDATEN_B_n7124 +_im_sysclk1_1 _im_sysclk1_1~_FBCLKIN_n7125 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_DPACLK0_I_n7126 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALP_R_n7127 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALP_R_n7128 +_io_oc_rsrtcal1_1 _io_oc_rsrtcal1_1~_SER_DATA_OUT_n7129 +_pl_fpll_ip2_2 _pl_fpll_ip2_2~_CLKIN_TM_BO_BIDIR_OUT_n7130 +_ir_dll_top0_n19 _ir_dll_top0_n19~_UPDATEN_A_n7131 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALN_R_n7132 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_LVDS_CLK_R0_n7133 +_im_sysclk2_2 _im_sysclk2_2~_FBIN_n7134 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_RX_IMPCTRL_n7135 +_im_sysclk2_2 _im_sysclk2_2~_LVDSCLKA_n7136 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_B_n7137 +_io_oc_rsrtcal0_n18 _io_oc_rsrtcal0_n18~_ENSEROUT_n7138 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_B_n7139 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_TM_BO_BIDIR_OUT_n7140 +_io_oct_serpar0_n23 _io_oct_serpar0_n23~_OCTRTCALN_R_n7141 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALN_L_n7142 +_im_sysclk3_3 _im_sysclk3_3~_LVDSCLKB_n7143 +_ir_dll_top0_n19 _ir_dll_top0_n19~_CTL_B_n7144 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_PLLCOUT_R_n7145 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALN_R_n7146 +_ir_dll_top2_2 _ir_dll_top2_2~_CTL_B_n7147 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALP_L_n7148 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_PLLCOUT_L_n7149 +_4iomodule_c55_5 _4iomodule_c55_5~_INPUT_BUF_n7150 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALP_R_n7151 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTCALN_L_n7152 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_R_n7153 +_4iomodule_h_c59_9 _4iomodule_h_c59_9~_INPUT_BUF_n7154 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_DPACLK0_I_n7155 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTRTCALP_R_n7156 +_io_oct_serpar2_2 _io_oct_serpar2_2~_OCTCALP_R_n7157 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_BIT_TX_n7158 +_ir_dll_top3_3 _ir_dll_top3_3~_CTL_A_n7159 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_LOADEN_R0_n7160 +_pl_fpll_ip3_3 _pl_fpll_ip3_3~_DPACLK0_I_n7161 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_R_BIT_RX_n7162 +_pl_fpll_ip5_5 _pl_fpll_ip5_5~_PLLCOUT_R_n7163 +_io_oct_serpar3_3 _io_oct_serpar3_3~_OCTRTCALN_L_n7164 +_pl_fpll_ip1_1 _pl_fpll_ip1_1~_CLKIN_TM_BO_BIDIR_OUT_n7165 +_pl_fpll_ip4_4 _pl_fpll_ip4_4~_LOADEN_R0_n7166 +_ir_dll_top2_2 _ir_dll_top2_2~_CTL_B_n7167 diff --git a/CH5/CH5-3/incremental_db/README b/CH5/CH5-3/incremental_db/README new file mode 100644 index 00000000..9f62dcda --- /dev/null +++ b/CH5/CH5-3/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.db_info b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.db_info new file mode 100644 index 00000000..83c882ff --- /dev/null +++ b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +Version_Index = 318808576 +Creation_Time = Thu Sep 5 19:10:01 2019 diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.ammdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.ammdb new file mode 100644 index 00000000..1efddb72 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.ammdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.cdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.cdb new file mode 100644 index 00000000..8be1f6e2 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.cdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.dfp b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.dfp new file mode 100644 index 00000000..b1c67d62 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.dfp differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.hdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.hdb new file mode 100644 index 00000000..98e250b2 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.hdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.logdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.logdb new file mode 100644 index 00000000..626799f0 --- /dev/null +++ b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.rcfdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.rcfdb new file mode 100644 index 00000000..0940ef73 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.cmp.rcfdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.cdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.cdb new file mode 100644 index 00000000..c37462d7 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.cdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.dpi b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.dpi new file mode 100644 index 00000000..6b8fcf43 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.dpi differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.cdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.cdb new file mode 100644 index 00000000..ac37ba1d Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.cdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.hb_info b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.hb_info new file mode 100644 index 00000000..8210c559 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.hb_info differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.hdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.hdb new file mode 100644 index 00000000..cd4e5957 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.hdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.sig b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.sig new file mode 100644 index 00000000..ef58eaac --- /dev/null +++ b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +d1187c24d5e18b5b14f48701f0f8928b \ No newline at end of file diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hdb new file mode 100644 index 00000000..82ff7b60 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.hdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.kpt b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.kpt new file mode 100644 index 00000000..c428fbb8 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D.root_partition.map.kpt differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.db_info b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.db_info new file mode 100644 index 00000000..ddb80aa9 --- /dev/null +++ b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +Version_Index = 318808576 +Creation_Time = Mon Sep 9 20:23:22 2019 diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.ammdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.ammdb new file mode 100644 index 00000000..3f2255b3 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.ammdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.cdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.cdb new file mode 100644 index 00000000..75a34fa4 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.cdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.dfp b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.dfp new file mode 100644 index 00000000..b1c67d62 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.dfp differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.hdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.hdb new file mode 100644 index 00000000..f1340c05 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.hdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.logdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.logdb new file mode 100644 index 00000000..626799f0 --- /dev/null +++ b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.rcfdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.rcfdb new file mode 100644 index 00000000..f5650713 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.cmp.rcfdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.cdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.cdb new file mode 100644 index 00000000..8d53e1d4 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.cdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.dpi b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.dpi new file mode 100644 index 00000000..b4a323da Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.dpi differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.cdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.cdb new file mode 100644 index 00000000..8ce47aef Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.cdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.hb_info b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.hb_info new file mode 100644 index 00000000..8210c559 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.hb_info differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.hdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.hdb new file mode 100644 index 00000000..cd8a9c8d Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.hdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.sig b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.sig new file mode 100644 index 00000000..ef58eaac --- /dev/null +++ b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +d1187c24d5e18b5b14f48701f0f8928b \ No newline at end of file diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hdb new file mode 100644 index 00000000..234a0756 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.hdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.kpt b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.kpt new file mode 100644 index 00000000..4bde6434 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_1D_G.root_partition.map.kpt differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.db_info b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.db_info new file mode 100644 index 00000000..7e08802e --- /dev/null +++ b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +Version_Index = 318808576 +Creation_Time = Mon Aug 26 22:50:43 2019 diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.ammdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.ammdb new file mode 100644 index 00000000..90c90bd3 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.ammdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.cdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.cdb new file mode 100644 index 00000000..cfced6a9 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.cdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.dfp b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.dfp new file mode 100644 index 00000000..b1c67d62 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.dfp differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hbdb.cdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hbdb.cdb new file mode 100644 index 00000000..439e6c56 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hbdb.cdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hbdb.hdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hbdb.hdb new file mode 100644 index 00000000..4623b6c6 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hbdb.hdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hbdb.sig b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hbdb.sig new file mode 100644 index 00000000..af9b8e9a --- /dev/null +++ b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3 \ No newline at end of file diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hdb new file mode 100644 index 00000000..8114233a Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.hdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.logdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.logdb new file mode 100644 index 00000000..626799f0 --- /dev/null +++ b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.rcfdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.rcfdb new file mode 100644 index 00000000..3c7f2b08 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.cmp.rcfdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.cdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.cdb new file mode 100644 index 00000000..86f5abf6 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.cdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.dpi b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.dpi new file mode 100644 index 00000000..e4080979 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.dpi differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.cdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.cdb new file mode 100644 index 00000000..fce9c393 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.cdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.hb_info b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.hb_info new file mode 100644 index 00000000..8210c559 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.hb_info differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.hdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.hdb new file mode 100644 index 00000000..5645ec2d Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.hdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.sig b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.sig new file mode 100644 index 00000000..ef58eaac --- /dev/null +++ b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +d1187c24d5e18b5b14f48701f0f8928b \ No newline at end of file diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hdb b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hdb new file mode 100644 index 00000000..3b6f116d Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.hdb differ diff --git a/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.kpt b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.kpt new file mode 100644 index 00000000..eb2584f7 Binary files /dev/null and b/CH5/CH5-3/incremental_db/compiled_partitions/BCD_adder_7483.root_partition.map.kpt differ diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.asm.rpt b/CH5/CH5-3/output_files/BCD_adder_1D.asm.rpt new file mode 100644 index 00000000..9f39898f --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.asm.rpt @@ -0,0 +1,116 @@ +Assembler report for BCD_adder_1D +Thu Sep 5 20:29:04 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: BCD_adder_1D.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Sep 5 20:29:04 2019 ; +; Revision Name ; BCD_adder_1D ; +; Top-level Entity Name ; BCD_adder_1D ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Use configuration device ; Off ; Off ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Enable OCT_DONE ; Off ; Off ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++---------------------------+ +; Assembler Generated Files ; ++---------------------------+ +; File Name ; ++---------------------------+ +; BCD_adder_1D.sof ; ++---------------------------+ + + ++--------------------------------------------+ +; Assembler Device Options: BCD_adder_1D.sof ; ++----------------+---------------------------+ +; Option ; Setting ; ++----------------+---------------------------+ +; Device ; EP3C16F484C6 ; +; JTAG usercode ; 0x000C9402 ; +; Checksum ; 0x000C9402 ; ++----------------+---------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit Assembler + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Thu Sep 5 20:29:01 2019 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 378 megabytes + Info: Processing ended: Thu Sep 5 20:29:04 2019 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.cdf b/CH5/CH5-3/output_files/BCD_adder_1D.cdf new file mode 100644 index 00000000..81e5f576 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.cdf @@ -0,0 +1,13 @@ +/* Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(EP3C16F484) Path("/home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/") File("BCD_adder_1D.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.done b/CH5/CH5-3/output_files/BCD_adder_1D.done new file mode 100644 index 00000000..3b532528 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.done @@ -0,0 +1 @@ +Thu Sep 5 20:29:15 2019 diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.eda.rpt b/CH5/CH5-3/output_files/BCD_adder_1D.eda.rpt new file mode 100644 index 00000000..e2367e7f --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.eda.rpt @@ -0,0 +1,107 @@ +EDA Netlist Writer report for BCD_adder_1D +Thu Sep 5 20:29:14 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Thu Sep 5 20:29:14 2019 ; +; Revision Name ; BCD_adder_1D ; +; Top-level Entity Name ; BCD_adder_1D ; +; Family ; Cyclone III ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+------------------------+ +; Tool Name ; ModelSim-Altera (VHDL) ; +; Generate netlist for functional simulation only ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++--------------------------------------------------------------------------------------------------+ +; Generated Files ; ++--------------------------------------------------------------------------------------------------+ +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_85c_slow.vho ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_0c_slow.vho ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_min_1200mv_0c_fast.vho ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_1D.vho ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_85c_vhd_slow.sdo ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_0c_vhd_slow.sdo ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_min_1200mv_0c_vhd_fast.sdo ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_vhd.sdo ; ++--------------------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit EDA Netlist Writer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Thu Sep 5 20:29:13 2019 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D +Info (204019): Generated file BCD_adder_1D_6_1200mv_85c_slow.vho in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_1D_6_1200mv_0c_slow.vho in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_1D_min_1200mv_0c_fast.vho in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_1D.vho in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_1D_6_1200mv_85c_vhd_slow.sdo in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_1D_6_1200mv_0c_vhd_slow.sdo in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_1D_min_1200mv_0c_vhd_fast.sdo in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_1D_vhd.sdo in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 342 megabytes + Info: Processing ended: Thu Sep 5 20:29:14 2019 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.fit.rpt b/CH5/CH5-3/output_files/BCD_adder_1D.fit.rpt new file mode 100644 index 00000000..e70c8769 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.fit.rpt @@ -0,0 +1,1266 @@ +Fitter report for BCD_adder_1D +Thu Sep 5 20:28:57 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. I/O Assignment Warnings + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Non-Global High Fan-Out Signals + 21. Routing Usage Summary + 22. LAB Logic Elements + 23. LAB Signals Sourced + 24. LAB Signals Sourced Out + 25. LAB Distinct Inputs + 26. I/O Rules Summary + 27. I/O Rules Details + 28. I/O Rules Matrix + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+--------------------------------------------+ +; Fitter Status ; Successful - Thu Sep 5 20:28:57 2019 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_1D ; +; Top-level Entity Name ; BCD_adder_1D ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Total logic elements ; 10 / 15,408 ( < 1 % ) ; +; Total combinational functions ; 10 / 15,408 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 13 / 347 ( 4 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 516,096 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+--------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP3C16F484C6 ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Device I/O Standard ; 2.5 V ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Off ; Off ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; RAM Bit Reservation (Cyclone III) ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-------------------------------------------------+ +; I/O Assignment Warnings ; ++----------+--------------------------------------+ +; Pin Name ; Reason ; ++----------+--------------------------------------+ +; S0 ; Missing drive strength and slew rate ; +; S1 ; Missing drive strength and slew rate ; +; S2 ; Missing drive strength and slew rate ; +; S3 ; Missing drive strength and slew rate ; +; C4 ; Missing drive strength and slew rate ; ++----------+--------------------------------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 47 ) ; 0.00 % ( 0 / 47 ) ; 0.00 % ( 0 / 47 ) ; +; -- Achieved ; 0.00 % ( 0 / 47 ) ; 0.00 % ( 0 / 47 ) ; 0.00 % ( 0 / 47 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 37 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 10 / 15,408 ( < 1 % ) ; +; -- Combinational with no register ; 10 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 5 ; +; -- 3 input functions ; 3 ; +; -- <=2 input functions ; 2 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 10 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 17,068 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; +; -- I/O registers ; 0 / 1,660 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 1 / 963 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 13 / 347 ( 4 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; Global signals ; 0 ; +; M9Ks ; 0 / 56 ( 0 % ) ; +; Total block memory bits ; 0 / 516,096 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 516,096 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out ; 3 ; +; Highest non-global fan-out ; 3 ; +; Total fan-out ; 56 ; +; Average fan-out ; 1.22 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 10 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % ) ; +; -- Combinational with no register ; 10 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 5 ; 0 ; +; -- 3 input functions ; 3 ; 0 ; +; -- <=2 input functions ; 2 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 10 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 15408 ( 0 % ) ; 0 / 15408 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 1 / 963 ( < 1 % ) ; 0 / 963 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 13 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; 0 / 112 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 51 ; 5 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 8 ; 0 ; +; -- Output Ports ; 5 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; A0 ; H7 ; 1 ; 0 ; 25 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; A1 ; E3 ; 1 ; 0 ; 26 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; A2 ; E4 ; 1 ; 0 ; 26 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; A3 ; D2 ; 1 ; 0 ; 25 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; B0 ; H6 ; 1 ; 0 ; 25 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; B1 ; G4 ; 1 ; 0 ; 23 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; B2 ; G5 ; 1 ; 0 ; 27 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; B3 ; J7 ; 1 ; 0 ; 22 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; C4 ; B1 ; 1 ; 0 ; 27 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; S0 ; E1 ; 1 ; 0 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; S1 ; C1 ; 1 ; 0 ; 26 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; S2 ; C2 ; 1 ; 0 ; 26 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; S3 ; B2 ; 1 ; 0 ; 27 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; E4 ; DIFFIO_L2p, nRESET ; Use as regular IO ; A2 ; Dual Purpose Pin ; +; D1 ; DIFFIO_L4n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; E2 ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; K6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; K2 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; K1 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; K5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; L3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; M18 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; M17 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; L18 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; L17 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; K20 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; K22 ; DIFFIO_R16n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 17 / 33 ( 52 % ) ; 2.5V ; -- ; +; 2 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 46 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 41 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 46 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 1 / 43 ( 2 % ) ; 2.5V ; -- ; +; 7 ; 0 / 47 ( 0 % ) ; 2.5V ; -- ; +; 8 ; 0 / 43 ( 0 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A3 ; 354 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 350 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 345 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 336 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 334 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 332 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 328 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 326 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 321 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A12 ; 319 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 314 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 312 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 307 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 298 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 296 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 291 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 290 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 284 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA3 ; 102 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA4 ; 106 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA5 ; 108 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA7 ; 115 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 123 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 134 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA12 ; 136 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA13 ; 138 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; 140 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 145 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 149 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 151 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; 163 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; 164 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 169 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 179 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 178 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB3 ; 103 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 107 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 109 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB7 ; 116 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 135 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AB12 ; 137 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AB13 ; 139 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 141 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 146 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 150 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 152 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 162 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 165 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 170 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 2 ; 1 ; C4 ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; B2 ; 1 ; 1 ; S3 ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; B3 ; 355 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 351 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 346 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 337 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 335 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 333 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; 329 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B10 ; 327 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 322 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B12 ; 320 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 315 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; 313 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 308 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; 299 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 297 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; 292 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B19 ; 289 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 285 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 269 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 268 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 7 ; 1 ; S1 ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; C2 ; 6 ; 1 ; S2 ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; C3 ; 358 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 359 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 349 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 340 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 339 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C10 ; 330 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; 309 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C15 ; 300 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 286 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C19 ; 282 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 270 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 267 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 266 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 9 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; D2 ; 8 ; 1 ; A3 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D6 ; 356 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D10 ; 324 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D13 ; 310 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D15 ; 293 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D17 ; 281 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D19 ; 283 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D20 ; 271 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D21 ; 261 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D22 ; 260 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 14 ; 1 ; S0 ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E2 ; 13 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; E3 ; 5 ; 1 ; A1 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E4 ; 4 ; 1 ; A2 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E5 ; 363 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E6 ; 362 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; 357 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E9 ; 338 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; E10 ; 325 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 317 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 316 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 311 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 301 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 294 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 275 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E18 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E21 ; 256 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 255 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 16 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F7 ; 360 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 352 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 347 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 348 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 318 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; 302 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F13 ; 306 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F14 ; 279 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F15 ; 276 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 274 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 272 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F19 ; 263 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 262 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 251 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 250 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 39 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G2 ; 38 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G3 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 17 ; 1 ; B1 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; G5 ; 3 ; 1 ; B2 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; G6 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G7 ; 361 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; 353 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G9 ; 342 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G10 ; 341 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 331 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 305 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; 295 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G14 ; 280 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G15 ; 278 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 277 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 273 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; 264 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G21 ; 226 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G22 ; 225 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; H1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H5 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H6 ; 11 ; 1 ; B0 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; H7 ; 10 ; 1 ; A0 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; 344 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H10 ; 343 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H11 ; 323 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 304 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 303 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 288 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 287 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; 259 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H17 ; 265 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 257 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; H19 ; 254 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 253 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 246 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 245 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J3 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; J4 ; 24 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J6 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J7 ; 22 ; 1 ; B3 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J15 ; 238 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; 243 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J17 ; 258 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J18 ; 249 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J21 ; 242 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 241 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 31 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; K2 ; 30 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K5 ; 32 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; K6 ; 19 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K8 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; 236 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; 244 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K17 ; 247 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K18 ; 248 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 237 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; K20 ; 231 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; K21 ; 240 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 239 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L1 ; 35 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; L2 ; 34 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; L3 ; 37 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L5 ; 33 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; L6 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L7 ; 50 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L8 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; 233 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; 232 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L17 ; 230 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 229 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; L19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L21 ; 235 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L22 ; 234 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 45 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M3 ; 47 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 46 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 51 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M6 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M7 ; 65 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M8 ; 66 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; 195 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; 222 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M17 ; 228 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 227 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; M19 ; 221 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M20 ; 220 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 219 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 218 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 49 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 48 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N5 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; 64 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N7 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N8 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 189 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 196 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; 205 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N17 ; 214 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N18 ; 215 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 213 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 212 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 217 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 216 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 53 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 52 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 63 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P7 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P8 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; 180 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 192 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 193 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P17 ; 197 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P18 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P20 ; 208 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; P21 ; 211 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 210 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; 55 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 54 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R5 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R7 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R9 ; 88 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 90 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 97 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 98 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 153 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R16 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R17 ; 194 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R18 ; 203 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; 204 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R20 ; 200 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; 207 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R22 ; 206 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 41 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T2 ; 40 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T3 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; T4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T7 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T8 ; 89 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 91 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T10 ; 121 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T11 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 148 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T14 ; 160 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T15 ; 161 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T16 ; 171 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T17 ; 181 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T18 ; 182 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 224 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T22 ; 223 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; U1 ; 60 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; 94 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; 95 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U9 ; 112 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U10 ; 122 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U11 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U12 ; 147 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U13 ; 156 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U14 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U15 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U19 ; 188 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 187 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 202 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 201 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 62 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; 61 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V5 ; 93 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; 92 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V7 ; 105 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 113 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 119 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; V10 ; 120 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 142 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 154 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 157 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 158 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 168 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; V17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V18 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V21 ; 199 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 198 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W6 ; 104 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 110 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 114 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W10 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W13 ; 143 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 155 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; W15 ; 159 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W17 ; 166 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W19 ; 184 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 183 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 191 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; 190 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y2 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y3 ; 99 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 96 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; 101 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 111 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 117 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 144 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y17 ; 167 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 186 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 185 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++-----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++-----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------+--------------+ +; |BCD_adder_1D ; 10 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 10 (2) ; 0 (0) ; 0 (0) ; |BCD_adder_1D ; work ; +; |four_bir_adder:inst2| ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst2 ; work ; +; |Full_adder_S:inst2| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst2 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1 ; work ; +; |Full_adder_S:inst3| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst3 ; work ; +; |Half_adder:inst| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst ; work ; +; |Full_adder_S:inst| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1 ; work ; +; |four_bir_adder:inst| ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst ; work ; +; |Full_adder_S:inst2| ; 2 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst2 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1 ; work ; +; |Full_adder_S:inst3| ; 2 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst3 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1 ; work ; +; |Full_adder_S:inst4| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst4 ; work ; +; |Half_adder:inst| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst ; work ; ++-----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; S0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S2 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S3 ; Output ; -- ; -- ; -- ; -- ; -- ; +; C4 ; Output ; -- ; -- ; -- ; -- ; -- ; +; A0 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; B0 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; A1 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; B1 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; A2 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; B2 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; B3 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; A3 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------------------------------------------+-------------------+---------+ +; A0 ; ; ; +; - four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst|inst ; 0 ; 6 ; +; - four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; - four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 0 ; 6 ; +; B0 ; ; ; +; - four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst|inst ; 0 ; 6 ; +; - four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; - four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 0 ; 6 ; +; A1 ; ; ; +; - four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; - four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 0 ; 6 ; +; B1 ; ; ; +; - four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst~0 ; 1 ; 6 ; +; - four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 1 ; 6 ; +; A2 ; ; ; +; - inst6~0 ; 0 ; 6 ; +; - four_bir_adder:inst|Full_adder_S:inst2|inst2~0 ; 0 ; 6 ; +; - four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; B2 ; ; ; +; - inst6~0 ; 0 ; 6 ; +; - four_bir_adder:inst|Full_adder_S:inst2|inst2~0 ; 0 ; 6 ; +; - four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; B3 ; ; ; +; - inst6~1 ; 1 ; 6 ; +; - four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1|inst~0 ; 1 ; 6 ; +; A3 ; ; ; +; - inst6~1 ; 1 ; 6 ; +; - four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1|inst~0 ; 1 ; 6 ; ++-----------------------------------------------------------------------+-------------------+---------+ + + ++---------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++-----------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++-----------------------------------------------------------------+---------+ +; B2~input ; 3 ; +; A2~input ; 3 ; +; B0~input ; 3 ; +; A0~input ; 3 ; +; inst6~1 ; 3 ; +; four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 3 ; +; four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst~0 ; 3 ; +; A3~input ; 2 ; +; B3~input ; 2 ; +; B1~input ; 2 ; +; A1~input ; 2 ; +; four_bir_adder:inst|Full_adder_S:inst2|inst2~0 ; 2 ; +; inst6~0 ; 2 ; +; four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1|inst~0 ; 1 ; +; four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1|inst~0 ; 1 ; +; four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1|inst~0 ; 1 ; +; four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst|inst ; 1 ; +; four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst|inst ; 1 ; ++-----------------------------------------------------------------+---------+ + + ++-----------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+-----------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+-----------------------+ +; Block interconnects ; 13 / 47,787 ( < 1 % ) ; +; C16 interconnects ; 0 / 1,804 ( 0 % ) ; +; C4 interconnects ; 12 / 31,272 ( < 1 % ) ; +; Direct links ; 1 / 47,787 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 6 / 15,408 ( < 1 % ) ; +; R24 interconnects ; 0 / 1,775 ( 0 % ) ; +; R4 interconnects ; 0 / 41,310 ( 0 % ) ; ++-----------------------+-----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 10.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++---------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 10.00) ; Number of LABs (Total = 1) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 1) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 8.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 13 ; 0 ; 13 ; 0 ; 0 ; 13 ; 13 ; 0 ; 13 ; 13 ; 0 ; 5 ; 0 ; 0 ; 8 ; 0 ; 5 ; 8 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 13 ; 0 ; 13 ; 13 ; 0 ; 0 ; 13 ; 0 ; 0 ; 13 ; 8 ; 13 ; 13 ; 5 ; 13 ; 8 ; 5 ; 13 ; 13 ; 13 ; 8 ; 13 ; 13 ; 13 ; 13 ; 13 ; 0 ; 13 ; 13 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; S0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; C4 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device EP3C16F484C6 for design "BCD_adder_1D" +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP3C40F484C6 is compatible + Info (176445): Device EP3C55F484C6 is compatible + Info (176445): Device EP3C80F484C6 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'BCD_adder_1D.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:03 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.24 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 +Info (144001): Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D.fit.smsg +Info: Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 535 megabytes + Info: Processing ended: Thu Sep 5 20:28:58 2019 + Info: Elapsed time: 00:00:12 + Info: Total CPU time (on all processors): 00:00:11 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D.fit.smsg. + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.fit.smsg b/CH5/CH5-3/output_files/BCD_adder_1D.fit.smsg new file mode 100644 index 00000000..7121cbb1 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.fit.summary b/CH5/CH5-3/output_files/BCD_adder_1D.fit.summary new file mode 100644 index 00000000..4ef452ad --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Thu Sep 5 20:28:57 2019 +Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition +Revision Name : BCD_adder_1D +Top-level Entity Name : BCD_adder_1D +Family : Cyclone III +Device : EP3C16F484C6 +Timing Models : Final +Total logic elements : 10 / 15,408 ( < 1 % ) + Total combinational functions : 10 / 15,408 ( < 1 % ) + Dedicated logic registers : 0 / 15,408 ( 0 % ) +Total registers : 0 +Total pins : 13 / 347 ( 4 % ) +Total virtual pins : 0 +Total memory bits : 0 / 516,096 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.flow.rpt b/CH5/CH5-3/output_files/BCD_adder_1D.flow.rpt new file mode 100644 index 00000000..a97e308f --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.flow.rpt @@ -0,0 +1,128 @@ +Flow report for BCD_adder_1D +Thu Sep 5 20:29:14 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+--------------------------------------------+ +; Flow Status ; Successful - Thu Sep 5 20:29:14 2019 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_1D ; +; Top-level Entity Name ; BCD_adder_1D ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Total logic elements ; 10 / 15,408 ( < 1 % ) ; +; Total combinational functions ; 10 / 15,408 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 13 / 347 ( 4 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 516,096 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+--------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 09/05/2019 20:28:42 ; +; Main task ; Compilation ; +; Revision Name ; BCD_adder_1D ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 0.156768652223373 ; -- ; -- ; -- ; +; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+------------------------+---------------+-------------+----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 372 MB ; 00:00:02 ; +; Fitter ; 00:00:11 ; 1.0 ; 535 MB ; 00:00:11 ; +; Assembler ; 00:00:03 ; 1.0 ; 378 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 369 MB ; 00:00:03 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 327 MB ; 00:00:01 ; +; Total ; 00:00:19 ; -- ; -- ; 00:00:19 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+-------------------+----------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+-------------------+----------------+------------+----------------+ +; Analysis & Synthesis ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; Fitter ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; Assembler ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; TimeQuest Timing Analyzer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; EDA Netlist Writer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; ++---------------------------+-------------------+----------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D -c BCD_adder_1D +quartus_fit --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D +quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D +quartus_sta BCD_adder_1D -c BCD_adder_1D +quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_1D -c BCD_adder_1D + + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.jdi b/CH5/CH5-3/output_files/BCD_adder_1D.jdi new file mode 100644 index 00000000..2048be73 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.map.rpt b/CH5/CH5-3/output_files/BCD_adder_1D.map.rpt new file mode 100644 index 00000000..600028bf --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.map.rpt @@ -0,0 +1,287 @@ +Analysis & Synthesis report for BCD_adder_1D +Thu Sep 5 20:28:44 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Elapsed Time Per Partition + 10. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+--------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Sep 5 20:28:44 2019 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_1D ; +; Top-level Entity Name ; BCD_adder_1D ; +; Family ; Cyclone III ; +; Total logic elements ; 10 ; +; Total combinational functions ; 10 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 13 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+--------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP3C16F484C6 ; ; +; Top-level entity name ; BCD_adder_1D ; BCD_adder_1D ; +; Family name ; Cyclone III ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+ +; ../CH5-1/Full_adder_S.bdf ; yes ; User Block Diagram/Schematic File ; /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf ; ; +; ../CH5-1/four_bir_adder.bdf ; yes ; User Block Diagram/Schematic File ; /home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf ; ; +; ../CH5-1/Half_adder.bdf ; yes ; User Block Diagram/Schematic File ; /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf ; ; +; BCD_adder_1D.bdf ; yes ; User Block Diagram/Schematic File ; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf ; ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------------------------------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------------------------------------------------+ +; Estimated Total logic elements ; 10 ; +; ; ; +; Total combinational functions ; 10 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 5 ; +; -- 3 input functions ; 3 ; +; -- <=2 input functions ; 2 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 10 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 13 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst~0 ; +; Maximum fan-out ; 3 ; +; Total fan-out ; 51 ; +; Average fan-out ; 1.42 ; ++---------------------------------------------+----------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++-----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------+--------------+ +; |BCD_adder_1D ; 10 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; |BCD_adder_1D ; work ; +; |four_bir_adder:inst2| ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst2 ; work ; +; |Full_adder_S:inst2| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst2 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1 ; work ; +; |Full_adder_S:inst3| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst3 ; work ; +; |Half_adder:inst| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst ; work ; +; |Full_adder_S:inst| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1 ; work ; +; |four_bir_adder:inst| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst ; work ; +; |Full_adder_S:inst2| ; 2 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst2 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1 ; work ; +; |Full_adder_S:inst3| ; 2 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst3 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1 ; work ; +; |Full_adder_S:inst4| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst4 ; work ; +; |Half_adder:inst| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst ; work ; ++-----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit Analysis & Synthesis + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Thu Sep 5 20:28:42 2019 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D -c BCD_adder_1D +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file BCD_adder_7483.bdf + Info (12023): Found entity 1: BCD_adder_7483 +Info (12021): Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf + Info (12023): Found entity 1: Full_adder_S +Info (12021): Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf + Info (12023): Found entity 1: four_bir_adder +Info (12021): Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf + Info (12023): Found entity 1: eight_bit_adder +Info (12021): Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf + Info (12023): Found entity 1: Half_adder +Info (12021): Found 1 design units, including 1 entities, in source file BCD_adder_1D.bdf + Info (12023): Found entity 1: BCD_adder_1D +Info (12127): Elaborating entity "BCD_adder_1D" for the top level hierarchy +Info (12128): Elaborating entity "four_bir_adder" for hierarchy "four_bir_adder:inst2" +Info (12128): Elaborating entity "Full_adder_S" for hierarchy "four_bir_adder:inst2|Full_adder_S:inst2" +Info (12128): Elaborating entity "Half_adder" for hierarchy "four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1" +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 23 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 8 input pins + Info (21059): Implemented 5 output pins + Info (21061): Implemented 10 logic cells +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 383 megabytes + Info: Processing ended: Thu Sep 5 20:28:44 2019 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.map.summary b/CH5/CH5-3/output_files/BCD_adder_1D.map.summary new file mode 100644 index 00000000..f98c03af --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Thu Sep 5 20:28:44 2019 +Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition +Revision Name : BCD_adder_1D +Top-level Entity Name : BCD_adder_1D +Family : Cyclone III +Total logic elements : 10 + Total combinational functions : 10 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 13 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.pin b/CH5/CH5-3/output_files/BCD_adder_1D.pin new file mode 100644 index 00000000..0a219f31 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.pin @@ -0,0 +1,554 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +CHIP "BCD_adder_1D" ASSIGNED TO AN: EP3C16F484C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO8 : A2 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 : +GND+ : A11 : : : : 8 : +GND+ : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +VCCIO7 : A21 : power : : 2.5V : 7 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +VCCIO3 : AA6 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +GND+ : AA11 : : : : 3 : +GND+ : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +VCCIO3 : AB2 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +GND : AB6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 : +GND+ : AB11 : : : : 3 : +GND+ : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +VCCIO4 : AB21 : power : : 2.5V : 4 : +GND : AB22 : gnd : : : : +C4 : B1 : output : 2.5 V : : 1 : Y +S3 : B2 : output : 2.5 V : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 : +GND+ : B11 : : : : 8 : +GND+ : B12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +S1 : C1 : output : 2.5 V : : 1 : Y +S2 : C2 : output : 2.5 V : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +GND : C5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +GND : C9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 : +GND : C11 : gnd : : : : +GND : C12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +GND : C14 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +GND : C16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +GND : C18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : input : 2.5 V : : 1 : N +A3 : D2 : input : 2.5 V : : 1 : Y +GND : D3 : gnd : : : : +VCCIO1 : D4 : power : : 2.5V : 1 : +VCCIO8 : D5 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +GND : D7 : gnd : : : : +GND : D8 : gnd : : : : +VCCIO8 : D9 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +VCCIO8 : D11 : power : : 2.5V : 8 : +VCCIO7 : D12 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +VCCIO7 : D14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +VCCIO7 : D16 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +VCCIO7 : D18 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +S0 : E1 : output : 2.5 V : : 1 : Y +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N +A1 : E3 : input : 2.5 V : : 1 : Y +A2 : E4 : input : 2.5 V : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : +VCCIO8 : E8 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 : +VCCD_PLL2 : E17 : power : : 1.2V : : +GNDA2 : E18 : gnd : : : : +VCCIO6 : E19 : power : : 2.5V : 6 : +GND : E20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 : +GND : F3 : gnd : : : : +VCCIO1 : F4 : power : : 2.5V : 1 : +GNDA3 : F5 : gnd : : : : +VCCD_PLL3 : F6 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +VCCA2 : F18 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +GND+ : G1 : : : : 1 : +GND+ : G2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 : +B1 : G4 : input : 2.5 V : : 1 : Y +B2 : G5 : input : 2.5 V : : 1 : Y +VCCA3 : G6 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 6 : +VCCIO6 : G19 : power : : 2.5V : 6 : +GND : G20 : gnd : : : : +GND+ : G21 : : : : 6 : +GND+ : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : : : : 1 : +GND : H3 : gnd : : : : +VCCIO1 : H4 : power : : 2.5V : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 : +B0 : H6 : input : 2.5 V : : 1 : Y +A0 : H7 : input : 2.5 V : : 1 : Y +GND : H8 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 : +GND : J5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 : +B3 : J7 : input : 2.5 V : : 1 : Y +VCCINT : J8 : power : : 1.2V : : +GND : J9 : gnd : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +VCCINT : J14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +VCCIO6 : J20 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : input : 2.5 V : : 1 : N +~ALTERA_DCLK~ : K2 : output : 2.5 V : : 1 : N +GND : K3 : gnd : : : : +VCCIO1 : K4 : power : : 2.5V : 1 : +nCONFIG : K5 : : : : 1 : +nSTATUS : K6 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +MSEL3 : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22 : output : 2.5 V : : 6 : N +TMS : L1 : input : : : 1 : +TCK : L2 : input : : : 1 : +nCE : L3 : : : : 1 : +TDO : L4 : output : : : 1 : +TDI : L5 : input : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 : +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 6 : +MSEL2 : L17 : : : : 6 : +MSEL1 : L18 : : : : 6 : +VCCIO6 : L19 : power : : 2.5V : 6 : +GND : L20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M16 : : : : 5 : +MSEL0 : M17 : : : : 6 : +CONF_DONE : M18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +GND : N3 : gnd : : : : +VCCIO2 : N4 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +VCCINT : P9 : power : : 1.2V : : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P17 : : : : 5 : +VCCIO5 : P18 : power : : 2.5V : 5 : +GND : P19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +GND : R3 : gnd : : : : +VCCIO2 : R4 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +GND+ : T1 : : : : 2 : +GND+ : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +VCCA1 : T6 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 4 : +VCCINT : T13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +VCCIO5 : T19 : power : : 2.5V : 5 : +GND : T20 : gnd : : : : +GND+ : T21 : : : : 5 : +GND+ : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +GND : U3 : gnd : : : : +VCCIO2 : U4 : power : : 2.5V : 2 : +GNDA1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCINT : U16 : power : : 1.2V : : +VCCINT : U17 : power : : 1.2V : : +VCCA4 : U18 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +VCCD_PLL4 : V17 : power : : 1.2V : : +GNDA4 : V18 : gnd : : : : +VCCIO5 : V19 : power : : 2.5V : 5 : +GND : V20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +GND : W3 : gnd : : : : +VCCIO2 : W4 : power : : 2.5V : 2 : +VCCIO3 : W5 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +VCCIO3 : W9 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +VCCIO3 : W11 : power : : 2.5V : 3 : +VCCIO4 : W12 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +VCCIO4 : W16 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +VCCIO4 : W18 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +GND : Y5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +GND : Y11 : gnd : : : : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +VCCIO4 : Y14 : power : : 2.5V : 4 : +GND : Y15 : gnd : : : : +GND : Y16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +GND : Y18 : gnd : : : : +VCCIO5 : Y19 : power : : 2.5V : 5 : +GND : Y20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.sof b/CH5/CH5-3/output_files/BCD_adder_1D.sof new file mode 100644 index 00000000..a5e1c0a2 Binary files /dev/null and b/CH5/CH5-3/output_files/BCD_adder_1D.sof differ diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.sta.rpt b/CH5/CH5-3/output_files/BCD_adder_1D.sta.rpt new file mode 100644 index 00000000..3bf0edab --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.sta.rpt @@ -0,0 +1,731 @@ +TimeQuest Timing Analyzer report for BCD_adder_1D +Thu Sep 5 20:29:09 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Propagation Delay + 13. Minimum Propagation Delay + 14. Slow 1200mV 85C Model Metastability Report + 15. Slow 1200mV 0C Model Fmax Summary + 16. Slow 1200mV 0C Model Setup Summary + 17. Slow 1200mV 0C Model Hold Summary + 18. Slow 1200mV 0C Model Recovery Summary + 19. Slow 1200mV 0C Model Removal Summary + 20. Slow 1200mV 0C Model Minimum Pulse Width Summary + 21. Propagation Delay + 22. Minimum Propagation Delay + 23. Slow 1200mV 0C Model Metastability Report + 24. Fast 1200mV 0C Model Setup Summary + 25. Fast 1200mV 0C Model Hold Summary + 26. Fast 1200mV 0C Model Recovery Summary + 27. Fast 1200mV 0C Model Removal Summary + 28. Fast 1200mV 0C Model Minimum Pulse Width Summary + 29. Propagation Delay + 30. Minimum Propagation Delay + 31. Fast 1200mV 0C Model Metastability Report + 32. Multicorner Timing Analysis Summary + 33. Propagation Delay + 34. Minimum Propagation Delay + 35. Board Trace Model Assignments + 36. Input Transition Times + 37. Slow Corner Signal Integrity Metrics + 38. Fast Corner Signal Integrity Metrics + 39. Clock Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths + 43. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+----------------------------------------------------+ +; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_1D ; +; Device Family ; Cyclone III ; +; Device Name ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+----------------------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 7.543 ; 7.609 ; 7.932 ; 8.045 ; +; A0 ; S0 ; 6.290 ; 6.269 ; 6.678 ; 6.689 ; +; A0 ; S1 ; 7.865 ; 7.834 ; 8.301 ; 8.270 ; +; A0 ; S2 ; 7.875 ; 7.840 ; 8.311 ; 8.276 ; +; A0 ; S3 ; 7.572 ; 7.577 ; 7.993 ; 7.998 ; +; A1 ; C4 ; 7.456 ; 7.524 ; 7.892 ; 7.966 ; +; A1 ; S1 ; 7.780 ; 7.749 ; 8.222 ; 8.191 ; +; A1 ; S2 ; 7.790 ; 7.755 ; 8.232 ; 8.197 ; +; A1 ; S3 ; 7.487 ; 7.492 ; 7.914 ; 7.919 ; +; A2 ; C4 ; 7.269 ; 7.187 ; 7.557 ; 7.771 ; +; A2 ; S1 ; 7.522 ; 7.500 ; 8.027 ; 7.996 ; +; A2 ; S2 ; 7.532 ; 7.506 ; 8.037 ; 8.002 ; +; A2 ; S3 ; 7.241 ; 7.290 ; 7.719 ; 7.711 ; +; A3 ; C4 ; 6.829 ; ; ; 7.297 ; +; A3 ; S1 ; 7.082 ; 7.060 ; 7.553 ; 7.522 ; +; A3 ; S2 ; 7.092 ; 7.066 ; 7.563 ; 7.528 ; +; A3 ; S3 ; 6.801 ; 6.847 ; 7.235 ; 7.237 ; +; B0 ; C4 ; 7.660 ; 7.769 ; 8.102 ; 8.173 ; +; B0 ; S0 ; 6.420 ; 6.429 ; 6.848 ; 6.843 ; +; B0 ; S1 ; 8.025 ; 7.994 ; 8.429 ; 8.398 ; +; B0 ; S2 ; 8.035 ; 8.000 ; 8.439 ; 8.404 ; +; B0 ; S3 ; 7.732 ; 7.737 ; 8.121 ; 8.113 ; +; B1 ; C4 ; 7.732 ; 7.824 ; 8.168 ; 8.257 ; +; B1 ; S1 ; 8.080 ; 8.049 ; 8.513 ; 8.482 ; +; B1 ; S2 ; 8.090 ; 8.055 ; 8.523 ; 8.488 ; +; B1 ; S3 ; 7.787 ; 7.792 ; 8.220 ; 8.225 ; +; B2 ; C4 ; 7.373 ; 7.019 ; 7.406 ; 7.907 ; +; B2 ; S1 ; 7.626 ; 7.604 ; 8.163 ; 8.132 ; +; B2 ; S2 ; 7.636 ; 7.610 ; 8.173 ; 8.138 ; +; B2 ; S3 ; 7.345 ; 7.394 ; 7.855 ; 7.847 ; +; B3 ; C4 ; 6.646 ; ; ; 7.081 ; +; B3 ; S1 ; 6.899 ; 6.877 ; 7.337 ; 7.306 ; +; B3 ; S2 ; 6.909 ; 6.883 ; 7.347 ; 7.312 ; +; B3 ; S3 ; 6.610 ; 6.622 ; 7.003 ; 7.047 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 7.108 ; 7.128 ; 7.535 ; 7.546 ; +; A0 ; S0 ; 6.150 ; 6.129 ; 6.528 ; 6.538 ; +; A0 ; S1 ; 6.951 ; 6.913 ; 7.330 ; 7.292 ; +; A0 ; S2 ; 6.923 ; 6.925 ; 7.302 ; 7.304 ; +; A0 ; S3 ; 7.077 ; 7.089 ; 7.504 ; 7.515 ; +; A1 ; C4 ; 7.028 ; 7.048 ; 7.461 ; 7.472 ; +; A1 ; S1 ; 6.870 ; 6.832 ; 7.293 ; 7.255 ; +; A1 ; S2 ; 6.842 ; 6.844 ; 7.265 ; 7.267 ; +; A1 ; S3 ; 6.997 ; 7.009 ; 7.430 ; 7.441 ; +; A2 ; C4 ; 6.943 ; 6.977 ; 7.340 ; 7.350 ; +; A2 ; S1 ; 7.186 ; 7.164 ; 7.583 ; 7.561 ; +; A2 ; S2 ; 6.889 ; 6.865 ; 7.269 ; 7.245 ; +; A2 ; S3 ; 6.912 ; 6.924 ; 7.309 ; 7.319 ; +; A3 ; C4 ; 6.636 ; ; ; 7.048 ; +; A3 ; S1 ; 6.879 ; 6.857 ; 7.294 ; 7.263 ; +; A3 ; S2 ; 6.888 ; 6.863 ; 7.303 ; 7.269 ; +; A3 ; S3 ; 6.582 ; 6.643 ; 7.022 ; 7.002 ; +; B0 ; C4 ; 7.188 ; 7.208 ; 7.600 ; 7.611 ; +; B0 ; S0 ; 6.215 ; 6.221 ; 6.631 ; 6.607 ; +; B0 ; S1 ; 7.018 ; 6.980 ; 7.433 ; 7.395 ; +; B0 ; S2 ; 6.990 ; 6.992 ; 7.405 ; 7.407 ; +; B0 ; S3 ; 7.157 ; 7.169 ; 7.569 ; 7.580 ; +; B1 ; C4 ; 7.229 ; 7.249 ; 7.672 ; 7.683 ; +; B1 ; S1 ; 7.072 ; 7.034 ; 7.505 ; 7.467 ; +; B1 ; S2 ; 7.044 ; 7.046 ; 7.477 ; 7.479 ; +; B1 ; S3 ; 7.198 ; 7.210 ; 7.641 ; 7.652 ; +; B2 ; C4 ; 6.831 ; 6.849 ; 7.228 ; 7.277 ; +; B2 ; S1 ; 7.074 ; 7.052 ; 7.471 ; 7.449 ; +; B2 ; S2 ; 6.940 ; 6.916 ; 7.370 ; 7.352 ; +; B2 ; S3 ; 6.800 ; 6.812 ; 7.197 ; 7.209 ; +; B3 ; C4 ; 6.492 ; ; ; 6.915 ; +; B3 ; S1 ; 6.735 ; 6.713 ; 7.161 ; 7.130 ; +; B3 ; S2 ; 6.744 ; 6.719 ; 7.170 ; 7.136 ; +; B3 ; S3 ; 6.458 ; 6.468 ; 6.842 ; 6.883 ; ++------------+-------------+-------+-------+-------+-------+ + + +---------------------------------------------- +; Slow 1200mV 85C Model Metastability Report ; +---------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 6.995 ; 7.012 ; 7.324 ; 7.380 ; +; A0 ; S0 ; 5.851 ; 5.818 ; 6.176 ; 6.172 ; +; A0 ; S1 ; 7.262 ; 7.227 ; 7.630 ; 7.595 ; +; A0 ; S2 ; 7.272 ; 7.230 ; 7.640 ; 7.598 ; +; A0 ; S3 ; 7.003 ; 6.982 ; 7.361 ; 7.340 ; +; A1 ; C4 ; 6.919 ; 6.938 ; 7.284 ; 7.307 ; +; A1 ; S1 ; 7.188 ; 7.153 ; 7.557 ; 7.522 ; +; A1 ; S2 ; 7.198 ; 7.156 ; 7.567 ; 7.525 ; +; A1 ; S3 ; 6.929 ; 6.908 ; 7.286 ; 7.265 ; +; A2 ; C4 ; 6.738 ; 6.638 ; 6.994 ; 7.156 ; +; A2 ; S1 ; 6.966 ; 6.939 ; 7.406 ; 7.371 ; +; A2 ; S2 ; 6.976 ; 6.942 ; 7.416 ; 7.374 ; +; A2 ; S3 ; 6.712 ; 6.730 ; 7.129 ; 7.100 ; +; A3 ; C4 ; 6.353 ; ; ; 6.718 ; +; A3 ; S1 ; 6.581 ; 6.554 ; 6.968 ; 6.933 ; +; A3 ; S2 ; 6.591 ; 6.557 ; 6.978 ; 6.936 ; +; A3 ; S3 ; 6.324 ; 6.338 ; 6.684 ; 6.662 ; +; B0 ; C4 ; 7.096 ; 7.152 ; 7.469 ; 7.488 ; +; B0 ; S0 ; 5.962 ; 5.957 ; 6.327 ; 6.308 ; +; B0 ; S1 ; 7.402 ; 7.367 ; 7.738 ; 7.703 ; +; B0 ; S2 ; 7.412 ; 7.370 ; 7.748 ; 7.706 ; +; B0 ; S3 ; 7.143 ; 7.122 ; 7.461 ; 7.432 ; +; B1 ; C4 ; 7.165 ; 7.206 ; 7.530 ; 7.567 ; +; B1 ; S1 ; 7.456 ; 7.421 ; 7.817 ; 7.782 ; +; B1 ; S2 ; 7.466 ; 7.424 ; 7.827 ; 7.785 ; +; B1 ; S3 ; 7.197 ; 7.176 ; 7.558 ; 7.537 ; +; B2 ; C4 ; 6.832 ; 6.485 ; 6.846 ; 7.250 ; +; B2 ; S1 ; 7.060 ; 7.033 ; 7.500 ; 7.465 ; +; B2 ; S2 ; 7.070 ; 7.036 ; 7.510 ; 7.468 ; +; B2 ; S3 ; 6.806 ; 6.824 ; 7.223 ; 7.194 ; +; B3 ; C4 ; 6.183 ; ; ; 6.538 ; +; B3 ; S1 ; 6.411 ; 6.384 ; 6.788 ; 6.753 ; +; B3 ; S2 ; 6.421 ; 6.387 ; 6.798 ; 6.756 ; +; B3 ; S3 ; 6.150 ; 6.135 ; 6.492 ; 6.506 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 6.611 ; 6.596 ; 6.966 ; 6.945 ; +; A0 ; S0 ; 5.731 ; 5.698 ; 6.049 ; 6.044 ; +; A0 ; S1 ; 6.456 ; 6.421 ; 6.777 ; 6.742 ; +; A0 ; S2 ; 6.434 ; 6.428 ; 6.755 ; 6.749 ; +; A0 ; S3 ; 6.580 ; 6.566 ; 6.935 ; 6.916 ; +; A1 ; C4 ; 6.541 ; 6.526 ; 6.898 ; 6.877 ; +; A1 ; S1 ; 6.385 ; 6.350 ; 6.740 ; 6.705 ; +; A1 ; S2 ; 6.363 ; 6.357 ; 6.718 ; 6.710 ; +; A1 ; S3 ; 6.510 ; 6.496 ; 6.867 ; 6.848 ; +; A2 ; C4 ; 6.456 ; 6.454 ; 6.803 ; 6.782 ; +; A2 ; S1 ; 6.675 ; 6.648 ; 7.021 ; 6.988 ; +; A2 ; S2 ; 6.402 ; 6.368 ; 6.744 ; 6.710 ; +; A2 ; S3 ; 6.425 ; 6.411 ; 6.772 ; 6.753 ; +; A3 ; C4 ; 6.184 ; ; ; 6.502 ; +; A3 ; S1 ; 6.403 ; 6.376 ; 6.741 ; 6.708 ; +; A3 ; S2 ; 6.413 ; 6.379 ; 6.752 ; 6.712 ; +; A3 ; S3 ; 6.132 ; 6.163 ; 6.501 ; 6.459 ; +; B0 ; C4 ; 6.678 ; 6.663 ; 7.019 ; 6.998 ; +; B0 ; S0 ; 5.783 ; 5.779 ; 6.140 ; 6.105 ; +; B0 ; S1 ; 6.511 ; 6.476 ; 6.863 ; 6.828 ; +; B0 ; S2 ; 6.489 ; 6.483 ; 6.841 ; 6.835 ; +; B0 ; S3 ; 6.647 ; 6.633 ; 6.988 ; 6.969 ; +; B1 ; C4 ; 6.717 ; 6.702 ; 7.083 ; 7.062 ; +; B1 ; S1 ; 6.563 ; 6.528 ; 6.926 ; 6.891 ; +; B1 ; S2 ; 6.541 ; 6.535 ; 6.904 ; 6.898 ; +; B1 ; S3 ; 6.686 ; 6.672 ; 7.052 ; 7.033 ; +; B2 ; C4 ; 6.357 ; 6.340 ; 6.693 ; 6.704 ; +; B2 ; S1 ; 6.576 ; 6.546 ; 6.912 ; 6.885 ; +; B2 ; S2 ; 6.446 ; 6.412 ; 6.806 ; 6.777 ; +; B2 ; S3 ; 6.326 ; 6.311 ; 6.662 ; 6.648 ; +; B3 ; C4 ; 6.050 ; ; ; 6.396 ; +; B3 ; S1 ; 6.269 ; 6.242 ; 6.635 ; 6.602 ; +; B3 ; S2 ; 6.279 ; 6.245 ; 6.646 ; 6.606 ; +; B3 ; S3 ; 6.020 ; 6.004 ; 6.354 ; 6.366 ; ++------------+-------------+-------+-------+-------+-------+ + + +--------------------------------------------- +; Slow 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 4.469 ; 4.536 ; 5.018 ; 5.118 ; +; A0 ; S0 ; 3.762 ; 3.761 ; 4.310 ; 4.327 ; +; A0 ; S1 ; 4.647 ; 4.662 ; 5.229 ; 5.244 ; +; A0 ; S2 ; 4.658 ; 4.664 ; 5.240 ; 5.246 ; +; A0 ; S3 ; 4.502 ; 4.520 ; 5.078 ; 5.087 ; +; A1 ; C4 ; 4.431 ; 4.501 ; 5.002 ; 5.080 ; +; A1 ; S1 ; 4.612 ; 4.627 ; 5.191 ; 5.206 ; +; A1 ; S2 ; 4.623 ; 4.629 ; 5.202 ; 5.208 ; +; A1 ; S3 ; 4.467 ; 4.485 ; 5.040 ; 5.049 ; +; A2 ; C4 ; 4.337 ; 4.305 ; 4.841 ; 4.980 ; +; A2 ; S1 ; 4.452 ; 4.474 ; 5.091 ; 5.106 ; +; A2 ; S2 ; 4.463 ; 4.476 ; 5.102 ; 5.108 ; +; A2 ; S3 ; 4.319 ; 4.359 ; 4.940 ; 4.941 ; +; A3 ; C4 ; 4.115 ; ; ; 4.725 ; +; A3 ; S1 ; 4.230 ; 4.252 ; 4.836 ; 4.851 ; +; A3 ; S2 ; 4.241 ; 4.254 ; 4.847 ; 4.853 ; +; A3 ; S3 ; 4.096 ; 4.135 ; 4.681 ; 4.688 ; +; B0 ; C4 ; 4.531 ; 4.620 ; 5.127 ; 5.196 ; +; B0 ; S0 ; 3.835 ; 3.848 ; 4.422 ; 4.422 ; +; B0 ; S1 ; 4.731 ; 4.746 ; 5.307 ; 5.322 ; +; B0 ; S2 ; 4.742 ; 4.748 ; 5.318 ; 5.324 ; +; B0 ; S3 ; 4.586 ; 4.604 ; 5.156 ; 5.157 ; +; B1 ; C4 ; 4.577 ; 4.657 ; 5.165 ; 5.240 ; +; B1 ; S1 ; 4.768 ; 4.783 ; 5.351 ; 5.366 ; +; B1 ; S2 ; 4.779 ; 4.785 ; 5.362 ; 5.368 ; +; B1 ; S3 ; 4.623 ; 4.641 ; 5.202 ; 5.220 ; +; B2 ; C4 ; 4.390 ; 4.212 ; 4.730 ; 5.041 ; +; B2 ; S1 ; 4.505 ; 4.527 ; 5.152 ; 5.167 ; +; B2 ; S2 ; 4.516 ; 4.529 ; 5.163 ; 5.169 ; +; B2 ; S3 ; 4.372 ; 4.412 ; 5.001 ; 5.002 ; +; B3 ; C4 ; 3.998 ; ; ; 4.584 ; +; B3 ; S1 ; 4.113 ; 4.135 ; 4.695 ; 4.710 ; +; B3 ; S2 ; 4.124 ; 4.137 ; 4.706 ; 4.712 ; +; B3 ; S3 ; 3.979 ; 4.001 ; 4.527 ; 4.567 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 4.221 ; 4.259 ; 4.801 ; 4.832 ; +; A0 ; S0 ; 3.682 ; 3.679 ; 4.223 ; 4.240 ; +; A0 ; S1 ; 4.133 ; 4.138 ; 4.676 ; 4.681 ; +; A0 ; S2 ; 4.124 ; 4.144 ; 4.667 ; 4.687 ; +; A0 ; S3 ; 4.204 ; 4.228 ; 4.784 ; 4.808 ; +; A1 ; C4 ; 4.184 ; 4.222 ; 4.765 ; 4.796 ; +; A1 ; S1 ; 4.097 ; 4.102 ; 4.662 ; 4.667 ; +; A1 ; S2 ; 4.088 ; 4.108 ; 4.653 ; 4.673 ; +; A1 ; S3 ; 4.167 ; 4.191 ; 4.748 ; 4.772 ; +; A2 ; C4 ; 4.146 ; 4.185 ; 4.712 ; 4.740 ; +; A2 ; S1 ; 4.256 ; 4.277 ; 4.822 ; 4.843 ; +; A2 ; S2 ; 4.113 ; 4.122 ; 4.661 ; 4.670 ; +; A2 ; S3 ; 4.129 ; 4.153 ; 4.695 ; 4.719 ; +; A3 ; C4 ; 4.001 ; ; ; 4.582 ; +; A3 ; S1 ; 4.111 ; 4.132 ; 4.688 ; 4.702 ; +; A3 ; S2 ; 4.122 ; 4.135 ; 4.699 ; 4.705 ; +; A3 ; S3 ; 3.970 ; 4.016 ; 4.558 ; 4.555 ; +; B0 ; C4 ; 4.261 ; 4.299 ; 4.840 ; 4.871 ; +; B0 ; S0 ; 3.717 ; 3.727 ; 4.292 ; 4.285 ; +; B0 ; S1 ; 4.168 ; 4.173 ; 4.741 ; 4.746 ; +; B0 ; S2 ; 4.159 ; 4.179 ; 4.732 ; 4.752 ; +; B0 ; S3 ; 4.244 ; 4.268 ; 4.823 ; 4.847 ; +; B1 ; C4 ; 4.290 ; 4.328 ; 4.884 ; 4.915 ; +; B1 ; S1 ; 4.203 ; 4.208 ; 4.785 ; 4.790 ; +; B1 ; S2 ; 4.194 ; 4.214 ; 4.776 ; 4.796 ; +; B1 ; S3 ; 4.273 ; 4.297 ; 4.867 ; 4.891 ; +; B2 ; C4 ; 4.081 ; 4.114 ; 4.626 ; 4.679 ; +; B2 ; S1 ; 4.191 ; 4.212 ; 4.736 ; 4.757 ; +; B2 ; S2 ; 4.136 ; 4.145 ; 4.709 ; 4.720 ; +; B2 ; S3 ; 4.064 ; 4.088 ; 4.609 ; 4.633 ; +; B3 ; C4 ; 3.908 ; ; ; 4.488 ; +; B3 ; S1 ; 4.018 ; 4.039 ; 4.594 ; 4.608 ; +; B3 ; S2 ; 4.029 ; 4.042 ; 4.605 ; 4.611 ; +; B3 ; S3 ; 3.890 ; 3.909 ; 4.432 ; 4.471 ; ++------------+-------------+-------+-------+-------+-------+ + + +--------------------------------------------- +; Fast 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 7.543 ; 7.609 ; 7.932 ; 8.045 ; +; A0 ; S0 ; 6.290 ; 6.269 ; 6.678 ; 6.689 ; +; A0 ; S1 ; 7.865 ; 7.834 ; 8.301 ; 8.270 ; +; A0 ; S2 ; 7.875 ; 7.840 ; 8.311 ; 8.276 ; +; A0 ; S3 ; 7.572 ; 7.577 ; 7.993 ; 7.998 ; +; A1 ; C4 ; 7.456 ; 7.524 ; 7.892 ; 7.966 ; +; A1 ; S1 ; 7.780 ; 7.749 ; 8.222 ; 8.191 ; +; A1 ; S2 ; 7.790 ; 7.755 ; 8.232 ; 8.197 ; +; A1 ; S3 ; 7.487 ; 7.492 ; 7.914 ; 7.919 ; +; A2 ; C4 ; 7.269 ; 7.187 ; 7.557 ; 7.771 ; +; A2 ; S1 ; 7.522 ; 7.500 ; 8.027 ; 7.996 ; +; A2 ; S2 ; 7.532 ; 7.506 ; 8.037 ; 8.002 ; +; A2 ; S3 ; 7.241 ; 7.290 ; 7.719 ; 7.711 ; +; A3 ; C4 ; 6.829 ; ; ; 7.297 ; +; A3 ; S1 ; 7.082 ; 7.060 ; 7.553 ; 7.522 ; +; A3 ; S2 ; 7.092 ; 7.066 ; 7.563 ; 7.528 ; +; A3 ; S3 ; 6.801 ; 6.847 ; 7.235 ; 7.237 ; +; B0 ; C4 ; 7.660 ; 7.769 ; 8.102 ; 8.173 ; +; B0 ; S0 ; 6.420 ; 6.429 ; 6.848 ; 6.843 ; +; B0 ; S1 ; 8.025 ; 7.994 ; 8.429 ; 8.398 ; +; B0 ; S2 ; 8.035 ; 8.000 ; 8.439 ; 8.404 ; +; B0 ; S3 ; 7.732 ; 7.737 ; 8.121 ; 8.113 ; +; B1 ; C4 ; 7.732 ; 7.824 ; 8.168 ; 8.257 ; +; B1 ; S1 ; 8.080 ; 8.049 ; 8.513 ; 8.482 ; +; B1 ; S2 ; 8.090 ; 8.055 ; 8.523 ; 8.488 ; +; B1 ; S3 ; 7.787 ; 7.792 ; 8.220 ; 8.225 ; +; B2 ; C4 ; 7.373 ; 7.019 ; 7.406 ; 7.907 ; +; B2 ; S1 ; 7.626 ; 7.604 ; 8.163 ; 8.132 ; +; B2 ; S2 ; 7.636 ; 7.610 ; 8.173 ; 8.138 ; +; B2 ; S3 ; 7.345 ; 7.394 ; 7.855 ; 7.847 ; +; B3 ; C4 ; 6.646 ; ; ; 7.081 ; +; B3 ; S1 ; 6.899 ; 6.877 ; 7.337 ; 7.306 ; +; B3 ; S2 ; 6.909 ; 6.883 ; 7.347 ; 7.312 ; +; B3 ; S3 ; 6.610 ; 6.622 ; 7.003 ; 7.047 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 4.221 ; 4.259 ; 4.801 ; 4.832 ; +; A0 ; S0 ; 3.682 ; 3.679 ; 4.223 ; 4.240 ; +; A0 ; S1 ; 4.133 ; 4.138 ; 4.676 ; 4.681 ; +; A0 ; S2 ; 4.124 ; 4.144 ; 4.667 ; 4.687 ; +; A0 ; S3 ; 4.204 ; 4.228 ; 4.784 ; 4.808 ; +; A1 ; C4 ; 4.184 ; 4.222 ; 4.765 ; 4.796 ; +; A1 ; S1 ; 4.097 ; 4.102 ; 4.662 ; 4.667 ; +; A1 ; S2 ; 4.088 ; 4.108 ; 4.653 ; 4.673 ; +; A1 ; S3 ; 4.167 ; 4.191 ; 4.748 ; 4.772 ; +; A2 ; C4 ; 4.146 ; 4.185 ; 4.712 ; 4.740 ; +; A2 ; S1 ; 4.256 ; 4.277 ; 4.822 ; 4.843 ; +; A2 ; S2 ; 4.113 ; 4.122 ; 4.661 ; 4.670 ; +; A2 ; S3 ; 4.129 ; 4.153 ; 4.695 ; 4.719 ; +; A3 ; C4 ; 4.001 ; ; ; 4.582 ; +; A3 ; S1 ; 4.111 ; 4.132 ; 4.688 ; 4.702 ; +; A3 ; S2 ; 4.122 ; 4.135 ; 4.699 ; 4.705 ; +; A3 ; S3 ; 3.970 ; 4.016 ; 4.558 ; 4.555 ; +; B0 ; C4 ; 4.261 ; 4.299 ; 4.840 ; 4.871 ; +; B0 ; S0 ; 3.717 ; 3.727 ; 4.292 ; 4.285 ; +; B0 ; S1 ; 4.168 ; 4.173 ; 4.741 ; 4.746 ; +; B0 ; S2 ; 4.159 ; 4.179 ; 4.732 ; 4.752 ; +; B0 ; S3 ; 4.244 ; 4.268 ; 4.823 ; 4.847 ; +; B1 ; C4 ; 4.290 ; 4.328 ; 4.884 ; 4.915 ; +; B1 ; S1 ; 4.203 ; 4.208 ; 4.785 ; 4.790 ; +; B1 ; S2 ; 4.194 ; 4.214 ; 4.776 ; 4.796 ; +; B1 ; S3 ; 4.273 ; 4.297 ; 4.867 ; 4.891 ; +; B2 ; C4 ; 4.081 ; 4.114 ; 4.626 ; 4.679 ; +; B2 ; S1 ; 4.191 ; 4.212 ; 4.736 ; 4.757 ; +; B2 ; S2 ; 4.136 ; 4.145 ; 4.709 ; 4.720 ; +; B2 ; S3 ; 4.064 ; 4.088 ; 4.609 ; 4.633 ; +; B3 ; C4 ; 3.908 ; ; ; 4.488 ; +; B3 ; S1 ; 4.018 ; 4.039 ; 4.594 ; 4.608 ; +; B3 ; S2 ; 4.029 ; 4.042 ; 4.605 ; 4.611 ; +; B3 ; S3 ; 3.890 ; 3.909 ; 4.432 ; 4.471 ; ++------------+-------------+-------+-------+-------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; S0 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S1 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S2 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S3 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; C4 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; A0 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B0 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A1 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B1 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A2 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B2 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B3 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A3 ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; S0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; C4 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.68e-07 V ; 2.35 V ; -0.0132 V ; 0.2 V ; 0.027 V ; 5.26e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 5.68e-07 V ; 2.35 V ; -0.0132 V ; 0.2 V ; 0.027 V ; 5.26e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.36e-07 V ; 2.35 V ; -0.00444 V ; 0.18 V ; 0.019 V ; 7.23e-10 s ; 9.82e-10 s ; Yes ; Yes ; 2.32 V ; 9.36e-07 V ; 2.35 V ; -0.00444 V ; 0.18 V ; 0.019 V ; 7.23e-10 s ; 9.82e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; S0 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S1 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S2 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S3 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; C4 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.72 V ; -0.0747 V ; 0.28 V ; 0.169 V ; 3.1e-10 s ; 3.01e-10 s ; No ; Yes ; 2.62 V ; 2.22e-08 V ; 2.72 V ; -0.0747 V ; 0.28 V ; 0.169 V ; 3.1e-10 s ; 3.01e-10 s ; No ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.53e-08 V ; 2.7 V ; -0.0212 V ; 0.204 V ; 0.049 V ; 4.85e-10 s ; 6.73e-10 s ; No ; Yes ; 2.62 V ; 3.53e-08 V ; 2.7 V ; -0.0212 V ; 0.204 V ; 0.049 V ; 4.85e-10 s ; 6.73e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 8 ; 8 ; +; Unconstrained Input Port Paths ; 34 ; 34 ; +; Unconstrained Output Ports ; 5 ; 5 ; +; Unconstrained Output Port Paths ; 34 ; 34 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit TimeQuest Timing Analyzer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Thu Sep 5 20:29:07 2019 +Info: Command: quartus_sta BCD_adder_1D -c BCD_adder_1D +Info: qsta_default_script.tcl version: #1 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'BCD_adder_1D.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 369 megabytes + Info: Processing ended: Thu Sep 5 20:29:09 2019 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D.sta.summary b/CH5/CH5-3/output_files/BCD_adder_1D.sta.summary new file mode 100644 index 00000000..33f74363 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.asm.rpt b/CH5/CH5-3/output_files/BCD_adder_1D_G.asm.rpt new file mode 100644 index 00000000..d1d489f3 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.asm.rpt @@ -0,0 +1,116 @@ +Assembler report for BCD_adder_1D_G +Mon Sep 9 21:05:54 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: BCD_adder_1D_G.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon Sep 9 21:05:54 2019 ; +; Revision Name ; BCD_adder_1D_G ; +; Top-level Entity Name ; BCD_adder_1D_G ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Use configuration device ; Off ; Off ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Enable OCT_DONE ; Off ; Off ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++---------------------------+ +; Assembler Generated Files ; ++---------------------------+ +; File Name ; ++---------------------------+ +; BCD_adder_1D_G.sof ; ++---------------------------+ + + ++----------------------------------------------+ +; Assembler Device Options: BCD_adder_1D_G.sof ; ++----------------+-----------------------------+ +; Option ; Setting ; ++----------------+-----------------------------+ +; Device ; EP3C16F484C6 ; +; JTAG usercode ; 0x000CBEB6 ; +; Checksum ; 0x000CBEB6 ; ++----------------+-----------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit Assembler + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Mon Sep 9 21:05:51 2019 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 378 megabytes + Info: Processing ended: Mon Sep 9 21:05:54 2019 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.done b/CH5/CH5-3/output_files/BCD_adder_1D_G.done new file mode 100644 index 00000000..5b1f485c --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.done @@ -0,0 +1 @@ +Mon Sep 9 21:06:05 2019 diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.eda.rpt b/CH5/CH5-3/output_files/BCD_adder_1D_G.eda.rpt new file mode 100644 index 00000000..ace2c183 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.eda.rpt @@ -0,0 +1,105 @@ +EDA Netlist Writer report for BCD_adder_1D_G +Mon Sep 9 21:07:09 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Mon Sep 9 21:07:09 2019 ; +; Revision Name ; BCD_adder_1D_G ; +; Top-level Entity Name ; BCD_adder_1D_G ; +; Family ; Cyclone III ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate netlist for functional simulation only ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++-------------------------------------------------------------------------+ +; Simulation Generated Files ; ++-------------------------------------------------------------------------+ +; Generated Files ; ++-------------------------------------------------------------------------+ +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/qsim//BCD_adder_1D_G.vo ; ++-------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit EDA Netlist Writer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. + Info: Your use of Altera Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Altera Program License + Info: Subscription Agreement, Altera MegaCore Function License + Info: Agreement, or other applicable license agreement, including, + Info: without limitation, that your use is for the sole purpose of + Info: programming logic devices manufactured by Altera and sold by + Info: Altera or its authorized distributors. Please refer to the + Info: applicable agreement for further details. + Info: Processing started: Mon Sep 9 21:07:08 2019 +Info: Command: quartus_eda --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/qsim/ BCD_adder_1D_G -c BCD_adder_1D_G +Info (204019): Generated file BCD_adder_1D_G.vo in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/qsim//" for EDA simulation tool +Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 348 megabytes + Info: Processing ended: Mon Sep 9 21:07:09 2019 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.rpt b/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.rpt new file mode 100644 index 00000000..8a098977 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.rpt @@ -0,0 +1,1421 @@ +Fitter report for BCD_adder_1D_G +Mon Sep 9 21:05:47 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. I/O Assignment Warnings + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Non-Global High Fan-Out Signals + 21. Routing Usage Summary + 22. LAB Logic Elements + 23. LAB Signals Sourced + 24. LAB Signals Sourced Out + 25. LAB Distinct Inputs + 26. I/O Rules Summary + 27. I/O Rules Details + 28. I/O Rules Matrix + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+--------------------------------------------+ +; Fitter Status ; Successful - Mon Sep 9 21:05:47 2019 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_1D_G ; +; Top-level Entity Name ; BCD_adder_1D_G ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Total logic elements ; 25 / 15,408 ( < 1 % ) ; +; Total combinational functions ; 25 / 15,408 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 25 / 347 ( 7 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 516,096 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+--------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP3C16F484C6 ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Device I/O Standard ; 2.5 V ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Off ; Off ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; RAM Bit Reservation (Cyclone III) ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-------------------------------------------------+ +; I/O Assignment Warnings ; ++----------+--------------------------------------+ +; Pin Name ; Reason ; ++----------+--------------------------------------+ +; S3 ; Missing drive strength and slew rate ; +; S2 ; Missing drive strength and slew rate ; +; S1 ; Missing drive strength and slew rate ; +; S0 ; Missing drive strength and slew rate ; +; S7 ; Missing drive strength and slew rate ; +; S6 ; Missing drive strength and slew rate ; +; S5 ; Missing drive strength and slew rate ; +; S4 ; Missing drive strength and slew rate ; +; C8 ; Missing drive strength and slew rate ; ++----------+--------------------------------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 86 ) ; 0.00 % ( 0 / 86 ) ; 0.00 % ( 0 / 86 ) ; +; -- Achieved ; 0.00 % ( 0 / 86 ) ; 0.00 % ( 0 / 86 ) ; 0.00 % ( 0 / 86 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 76 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D_G.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 25 / 15,408 ( < 1 % ) ; +; -- Combinational with no register ; 25 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 13 ; +; -- 3 input functions ; 8 ; +; -- <=2 input functions ; 4 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 25 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 17,068 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; +; -- I/O registers ; 0 / 1,660 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 963 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 25 / 347 ( 7 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; Global signals ; 0 ; +; M9Ks ; 0 / 56 ( 0 % ) ; +; Total block memory bits ; 0 / 516,096 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 516,096 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out ; 8 ; +; Highest non-global fan-out ; 8 ; +; Total fan-out ; 123 ; +; Average fan-out ; 1.45 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 25 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % ) ; +; -- Combinational with no register ; 25 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 13 ; 0 ; +; -- 3 input functions ; 8 ; 0 ; +; -- <=2 input functions ; 4 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 25 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 15408 ( 0 % ) ; 0 / 15408 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 963 ( < 1 % ) ; 0 / 963 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 25 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; 0 / 112 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 118 ; 5 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 16 ; 0 ; +; -- Output Ports ; 9 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; A0 ; AA5 ; 3 ; 9 ; 0 ; 28 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; A1 ; R1 ; 2 ; 0 ; 10 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; A2 ; U7 ; 3 ; 3 ; 0 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; A3 ; N1 ; 2 ; 0 ; 12 ; 21 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; A4 ; H5 ; 1 ; 0 ; 27 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; A5 ; G4 ; 1 ; 0 ; 23 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; A6 ; K8 ; 1 ; 0 ; 22 ; 7 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; A7 ; G5 ; 1 ; 0 ; 27 ; 21 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; B0 ; U8 ; 3 ; 3 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; B1 ; P5 ; 2 ; 0 ; 8 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; B2 ; N5 ; 2 ; 0 ; 10 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; B3 ; L7 ; 2 ; 0 ; 11 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; B4 ; E4 ; 1 ; 0 ; 26 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; B5 ; H2 ; 1 ; 0 ; 21 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; B6 ; J3 ; 1 ; 0 ; 21 ; 21 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; +; B7 ; J4 ; 1 ; 0 ; 21 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; C8 ; H1 ; 1 ; 0 ; 21 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S0 ; U2 ; 2 ; 0 ; 9 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S1 ; V2 ; 2 ; 0 ; 9 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S2 ; P4 ; 2 ; 0 ; 10 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S3 ; R2 ; 2 ; 0 ; 10 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S4 ; L8 ; 1 ; 0 ; 22 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S5 ; E6 ; 8 ; 1 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S6 ; C1 ; 1 ; 0 ; 26 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S7 ; K7 ; 1 ; 0 ; 22 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; E4 ; DIFFIO_L2p, nRESET ; Use as regular IO ; B4 ; Dual Purpose Pin ; +; D1 ; DIFFIO_L4n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; E2 ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; K6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; K2 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; K1 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; K5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; L3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; M18 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; M17 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; L18 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; L17 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; K20 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; K22 ; DIFFIO_R16n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 16 / 33 ( 48 % ) ; 2.5V ; -- ; +; 2 ; 9 / 48 ( 19 % ) ; 2.5V ; -- ; +; 3 ; 3 / 46 ( 7 % ) ; 2.5V ; -- ; +; 4 ; 0 / 41 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 46 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 1 / 43 ( 2 % ) ; 2.5V ; -- ; +; 7 ; 0 / 47 ( 0 % ) ; 2.5V ; -- ; +; 8 ; 1 / 43 ( 2 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A3 ; 354 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 350 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 345 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 336 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 334 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 332 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 328 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 326 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 321 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A12 ; 319 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 314 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 312 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 307 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 298 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 296 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 291 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 290 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 284 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA3 ; 102 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA4 ; 106 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA5 ; 108 ; 3 ; A0 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AA6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA7 ; 115 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 123 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 134 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA12 ; 136 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA13 ; 138 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; 140 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 145 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 149 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 151 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; 163 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; 164 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 169 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 179 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 178 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB3 ; 103 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 107 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 109 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB7 ; 116 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 135 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AB12 ; 137 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AB13 ; 139 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 141 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 146 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 150 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 152 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 162 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 165 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 170 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B3 ; 355 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 351 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 346 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 337 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 335 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 333 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; 329 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B10 ; 327 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 322 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B12 ; 320 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 315 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; 313 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 308 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; 299 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 297 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; 292 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B19 ; 289 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 285 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 269 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 268 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 7 ; 1 ; S6 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; C2 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C3 ; 358 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 359 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 349 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 340 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 339 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C10 ; 330 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; 309 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C15 ; 300 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 286 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C19 ; 282 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 270 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 267 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 266 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 9 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; D2 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D6 ; 356 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D10 ; 324 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D13 ; 310 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D15 ; 293 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D17 ; 281 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D19 ; 283 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D20 ; 271 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D21 ; 261 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D22 ; 260 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; 13 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; E3 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 4 ; 1 ; B4 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E5 ; 363 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E6 ; 362 ; 8 ; S5 ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E7 ; 357 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E9 ; 338 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; E10 ; 325 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 317 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 316 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 311 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 301 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 294 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 275 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E18 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E21 ; 256 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 255 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 16 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F7 ; 360 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 352 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 347 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 348 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 318 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; 302 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F13 ; 306 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F14 ; 279 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F15 ; 276 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 274 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 272 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F19 ; 263 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 262 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 251 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 250 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 39 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G2 ; 38 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G3 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 17 ; 1 ; A5 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G5 ; 3 ; 1 ; A7 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G6 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G7 ; 361 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; 353 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G9 ; 342 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G10 ; 341 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 331 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 305 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; 295 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G14 ; 280 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G15 ; 278 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 277 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 273 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; 264 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G21 ; 226 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G22 ; 225 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; H1 ; 26 ; 1 ; C8 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H2 ; 25 ; 1 ; B5 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H5 ; 0 ; 1 ; A4 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H7 ; 10 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; 344 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H10 ; 343 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H11 ; 323 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 304 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 303 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 288 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 287 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; 259 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H17 ; 265 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 257 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; H19 ; 254 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 253 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 246 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 245 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J3 ; 27 ; 1 ; B6 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J4 ; 24 ; 1 ; B7 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J6 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J7 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J15 ; 238 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; 243 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J17 ; 258 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J18 ; 249 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J21 ; 242 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 241 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 31 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; K2 ; 30 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K5 ; 32 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; K6 ; 19 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 23 ; 1 ; S7 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K8 ; 21 ; 1 ; A6 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; 236 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; 244 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K17 ; 247 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K18 ; 248 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 237 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; K20 ; 231 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; K21 ; 240 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 239 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L1 ; 35 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; L2 ; 34 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; L3 ; 37 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L5 ; 33 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; L6 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L7 ; 50 ; 2 ; B3 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L8 ; 20 ; 1 ; S4 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; 233 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; 232 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L17 ; 230 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 229 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; L19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L21 ; 235 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L22 ; 234 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 45 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M3 ; 47 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 46 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 51 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M6 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M7 ; 65 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M8 ; 66 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; 195 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; 222 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M17 ; 228 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 227 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; M19 ; 221 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M20 ; 220 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 219 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 218 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 49 ; 2 ; A3 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N2 ; 48 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N5 ; 56 ; 2 ; B2 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N6 ; 64 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N7 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N8 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 189 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 196 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; 205 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N17 ; 214 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N18 ; 215 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 213 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 212 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 217 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 216 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 53 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 52 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; S2 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; P5 ; 63 ; 2 ; B1 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; P6 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P7 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P8 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; 180 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 192 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 193 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P17 ; 197 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P18 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P20 ; 208 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; P21 ; 211 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 210 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; 55 ; 2 ; A1 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; R2 ; 54 ; 2 ; S3 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R5 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R7 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R9 ; 88 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 90 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 97 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 98 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 153 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R16 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R17 ; 194 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R18 ; 203 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; 204 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R20 ; 200 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; 207 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R22 ; 206 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 41 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T2 ; 40 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T3 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; T4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T7 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T8 ; 89 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 91 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T10 ; 121 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T11 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 148 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T14 ; 160 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T15 ; 161 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T16 ; 171 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T17 ; 181 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T18 ; 182 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 224 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T22 ; 223 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; U1 ; 60 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 59 ; 2 ; S0 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; 94 ; 3 ; A2 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; U8 ; 95 ; 3 ; B0 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; U9 ; 112 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U10 ; 122 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U11 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U12 ; 147 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U13 ; 156 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U14 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U15 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U19 ; 188 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 187 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 202 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 201 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 62 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; 61 ; 2 ; S1 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; V3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V5 ; 93 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; 92 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V7 ; 105 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 113 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 119 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; V10 ; 120 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 142 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 154 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 157 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 158 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 168 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; V17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V18 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V21 ; 199 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 198 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W6 ; 104 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 110 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 114 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W10 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W13 ; 143 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 155 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; W15 ; 159 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W17 ; 166 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W19 ; 184 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 183 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 191 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; 190 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y2 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y3 ; 99 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 96 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; 101 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 111 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 117 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 144 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y17 ; 167 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 186 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 185 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++--------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++--------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------------------+--------------+ +; |BCD_adder_1D_G ; 25 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 25 ; 0 ; 25 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G ; work ; +; |BCD_adder_1D:inst4| ; 15 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 (2) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4 ; work ; +; |four_bir_adder:inst2| ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2 ; work ; +; |Full_adder_S:inst2| ; 2 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst2 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1 ; work ; +; |Full_adder_S:inst3| ; 2 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst3 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst1 ; work ; +; |Full_adder_S:inst| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1 ; work ; +; |four_bir_adder:inst| ; 8 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst ; work ; +; |Full_adder_S:inst2| ; 2 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2 ; work ; +; |Half_adder:inst| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst ; work ; +; |Full_adder_S:inst3| ; 2 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1 ; work ; +; |Full_adder_S:inst4| ; 3 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (2) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst1 ; work ; +; |Full_adder_S:inst| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst1 ; work ; +; |BCD_adder_1D:inst| ; 10 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (2) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst ; work ; +; |four_bir_adder:inst2| ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2 ; work ; +; |Full_adder_S:inst2| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst2 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1 ; work ; +; |Full_adder_S:inst3| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst3 ; work ; +; |Half_adder:inst| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst ; work ; +; |Full_adder_S:inst| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1 ; work ; +; |four_bir_adder:inst| ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst ; work ; +; |Full_adder_S:inst2| ; 2 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1 ; work ; +; |Full_adder_S:inst3| ; 2 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1 ; work ; +; |Full_adder_S:inst4| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst4 ; work ; +; |Half_adder:inst| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst ; work ; ++--------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; S3 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S2 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S7 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S6 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S5 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S4 ; Output ; -- ; -- ; -- ; -- ; -- ; +; C8 ; Output ; -- ; -- ; -- ; -- ; -- ; +; B3 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; A3 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; A2 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; B2 ; Input ; (6) 1314 ps ; (6) 1314 ps ; -- ; -- ; -- ; +; B0 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; A0 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; A1 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; B1 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; B7 ; Input ; (6) 1314 ps ; (6) 1314 ps ; -- ; -- ; -- ; +; A4 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; B4 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; A5 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; B5 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; A6 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; B6 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; A7 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+------+ + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------------------------------------------------------------+-------------------+---------+ +; B3 ; ; ; +; - BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1|inst~0 ; 1 ; 6 ; +; - BCD_adder_1D:inst|inst6~1 ; 1 ; 6 ; +; A3 ; ; ; +; - BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst|inst6~1 ; 0 ; 6 ; +; A2 ; ; ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2|inst2~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst|inst6~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; B2 ; ; ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2|inst2~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst|inst6~0 ; 1 ; 6 ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; B0 ; ; ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst|inst ; 0 ; 6 ; +; A0 ; ; ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 1 ; 6 ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst~0 ; 1 ; 6 ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst|inst ; 1 ; 6 ; +; A1 ; ; ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; B1 ; ; ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; B7 ; ; ; +; - BCD_adder_1D:inst4|inst6~1 ; 1 ; 6 ; +; - BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1|inst ; 0 ; 6 ; +; A4 ; ; ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|inst2~0 ; 1 ; 6 ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|inst2~1 ; 1 ; 6 ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst1|inst ; 1 ; 6 ; +; B4 ; ; ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|inst2~1 ; 1 ; 6 ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst1|inst ; 1 ; 6 ; +; A5 ; ; ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst ; 0 ; 6 ; +; B5 ; ; ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 1 ; 6 ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst ; 1 ; 6 ; +; A6 ; ; ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst|inst ; 0 ; 6 ; +; - BCD_adder_1D:inst4|inst6~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2|inst2~0 ; 0 ; 6 ; +; B6 ; ; ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst1|inst~0 ; 1 ; 6 ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst|inst ; 1 ; 6 ; +; - BCD_adder_1D:inst4|inst6~0 ; 1 ; 6 ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2|inst2~0 ; 1 ; 6 ; +; A7 ; ; ; +; - BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst1|inst~0 ; 0 ; 6 ; +; - BCD_adder_1D:inst4|inst6~1 ; 0 ; 6 ; ++-----------------------------------------------------------------------------------------+-------------------+---------+ + + ++---------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++-----------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++-----------------------------------------------------------------------------------+---------+ +; BCD_adder_1D:inst|inst6~1 ; 8 ; +; BCD_adder_1D:inst4|inst6~1 ; 5 ; +; BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 5 ; +; B6~input ; 4 ; +; A6~input ; 4 ; +; A4~input ; 3 ; +; A0~input ; 3 ; +; B0~input ; 3 ; +; B2~input ; 3 ; +; A2~input ; 3 ; +; BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst ; 3 ; +; BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1|inst~0 ; 3 ; +; BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|inst2~0 ; 3 ; +; A7~input ; 2 ; +; B5~input ; 2 ; +; A5~input ; 2 ; +; B4~input ; 2 ; +; B7~input ; 2 ; +; B1~input ; 2 ; +; A1~input ; 2 ; +; A3~input ; 2 ; +; B3~input ; 2 ; +; BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst3|inst2~0 ; 2 ; +; BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst|inst ; 2 ; +; BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|inst2~1 ; 2 ; +; BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|inst2~0 ; 2 ; +; BCD_adder_1D:inst|inst6~0 ; 2 ; +; BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2|inst2~0 ; 2 ; +; BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst1|inst ; 1 ; +; BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst1|inst ; 1 ; +; BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1|inst ; 1 ; +; BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1|inst ; 1 ; +; BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst2|inst2~0 ; 1 ; +; BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2|inst2~0 ; 1 ; +; BCD_adder_1D:inst4|inst6~0 ; 1 ; +; BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst1|inst~0 ; 1 ; +; BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst|inst ; 1 ; +; BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst|inst ; 1 ; +; BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1|inst~0 ; 1 ; +; BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1|inst~0 ; 1 ; +; BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1|inst~0 ; 1 ; ++-----------------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+-----------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+-----------------------+ +; Block interconnects ; 29 / 47,787 ( < 1 % ) ; +; C16 interconnects ; 4 / 1,804 ( < 1 % ) ; +; C4 interconnects ; 22 / 31,272 ( < 1 % ) ; +; Direct links ; 4 / 47,787 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 16 / 15,408 ( < 1 % ) ; +; R24 interconnects ; 1 / 1,775 ( < 1 % ) ; +; R4 interconnects ; 4 / 41,310 ( < 1 % ) ; ++-----------------------+-----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 12.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; +; 16 ; 0 ; ++---------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 12.50) ; Number of LABs (Total = 2) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 2 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 8.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; +; 9 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 25 ; 0 ; 0 ; 25 ; 25 ; 0 ; 9 ; 0 ; 0 ; 16 ; 0 ; 9 ; 16 ; 0 ; 0 ; 0 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 25 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 25 ; 25 ; 25 ; 25 ; 25 ; 0 ; 25 ; 25 ; 0 ; 0 ; 25 ; 16 ; 25 ; 25 ; 9 ; 25 ; 16 ; 9 ; 25 ; 25 ; 25 ; 16 ; 25 ; 25 ; 25 ; 25 ; 25 ; 0 ; 25 ; 25 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; S3 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S2 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S7 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S6 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S5 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S4 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; C8 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B3 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A3 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A2 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B2 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B7 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A4 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B4 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A5 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B5 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A6 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B6 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A7 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device EP3C16F484C6 for design "BCD_adder_1D_G" +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP3C40F484C6 is compatible + Info (176445): Device EP3C55F484C6 is compatible + Info (176445): Device EP3C80F484C6 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 25 pins of 25 total pins + Info (169086): Pin S3 not assigned to an exact location on the device + Info (169086): Pin S2 not assigned to an exact location on the device + Info (169086): Pin S1 not assigned to an exact location on the device + Info (169086): Pin S0 not assigned to an exact location on the device + Info (169086): Pin S7 not assigned to an exact location on the device + Info (169086): Pin S6 not assigned to an exact location on the device + Info (169086): Pin S5 not assigned to an exact location on the device + Info (169086): Pin S4 not assigned to an exact location on the device + Info (169086): Pin C8 not assigned to an exact location on the device + Info (169086): Pin B3 not assigned to an exact location on the device + Info (169086): Pin A3 not assigned to an exact location on the device + Info (169086): Pin A2 not assigned to an exact location on the device + Info (169086): Pin B2 not assigned to an exact location on the device + Info (169086): Pin B0 not assigned to an exact location on the device + Info (169086): Pin A0 not assigned to an exact location on the device + Info (169086): Pin A1 not assigned to an exact location on the device + Info (169086): Pin B1 not assigned to an exact location on the device + Info (169086): Pin B7 not assigned to an exact location on the device + Info (169086): Pin A4 not assigned to an exact location on the device + Info (169086): Pin B4 not assigned to an exact location on the device + Info (169086): Pin A5 not assigned to an exact location on the device + Info (169086): Pin B5 not assigned to an exact location on the device + Info (169086): Pin A6 not assigned to an exact location on the device + Info (169086): Pin B6 not assigned to an exact location on the device + Info (169086): Pin A7 not assigned to an exact location on the device +Critical Warning (332012): Synopsys Design Constraints File file not found: 'BCD_adder_1D_G.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 25 (unused VREF, 2.5V VCCIO, 16 input, 9 output, 0 bidirectional) + Info (176212): I/O standards used: 2.5 V. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 29 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 42 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 47 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.18 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 +Info (144001): Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.smsg +Info: Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 533 megabytes + Info: Processing ended: Mon Sep 9 21:05:48 2019 + Info: Elapsed time: 00:00:12 + Info: Total CPU time (on all processors): 00:00:12 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.smsg. + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.smsg b/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.smsg new file mode 100644 index 00000000..7121cbb1 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.summary b/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.summary new file mode 100644 index 00000000..b018a3d3 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon Sep 9 21:05:47 2019 +Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition +Revision Name : BCD_adder_1D_G +Top-level Entity Name : BCD_adder_1D_G +Family : Cyclone III +Device : EP3C16F484C6 +Timing Models : Final +Total logic elements : 25 / 15,408 ( < 1 % ) + Total combinational functions : 25 / 15,408 ( < 1 % ) + Dedicated logic registers : 0 / 15,408 ( 0 % ) +Total registers : 0 +Total pins : 25 / 347 ( 7 % ) +Total virtual pins : 0 +Total memory bits : 0 / 516,096 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.flow.rpt b/CH5/CH5-3/output_files/BCD_adder_1D_G.flow.rpt new file mode 100644 index 00000000..ea8ac216 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.flow.rpt @@ -0,0 +1,136 @@ +Flow report for BCD_adder_1D_G +Mon Sep 9 21:07:09 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+--------------------------------------------+ +; Flow Status ; Successful - Mon Sep 9 21:07:09 2019 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_1D_G ; +; Top-level Entity Name ; BCD_adder_1D_G ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Total logic elements ; 25 / 15,408 ( < 1 % ) ; +; Total combinational functions ; 25 / 15,408 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 25 / 347 ( 7 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 516,096 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+--------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 09/09/2019 21:05:31 ; +; Main task ; Compilation ; +; Revision Name ; BCD_adder_1D_G ; ++-------------------+---------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+---------------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+---------------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 0.156803433105129 ; -- ; -- ; -- ; +; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+---------------------------------------+---------------+-------------+----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 372 MB ; 00:00:03 ; +; Fitter ; 00:00:11 ; 1.0 ; 533 MB ; 00:00:12 ; +; Assembler ; 00:00:03 ; 1.0 ; 378 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 383 MB ; 00:00:03 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 332 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 348 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 348 MB ; 00:00:01 ; +; Total ; 00:00:22 ; -- ; -- ; 00:00:23 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+-------------------+----------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+-------------------+----------------+------------+----------------+ +; Analysis & Synthesis ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; Fitter ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; Assembler ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; TimeQuest Timing Analyzer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; EDA Netlist Writer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; EDA Netlist Writer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; EDA Netlist Writer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; ++---------------------------+-------------------+----------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G +quartus_fit --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G +quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G +quartus_sta BCD_adder_1D_G -c BCD_adder_1D_G +quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G +quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog BCD_adder_1D_G -c BCD_adder_1D_G --vector_source=/home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.vwf --testbench_file=/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.vwf.vt +quartus_eda --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/qsim/ BCD_adder_1D_G -c BCD_adder_1D_G + + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.jdi b/CH5/CH5-3/output_files/BCD_adder_1D_G.jdi new file mode 100644 index 00000000..15f1fc80 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.map.rpt b/CH5/CH5-3/output_files/BCD_adder_1D_G.map.rpt new file mode 100644 index 00000000..31fba9b8 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.map.rpt @@ -0,0 +1,309 @@ +Analysis & Synthesis report for BCD_adder_1D_G +Mon Sep 9 21:05:34 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Elapsed Time Per Partition + 10. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+--------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Sep 9 21:05:34 2019 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_1D_G ; +; Top-level Entity Name ; BCD_adder_1D_G ; +; Family ; Cyclone III ; +; Total logic elements ; 25 ; +; Total combinational functions ; 25 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 25 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+--------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP3C16F484C6 ; ; +; Top-level entity name ; BCD_adder_1D_G ; BCD_adder_1D_G ; +; Family name ; Cyclone III ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+ +; ../CH5-1/Full_adder_S.bdf ; yes ; User Block Diagram/Schematic File ; /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf ; ; +; ../CH5-1/Half_adder.bdf ; yes ; User Block Diagram/Schematic File ; /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf ; ; +; ../CH5-1/four_bir_adder.bdf ; yes ; User Block Diagram/Schematic File ; /home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf ; ; +; BCD_adder_1D.bdf ; yes ; User Block Diagram/Schematic File ; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf ; ; +; BCD_adder_1D_G.bdf ; yes ; User Block Diagram/Schematic File ; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf ; ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+ + + ++-------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+---------------------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------------------+ +; Estimated Total logic elements ; 25 ; +; ; ; +; Total combinational functions ; 25 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 13 ; +; -- 3 input functions ; 8 ; +; -- <=2 input functions ; 4 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 25 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 25 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; BCD_adder_1D:inst|inst6~1 ; +; Maximum fan-out ; 8 ; +; Total fan-out ; 118 ; +; Average fan-out ; 1.57 ; ++---------------------------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------+--------------+ +; |BCD_adder_1D_G ; 25 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 25 ; 0 ; |BCD_adder_1D_G ; work ; +; |BCD_adder_1D:inst4| ; 15 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4 ; work ; +; |four_bir_adder:inst2| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2 ; work ; +; |Full_adder_S:inst2| ; 2 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst2 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1 ; work ; +; |Full_adder_S:inst3| ; 2 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst3 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst1 ; work ; +; |Full_adder_S:inst| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1 ; work ; +; |four_bir_adder:inst| ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst ; work ; +; |Full_adder_S:inst2| ; 2 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2 ; work ; +; |Half_adder:inst| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst ; work ; +; |Full_adder_S:inst3| ; 2 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1 ; work ; +; |Full_adder_S:inst4| ; 3 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst1 ; work ; +; |Full_adder_S:inst| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst4|four_bir_adder:inst|Full_adder_S:inst|Half_adder:inst1 ; work ; +; |BCD_adder_1D:inst| ; 10 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst ; work ; +; |four_bir_adder:inst2| ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2 ; work ; +; |Full_adder_S:inst2| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst2 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1 ; work ; +; |Full_adder_S:inst3| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst3 ; work ; +; |Half_adder:inst| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst3|Half_adder:inst ; work ; +; |Full_adder_S:inst| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst|Half_adder:inst1 ; work ; +; |four_bir_adder:inst| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst ; work ; +; |Full_adder_S:inst2| ; 2 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst2|Half_adder:inst1 ; work ; +; |Full_adder_S:inst3| ; 2 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3 ; work ; +; |Half_adder:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst3|Half_adder:inst1 ; work ; +; |Full_adder_S:inst4| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst4 ; work ; +; |Half_adder:inst| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_1D_G|BCD_adder_1D:inst|four_bir_adder:inst|Full_adder_S:inst4|Half_adder:inst ; work ; ++--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit Analysis & Synthesis + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Mon Sep 9 21:05:31 2019 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_1D_G -c BCD_adder_1D_G +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf + Info (12023): Found entity 1: eight_bit_adder +Info (12021): Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf + Info (12023): Found entity 1: Full_adder_S +Info (12021): Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf + Info (12023): Found entity 1: Half_adder +Info (12021): Found 1 design units, including 1 entities, in source file /home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf + Info (12023): Found entity 1: four_bir_adder +Info (12021): Found 1 design units, including 1 entities, in source file BCD_adder_7483.bdf + Info (12023): Found entity 1: BCD_adder_7483 +Info (12021): Found 1 design units, including 1 entities, in source file BCD_adder_1D.bdf + Info (12023): Found entity 1: BCD_adder_1D +Info (12021): Found 1 design units, including 1 entities, in source file BCD_adder_1D_G.bdf + Info (12023): Found entity 1: BCD_adder_1D_G +Info (12127): Elaborating entity "BCD_adder_1D_G" for the top level hierarchy +Info (12128): Elaborating entity "BCD_adder_1D" for hierarchy "BCD_adder_1D:inst" +Info (12128): Elaborating entity "four_bir_adder" for hierarchy "BCD_adder_1D:inst|four_bir_adder:inst2" +Info (12128): Elaborating entity "Full_adder_S" for hierarchy "BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst2" +Info (12128): Elaborating entity "Half_adder" for hierarchy "BCD_adder_1D:inst|four_bir_adder:inst2|Full_adder_S:inst2|Half_adder:inst1" +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 50 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 16 input pins + Info (21059): Implemented 9 output pins + Info (21061): Implemented 25 logic cells +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 383 megabytes + Info: Processing ended: Mon Sep 9 21:05:34 2019 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.map.summary b/CH5/CH5-3/output_files/BCD_adder_1D_G.map.summary new file mode 100644 index 00000000..b687c40d --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon Sep 9 21:05:34 2019 +Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition +Revision Name : BCD_adder_1D_G +Top-level Entity Name : BCD_adder_1D_G +Family : Cyclone III +Total logic elements : 25 + Total combinational functions : 25 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 25 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.pin b/CH5/CH5-3/output_files/BCD_adder_1D_G.pin new file mode 100644 index 00000000..351ec9c9 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.pin @@ -0,0 +1,554 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +CHIP "BCD_adder_1D_G" ASSIGNED TO AN: EP3C16F484C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO8 : A2 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 : +GND+ : A11 : : : : 8 : +GND+ : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +VCCIO7 : A21 : power : : 2.5V : 7 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 3 : +A0 : AA5 : input : 2.5 V : : 3 : N +VCCIO3 : AA6 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +GND+ : AA11 : : : : 3 : +GND+ : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +VCCIO3 : AB2 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +GND : AB6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 : +GND+ : AB11 : : : : 3 : +GND+ : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +VCCIO4 : AB21 : power : : 2.5V : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 : +GND+ : B11 : : : : 8 : +GND+ : B12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +S6 : C1 : output : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +GND : C5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +GND : C9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 : +GND : C11 : gnd : : : : +GND : C12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +GND : C14 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +GND : C16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +GND : C18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 : +GND : D3 : gnd : : : : +VCCIO1 : D4 : power : : 2.5V : 1 : +VCCIO8 : D5 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +GND : D7 : gnd : : : : +GND : D8 : gnd : : : : +VCCIO8 : D9 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +VCCIO8 : D11 : power : : 2.5V : 8 : +VCCIO7 : D12 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +VCCIO7 : D14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +VCCIO7 : D16 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +VCCIO7 : D18 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 : +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 : +B4 : E4 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 : +S5 : E6 : output : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : +VCCIO8 : E8 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 : +VCCD_PLL2 : E17 : power : : 1.2V : : +GNDA2 : E18 : gnd : : : : +VCCIO6 : E19 : power : : 2.5V : 6 : +GND : E20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 : +GND : F3 : gnd : : : : +VCCIO1 : F4 : power : : 2.5V : 1 : +GNDA3 : F5 : gnd : : : : +VCCD_PLL3 : F6 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +VCCA2 : F18 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +GND+ : G1 : : : : 1 : +GND+ : G2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 : +A5 : G4 : input : 2.5 V : : 1 : N +A7 : G5 : input : 2.5 V : : 1 : N +VCCA3 : G6 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 6 : +VCCIO6 : G19 : power : : 2.5V : 6 : +GND : G20 : gnd : : : : +GND+ : G21 : : : : 6 : +GND+ : G22 : : : : 6 : +C8 : H1 : output : 2.5 V : : 1 : N +B5 : H2 : input : 2.5 V : : 1 : N +GND : H3 : gnd : : : : +VCCIO1 : H4 : power : : 2.5V : 1 : +A4 : H5 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 : +GND : H8 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 1 : +B6 : J3 : input : 2.5 V : : 1 : N +B7 : J4 : input : 2.5 V : : 1 : N +GND : J5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 : +VCCINT : J8 : power : : 1.2V : : +GND : J9 : gnd : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +VCCINT : J14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +VCCIO6 : J20 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : input : 2.5 V : : 1 : N +~ALTERA_DCLK~ : K2 : output : 2.5 V : : 1 : N +GND : K3 : gnd : : : : +VCCIO1 : K4 : power : : 2.5V : 1 : +nCONFIG : K5 : : : : 1 : +nSTATUS : K6 : : : : 1 : +S7 : K7 : output : 2.5 V : : 1 : N +A6 : K8 : input : 2.5 V : : 1 : N +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +MSEL3 : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22 : output : 2.5 V : : 6 : N +TMS : L1 : input : : : 1 : +TCK : L2 : input : : : 1 : +nCE : L3 : : : : 1 : +TDO : L4 : output : : : 1 : +TDI : L5 : input : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 2 : +B3 : L7 : input : 2.5 V : : 2 : N +S4 : L8 : output : 2.5 V : : 1 : N +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 6 : +MSEL2 : L17 : : : : 6 : +MSEL1 : L18 : : : : 6 : +VCCIO6 : L19 : power : : 2.5V : 6 : +GND : L20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M16 : : : : 5 : +MSEL0 : M17 : : : : 6 : +CONF_DONE : M18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +A3 : N1 : input : 2.5 V : : 2 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +GND : N3 : gnd : : : : +VCCIO2 : N4 : power : : 2.5V : 2 : +B2 : N5 : input : 2.5 V : : 2 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +S2 : P4 : output : 2.5 V : : 2 : N +B1 : P5 : input : 2.5 V : : 2 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +VCCINT : P9 : power : : 1.2V : : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P17 : : : : 5 : +VCCIO5 : P18 : power : : 2.5V : 5 : +GND : P19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +A1 : R1 : input : 2.5 V : : 2 : N +S3 : R2 : output : 2.5 V : : 2 : N +GND : R3 : gnd : : : : +VCCIO2 : R4 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +GND+ : T1 : : : : 2 : +GND+ : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +VCCA1 : T6 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 4 : +VCCINT : T13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +VCCIO5 : T19 : power : : 2.5V : 5 : +GND : T20 : gnd : : : : +GND+ : T21 : : : : 5 : +GND+ : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +S0 : U2 : output : 2.5 V : : 2 : N +GND : U3 : gnd : : : : +VCCIO2 : U4 : power : : 2.5V : 2 : +GNDA1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +A2 : U7 : input : 2.5 V : : 3 : N +B0 : U8 : input : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCINT : U16 : power : : 1.2V : : +VCCINT : U17 : power : : 1.2V : : +VCCA4 : U18 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +S1 : V2 : output : 2.5 V : : 2 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +VCCD_PLL4 : V17 : power : : 1.2V : : +GNDA4 : V18 : gnd : : : : +VCCIO5 : V19 : power : : 2.5V : 5 : +GND : V20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +GND : W3 : gnd : : : : +VCCIO2 : W4 : power : : 2.5V : 2 : +VCCIO3 : W5 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +VCCIO3 : W9 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +VCCIO3 : W11 : power : : 2.5V : 3 : +VCCIO4 : W12 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +VCCIO4 : W16 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +VCCIO4 : W18 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +GND : Y5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +GND : Y11 : gnd : : : : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +VCCIO4 : Y14 : power : : 2.5V : 4 : +GND : Y15 : gnd : : : : +GND : Y16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +GND : Y18 : gnd : : : : +VCCIO5 : Y19 : power : : 2.5V : 5 : +GND : Y20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.sof b/CH5/CH5-3/output_files/BCD_adder_1D_G.sof new file mode 100644 index 00000000..8e319f05 Binary files /dev/null and b/CH5/CH5-3/output_files/BCD_adder_1D_G.sof differ diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.sta.rpt b/CH5/CH5-3/output_files/BCD_adder_1D_G.sta.rpt new file mode 100644 index 00000000..f5b56124 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.sta.rpt @@ -0,0 +1,1279 @@ +TimeQuest Timing Analyzer report for BCD_adder_1D_G +Mon Sep 9 21:06:00 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Propagation Delay + 13. Minimum Propagation Delay + 14. Slow 1200mV 85C Model Metastability Report + 15. Slow 1200mV 0C Model Fmax Summary + 16. Slow 1200mV 0C Model Setup Summary + 17. Slow 1200mV 0C Model Hold Summary + 18. Slow 1200mV 0C Model Recovery Summary + 19. Slow 1200mV 0C Model Removal Summary + 20. Slow 1200mV 0C Model Minimum Pulse Width Summary + 21. Propagation Delay + 22. Minimum Propagation Delay + 23. Slow 1200mV 0C Model Metastability Report + 24. Fast 1200mV 0C Model Setup Summary + 25. Fast 1200mV 0C Model Hold Summary + 26. Fast 1200mV 0C Model Recovery Summary + 27. Fast 1200mV 0C Model Removal Summary + 28. Fast 1200mV 0C Model Minimum Pulse Width Summary + 29. Propagation Delay + 30. Minimum Propagation Delay + 31. Fast 1200mV 0C Model Metastability Report + 32. Multicorner Timing Analysis Summary + 33. Propagation Delay + 34. Minimum Propagation Delay + 35. Board Trace Model Assignments + 36. Input Transition Times + 37. Slow Corner Signal Integrity Metrics + 38. Fast Corner Signal Integrity Metrics + 39. Clock Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths + 43. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+----------------------------------------------------+ +; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_1D_G ; +; Device Family ; Cyclone III ; +; Device Name ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+----------------------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + ++--------------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+--------+--------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+--------+--------+--------+ +; A0 ; C8 ; 10.441 ; 10.405 ; 11.054 ; 11.018 ; +; A0 ; S0 ; 7.027 ; 7.017 ; 7.453 ; 7.475 ; +; A0 ; S1 ; 8.453 ; 8.437 ; 9.020 ; 9.036 ; +; A0 ; S2 ; 8.134 ; 8.114 ; 8.700 ; 8.712 ; +; A0 ; S3 ; 7.702 ; 7.684 ; 8.233 ; 8.247 ; +; A0 ; S4 ; 9.130 ; 9.117 ; 9.719 ; 9.697 ; +; A0 ; S5 ; 11.086 ; 11.015 ; 11.699 ; 11.628 ; +; A0 ; S6 ; 11.658 ; 11.688 ; 12.271 ; 12.301 ; +; A0 ; S7 ; 11.891 ; 11.896 ; 12.504 ; 12.509 ; +; A1 ; C8 ; 9.958 ; 9.922 ; 10.508 ; 10.472 ; +; A1 ; S1 ; 7.924 ; 7.940 ; 8.474 ; 8.490 ; +; A1 ; S2 ; 7.604 ; 7.616 ; 8.154 ; 8.166 ; +; A1 ; S3 ; 7.174 ; 7.149 ; 7.687 ; 7.701 ; +; A1 ; S4 ; 8.623 ; 8.601 ; 9.173 ; 9.151 ; +; A1 ; S5 ; 10.603 ; 10.532 ; 11.153 ; 11.082 ; +; A1 ; S6 ; 11.175 ; 11.205 ; 11.725 ; 11.755 ; +; A1 ; S7 ; 11.408 ; 11.413 ; 11.958 ; 11.963 ; +; A2 ; C8 ; 9.640 ; 9.604 ; 10.223 ; 10.187 ; +; A2 ; S1 ; 7.703 ; 7.687 ; 8.189 ; 8.205 ; +; A2 ; S2 ; 7.384 ; 7.364 ; 7.869 ; 7.881 ; +; A2 ; S3 ; 6.952 ; 6.934 ; 7.402 ; 7.416 ; +; A2 ; S4 ; 8.380 ; 8.367 ; 8.888 ; 8.866 ; +; A2 ; S5 ; 10.285 ; 10.214 ; 10.868 ; 10.797 ; +; A2 ; S6 ; 10.857 ; 10.887 ; 11.440 ; 11.470 ; +; A2 ; S7 ; 11.090 ; 11.095 ; 11.673 ; 11.678 ; +; A3 ; C8 ; 9.088 ; 9.109 ; 9.700 ; 9.664 ; +; A3 ; S1 ; 7.212 ; 7.196 ; 7.666 ; 7.682 ; +; A3 ; S2 ; 6.893 ; 6.873 ; 7.346 ; 7.358 ; +; A3 ; S3 ; 6.471 ; 6.487 ; 6.899 ; 6.871 ; +; A3 ; S4 ; 7.889 ; 7.876 ; 8.365 ; 8.343 ; +; A3 ; S5 ; 9.790 ; 9.717 ; 10.345 ; 10.274 ; +; A3 ; S6 ; 10.362 ; 10.392 ; 10.917 ; 10.947 ; +; A3 ; S7 ; 10.595 ; 10.600 ; 11.150 ; 11.155 ; +; A4 ; C8 ; 8.179 ; 8.200 ; 8.800 ; 8.764 ; +; A4 ; S4 ; 6.991 ; 7.002 ; 7.452 ; 7.460 ; +; A4 ; S5 ; 8.881 ; 8.808 ; 9.445 ; 9.374 ; +; A4 ; S6 ; 9.453 ; 9.483 ; 10.017 ; 10.047 ; +; A4 ; S7 ; 9.686 ; 9.691 ; 10.250 ; 10.255 ; +; A5 ; C8 ; 7.155 ; 7.176 ; 7.657 ; 7.621 ; +; A5 ; S5 ; 7.857 ; 7.784 ; 8.302 ; 8.231 ; +; A5 ; S6 ; 8.429 ; 8.459 ; 8.874 ; 8.904 ; +; A5 ; S7 ; 8.662 ; 8.667 ; 9.107 ; 9.112 ; +; A6 ; C8 ; 6.719 ; 6.591 ; 6.999 ; 7.152 ; +; A6 ; S5 ; 7.357 ; 7.293 ; 7.833 ; 7.760 ; +; A6 ; S6 ; 7.930 ; 7.928 ; 8.405 ; 8.435 ; +; A6 ; S7 ; 8.131 ; 8.104 ; 8.638 ; 8.643 ; +; A7 ; C8 ; 6.742 ; ; ; 7.216 ; +; A7 ; S5 ; 7.380 ; 7.316 ; 7.897 ; 7.824 ; +; A7 ; S6 ; 7.953 ; 7.951 ; 8.469 ; 8.499 ; +; A7 ; S7 ; 8.154 ; 8.127 ; 8.702 ; 8.707 ; +; B0 ; C8 ; 10.597 ; 10.561 ; 11.180 ; 11.144 ; +; B0 ; S0 ; 7.156 ; 7.176 ; 7.628 ; 7.634 ; +; B0 ; S1 ; 8.563 ; 8.579 ; 9.146 ; 9.162 ; +; B0 ; S2 ; 8.243 ; 8.255 ; 8.826 ; 8.838 ; +; B0 ; S3 ; 7.813 ; 7.788 ; 8.359 ; 8.373 ; +; B0 ; S4 ; 9.262 ; 9.240 ; 9.845 ; 9.823 ; +; B0 ; S5 ; 11.242 ; 11.171 ; 11.825 ; 11.754 ; +; B0 ; S6 ; 11.814 ; 11.844 ; 12.397 ; 12.427 ; +; B0 ; S7 ; 12.047 ; 12.052 ; 12.630 ; 12.635 ; +; B1 ; C8 ; 9.937 ; 9.901 ; 10.495 ; 10.459 ; +; B1 ; S1 ; 7.946 ; 7.930 ; 8.461 ; 8.477 ; +; B1 ; S2 ; 7.627 ; 7.607 ; 8.141 ; 8.153 ; +; B1 ; S3 ; 7.195 ; 7.177 ; 7.674 ; 7.688 ; +; B1 ; S4 ; 8.623 ; 8.610 ; 9.160 ; 9.138 ; +; B1 ; S5 ; 10.582 ; 10.511 ; 11.140 ; 11.069 ; +; B1 ; S6 ; 11.154 ; 11.184 ; 11.712 ; 11.742 ; +; B1 ; S7 ; 11.387 ; 11.392 ; 11.945 ; 11.950 ; +; B2 ; C8 ; 9.178 ; 9.199 ; 9.847 ; 9.811 ; +; B2 ; S1 ; 7.302 ; 7.286 ; 7.813 ; 7.829 ; +; B2 ; S2 ; 6.983 ; 6.963 ; 7.493 ; 7.505 ; +; B2 ; S3 ; 6.551 ; 6.533 ; 7.026 ; 7.040 ; +; B2 ; S4 ; 7.979 ; 7.966 ; 8.512 ; 8.490 ; +; B2 ; S5 ; 9.880 ; 9.807 ; 10.492 ; 10.421 ; +; B2 ; S6 ; 10.452 ; 10.482 ; 11.064 ; 11.094 ; +; B2 ; S7 ; 10.685 ; 10.690 ; 11.297 ; 11.302 ; +; B3 ; C8 ; 9.047 ; 9.068 ; 9.678 ; 9.642 ; +; B3 ; S1 ; 7.171 ; 7.155 ; 7.644 ; 7.660 ; +; B3 ; S2 ; 6.852 ; 6.832 ; 7.324 ; 7.336 ; +; B3 ; S3 ; 6.429 ; 6.448 ; 6.889 ; 6.851 ; +; B3 ; S4 ; 7.848 ; 7.835 ; 8.343 ; 8.321 ; +; B3 ; S5 ; 9.749 ; 9.676 ; 10.323 ; 10.252 ; +; B3 ; S6 ; 10.321 ; 10.351 ; 10.895 ; 10.925 ; +; B3 ; S7 ; 10.554 ; 10.559 ; 11.128 ; 11.133 ; +; B4 ; C8 ; 7.986 ; 8.007 ; 8.566 ; 8.530 ; +; B4 ; S4 ; 6.786 ; 6.771 ; 7.188 ; 7.205 ; +; B4 ; S5 ; 8.688 ; 8.615 ; 9.211 ; 9.140 ; +; B4 ; S6 ; 9.260 ; 9.290 ; 9.783 ; 9.813 ; +; B4 ; S7 ; 9.493 ; 9.498 ; 10.016 ; 10.021 ; +; B5 ; C8 ; 7.085 ; 7.106 ; 7.604 ; 7.568 ; +; B5 ; S5 ; 7.787 ; 7.714 ; 8.249 ; 8.178 ; +; B5 ; S6 ; 8.359 ; 8.389 ; 8.821 ; 8.851 ; +; B5 ; S7 ; 8.592 ; 8.597 ; 9.054 ; 9.059 ; +; B6 ; C8 ; 6.599 ; 6.516 ; 6.955 ; 7.060 ; +; B6 ; S5 ; 7.237 ; 7.173 ; 7.741 ; 7.668 ; +; B6 ; S6 ; 7.810 ; 7.808 ; 8.313 ; 8.343 ; +; B6 ; S7 ; 8.011 ; 8.007 ; 8.546 ; 8.551 ; +; B7 ; C8 ; 6.163 ; ; ; 6.594 ; +; B7 ; S5 ; 6.801 ; 6.737 ; 7.275 ; 7.202 ; +; B7 ; S6 ; 7.374 ; 7.372 ; 7.847 ; 7.877 ; +; B7 ; S7 ; 7.575 ; 7.548 ; 8.080 ; 8.085 ; ++------------+-------------+--------+--------+--------+--------+ + + ++------------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+--------+--------+ +; A0 ; C8 ; 9.480 ; 9.477 ; 9.900 ; 9.897 ; +; A0 ; S0 ; 6.854 ; 6.844 ; 7.272 ; 7.293 ; +; A0 ; S1 ; 7.331 ; 7.339 ; 7.751 ; 7.759 ; +; A0 ; S2 ; 7.024 ; 7.048 ; 7.444 ; 7.483 ; +; A0 ; S3 ; 7.335 ; 7.318 ; 7.755 ; 7.738 ; +; A0 ; S4 ; 8.706 ; 8.693 ; 9.126 ; 9.113 ; +; A0 ; S5 ; 8.918 ; 8.876 ; 9.338 ; 9.296 ; +; A0 ; S6 ; 9.500 ; 9.496 ; 9.920 ; 9.916 ; +; A0 ; S7 ; 8.867 ; 8.870 ; 9.287 ; 9.290 ; +; A1 ; C8 ; 8.935 ; 8.932 ; 9.353 ; 9.350 ; +; A1 ; S1 ; 6.786 ; 6.794 ; 7.204 ; 7.212 ; +; A1 ; S2 ; 6.479 ; 6.518 ; 6.897 ; 6.936 ; +; A1 ; S3 ; 6.790 ; 6.773 ; 7.208 ; 7.191 ; +; A1 ; S4 ; 8.161 ; 8.148 ; 8.579 ; 8.566 ; +; A1 ; S5 ; 8.373 ; 8.331 ; 8.791 ; 8.749 ; +; A1 ; S6 ; 8.955 ; 8.951 ; 9.373 ; 9.369 ; +; A1 ; S7 ; 8.322 ; 8.325 ; 8.740 ; 8.743 ; +; A2 ; C8 ; 8.820 ; 8.817 ; 9.259 ; 9.256 ; +; A2 ; S1 ; 7.396 ; 7.380 ; 7.835 ; 7.819 ; +; A2 ; S2 ; 6.654 ; 6.636 ; 7.097 ; 7.075 ; +; A2 ; S3 ; 6.675 ; 6.658 ; 7.114 ; 7.095 ; +; A2 ; S4 ; 8.046 ; 8.033 ; 8.485 ; 8.472 ; +; A2 ; S5 ; 8.258 ; 8.216 ; 8.697 ; 8.655 ; +; A2 ; S6 ; 8.840 ; 8.836 ; 9.279 ; 9.275 ; +; A2 ; S7 ; 8.207 ; 8.210 ; 8.646 ; 8.649 ; +; A3 ; C8 ; 8.424 ; 8.421 ; 8.844 ; 8.872 ; +; A3 ; S1 ; 7.000 ; 6.984 ; 7.401 ; 7.416 ; +; A3 ; S2 ; 6.694 ; 6.675 ; 7.093 ; 7.104 ; +; A3 ; S3 ; 6.262 ; 6.294 ; 6.697 ; 6.648 ; +; A3 ; S4 ; 7.650 ; 7.637 ; 8.071 ; 8.049 ; +; A3 ; S5 ; 7.862 ; 7.820 ; 8.312 ; 8.263 ; +; A3 ; S6 ; 8.444 ; 8.440 ; 8.876 ; 8.903 ; +; A3 ; S7 ; 7.811 ; 7.814 ; 8.261 ; 8.226 ; +; A4 ; C8 ; 7.536 ; 7.533 ; 7.989 ; 8.017 ; +; A4 ; S4 ; 6.761 ; 6.775 ; 7.219 ; 7.196 ; +; A4 ; S5 ; 7.694 ; 7.655 ; 8.147 ; 8.108 ; +; A4 ; S6 ; 7.863 ; 7.888 ; 8.393 ; 8.381 ; +; A4 ; S7 ; 7.766 ; 7.741 ; 8.273 ; 8.244 ; +; A5 ; C8 ; 6.727 ; 6.726 ; 7.157 ; 7.147 ; +; A5 ; S5 ; 6.885 ; 6.846 ; 7.315 ; 7.276 ; +; A5 ; S6 ; 7.054 ; 7.079 ; 7.523 ; 7.511 ; +; A5 ; S7 ; 6.957 ; 6.932 ; 7.403 ; 7.374 ; +; A6 ; C8 ; 6.459 ; 6.441 ; 6.838 ; 6.852 ; +; A6 ; S5 ; 7.066 ; 7.002 ; 7.445 ; 7.381 ; +; A6 ; S6 ; 7.204 ; 7.214 ; 7.585 ; 7.593 ; +; A6 ; S7 ; 6.674 ; 6.649 ; 7.051 ; 7.026 ; +; A7 ; C8 ; 6.545 ; ; ; 6.965 ; +; A7 ; S5 ; 7.152 ; 7.088 ; 7.612 ; 7.539 ; +; A7 ; S6 ; 7.302 ; 7.300 ; 7.763 ; 7.752 ; +; A7 ; S7 ; 7.052 ; 7.027 ; 7.495 ; 7.470 ; +; B0 ; C8 ; 9.542 ; 9.539 ; 10.003 ; 10.000 ; +; B0 ; S0 ; 6.917 ; 6.934 ; 7.378 ; 7.365 ; +; B0 ; S1 ; 7.393 ; 7.401 ; 7.854 ; 7.862 ; +; B0 ; S2 ; 7.086 ; 7.125 ; 7.547 ; 7.586 ; +; B0 ; S3 ; 7.397 ; 7.380 ; 7.858 ; 7.841 ; +; B0 ; S4 ; 8.768 ; 8.755 ; 9.229 ; 9.216 ; +; B0 ; S5 ; 8.980 ; 8.938 ; 9.441 ; 9.399 ; +; B0 ; S6 ; 9.562 ; 9.558 ; 10.023 ; 10.019 ; +; B0 ; S7 ; 8.929 ; 8.932 ; 9.390 ; 9.393 ; +; B1 ; C8 ; 9.000 ; 8.997 ; 9.402 ; 9.399 ; +; B1 ; S1 ; 6.851 ; 6.859 ; 7.253 ; 7.261 ; +; B1 ; S2 ; 6.544 ; 6.570 ; 6.946 ; 6.963 ; +; B1 ; S3 ; 6.855 ; 6.838 ; 7.257 ; 7.240 ; +; B1 ; S4 ; 8.226 ; 8.213 ; 8.628 ; 8.615 ; +; B1 ; S5 ; 8.438 ; 8.396 ; 8.840 ; 8.798 ; +; B1 ; S6 ; 9.020 ; 9.016 ; 9.422 ; 9.418 ; +; B1 ; S7 ; 8.387 ; 8.390 ; 8.789 ; 8.792 ; +; B2 ; C8 ; 8.326 ; 8.323 ; 8.707 ; 8.704 ; +; B2 ; S1 ; 6.902 ; 6.886 ; 7.283 ; 7.267 ; +; B2 ; S2 ; 6.220 ; 6.202 ; 6.653 ; 6.635 ; +; B2 ; S3 ; 6.181 ; 6.164 ; 6.562 ; 6.545 ; +; B2 ; S4 ; 7.552 ; 7.539 ; 7.933 ; 7.920 ; +; B2 ; S5 ; 7.764 ; 7.722 ; 8.145 ; 8.103 ; +; B2 ; S6 ; 8.346 ; 8.342 ; 8.727 ; 8.723 ; +; B2 ; S7 ; 7.713 ; 7.716 ; 8.094 ; 8.097 ; +; B3 ; C8 ; 8.380 ; 8.377 ; 8.818 ; 8.846 ; +; B3 ; S1 ; 6.956 ; 6.940 ; 7.375 ; 7.390 ; +; B3 ; S2 ; 6.650 ; 6.631 ; 7.067 ; 7.078 ; +; B3 ; S3 ; 6.224 ; 6.256 ; 6.685 ; 6.627 ; +; B3 ; S4 ; 7.606 ; 7.593 ; 8.045 ; 8.023 ; +; B3 ; S5 ; 7.818 ; 7.776 ; 8.286 ; 8.237 ; +; B3 ; S6 ; 8.400 ; 8.396 ; 8.850 ; 8.877 ; +; B3 ; S7 ; 7.767 ; 7.770 ; 8.235 ; 8.200 ; +; B4 ; C8 ; 7.473 ; 7.500 ; 7.947 ; 7.962 ; +; B4 ; S4 ; 6.625 ; 6.610 ; 7.017 ; 7.033 ; +; B4 ; S5 ; 7.631 ; 7.592 ; 8.105 ; 8.066 ; +; B4 ; S6 ; 7.815 ; 7.840 ; 8.318 ; 8.306 ; +; B4 ; S7 ; 7.718 ; 7.693 ; 8.198 ; 8.169 ; +; B5 ; C8 ; 6.612 ; 6.638 ; 7.026 ; 7.015 ; +; B5 ; S5 ; 6.770 ; 6.731 ; 7.184 ; 7.145 ; +; B5 ; S6 ; 6.947 ; 6.972 ; 7.393 ; 7.381 ; +; B5 ; S7 ; 6.850 ; 6.825 ; 7.273 ; 7.244 ; +; B6 ; C8 ; 6.326 ; 6.332 ; 6.762 ; 6.768 ; +; B6 ; S5 ; 6.933 ; 6.869 ; 7.369 ; 7.305 ; +; B6 ; S6 ; 7.040 ; 7.066 ; 7.473 ; 7.490 ; +; B6 ; S7 ; 6.517 ; 6.492 ; 6.946 ; 6.912 ; +; B7 ; C8 ; 5.992 ; ; ; 6.371 ; +; B7 ; S5 ; 6.599 ; 6.535 ; 7.018 ; 6.945 ; +; B7 ; S6 ; 6.749 ; 6.747 ; 7.169 ; 7.158 ; +; B7 ; S7 ; 6.160 ; 6.162 ; 6.580 ; 6.545 ; ++------------+-------------+-------+-------+--------+--------+ + + +---------------------------------------------- +; Slow 1200mV 85C Model Metastability Report ; +---------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + ++--------------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+--------+--------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+--------+--------+--------+ +; A0 ; C8 ; 9.566 ; 9.528 ; 10.080 ; 10.028 ; +; A0 ; S0 ; 6.533 ; 6.503 ; 6.878 ; 6.877 ; +; A0 ; S1 ; 7.818 ; 7.782 ; 8.282 ; 8.275 ; +; A0 ; S2 ; 7.521 ; 7.491 ; 7.983 ; 7.983 ; +; A0 ; S3 ; 7.133 ; 7.102 ; 7.567 ; 7.565 ; +; A0 ; S4 ; 8.461 ; 8.421 ; 8.899 ; 8.851 ; +; A0 ; S5 ; 10.148 ; 10.084 ; 10.655 ; 10.598 ; +; A0 ; S6 ; 10.689 ; 10.674 ; 11.199 ; 11.174 ; +; A0 ; S7 ; 10.879 ; 10.863 ; 11.379 ; 11.363 ; +; A1 ; C8 ; 9.111 ; 9.059 ; 9.590 ; 9.538 ; +; A1 ; S1 ; 7.313 ; 7.306 ; 7.792 ; 7.785 ; +; A1 ; S2 ; 7.015 ; 7.014 ; 7.493 ; 7.493 ; +; A1 ; S3 ; 6.631 ; 6.596 ; 7.077 ; 7.075 ; +; A1 ; S4 ; 7.955 ; 7.915 ; 8.409 ; 8.361 ; +; A1 ; S5 ; 9.686 ; 9.629 ; 10.165 ; 10.108 ; +; A1 ; S6 ; 10.230 ; 10.205 ; 10.709 ; 10.684 ; +; A1 ; S7 ; 10.410 ; 10.394 ; 10.889 ; 10.873 ; +; A2 ; C8 ; 8.862 ; 8.857 ; 9.332 ; 9.280 ; +; A2 ; S1 ; 7.147 ; 7.111 ; 7.534 ; 7.527 ; +; A2 ; S2 ; 6.850 ; 6.820 ; 7.235 ; 7.235 ; +; A2 ; S3 ; 6.462 ; 6.431 ; 6.819 ; 6.817 ; +; A2 ; S4 ; 7.790 ; 7.750 ; 8.151 ; 8.103 ; +; A2 ; S5 ; 9.477 ; 9.412 ; 9.907 ; 9.850 ; +; A2 ; S6 ; 10.018 ; 10.003 ; 10.451 ; 10.426 ; +; A2 ; S7 ; 10.208 ; 10.192 ; 10.631 ; 10.615 ; +; A3 ; C8 ; 8.406 ; 8.401 ; 8.879 ; 8.827 ; +; A3 ; S1 ; 6.691 ; 6.655 ; 7.081 ; 7.074 ; +; A3 ; S2 ; 6.394 ; 6.364 ; 6.782 ; 6.782 ; +; A3 ; S3 ; 6.014 ; 6.012 ; 6.382 ; 6.344 ; +; A3 ; S4 ; 7.334 ; 7.294 ; 7.698 ; 7.650 ; +; A3 ; S5 ; 9.021 ; 8.956 ; 9.454 ; 9.397 ; +; A3 ; S6 ; 9.562 ; 9.547 ; 9.998 ; 9.973 ; +; A3 ; S7 ; 9.752 ; 9.736 ; 10.178 ; 10.162 ; +; A4 ; C8 ; 7.557 ; 7.552 ; 8.052 ; 8.000 ; +; A4 ; S4 ; 6.495 ; 6.477 ; 6.860 ; 6.838 ; +; A4 ; S5 ; 8.172 ; 8.107 ; 8.627 ; 8.570 ; +; A4 ; S6 ; 8.713 ; 8.698 ; 9.171 ; 9.146 ; +; A4 ; S7 ; 8.903 ; 8.887 ; 9.351 ; 9.335 ; +; A5 ; C8 ; 6.637 ; 6.632 ; 7.058 ; 7.006 ; +; A5 ; S5 ; 7.252 ; 7.187 ; 7.633 ; 7.576 ; +; A5 ; S6 ; 7.793 ; 7.778 ; 8.177 ; 8.152 ; +; A5 ; S7 ; 7.983 ; 7.967 ; 8.357 ; 8.341 ; +; A6 ; C8 ; 6.243 ; 6.105 ; 6.484 ; 6.602 ; +; A6 ; S5 ; 6.818 ; 6.761 ; 7.222 ; 7.157 ; +; A6 ; S6 ; 7.362 ; 7.318 ; 7.763 ; 7.748 ; +; A6 ; S7 ; 7.526 ; 7.481 ; 7.953 ; 7.937 ; +; A7 ; C8 ; 6.263 ; ; ; 6.636 ; +; A7 ; S5 ; 6.838 ; 6.781 ; 7.256 ; 7.191 ; +; A7 ; S6 ; 7.382 ; 7.338 ; 7.797 ; 7.782 ; +; A7 ; S7 ; 7.546 ; 7.501 ; 7.987 ; 7.971 ; +; B0 ; C8 ; 9.694 ; 9.642 ; 10.184 ; 10.132 ; +; B0 ; S0 ; 6.637 ; 6.635 ; 7.028 ; 7.012 ; +; B0 ; S1 ; 7.896 ; 7.889 ; 8.386 ; 8.379 ; +; B0 ; S2 ; 7.597 ; 7.597 ; 8.087 ; 8.087 ; +; B0 ; S3 ; 7.214 ; 7.177 ; 7.671 ; 7.669 ; +; B0 ; S4 ; 8.533 ; 8.493 ; 9.003 ; 8.955 ; +; B0 ; S5 ; 10.269 ; 10.212 ; 10.759 ; 10.702 ; +; B0 ; S6 ; 10.813 ; 10.788 ; 11.303 ; 11.278 ; +; B0 ; S7 ; 10.993 ; 10.977 ; 11.483 ; 11.467 ; +; B1 ; C8 ; 9.098 ; 9.058 ; 9.592 ; 9.540 ; +; B1 ; S1 ; 7.348 ; 7.312 ; 7.794 ; 7.787 ; +; B1 ; S2 ; 7.051 ; 7.021 ; 7.495 ; 7.495 ; +; B1 ; S3 ; 6.663 ; 6.632 ; 7.079 ; 7.077 ; +; B1 ; S4 ; 7.991 ; 7.951 ; 8.411 ; 8.363 ; +; B1 ; S5 ; 9.678 ; 9.616 ; 10.167 ; 10.110 ; +; B1 ; S6 ; 10.219 ; 10.204 ; 10.711 ; 10.686 ; +; B1 ; S7 ; 10.409 ; 10.393 ; 10.891 ; 10.875 ; +; B2 ; C8 ; 8.474 ; 8.469 ; 9.001 ; 8.949 ; +; B2 ; S1 ; 6.759 ; 6.723 ; 7.203 ; 7.196 ; +; B2 ; S2 ; 6.462 ; 6.432 ; 6.904 ; 6.904 ; +; B2 ; S3 ; 6.074 ; 6.043 ; 6.488 ; 6.486 ; +; B2 ; S4 ; 7.402 ; 7.362 ; 7.820 ; 7.772 ; +; B2 ; S5 ; 9.089 ; 9.024 ; 9.576 ; 9.519 ; +; B2 ; S6 ; 9.630 ; 9.615 ; 10.120 ; 10.095 ; +; B2 ; S7 ; 9.820 ; 9.804 ; 10.300 ; 10.284 ; +; B3 ; C8 ; 8.364 ; 8.359 ; 8.847 ; 8.795 ; +; B3 ; S1 ; 6.649 ; 6.613 ; 7.049 ; 7.042 ; +; B3 ; S2 ; 6.352 ; 6.322 ; 6.750 ; 6.750 ; +; B3 ; S3 ; 5.973 ; 5.975 ; 6.360 ; 6.315 ; +; B3 ; S4 ; 7.292 ; 7.252 ; 7.666 ; 7.618 ; +; B3 ; S5 ; 8.979 ; 8.914 ; 9.422 ; 9.365 ; +; B3 ; S6 ; 9.520 ; 9.505 ; 9.966 ; 9.941 ; +; B3 ; S7 ; 9.710 ; 9.694 ; 10.146 ; 10.130 ; +; B4 ; C8 ; 7.389 ; 7.384 ; 7.868 ; 7.816 ; +; B4 ; S4 ; 6.316 ; 6.274 ; 6.649 ; 6.636 ; +; B4 ; S5 ; 8.004 ; 7.939 ; 8.443 ; 8.386 ; +; B4 ; S6 ; 8.545 ; 8.530 ; 8.987 ; 8.962 ; +; B4 ; S7 ; 8.735 ; 8.719 ; 9.167 ; 9.151 ; +; B5 ; C8 ; 6.563 ; 6.558 ; 7.002 ; 6.950 ; +; B5 ; S5 ; 7.178 ; 7.113 ; 7.577 ; 7.520 ; +; B5 ; S6 ; 7.719 ; 7.704 ; 8.121 ; 8.096 ; +; B5 ; S7 ; 7.909 ; 7.893 ; 8.301 ; 8.285 ; +; B6 ; C8 ; 6.127 ; 6.027 ; 6.432 ; 6.510 ; +; B6 ; S5 ; 6.702 ; 6.645 ; 7.130 ; 7.065 ; +; B6 ; S6 ; 7.246 ; 7.202 ; 7.671 ; 7.656 ; +; B6 ; S7 ; 7.410 ; 7.365 ; 7.861 ; 7.845 ; +; B7 ; C8 ; 5.732 ; ; ; 6.084 ; +; B7 ; S5 ; 6.307 ; 6.250 ; 6.704 ; 6.639 ; +; B7 ; S6 ; 6.851 ; 6.807 ; 7.245 ; 7.230 ; +; B7 ; S7 ; 7.015 ; 6.970 ; 7.435 ; 7.419 ; ++------------+-------------+--------+--------+--------+--------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C8 ; 8.789 ; 8.760 ; 9.129 ; 9.100 ; +; A0 ; S0 ; 6.385 ; 6.354 ; 6.724 ; 6.721 ; +; A0 ; S1 ; 6.817 ; 6.808 ; 7.157 ; 7.148 ; +; A0 ; S2 ; 6.531 ; 6.534 ; 6.871 ; 6.900 ; +; A0 ; S3 ; 6.817 ; 6.789 ; 7.157 ; 7.129 ; +; A0 ; S4 ; 8.093 ; 8.054 ; 8.433 ; 8.394 ; +; A0 ; S5 ; 8.266 ; 8.233 ; 8.606 ; 8.573 ; +; A0 ; S6 ; 8.817 ; 8.775 ; 9.157 ; 9.115 ; +; A0 ; S7 ; 8.225 ; 8.208 ; 8.565 ; 8.552 ; +; A1 ; C8 ; 8.276 ; 8.247 ; 8.630 ; 8.605 ; +; A1 ; S1 ; 6.304 ; 6.295 ; 6.662 ; 6.653 ; +; A1 ; S2 ; 6.018 ; 6.047 ; 6.376 ; 6.397 ; +; A1 ; S3 ; 6.304 ; 6.276 ; 6.662 ; 6.634 ; +; A1 ; S4 ; 7.580 ; 7.541 ; 7.936 ; 7.891 ; +; A1 ; S5 ; 7.753 ; 7.720 ; 8.111 ; 8.078 ; +; A1 ; S6 ; 8.304 ; 8.262 ; 8.662 ; 8.620 ; +; A1 ; S7 ; 7.712 ; 7.695 ; 8.070 ; 8.045 ; +; A2 ; C8 ; 8.169 ; 8.165 ; 8.513 ; 8.512 ; +; A2 ; S1 ; 6.880 ; 6.844 ; 7.228 ; 7.194 ; +; A2 ; S2 ; 6.201 ; 6.171 ; 6.553 ; 6.519 ; +; A2 ; S3 ; 6.222 ; 6.194 ; 6.572 ; 6.538 ; +; A2 ; S4 ; 7.475 ; 7.430 ; 7.819 ; 7.774 ; +; A2 ; S5 ; 7.671 ; 7.629 ; 8.015 ; 7.973 ; +; A2 ; S6 ; 8.207 ; 8.180 ; 8.551 ; 8.530 ; +; A2 ; S7 ; 7.630 ; 7.584 ; 7.977 ; 7.928 ; +; A3 ; C8 ; 7.819 ; 7.790 ; 8.134 ; 8.133 ; +; A3 ; S1 ; 6.505 ; 6.469 ; 6.849 ; 6.841 ; +; A3 ; S2 ; 6.221 ; 6.191 ; 6.562 ; 6.560 ; +; A3 ; S3 ; 5.831 ; 5.848 ; 6.208 ; 6.152 ; +; A3 ; S4 ; 7.123 ; 7.084 ; 7.440 ; 7.395 ; +; A3 ; S5 ; 7.296 ; 7.263 ; 7.636 ; 7.594 ; +; A3 ; S6 ; 7.847 ; 7.805 ; 8.172 ; 8.158 ; +; A3 ; S7 ; 7.255 ; 7.242 ; 7.598 ; 7.549 ; +; A4 ; C8 ; 6.989 ; 6.960 ; 7.350 ; 7.349 ; +; A4 ; S4 ; 6.293 ; 6.282 ; 6.656 ; 6.610 ; +; A4 ; S5 ; 7.120 ; 7.089 ; 7.481 ; 7.450 ; +; A4 ; S6 ; 7.295 ; 7.282 ; 7.720 ; 7.674 ; +; A4 ; S7 ; 7.195 ; 7.151 ; 7.601 ; 7.553 ; +; A5 ; C8 ; 6.261 ; 6.234 ; 6.627 ; 6.594 ; +; A5 ; S5 ; 6.392 ; 6.361 ; 6.758 ; 6.727 ; +; A5 ; S6 ; 6.568 ; 6.555 ; 6.965 ; 6.919 ; +; A5 ; S7 ; 6.468 ; 6.424 ; 6.846 ; 6.798 ; +; A6 ; C8 ; 6.016 ; 5.977 ; 6.347 ; 6.337 ; +; A6 ; S5 ; 6.561 ; 6.502 ; 6.892 ; 6.834 ; +; A6 ; S6 ; 6.710 ; 6.671 ; 7.040 ; 7.013 ; +; A6 ; S7 ; 6.211 ; 6.165 ; 6.539 ; 6.497 ; +; A7 ; C8 ; 6.095 ; ; ; 6.420 ; +; A7 ; S5 ; 6.640 ; 6.582 ; 7.009 ; 6.945 ; +; A7 ; S6 ; 6.801 ; 6.761 ; 7.170 ; 7.124 ; +; A7 ; S7 ; 6.557 ; 6.515 ; 6.918 ; 6.870 ; +; B0 ; C8 ; 8.831 ; 8.802 ; 9.203 ; 9.184 ; +; B0 ; S0 ; 6.429 ; 6.427 ; 6.812 ; 6.779 ; +; B0 ; S1 ; 6.859 ; 6.850 ; 7.241 ; 7.232 ; +; B0 ; S2 ; 6.573 ; 6.602 ; 6.955 ; 6.973 ; +; B0 ; S3 ; 6.859 ; 6.831 ; 7.241 ; 7.213 ; +; B0 ; S4 ; 8.135 ; 8.096 ; 8.509 ; 8.464 ; +; B0 ; S5 ; 8.308 ; 8.275 ; 8.690 ; 8.657 ; +; B0 ; S6 ; 8.859 ; 8.817 ; 9.241 ; 9.199 ; +; B0 ; S7 ; 8.267 ; 8.254 ; 8.649 ; 8.618 ; +; B1 ; C8 ; 8.342 ; 8.313 ; 8.691 ; 8.667 ; +; B1 ; S1 ; 6.370 ; 6.361 ; 6.724 ; 6.715 ; +; B1 ; S2 ; 6.084 ; 6.089 ; 6.438 ; 6.437 ; +; B1 ; S3 ; 6.370 ; 6.342 ; 6.724 ; 6.696 ; +; B1 ; S4 ; 7.646 ; 7.607 ; 7.997 ; 7.952 ; +; B1 ; S5 ; 7.819 ; 7.786 ; 8.173 ; 8.140 ; +; B1 ; S6 ; 8.370 ; 8.328 ; 8.724 ; 8.682 ; +; B1 ; S7 ; 7.778 ; 7.761 ; 8.132 ; 8.106 ; +; B2 ; C8 ; 7.703 ; 7.701 ; 8.060 ; 8.031 ; +; B2 ; S1 ; 6.416 ; 6.380 ; 6.746 ; 6.710 ; +; B2 ; S2 ; 5.786 ; 5.758 ; 6.161 ; 6.133 ; +; B2 ; S3 ; 5.758 ; 5.728 ; 6.088 ; 6.060 ; +; B2 ; S4 ; 7.009 ; 6.964 ; 7.364 ; 7.322 ; +; B2 ; S5 ; 7.205 ; 7.163 ; 7.537 ; 7.504 ; +; B2 ; S6 ; 7.741 ; 7.716 ; 8.088 ; 8.046 ; +; B2 ; S7 ; 7.166 ; 7.118 ; 7.496 ; 7.476 ; +; B3 ; C8 ; 7.777 ; 7.748 ; 8.101 ; 8.100 ; +; B3 ; S1 ; 6.463 ; 6.427 ; 6.816 ; 6.808 ; +; B3 ; S2 ; 6.179 ; 6.149 ; 6.529 ; 6.527 ; +; B3 ; S3 ; 5.794 ; 5.812 ; 6.187 ; 6.124 ; +; B3 ; S4 ; 7.081 ; 7.042 ; 7.407 ; 7.362 ; +; B3 ; S5 ; 7.254 ; 7.221 ; 7.603 ; 7.561 ; +; B3 ; S6 ; 7.805 ; 7.763 ; 8.139 ; 8.125 ; +; B3 ; S7 ; 7.213 ; 7.200 ; 7.565 ; 7.516 ; +; B4 ; C8 ; 6.939 ; 6.941 ; 7.329 ; 7.318 ; +; B4 ; S4 ; 6.177 ; 6.136 ; 6.503 ; 6.490 ; +; B4 ; S5 ; 7.070 ; 7.039 ; 7.460 ; 7.429 ; +; B4 ; S6 ; 7.260 ; 7.247 ; 7.670 ; 7.624 ; +; B4 ; S7 ; 7.160 ; 7.116 ; 7.551 ; 7.503 ; +; B5 ; C8 ; 6.147 ; 6.147 ; 6.502 ; 6.469 ; +; B5 ; S5 ; 6.278 ; 6.247 ; 6.633 ; 6.602 ; +; B5 ; S6 ; 6.464 ; 6.451 ; 6.840 ; 6.794 ; +; B5 ; S7 ; 6.364 ; 6.320 ; 6.721 ; 6.673 ; +; B6 ; C8 ; 5.886 ; 5.876 ; 6.269 ; 6.252 ; +; B6 ; S5 ; 6.431 ; 6.373 ; 6.814 ; 6.756 ; +; B6 ; S6 ; 6.553 ; 6.541 ; 6.930 ; 6.889 ; +; B6 ; S7 ; 6.062 ; 6.020 ; 6.426 ; 6.378 ; +; B7 ; C8 ; 5.585 ; ; ; 5.891 ; +; B7 ; S5 ; 6.130 ; 6.072 ; 6.480 ; 6.416 ; +; B7 ; S6 ; 6.291 ; 6.251 ; 6.641 ; 6.595 ; +; B7 ; S7 ; 5.733 ; 5.718 ; 6.094 ; 6.046 ; ++------------+-------------+-------+-------+-------+-------+ + + +--------------------------------------------- +; Slow 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C8 ; 6.136 ; 6.124 ; 6.840 ; 6.828 ; +; A0 ; S0 ; 4.194 ; 4.220 ; 4.793 ; 4.837 ; +; A0 ; S1 ; 4.964 ; 4.997 ; 5.662 ; 5.701 ; +; A0 ; S2 ; 4.765 ; 4.776 ; 5.461 ; 5.480 ; +; A0 ; S3 ; 4.539 ; 4.540 ; 5.213 ; 5.232 ; +; A0 ; S4 ; 5.397 ; 5.412 ; 6.101 ; 6.116 ; +; A0 ; S5 ; 6.437 ; 6.481 ; 7.141 ; 7.185 ; +; A0 ; S6 ; 6.825 ; 6.869 ; 7.529 ; 7.573 ; +; A0 ; S7 ; 6.926 ; 6.960 ; 7.630 ; 7.664 ; +; A1 ; C8 ; 5.851 ; 5.839 ; 6.483 ; 6.471 ; +; A1 ; S1 ; 4.673 ; 4.712 ; 5.305 ; 5.344 ; +; A1 ; S2 ; 4.472 ; 4.491 ; 5.104 ; 5.123 ; +; A1 ; S3 ; 4.243 ; 4.240 ; 4.856 ; 4.875 ; +; A1 ; S4 ; 5.112 ; 5.127 ; 5.744 ; 5.759 ; +; A1 ; S5 ; 6.152 ; 6.196 ; 6.784 ; 6.828 ; +; A1 ; S6 ; 6.540 ; 6.584 ; 7.172 ; 7.216 ; +; A1 ; S7 ; 6.641 ; 6.675 ; 7.273 ; 7.307 ; +; A2 ; C8 ; 5.695 ; 5.683 ; 6.372 ; 6.360 ; +; A2 ; S1 ; 4.555 ; 4.576 ; 5.194 ; 5.233 ; +; A2 ; S2 ; 4.356 ; 4.356 ; 4.993 ; 5.012 ; +; A2 ; S3 ; 4.130 ; 4.131 ; 4.745 ; 4.764 ; +; A2 ; S4 ; 4.956 ; 4.971 ; 5.633 ; 5.648 ; +; A2 ; S5 ; 5.996 ; 6.040 ; 6.673 ; 6.717 ; +; A2 ; S6 ; 6.384 ; 6.428 ; 7.061 ; 7.105 ; +; A2 ; S7 ; 6.485 ; 6.519 ; 7.162 ; 7.196 ; +; A3 ; C8 ; 5.302 ; 5.329 ; 6.067 ; 6.055 ; +; A3 ; S1 ; 4.287 ; 4.308 ; 4.889 ; 4.928 ; +; A3 ; S2 ; 4.088 ; 4.088 ; 4.688 ; 4.707 ; +; A3 ; S3 ; 3.868 ; 3.886 ; 4.458 ; 4.444 ; +; A3 ; S4 ; 4.667 ; 4.689 ; 5.328 ; 5.343 ; +; A3 ; S5 ; 5.642 ; 5.686 ; 6.368 ; 6.412 ; +; A3 ; S6 ; 6.030 ; 6.074 ; 6.756 ; 6.800 ; +; A3 ; S7 ; 6.131 ; 6.165 ; 6.857 ; 6.891 ; +; A4 ; C8 ; 4.796 ; 4.823 ; 5.508 ; 5.496 ; +; A4 ; S4 ; 4.166 ; 4.198 ; 4.771 ; 4.794 ; +; A4 ; S5 ; 5.136 ; 5.180 ; 5.809 ; 5.853 ; +; A4 ; S6 ; 5.524 ; 5.568 ; 6.197 ; 6.241 ; +; A4 ; S7 ; 5.625 ; 5.659 ; 6.298 ; 6.332 ; +; A5 ; C8 ; 4.225 ; 4.252 ; 4.867 ; 4.855 ; +; A5 ; S5 ; 4.565 ; 4.609 ; 5.168 ; 5.212 ; +; A5 ; S6 ; 4.953 ; 4.997 ; 5.556 ; 5.600 ; +; A5 ; S7 ; 5.054 ; 5.088 ; 5.657 ; 5.691 ; +; A6 ; C8 ; 3.990 ; 3.938 ; 4.488 ; 4.588 ; +; A6 ; S5 ; 4.279 ; 4.330 ; 4.901 ; 4.945 ; +; A6 ; S6 ; 4.662 ; 4.688 ; 5.289 ; 5.333 ; +; A6 ; S7 ; 4.742 ; 4.774 ; 5.390 ; 5.424 ; +; A7 ; C8 ; 4.026 ; ; ; 4.650 ; +; A7 ; S5 ; 4.315 ; 4.366 ; 4.963 ; 5.007 ; +; A7 ; S6 ; 4.698 ; 4.724 ; 5.351 ; 5.395 ; +; A7 ; S7 ; 4.778 ; 4.794 ; 5.452 ; 5.486 ; +; B0 ; C8 ; 6.199 ; 6.187 ; 6.891 ; 6.879 ; +; B0 ; S0 ; 4.245 ; 4.285 ; 4.882 ; 4.909 ; +; B0 ; S1 ; 5.021 ; 5.060 ; 5.713 ; 5.752 ; +; B0 ; S2 ; 4.820 ; 4.839 ; 5.512 ; 5.531 ; +; B0 ; S3 ; 4.591 ; 4.588 ; 5.264 ; 5.283 ; +; B0 ; S4 ; 5.460 ; 5.475 ; 6.152 ; 6.167 ; +; B0 ; S5 ; 6.500 ; 6.544 ; 7.192 ; 7.236 ; +; B0 ; S6 ; 6.888 ; 6.932 ; 7.580 ; 7.624 ; +; B0 ; S7 ; 6.989 ; 7.023 ; 7.681 ; 7.715 ; +; B1 ; C8 ; 5.847 ; 5.835 ; 6.497 ; 6.485 ; +; B1 ; S1 ; 4.671 ; 4.708 ; 5.319 ; 5.358 ; +; B1 ; S2 ; 4.472 ; 4.487 ; 5.118 ; 5.137 ; +; B1 ; S3 ; 4.246 ; 4.247 ; 4.870 ; 4.889 ; +; B1 ; S4 ; 5.108 ; 5.123 ; 5.758 ; 5.773 ; +; B1 ; S5 ; 6.148 ; 6.192 ; 6.798 ; 6.842 ; +; B1 ; S6 ; 6.536 ; 6.580 ; 7.186 ; 7.230 ; +; B1 ; S7 ; 6.637 ; 6.671 ; 7.287 ; 7.321 ; +; B2 ; C8 ; 5.378 ; 5.366 ; 6.103 ; 6.091 ; +; B2 ; S1 ; 4.314 ; 4.335 ; 4.925 ; 4.964 ; +; B2 ; S2 ; 4.115 ; 4.115 ; 4.724 ; 4.743 ; +; B2 ; S3 ; 3.889 ; 3.890 ; 4.476 ; 4.495 ; +; B2 ; S4 ; 4.694 ; 4.716 ; 5.364 ; 5.379 ; +; B2 ; S5 ; 5.679 ; 5.723 ; 6.404 ; 6.448 ; +; B2 ; S6 ; 6.067 ; 6.111 ; 6.792 ; 6.836 ; +; B2 ; S7 ; 6.168 ; 6.202 ; 6.893 ; 6.927 ; +; B3 ; C8 ; 5.265 ; 5.292 ; 6.036 ; 6.024 ; +; B3 ; S1 ; 4.250 ; 4.271 ; 4.858 ; 4.897 ; +; B3 ; S2 ; 4.051 ; 4.051 ; 4.657 ; 4.676 ; +; B3 ; S3 ; 3.833 ; 3.852 ; 4.434 ; 4.414 ; +; B3 ; S4 ; 4.630 ; 4.652 ; 5.297 ; 5.312 ; +; B3 ; S5 ; 5.605 ; 5.649 ; 6.337 ; 6.381 ; +; B3 ; S6 ; 5.993 ; 6.037 ; 6.725 ; 6.769 ; +; B3 ; S7 ; 6.094 ; 6.128 ; 6.826 ; 6.860 ; +; B4 ; C8 ; 4.688 ; 4.715 ; 5.383 ; 5.371 ; +; B4 ; S4 ; 4.051 ; 4.070 ; 4.621 ; 4.658 ; +; B4 ; S5 ; 5.028 ; 5.072 ; 5.684 ; 5.728 ; +; B4 ; S6 ; 5.416 ; 5.460 ; 6.072 ; 6.116 ; +; B4 ; S7 ; 5.517 ; 5.551 ; 6.173 ; 6.207 ; +; B5 ; C8 ; 4.180 ; 4.207 ; 4.808 ; 4.796 ; +; B5 ; S5 ; 4.520 ; 4.564 ; 5.109 ; 5.153 ; +; B5 ; S6 ; 4.908 ; 4.952 ; 5.497 ; 5.541 ; +; B5 ; S7 ; 5.009 ; 5.043 ; 5.598 ; 5.632 ; +; B6 ; C8 ; 3.924 ; 3.897 ; 4.449 ; 4.513 ; +; B6 ; S5 ; 4.213 ; 4.264 ; 4.826 ; 4.870 ; +; B6 ; S6 ; 4.598 ; 4.642 ; 5.214 ; 5.258 ; +; B6 ; S7 ; 4.699 ; 4.733 ; 5.315 ; 5.349 ; +; B7 ; C8 ; 3.677 ; ; ; 4.246 ; +; B7 ; S5 ; 3.966 ; 4.017 ; 4.559 ; 4.603 ; +; B7 ; S6 ; 4.349 ; 4.375 ; 4.947 ; 4.991 ; +; B7 ; S7 ; 4.429 ; 4.445 ; 5.048 ; 5.082 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C8 ; 5.504 ; 5.527 ; 6.095 ; 6.118 ; +; A0 ; S0 ; 4.100 ; 4.123 ; 4.689 ; 4.732 ; +; A0 ; S1 ; 4.360 ; 4.389 ; 4.951 ; 4.980 ; +; A0 ; S2 ; 4.169 ; 4.197 ; 4.760 ; 4.788 ; +; A0 ; S3 ; 4.336 ; 4.339 ; 4.927 ; 4.930 ; +; A0 ; S4 ; 5.107 ; 5.128 ; 5.698 ; 5.719 ; +; A0 ; S5 ; 5.165 ; 5.220 ; 5.756 ; 5.811 ; +; A0 ; S6 ; 5.558 ; 5.580 ; 6.149 ; 6.171 ; +; A0 ; S7 ; 5.192 ; 5.218 ; 5.783 ; 5.809 ; +; A1 ; C8 ; 5.182 ; 5.205 ; 5.741 ; 5.764 ; +; A1 ; S1 ; 4.038 ; 4.067 ; 4.597 ; 4.626 ; +; A1 ; S2 ; 3.847 ; 3.875 ; 4.406 ; 4.434 ; +; A1 ; S3 ; 4.014 ; 4.017 ; 4.573 ; 4.576 ; +; A1 ; S4 ; 4.785 ; 4.806 ; 5.344 ; 5.365 ; +; A1 ; S5 ; 4.843 ; 4.898 ; 5.402 ; 5.457 ; +; A1 ; S6 ; 5.236 ; 5.258 ; 5.795 ; 5.817 ; +; A1 ; S7 ; 4.870 ; 4.896 ; 5.429 ; 5.455 ; +; A2 ; C8 ; 5.142 ; 5.165 ; 5.742 ; 5.765 ; +; A2 ; S1 ; 4.383 ; 4.401 ; 4.983 ; 5.001 ; +; A2 ; S2 ; 3.956 ; 3.959 ; 4.555 ; 4.558 ; +; A2 ; S3 ; 3.974 ; 3.977 ; 4.574 ; 4.577 ; +; A2 ; S4 ; 4.745 ; 4.766 ; 5.345 ; 5.366 ; +; A2 ; S5 ; 4.803 ; 4.858 ; 5.403 ; 5.458 ; +; A2 ; S6 ; 5.196 ; 5.218 ; 5.796 ; 5.818 ; +; A2 ; S7 ; 4.830 ; 4.856 ; 5.430 ; 5.456 ; +; A3 ; C8 ; 4.925 ; 4.948 ; 5.561 ; 5.604 ; +; A3 ; S1 ; 4.166 ; 4.184 ; 4.737 ; 4.775 ; +; A3 ; S2 ; 3.973 ; 3.972 ; 4.543 ; 4.561 ; +; A3 ; S3 ; 3.749 ; 3.774 ; 4.341 ; 4.317 ; +; A3 ; S4 ; 4.528 ; 4.549 ; 5.157 ; 5.171 ; +; A3 ; S5 ; 4.586 ; 4.641 ; 5.235 ; 5.288 ; +; A3 ; S6 ; 4.979 ; 5.001 ; 5.622 ; 5.664 ; +; A3 ; S7 ; 4.613 ; 4.639 ; 5.262 ; 5.269 ; +; A4 ; C8 ; 4.431 ; 4.454 ; 5.030 ; 5.073 ; +; A4 ; S4 ; 4.034 ; 4.062 ; 4.632 ; 4.642 ; +; A4 ; S5 ; 4.476 ; 4.533 ; 5.075 ; 5.132 ; +; A4 ; S6 ; 4.649 ; 4.684 ; 5.302 ; 5.319 ; +; A4 ; S7 ; 4.562 ; 4.580 ; 5.202 ; 5.220 ; +; A5 ; C8 ; 3.980 ; 4.008 ; 4.566 ; 4.587 ; +; A5 ; S5 ; 4.025 ; 4.082 ; 4.611 ; 4.668 ; +; A5 ; S6 ; 4.196 ; 4.231 ; 4.816 ; 4.833 ; +; A5 ; S7 ; 4.109 ; 4.127 ; 4.716 ; 4.734 ; +; A6 ; C8 ; 3.842 ; 3.849 ; 4.394 ; 4.420 ; +; A6 ; S5 ; 4.113 ; 4.162 ; 4.665 ; 4.714 ; +; A6 ; S6 ; 4.270 ; 4.299 ; 4.822 ; 4.851 ; +; A6 ; S7 ; 3.959 ; 3.977 ; 4.511 ; 4.529 ; +; A7 ; C8 ; 3.912 ; ; ; 4.502 ; +; A7 ; S5 ; 4.183 ; 4.232 ; 4.796 ; 4.838 ; +; A7 ; S6 ; 4.342 ; 4.369 ; 4.956 ; 4.976 ; +; A7 ; S7 ; 4.179 ; 4.197 ; 4.778 ; 4.796 ; +; B0 ; C8 ; 5.516 ; 5.539 ; 6.135 ; 6.158 ; +; B0 ; S0 ; 4.112 ; 4.148 ; 4.732 ; 4.751 ; +; B0 ; S1 ; 4.372 ; 4.401 ; 4.991 ; 5.020 ; +; B0 ; S2 ; 4.181 ; 4.209 ; 4.800 ; 4.828 ; +; B0 ; S3 ; 4.348 ; 4.351 ; 4.967 ; 4.970 ; +; B0 ; S4 ; 5.119 ; 5.140 ; 5.738 ; 5.759 ; +; B0 ; S5 ; 5.177 ; 5.232 ; 5.796 ; 5.851 ; +; B0 ; S6 ; 5.570 ; 5.592 ; 6.189 ; 6.211 ; +; B0 ; S7 ; 5.204 ; 5.230 ; 5.823 ; 5.849 ; +; B1 ; C8 ; 5.220 ; 5.243 ; 5.785 ; 5.808 ; +; B1 ; S1 ; 4.076 ; 4.105 ; 4.641 ; 4.670 ; +; B1 ; S2 ; 3.885 ; 3.913 ; 4.450 ; 4.477 ; +; B1 ; S3 ; 4.052 ; 4.055 ; 4.617 ; 4.620 ; +; B1 ; S4 ; 4.823 ; 4.844 ; 5.388 ; 5.409 ; +; B1 ; S5 ; 4.881 ; 4.936 ; 5.446 ; 5.501 ; +; B1 ; S6 ; 5.274 ; 5.296 ; 5.839 ; 5.861 ; +; B1 ; S7 ; 4.908 ; 4.934 ; 5.473 ; 5.499 ; +; B2 ; C8 ; 4.840 ; 4.863 ; 5.371 ; 5.394 ; +; B2 ; S1 ; 4.081 ; 4.099 ; 4.612 ; 4.630 ; +; B2 ; S2 ; 3.693 ; 3.696 ; 4.255 ; 4.258 ; +; B2 ; S3 ; 3.672 ; 3.675 ; 4.203 ; 4.206 ; +; B2 ; S4 ; 4.443 ; 4.464 ; 4.974 ; 4.995 ; +; B2 ; S5 ; 4.501 ; 4.556 ; 5.032 ; 5.087 ; +; B2 ; S6 ; 4.894 ; 4.916 ; 5.425 ; 5.447 ; +; B2 ; S7 ; 4.528 ; 4.554 ; 5.059 ; 5.085 ; +; B3 ; C8 ; 4.887 ; 4.910 ; 5.527 ; 5.570 ; +; B3 ; S1 ; 4.128 ; 4.146 ; 4.703 ; 4.741 ; +; B3 ; S2 ; 3.935 ; 3.934 ; 4.509 ; 4.527 ; +; B3 ; S3 ; 3.714 ; 3.738 ; 4.317 ; 4.287 ; +; B3 ; S4 ; 4.490 ; 4.511 ; 5.123 ; 5.137 ; +; B3 ; S5 ; 4.548 ; 4.603 ; 5.201 ; 5.254 ; +; B3 ; S6 ; 4.941 ; 4.963 ; 5.588 ; 5.630 ; +; B3 ; S7 ; 4.575 ; 4.601 ; 5.228 ; 5.235 ; +; B4 ; C8 ; 4.397 ; 4.433 ; 5.019 ; 5.051 ; +; B4 ; S4 ; 3.958 ; 3.974 ; 4.521 ; 4.557 ; +; B4 ; S5 ; 4.442 ; 4.499 ; 5.064 ; 5.121 ; +; B4 ; S6 ; 4.620 ; 4.655 ; 5.268 ; 5.285 ; +; B4 ; S7 ; 4.533 ; 4.551 ; 5.168 ; 5.186 ; +; B5 ; C8 ; 3.910 ; 3.946 ; 4.464 ; 4.482 ; +; B5 ; S5 ; 3.955 ; 4.012 ; 4.509 ; 4.566 ; +; B5 ; S6 ; 4.131 ; 4.166 ; 4.712 ; 4.729 ; +; B5 ; S7 ; 4.044 ; 4.062 ; 4.612 ; 4.630 ; +; B6 ; C8 ; 3.772 ; 3.788 ; 4.337 ; 4.351 ; +; B6 ; S5 ; 4.043 ; 4.092 ; 4.608 ; 4.657 ; +; B6 ; S6 ; 4.177 ; 4.212 ; 4.743 ; 4.778 ; +; B6 ; S7 ; 3.869 ; 3.887 ; 4.437 ; 4.448 ; +; B7 ; C8 ; 3.577 ; ; ; 4.118 ; +; B7 ; S5 ; 3.848 ; 3.897 ; 4.412 ; 4.454 ; +; B7 ; S6 ; 4.007 ; 4.034 ; 4.572 ; 4.592 ; +; B7 ; S7 ; 3.672 ; 3.698 ; 4.225 ; 4.233 ; ++------------+-------------+-------+-------+-------+-------+ + + +--------------------------------------------- +; Fast 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++--------------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+--------+--------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+--------+--------+--------+ +; A0 ; C8 ; 10.441 ; 10.405 ; 11.054 ; 11.018 ; +; A0 ; S0 ; 7.027 ; 7.017 ; 7.453 ; 7.475 ; +; A0 ; S1 ; 8.453 ; 8.437 ; 9.020 ; 9.036 ; +; A0 ; S2 ; 8.134 ; 8.114 ; 8.700 ; 8.712 ; +; A0 ; S3 ; 7.702 ; 7.684 ; 8.233 ; 8.247 ; +; A0 ; S4 ; 9.130 ; 9.117 ; 9.719 ; 9.697 ; +; A0 ; S5 ; 11.086 ; 11.015 ; 11.699 ; 11.628 ; +; A0 ; S6 ; 11.658 ; 11.688 ; 12.271 ; 12.301 ; +; A0 ; S7 ; 11.891 ; 11.896 ; 12.504 ; 12.509 ; +; A1 ; C8 ; 9.958 ; 9.922 ; 10.508 ; 10.472 ; +; A1 ; S1 ; 7.924 ; 7.940 ; 8.474 ; 8.490 ; +; A1 ; S2 ; 7.604 ; 7.616 ; 8.154 ; 8.166 ; +; A1 ; S3 ; 7.174 ; 7.149 ; 7.687 ; 7.701 ; +; A1 ; S4 ; 8.623 ; 8.601 ; 9.173 ; 9.151 ; +; A1 ; S5 ; 10.603 ; 10.532 ; 11.153 ; 11.082 ; +; A1 ; S6 ; 11.175 ; 11.205 ; 11.725 ; 11.755 ; +; A1 ; S7 ; 11.408 ; 11.413 ; 11.958 ; 11.963 ; +; A2 ; C8 ; 9.640 ; 9.604 ; 10.223 ; 10.187 ; +; A2 ; S1 ; 7.703 ; 7.687 ; 8.189 ; 8.205 ; +; A2 ; S2 ; 7.384 ; 7.364 ; 7.869 ; 7.881 ; +; A2 ; S3 ; 6.952 ; 6.934 ; 7.402 ; 7.416 ; +; A2 ; S4 ; 8.380 ; 8.367 ; 8.888 ; 8.866 ; +; A2 ; S5 ; 10.285 ; 10.214 ; 10.868 ; 10.797 ; +; A2 ; S6 ; 10.857 ; 10.887 ; 11.440 ; 11.470 ; +; A2 ; S7 ; 11.090 ; 11.095 ; 11.673 ; 11.678 ; +; A3 ; C8 ; 9.088 ; 9.109 ; 9.700 ; 9.664 ; +; A3 ; S1 ; 7.212 ; 7.196 ; 7.666 ; 7.682 ; +; A3 ; S2 ; 6.893 ; 6.873 ; 7.346 ; 7.358 ; +; A3 ; S3 ; 6.471 ; 6.487 ; 6.899 ; 6.871 ; +; A3 ; S4 ; 7.889 ; 7.876 ; 8.365 ; 8.343 ; +; A3 ; S5 ; 9.790 ; 9.717 ; 10.345 ; 10.274 ; +; A3 ; S6 ; 10.362 ; 10.392 ; 10.917 ; 10.947 ; +; A3 ; S7 ; 10.595 ; 10.600 ; 11.150 ; 11.155 ; +; A4 ; C8 ; 8.179 ; 8.200 ; 8.800 ; 8.764 ; +; A4 ; S4 ; 6.991 ; 7.002 ; 7.452 ; 7.460 ; +; A4 ; S5 ; 8.881 ; 8.808 ; 9.445 ; 9.374 ; +; A4 ; S6 ; 9.453 ; 9.483 ; 10.017 ; 10.047 ; +; A4 ; S7 ; 9.686 ; 9.691 ; 10.250 ; 10.255 ; +; A5 ; C8 ; 7.155 ; 7.176 ; 7.657 ; 7.621 ; +; A5 ; S5 ; 7.857 ; 7.784 ; 8.302 ; 8.231 ; +; A5 ; S6 ; 8.429 ; 8.459 ; 8.874 ; 8.904 ; +; A5 ; S7 ; 8.662 ; 8.667 ; 9.107 ; 9.112 ; +; A6 ; C8 ; 6.719 ; 6.591 ; 6.999 ; 7.152 ; +; A6 ; S5 ; 7.357 ; 7.293 ; 7.833 ; 7.760 ; +; A6 ; S6 ; 7.930 ; 7.928 ; 8.405 ; 8.435 ; +; A6 ; S7 ; 8.131 ; 8.104 ; 8.638 ; 8.643 ; +; A7 ; C8 ; 6.742 ; ; ; 7.216 ; +; A7 ; S5 ; 7.380 ; 7.316 ; 7.897 ; 7.824 ; +; A7 ; S6 ; 7.953 ; 7.951 ; 8.469 ; 8.499 ; +; A7 ; S7 ; 8.154 ; 8.127 ; 8.702 ; 8.707 ; +; B0 ; C8 ; 10.597 ; 10.561 ; 11.180 ; 11.144 ; +; B0 ; S0 ; 7.156 ; 7.176 ; 7.628 ; 7.634 ; +; B0 ; S1 ; 8.563 ; 8.579 ; 9.146 ; 9.162 ; +; B0 ; S2 ; 8.243 ; 8.255 ; 8.826 ; 8.838 ; +; B0 ; S3 ; 7.813 ; 7.788 ; 8.359 ; 8.373 ; +; B0 ; S4 ; 9.262 ; 9.240 ; 9.845 ; 9.823 ; +; B0 ; S5 ; 11.242 ; 11.171 ; 11.825 ; 11.754 ; +; B0 ; S6 ; 11.814 ; 11.844 ; 12.397 ; 12.427 ; +; B0 ; S7 ; 12.047 ; 12.052 ; 12.630 ; 12.635 ; +; B1 ; C8 ; 9.937 ; 9.901 ; 10.495 ; 10.459 ; +; B1 ; S1 ; 7.946 ; 7.930 ; 8.461 ; 8.477 ; +; B1 ; S2 ; 7.627 ; 7.607 ; 8.141 ; 8.153 ; +; B1 ; S3 ; 7.195 ; 7.177 ; 7.674 ; 7.688 ; +; B1 ; S4 ; 8.623 ; 8.610 ; 9.160 ; 9.138 ; +; B1 ; S5 ; 10.582 ; 10.511 ; 11.140 ; 11.069 ; +; B1 ; S6 ; 11.154 ; 11.184 ; 11.712 ; 11.742 ; +; B1 ; S7 ; 11.387 ; 11.392 ; 11.945 ; 11.950 ; +; B2 ; C8 ; 9.178 ; 9.199 ; 9.847 ; 9.811 ; +; B2 ; S1 ; 7.302 ; 7.286 ; 7.813 ; 7.829 ; +; B2 ; S2 ; 6.983 ; 6.963 ; 7.493 ; 7.505 ; +; B2 ; S3 ; 6.551 ; 6.533 ; 7.026 ; 7.040 ; +; B2 ; S4 ; 7.979 ; 7.966 ; 8.512 ; 8.490 ; +; B2 ; S5 ; 9.880 ; 9.807 ; 10.492 ; 10.421 ; +; B2 ; S6 ; 10.452 ; 10.482 ; 11.064 ; 11.094 ; +; B2 ; S7 ; 10.685 ; 10.690 ; 11.297 ; 11.302 ; +; B3 ; C8 ; 9.047 ; 9.068 ; 9.678 ; 9.642 ; +; B3 ; S1 ; 7.171 ; 7.155 ; 7.644 ; 7.660 ; +; B3 ; S2 ; 6.852 ; 6.832 ; 7.324 ; 7.336 ; +; B3 ; S3 ; 6.429 ; 6.448 ; 6.889 ; 6.851 ; +; B3 ; S4 ; 7.848 ; 7.835 ; 8.343 ; 8.321 ; +; B3 ; S5 ; 9.749 ; 9.676 ; 10.323 ; 10.252 ; +; B3 ; S6 ; 10.321 ; 10.351 ; 10.895 ; 10.925 ; +; B3 ; S7 ; 10.554 ; 10.559 ; 11.128 ; 11.133 ; +; B4 ; C8 ; 7.986 ; 8.007 ; 8.566 ; 8.530 ; +; B4 ; S4 ; 6.786 ; 6.771 ; 7.188 ; 7.205 ; +; B4 ; S5 ; 8.688 ; 8.615 ; 9.211 ; 9.140 ; +; B4 ; S6 ; 9.260 ; 9.290 ; 9.783 ; 9.813 ; +; B4 ; S7 ; 9.493 ; 9.498 ; 10.016 ; 10.021 ; +; B5 ; C8 ; 7.085 ; 7.106 ; 7.604 ; 7.568 ; +; B5 ; S5 ; 7.787 ; 7.714 ; 8.249 ; 8.178 ; +; B5 ; S6 ; 8.359 ; 8.389 ; 8.821 ; 8.851 ; +; B5 ; S7 ; 8.592 ; 8.597 ; 9.054 ; 9.059 ; +; B6 ; C8 ; 6.599 ; 6.516 ; 6.955 ; 7.060 ; +; B6 ; S5 ; 7.237 ; 7.173 ; 7.741 ; 7.668 ; +; B6 ; S6 ; 7.810 ; 7.808 ; 8.313 ; 8.343 ; +; B6 ; S7 ; 8.011 ; 8.007 ; 8.546 ; 8.551 ; +; B7 ; C8 ; 6.163 ; ; ; 6.594 ; +; B7 ; S5 ; 6.801 ; 6.737 ; 7.275 ; 7.202 ; +; B7 ; S6 ; 7.374 ; 7.372 ; 7.847 ; 7.877 ; +; B7 ; S7 ; 7.575 ; 7.548 ; 8.080 ; 8.085 ; ++------------+-------------+--------+--------+--------+--------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C8 ; 5.504 ; 5.527 ; 6.095 ; 6.118 ; +; A0 ; S0 ; 4.100 ; 4.123 ; 4.689 ; 4.732 ; +; A0 ; S1 ; 4.360 ; 4.389 ; 4.951 ; 4.980 ; +; A0 ; S2 ; 4.169 ; 4.197 ; 4.760 ; 4.788 ; +; A0 ; S3 ; 4.336 ; 4.339 ; 4.927 ; 4.930 ; +; A0 ; S4 ; 5.107 ; 5.128 ; 5.698 ; 5.719 ; +; A0 ; S5 ; 5.165 ; 5.220 ; 5.756 ; 5.811 ; +; A0 ; S6 ; 5.558 ; 5.580 ; 6.149 ; 6.171 ; +; A0 ; S7 ; 5.192 ; 5.218 ; 5.783 ; 5.809 ; +; A1 ; C8 ; 5.182 ; 5.205 ; 5.741 ; 5.764 ; +; A1 ; S1 ; 4.038 ; 4.067 ; 4.597 ; 4.626 ; +; A1 ; S2 ; 3.847 ; 3.875 ; 4.406 ; 4.434 ; +; A1 ; S3 ; 4.014 ; 4.017 ; 4.573 ; 4.576 ; +; A1 ; S4 ; 4.785 ; 4.806 ; 5.344 ; 5.365 ; +; A1 ; S5 ; 4.843 ; 4.898 ; 5.402 ; 5.457 ; +; A1 ; S6 ; 5.236 ; 5.258 ; 5.795 ; 5.817 ; +; A1 ; S7 ; 4.870 ; 4.896 ; 5.429 ; 5.455 ; +; A2 ; C8 ; 5.142 ; 5.165 ; 5.742 ; 5.765 ; +; A2 ; S1 ; 4.383 ; 4.401 ; 4.983 ; 5.001 ; +; A2 ; S2 ; 3.956 ; 3.959 ; 4.555 ; 4.558 ; +; A2 ; S3 ; 3.974 ; 3.977 ; 4.574 ; 4.577 ; +; A2 ; S4 ; 4.745 ; 4.766 ; 5.345 ; 5.366 ; +; A2 ; S5 ; 4.803 ; 4.858 ; 5.403 ; 5.458 ; +; A2 ; S6 ; 5.196 ; 5.218 ; 5.796 ; 5.818 ; +; A2 ; S7 ; 4.830 ; 4.856 ; 5.430 ; 5.456 ; +; A3 ; C8 ; 4.925 ; 4.948 ; 5.561 ; 5.604 ; +; A3 ; S1 ; 4.166 ; 4.184 ; 4.737 ; 4.775 ; +; A3 ; S2 ; 3.973 ; 3.972 ; 4.543 ; 4.561 ; +; A3 ; S3 ; 3.749 ; 3.774 ; 4.341 ; 4.317 ; +; A3 ; S4 ; 4.528 ; 4.549 ; 5.157 ; 5.171 ; +; A3 ; S5 ; 4.586 ; 4.641 ; 5.235 ; 5.288 ; +; A3 ; S6 ; 4.979 ; 5.001 ; 5.622 ; 5.664 ; +; A3 ; S7 ; 4.613 ; 4.639 ; 5.262 ; 5.269 ; +; A4 ; C8 ; 4.431 ; 4.454 ; 5.030 ; 5.073 ; +; A4 ; S4 ; 4.034 ; 4.062 ; 4.632 ; 4.642 ; +; A4 ; S5 ; 4.476 ; 4.533 ; 5.075 ; 5.132 ; +; A4 ; S6 ; 4.649 ; 4.684 ; 5.302 ; 5.319 ; +; A4 ; S7 ; 4.562 ; 4.580 ; 5.202 ; 5.220 ; +; A5 ; C8 ; 3.980 ; 4.008 ; 4.566 ; 4.587 ; +; A5 ; S5 ; 4.025 ; 4.082 ; 4.611 ; 4.668 ; +; A5 ; S6 ; 4.196 ; 4.231 ; 4.816 ; 4.833 ; +; A5 ; S7 ; 4.109 ; 4.127 ; 4.716 ; 4.734 ; +; A6 ; C8 ; 3.842 ; 3.849 ; 4.394 ; 4.420 ; +; A6 ; S5 ; 4.113 ; 4.162 ; 4.665 ; 4.714 ; +; A6 ; S6 ; 4.270 ; 4.299 ; 4.822 ; 4.851 ; +; A6 ; S7 ; 3.959 ; 3.977 ; 4.511 ; 4.529 ; +; A7 ; C8 ; 3.912 ; ; ; 4.502 ; +; A7 ; S5 ; 4.183 ; 4.232 ; 4.796 ; 4.838 ; +; A7 ; S6 ; 4.342 ; 4.369 ; 4.956 ; 4.976 ; +; A7 ; S7 ; 4.179 ; 4.197 ; 4.778 ; 4.796 ; +; B0 ; C8 ; 5.516 ; 5.539 ; 6.135 ; 6.158 ; +; B0 ; S0 ; 4.112 ; 4.148 ; 4.732 ; 4.751 ; +; B0 ; S1 ; 4.372 ; 4.401 ; 4.991 ; 5.020 ; +; B0 ; S2 ; 4.181 ; 4.209 ; 4.800 ; 4.828 ; +; B0 ; S3 ; 4.348 ; 4.351 ; 4.967 ; 4.970 ; +; B0 ; S4 ; 5.119 ; 5.140 ; 5.738 ; 5.759 ; +; B0 ; S5 ; 5.177 ; 5.232 ; 5.796 ; 5.851 ; +; B0 ; S6 ; 5.570 ; 5.592 ; 6.189 ; 6.211 ; +; B0 ; S7 ; 5.204 ; 5.230 ; 5.823 ; 5.849 ; +; B1 ; C8 ; 5.220 ; 5.243 ; 5.785 ; 5.808 ; +; B1 ; S1 ; 4.076 ; 4.105 ; 4.641 ; 4.670 ; +; B1 ; S2 ; 3.885 ; 3.913 ; 4.450 ; 4.477 ; +; B1 ; S3 ; 4.052 ; 4.055 ; 4.617 ; 4.620 ; +; B1 ; S4 ; 4.823 ; 4.844 ; 5.388 ; 5.409 ; +; B1 ; S5 ; 4.881 ; 4.936 ; 5.446 ; 5.501 ; +; B1 ; S6 ; 5.274 ; 5.296 ; 5.839 ; 5.861 ; +; B1 ; S7 ; 4.908 ; 4.934 ; 5.473 ; 5.499 ; +; B2 ; C8 ; 4.840 ; 4.863 ; 5.371 ; 5.394 ; +; B2 ; S1 ; 4.081 ; 4.099 ; 4.612 ; 4.630 ; +; B2 ; S2 ; 3.693 ; 3.696 ; 4.255 ; 4.258 ; +; B2 ; S3 ; 3.672 ; 3.675 ; 4.203 ; 4.206 ; +; B2 ; S4 ; 4.443 ; 4.464 ; 4.974 ; 4.995 ; +; B2 ; S5 ; 4.501 ; 4.556 ; 5.032 ; 5.087 ; +; B2 ; S6 ; 4.894 ; 4.916 ; 5.425 ; 5.447 ; +; B2 ; S7 ; 4.528 ; 4.554 ; 5.059 ; 5.085 ; +; B3 ; C8 ; 4.887 ; 4.910 ; 5.527 ; 5.570 ; +; B3 ; S1 ; 4.128 ; 4.146 ; 4.703 ; 4.741 ; +; B3 ; S2 ; 3.935 ; 3.934 ; 4.509 ; 4.527 ; +; B3 ; S3 ; 3.714 ; 3.738 ; 4.317 ; 4.287 ; +; B3 ; S4 ; 4.490 ; 4.511 ; 5.123 ; 5.137 ; +; B3 ; S5 ; 4.548 ; 4.603 ; 5.201 ; 5.254 ; +; B3 ; S6 ; 4.941 ; 4.963 ; 5.588 ; 5.630 ; +; B3 ; S7 ; 4.575 ; 4.601 ; 5.228 ; 5.235 ; +; B4 ; C8 ; 4.397 ; 4.433 ; 5.019 ; 5.051 ; +; B4 ; S4 ; 3.958 ; 3.974 ; 4.521 ; 4.557 ; +; B4 ; S5 ; 4.442 ; 4.499 ; 5.064 ; 5.121 ; +; B4 ; S6 ; 4.620 ; 4.655 ; 5.268 ; 5.285 ; +; B4 ; S7 ; 4.533 ; 4.551 ; 5.168 ; 5.186 ; +; B5 ; C8 ; 3.910 ; 3.946 ; 4.464 ; 4.482 ; +; B5 ; S5 ; 3.955 ; 4.012 ; 4.509 ; 4.566 ; +; B5 ; S6 ; 4.131 ; 4.166 ; 4.712 ; 4.729 ; +; B5 ; S7 ; 4.044 ; 4.062 ; 4.612 ; 4.630 ; +; B6 ; C8 ; 3.772 ; 3.788 ; 4.337 ; 4.351 ; +; B6 ; S5 ; 4.043 ; 4.092 ; 4.608 ; 4.657 ; +; B6 ; S6 ; 4.177 ; 4.212 ; 4.743 ; 4.778 ; +; B6 ; S7 ; 3.869 ; 3.887 ; 4.437 ; 4.448 ; +; B7 ; C8 ; 3.577 ; ; ; 4.118 ; +; B7 ; S5 ; 3.848 ; 3.897 ; 4.412 ; 4.454 ; +; B7 ; S6 ; 4.007 ; 4.034 ; 4.572 ; 4.592 ; +; B7 ; S7 ; 3.672 ; 3.698 ; 4.225 ; 4.233 ; ++------------+-------------+-------+-------+-------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; S3 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S2 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S1 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S0 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S7 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S6 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S5 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S4 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; C8 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; B3 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A3 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A2 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B2 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B0 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A0 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A1 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B1 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B7 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A4 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B4 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A5 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B5 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A6 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B6 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A7 ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; S3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S7 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S6 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S5 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.08e-06 V ; 2.36 V ; -0.0113 V ; 0.122 V ; 0.022 V ; 4.5e-10 s ; 4.45e-10 s ; Yes ; Yes ; 2.32 V ; 1.08e-06 V ; 2.36 V ; -0.0113 V ; 0.122 V ; 0.022 V ; 4.5e-10 s ; 4.45e-10 s ; Yes ; Yes ; +; S4 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; C8 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.68e-07 V ; 2.35 V ; -0.0132 V ; 0.2 V ; 0.027 V ; 5.26e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 5.68e-07 V ; 2.35 V ; -0.0132 V ; 0.2 V ; 0.027 V ; 5.26e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.36e-07 V ; 2.35 V ; -0.00444 V ; 0.18 V ; 0.019 V ; 7.23e-10 s ; 9.82e-10 s ; Yes ; Yes ; 2.32 V ; 9.36e-07 V ; 2.35 V ; -0.00444 V ; 0.18 V ; 0.019 V ; 7.23e-10 s ; 9.82e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; S3 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S2 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S1 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S0 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S7 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S6 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S5 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.11e-08 V ; 2.73 V ; -0.0566 V ; 0.191 V ; 0.12 V ; 2.69e-10 s ; 2.76e-10 s ; Yes ; Yes ; 2.62 V ; 4.11e-08 V ; 2.73 V ; -0.0566 V ; 0.191 V ; 0.12 V ; 2.69e-10 s ; 2.76e-10 s ; Yes ; Yes ; +; S4 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; C8 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.72 V ; -0.0747 V ; 0.28 V ; 0.169 V ; 3.1e-10 s ; 3.01e-10 s ; No ; Yes ; 2.62 V ; 2.22e-08 V ; 2.72 V ; -0.0747 V ; 0.28 V ; 0.169 V ; 3.1e-10 s ; 3.01e-10 s ; No ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.53e-08 V ; 2.7 V ; -0.0212 V ; 0.204 V ; 0.049 V ; 4.85e-10 s ; 6.73e-10 s ; No ; Yes ; 2.62 V ; 3.53e-08 V ; 2.7 V ; -0.0212 V ; 0.204 V ; 0.049 V ; 4.85e-10 s ; 6.73e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 16 ; 16 ; +; Unconstrained Input Port Paths ; 100 ; 100 ; +; Unconstrained Output Ports ; 9 ; 9 ; +; Unconstrained Output Port Paths ; 100 ; 100 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit TimeQuest Timing Analyzer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Mon Sep 9 21:05:57 2019 +Info: Command: quartus_sta BCD_adder_1D_G -c BCD_adder_1D_G +Info: qsta_default_script.tcl version: #1 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'BCD_adder_1D_G.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 383 megabytes + Info: Processing ended: Mon Sep 9 21:06:00 2019 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_1D_G.sta.summary b/CH5/CH5-3/output_files/BCD_adder_1D_G.sta.summary new file mode 100644 index 00000000..33f74363 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_1D_G.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.asm.rpt b/CH5/CH5-3/output_files/BCD_adder_7483.asm.rpt new file mode 100644 index 00000000..899fd93e --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.asm.rpt @@ -0,0 +1,116 @@ +Assembler report for BCD_adder_7483 +Mon Aug 26 23:13:30 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: BCD_adder_7483.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon Aug 26 23:13:30 2019 ; +; Revision Name ; BCD_adder_7483 ; +; Top-level Entity Name ; BCD_adder_7483 ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Use configuration device ; Off ; Off ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Enable OCT_DONE ; Off ; Off ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++---------------------------+ +; Assembler Generated Files ; ++---------------------------+ +; File Name ; ++---------------------------+ +; BCD_adder_7483.sof ; ++---------------------------+ + + ++----------------------------------------------+ +; Assembler Device Options: BCD_adder_7483.sof ; ++----------------+-----------------------------+ +; Option ; Setting ; ++----------------+-----------------------------+ +; Device ; EP3C16F484C6 ; +; JTAG usercode ; 0x000C9D78 ; +; Checksum ; 0x000C9D78 ; ++----------------+-----------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit Assembler + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Mon Aug 26 23:13:27 2019 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 382 megabytes + Info: Processing ended: Mon Aug 26 23:13:30 2019 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.done b/CH5/CH5-3/output_files/BCD_adder_7483.done new file mode 100644 index 00000000..c9c26805 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.done @@ -0,0 +1 @@ +Mon Aug 26 23:13:46 2019 diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.eda.rpt b/CH5/CH5-3/output_files/BCD_adder_7483.eda.rpt new file mode 100644 index 00000000..ad4dbed0 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.eda.rpt @@ -0,0 +1,107 @@ +EDA Netlist Writer report for BCD_adder_7483 +Mon Aug 26 23:13:46 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Mon Aug 26 23:13:46 2019 ; +; Revision Name ; BCD_adder_7483 ; +; Top-level Entity Name ; BCD_adder_7483 ; +; Family ; Cyclone III ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+------------------------+ +; Tool Name ; ModelSim-Altera (VHDL) ; +; Generate netlist for functional simulation only ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+------------------------+ + + ++----------------------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++----------------------------------------------------------------------------------------------------+ +; Generated Files ; ++----------------------------------------------------------------------------------------------------+ +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_85c_slow.vho ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_0c_slow.vho ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_min_1200mv_0c_fast.vho ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_7483.vho ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_85c_vhd_slow.sdo ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_0c_vhd_slow.sdo ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_min_1200mv_0c_vhd_fast.sdo ; +; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_vhd.sdo ; ++----------------------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit EDA Netlist Writer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Mon Aug 26 23:13:44 2019 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 +Info (204019): Generated file BCD_adder_7483_6_1200mv_85c_slow.vho in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_7483_6_1200mv_0c_slow.vho in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_7483_min_1200mv_0c_fast.vho in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_7483.vho in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_7483_6_1200mv_85c_vhd_slow.sdo in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_7483_6_1200mv_0c_vhd_slow.sdo in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_7483_min_1200mv_0c_vhd_fast.sdo in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file BCD_adder_7483_vhd.sdo in folder "/home/timmy/Git/Learn-VHDL/CH5/CH5-3/simulation/modelsim/" for EDA simulation tool +Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 348 megabytes + Info: Processing ended: Mon Aug 26 23:13:46 2019 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.fit.rpt b/CH5/CH5-3/output_files/BCD_adder_7483.fit.rpt new file mode 100644 index 00000000..1ec56c6c --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.fit.rpt @@ -0,0 +1,1264 @@ +Fitter report for BCD_adder_7483 +Mon Aug 26 23:13:19 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. I/O Assignment Warnings + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Non-Global High Fan-Out Signals + 21. Routing Usage Summary + 22. LAB Logic Elements + 23. LAB Signals Sourced + 24. LAB Signals Sourced Out + 25. LAB Distinct Inputs + 26. I/O Rules Summary + 27. I/O Rules Details + 28. I/O Rules Matrix + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+--------------------------------------------+ +; Fitter Status ; Successful - Mon Aug 26 23:13:19 2019 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_7483 ; +; Top-level Entity Name ; BCD_adder_7483 ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Total logic elements ; 12 / 15,408 ( < 1 % ) ; +; Total combinational functions ; 12 / 15,408 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 13 / 347 ( 4 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 516,096 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+--------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP3C16F484C6 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Device I/O Standard ; 2.5 V ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Off ; Off ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; RAM Bit Reservation (Cyclone III) ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-------------------------------------------------+ +; I/O Assignment Warnings ; ++----------+--------------------------------------+ +; Pin Name ; Reason ; ++----------+--------------------------------------+ +; S0 ; Missing drive strength and slew rate ; +; S1 ; Missing drive strength and slew rate ; +; S2 ; Missing drive strength and slew rate ; +; S3 ; Missing drive strength and slew rate ; +; C4 ; Missing drive strength and slew rate ; ++----------+--------------------------------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 49 ) ; 0.00 % ( 0 / 49 ) ; 0.00 % ( 0 / 49 ) ; +; -- Achieved ; 0.00 % ( 0 / 49 ) ; 0.00 % ( 0 / 49 ) ; 0.00 % ( 0 / 49 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 39 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_7483.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 12 / 15,408 ( < 1 % ) ; +; -- Combinational with no register ; 12 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 7 ; +; -- 3 input functions ; 3 ; +; -- <=2 input functions ; 2 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 12 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 17,068 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; +; -- I/O registers ; 0 / 1,660 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 1 / 963 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 13 / 347 ( 4 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; Global signals ; 0 ; +; M9Ks ; 0 / 56 ( 0 % ) ; +; Total block memory bits ; 0 / 516,096 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 516,096 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out ; 6 ; +; Highest non-global fan-out ; 6 ; +; Total fan-out ; 64 ; +; Average fan-out ; 1.33 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 12 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % ) ; +; -- Combinational with no register ; 12 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 7 ; 0 ; +; -- 3 input functions ; 3 ; 0 ; +; -- <=2 input functions ; 2 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 12 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 15408 ( 0 % ) ; 0 / 15408 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 1 / 963 ( < 1 % ) ; 0 / 963 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 13 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; 0 / 112 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 59 ; 5 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 8 ; 0 ; +; -- Output Ports ; 5 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; A0 ; D2 ; 1 ; 0 ; 25 ; 0 ; 6 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; A1 ; E4 ; 1 ; 0 ; 26 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; A2 ; E3 ; 1 ; 0 ; 26 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; A3 ; H7 ; 1 ; 0 ; 25 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; B0 ; J7 ; 1 ; 0 ; 22 ; 14 ; 6 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; B1 ; G5 ; 1 ; 0 ; 27 ; 21 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; B2 ; G4 ; 1 ; 0 ; 23 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; B3 ; H6 ; 1 ; 0 ; 25 ; 21 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; C4 ; B1 ; 1 ; 0 ; 27 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; S0 ; B2 ; 1 ; 0 ; 27 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; S1 ; C2 ; 1 ; 0 ; 26 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; S2 ; C1 ; 1 ; 0 ; 26 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; S3 ; E1 ; 1 ; 0 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; E4 ; DIFFIO_L2p, nRESET ; Use as regular IO ; A1 ; Dual Purpose Pin ; +; D1 ; DIFFIO_L4n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; E2 ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; K6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; K2 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; K1 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; K5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; L3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; M18 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; M17 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; L18 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; L17 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; K20 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; K22 ; DIFFIO_R16n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 17 / 33 ( 52 % ) ; 2.5V ; -- ; +; 2 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 46 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 41 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 46 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 1 / 43 ( 2 % ) ; 2.5V ; -- ; +; 7 ; 0 / 47 ( 0 % ) ; 2.5V ; -- ; +; 8 ; 0 / 43 ( 0 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A3 ; 354 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 350 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 345 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 336 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 334 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 332 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 328 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 326 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 321 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A12 ; 319 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 314 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 312 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 307 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 298 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 296 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 291 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 290 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 284 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA3 ; 102 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA4 ; 106 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA5 ; 108 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA7 ; 115 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 123 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 134 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA12 ; 136 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA13 ; 138 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; 140 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 145 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 149 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 151 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; 163 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; 164 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 169 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 179 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 178 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB3 ; 103 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 107 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 109 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB7 ; 116 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 135 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AB12 ; 137 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AB13 ; 139 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 141 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 146 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 150 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 152 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 162 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 165 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 170 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 2 ; 1 ; C4 ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; B2 ; 1 ; 1 ; S0 ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; B3 ; 355 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 351 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 346 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 337 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 335 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 333 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; 329 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B10 ; 327 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 322 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B12 ; 320 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 315 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; 313 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 308 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; 299 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 297 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; 292 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B19 ; 289 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 285 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 269 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 268 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 7 ; 1 ; S2 ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; C2 ; 6 ; 1 ; S1 ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; C3 ; 358 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 359 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 349 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 340 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 339 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C10 ; 330 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; 309 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C15 ; 300 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 286 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C19 ; 282 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 270 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 267 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 266 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 9 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; D2 ; 8 ; 1 ; A0 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D6 ; 356 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D10 ; 324 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D13 ; 310 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D15 ; 293 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D17 ; 281 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D19 ; 283 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D20 ; 271 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D21 ; 261 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D22 ; 260 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 14 ; 1 ; S3 ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E2 ; 13 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; E3 ; 5 ; 1 ; A2 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E4 ; 4 ; 1 ; A1 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E5 ; 363 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E6 ; 362 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; 357 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E9 ; 338 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; E10 ; 325 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 317 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 316 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 311 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 301 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 294 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 275 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E18 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E21 ; 256 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 255 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 16 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F7 ; 360 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 352 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 347 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 348 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 318 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; 302 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F13 ; 306 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F14 ; 279 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F15 ; 276 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 274 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 272 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F19 ; 263 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 262 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 251 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 250 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 39 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G2 ; 38 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G3 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 17 ; 1 ; B2 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; G5 ; 3 ; 1 ; B1 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; G6 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G7 ; 361 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; 353 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G9 ; 342 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G10 ; 341 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 331 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 305 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; 295 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G14 ; 280 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G15 ; 278 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 277 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 273 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; 264 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G21 ; 226 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G22 ; 225 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; H1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H5 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H6 ; 11 ; 1 ; B3 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; H7 ; 10 ; 1 ; A3 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; 344 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H10 ; 343 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H11 ; 323 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 304 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 303 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 288 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 287 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; 259 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H17 ; 265 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 257 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; H19 ; 254 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 253 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 246 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 245 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J3 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; J4 ; 24 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J6 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J7 ; 22 ; 1 ; B0 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J15 ; 238 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; 243 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J17 ; 258 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J18 ; 249 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J21 ; 242 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 241 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 31 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; K2 ; 30 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K5 ; 32 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; K6 ; 19 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K8 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; 236 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; 244 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K17 ; 247 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K18 ; 248 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 237 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; K20 ; 231 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; K21 ; 240 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 239 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L1 ; 35 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; L2 ; 34 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; L3 ; 37 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L5 ; 33 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; L6 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L7 ; 50 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L8 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; 233 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; 232 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L17 ; 230 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 229 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; L19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L21 ; 235 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L22 ; 234 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 45 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M3 ; 47 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 46 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 51 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M6 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M7 ; 65 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M8 ; 66 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; 195 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; 222 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M17 ; 228 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 227 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; M19 ; 221 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M20 ; 220 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 219 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 218 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 49 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 48 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N5 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; 64 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N7 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N8 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 189 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 196 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; 205 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N17 ; 214 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N18 ; 215 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 213 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 212 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 217 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 216 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 53 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 52 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 63 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P7 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P8 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; 180 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 192 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 193 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P17 ; 197 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P18 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P20 ; 208 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; P21 ; 211 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 210 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; 55 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 54 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R5 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R7 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R9 ; 88 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 90 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 97 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 98 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 153 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R16 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R17 ; 194 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R18 ; 203 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; 204 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R20 ; 200 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; 207 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R22 ; 206 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 41 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T2 ; 40 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T3 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; T4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T7 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T8 ; 89 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 91 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T10 ; 121 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T11 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 148 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T14 ; 160 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T15 ; 161 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T16 ; 171 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T17 ; 181 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T18 ; 182 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 224 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T22 ; 223 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; U1 ; 60 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; 94 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; 95 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U9 ; 112 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U10 ; 122 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U11 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U12 ; 147 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U13 ; 156 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U14 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U15 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U19 ; 188 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 187 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 202 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 201 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 62 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; 61 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V5 ; 93 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; 92 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V7 ; 105 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 113 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 119 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; V10 ; 120 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 142 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 154 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 157 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 158 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 168 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; V17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V18 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V21 ; 199 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 198 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W6 ; 104 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 110 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 114 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W10 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W13 ; 143 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 155 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; W15 ; 159 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W17 ; 166 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W19 ; 184 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 183 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 191 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; 190 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y2 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y3 ; 99 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 96 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; 101 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 111 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 117 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 144 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y17 ; 167 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 186 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 185 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------+--------------+ +; |BCD_adder_7483 ; 12 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 12 (1) ; 0 (0) ; 0 (0) ; |BCD_adder_7483 ; work ; +; |7483:inst1| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; |BCD_adder_7483|7483:inst1 ; work ; +; |7483:inst| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; |BCD_adder_7483|7483:inst ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; S0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S2 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S3 ; Output ; -- ; -- ; -- ; -- ; -- ; +; C4 ; Output ; -- ; -- ; -- ; -- ; -- ; +; A0 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; B0 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; A1 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; B1 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; A3 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; B3 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; A2 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; B2 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+------+ + + ++------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++------------------------+-------------------+---------+ +; A0 ; ; ; +; - 7483:inst|27~0 ; 0 ; 6 ; +; - 7483:inst|51~0 ; 0 ; 6 ; +; - 7483:inst1|45~0 ; 0 ; 6 ; +; - 7483:inst|51~1 ; 0 ; 6 ; +; - 7483:inst1|29~0 ; 0 ; 6 ; +; - 7483:inst1|51~0 ; 0 ; 6 ; +; B0 ; ; ; +; - 7483:inst|27~0 ; 1 ; 6 ; +; - 7483:inst|51~0 ; 1 ; 6 ; +; - 7483:inst1|45~0 ; 1 ; 6 ; +; - 7483:inst|51~1 ; 1 ; 6 ; +; - 7483:inst1|29~0 ; 1 ; 6 ; +; - 7483:inst1|51~0 ; 1 ; 6 ; +; A1 ; ; ; +; - 7483:inst|29~0 ; 1 ; 6 ; +; - 7483:inst|51~0 ; 1 ; 6 ; +; - 7483:inst|51~1 ; 1 ; 6 ; +; - 7483:inst1|51~0 ; 1 ; 6 ; +; B1 ; ; ; +; - 7483:inst|29~0 ; 0 ; 6 ; +; - 7483:inst|51~0 ; 0 ; 6 ; +; - 7483:inst|51~1 ; 0 ; 6 ; +; - 7483:inst1|51~0 ; 0 ; 6 ; +; A3 ; ; ; +; - inst6~0 ; 0 ; 6 ; +; - 7483:inst1|45~1 ; 0 ; 6 ; +; B3 ; ; ; +; - inst6~0 ; 0 ; 6 ; +; - 7483:inst1|45~1 ; 0 ; 6 ; +; A2 ; ; ; +; - 7483:inst|44~0 ; 1 ; 6 ; +; - 7483:inst|1~0 ; 1 ; 6 ; +; B2 ; ; ; +; - 7483:inst|44~0 ; 1 ; 6 ; +; - 7483:inst|1~0 ; 1 ; 6 ; ++------------------------+-------------------+---------+ + + ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++-----------------+---------------+ +; Name ; Fan-Out ; ++-----------------+---------------+ +; B0~input ; 6 ; +; A0~input ; 6 ; +; B1~input ; 4 ; +; A1~input ; 4 ; +; inst6~0 ; 3 ; +; B2~input ; 2 ; +; A2~input ; 2 ; +; B3~input ; 2 ; +; A3~input ; 2 ; +; 7483:inst|1~0 ; 2 ; +; 7483:inst1|45~0 ; 2 ; +; 7483:inst|44~0 ; 2 ; +; 7483:inst|29~0 ; 2 ; +; 7483:inst1|45~1 ; 1 ; +; 7483:inst1|44~0 ; 1 ; +; 7483:inst1|51~0 ; 1 ; +; 7483:inst1|29~0 ; 1 ; +; 7483:inst|51~1 ; 1 ; +; 7483:inst|51~0 ; 1 ; +; 7483:inst|27~0 ; 1 ; ++-----------------+---------------+ + + ++-----------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+-----------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+-----------------------+ +; Block interconnects ; 14 / 47,787 ( < 1 % ) ; +; C16 interconnects ; 0 / 1,804 ( 0 % ) ; +; C4 interconnects ; 9 / 31,272 ( < 1 % ) ; +; Direct links ; 1 / 47,787 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 7 / 15,408 ( < 1 % ) ; +; R24 interconnects ; 0 / 1,775 ( 0 % ) ; +; R4 interconnects ; 1 / 41,310 ( < 1 % ) ; ++-----------------------+-----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 12.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++---------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 12.00) ; Number of LABs (Total = 1) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 1) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 8.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 13 ; 0 ; 13 ; 0 ; 0 ; 13 ; 13 ; 0 ; 13 ; 13 ; 0 ; 5 ; 0 ; 0 ; 8 ; 0 ; 5 ; 8 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 13 ; 0 ; 13 ; 13 ; 0 ; 0 ; 13 ; 0 ; 0 ; 13 ; 8 ; 13 ; 13 ; 5 ; 13 ; 8 ; 5 ; 13 ; 13 ; 13 ; 8 ; 13 ; 13 ; 13 ; 13 ; 13 ; 0 ; 13 ; 13 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; S0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; C4 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device EP3C16F484C6 for design "BCD_adder_7483" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP3C40F484C6 is compatible + Info (176445): Device EP3C55F484C6 is compatible + Info (176445): Device EP3C80F484C6 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'BCD_adder_7483.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:04 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.32 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:04 +Info (144001): Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_7483.fit.smsg +Info: Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 535 megabytes + Info: Processing ended: Mon Aug 26 23:13:20 2019 + Info: Elapsed time: 00:00:21 + Info: Total CPU time (on all processors): 00:00:17 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/timmy/Git/Learn-VHDL/CH5/CH5-3/output_files/BCD_adder_7483.fit.smsg. + + diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.fit.smsg b/CH5/CH5-3/output_files/BCD_adder_7483.fit.smsg new file mode 100644 index 00000000..7121cbb1 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.fit.summary b/CH5/CH5-3/output_files/BCD_adder_7483.fit.summary new file mode 100644 index 00000000..f8a0830b --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon Aug 26 23:13:19 2019 +Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition +Revision Name : BCD_adder_7483 +Top-level Entity Name : BCD_adder_7483 +Family : Cyclone III +Device : EP3C16F484C6 +Timing Models : Final +Total logic elements : 12 / 15,408 ( < 1 % ) + Total combinational functions : 12 / 15,408 ( < 1 % ) + Dedicated logic registers : 0 / 15,408 ( 0 % ) +Total registers : 0 +Total pins : 13 / 347 ( 4 % ) +Total virtual pins : 0 +Total memory bits : 0 / 516,096 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.flow.rpt b/CH5/CH5-3/output_files/BCD_adder_7483.flow.rpt new file mode 100644 index 00000000..91353faa --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.flow.rpt @@ -0,0 +1,127 @@ +Flow report for BCD_adder_7483 +Mon Aug 26 23:13:46 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+--------------------------------------------+ +; Flow Status ; Successful - Mon Aug 26 23:13:46 2019 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_7483 ; +; Top-level Entity Name ; BCD_adder_7483 ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Total logic elements ; 12 / 15,408 ( < 1 % ) ; +; Total combinational functions ; 12 / 15,408 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 13 / 347 ( 4 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 516,096 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+--------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 08/26/2019 23:12:53 ; +; Main task ; Compilation ; +; Revision Name ; BCD_adder_7483 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 0.156683237327499 ; -- ; -- ; -- ; +; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+------------------------+---------------+-------------+----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:04 ; 1.0 ; 360 MB ; 00:00:03 ; +; Fitter ; 00:00:20 ; 1.0 ; 535 MB ; 00:00:16 ; +; Assembler ; 00:00:03 ; 1.0 ; 382 MB ; 00:00:03 ; +; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 383 MB ; 00:00:03 ; +; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 338 MB ; 00:00:02 ; +; Total ; 00:00:32 ; -- ; -- ; 00:00:27 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+-------------------+----------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+-------------------+----------------+------------+----------------+ +; Analysis & Synthesis ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; Fitter ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; Assembler ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; TimeQuest Timing Analyzer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; +; EDA Netlist Writer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16 ; x86_64 ; ++---------------------------+-------------------+----------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 +quartus_fit --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 +quartus_asm --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 +quartus_sta BCD_adder_7483 -c BCD_adder_7483 +quartus_eda --read_settings_files=off --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 + + + diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.jdi b/CH5/CH5-3/output_files/BCD_adder_7483.jdi new file mode 100644 index 00000000..2fa487a5 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.map.rpt b/CH5/CH5-3/output_files/BCD_adder_7483.map.rpt new file mode 100644 index 00000000..f5eec7a4 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.map.rpt @@ -0,0 +1,264 @@ +Analysis & Synthesis report for BCD_adder_7483 +Mon Aug 26 23:12:56 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Elapsed Time Per Partition + 10. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+--------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Aug 26 23:12:56 2019 ; +; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_7483 ; +; Top-level Entity Name ; BCD_adder_7483 ; +; Family ; Cyclone III ; +; Total logic elements ; 12 ; +; Total combinational functions ; 12 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 13 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+--------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP3C16F484C6 ; ; +; Top-level entity name ; BCD_adder_7483 ; BCD_adder_7483 ; +; Family name ; Cyclone III ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+---------+ +; BCD_adder_7483.bdf ; yes ; User Block Diagram/Schematic File ; /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf ; ; +; 7483.bdf ; yes ; Megafunction ; /home/timmy/altera/13.1/quartus/libraries/others/maxplus2/7483.bdf ; ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+---------+ + + ++--------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------+ +; Resource ; Usage ; ++---------------------------------------------+----------+ +; Estimated Total logic elements ; 12 ; +; ; ; +; Total combinational functions ; 12 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 7 ; +; -- 3 input functions ; 3 ; +; -- <=2 input functions ; 2 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 12 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 13 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; A0~input ; +; Maximum fan-out ; 6 ; +; Total fan-out ; 59 ; +; Average fan-out ; 1.55 ; ++---------------------------------------------+----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------+--------------+ +; |BCD_adder_7483 ; 12 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; |BCD_adder_7483 ; work ; +; |7483:inst1| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_7483|7483:inst1 ; work ; +; |7483:inst| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |BCD_adder_7483|7483:inst ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit Analysis & Synthesis + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Mon Aug 26 23:12:52 2019 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_adder_7483 -c BCD_adder_7483 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file BCD_adder_7483.bdf + Info (12023): Found entity 1: BCD_adder_7483 +Info (12127): Elaborating entity "BCD_adder_7483" for the top level hierarchy +Info (12128): Elaborating entity "7483" for hierarchy "7483:inst1" +Info (12130): Elaborated megafunction instantiation "7483:inst1" +Info (13014): Ignored 1 buffer(s) + Info (13019): Ignored 1 SOFT buffer(s) +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 25 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 8 input pins + Info (21059): Implemented 5 output pins + Info (21061): Implemented 12 logic cells +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 371 megabytes + Info: Processing ended: Mon Aug 26 23:12:56 2019 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:04 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.map.summary b/CH5/CH5-3/output_files/BCD_adder_7483.map.summary new file mode 100644 index 00000000..37f3a89d --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon Aug 26 23:12:56 2019 +Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition +Revision Name : BCD_adder_7483 +Top-level Entity Name : BCD_adder_7483 +Family : Cyclone III +Total logic elements : 12 + Total combinational functions : 12 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 13 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.pin b/CH5/CH5-3/output_files/BCD_adder_7483.pin new file mode 100644 index 00000000..4864b19a --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.pin @@ -0,0 +1,554 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +CHIP "BCD_adder_7483" ASSIGNED TO AN: EP3C16F484C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO8 : A2 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 : +GND+ : A11 : : : : 8 : +GND+ : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +VCCIO7 : A21 : power : : 2.5V : 7 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +VCCIO3 : AA6 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +GND+ : AA11 : : : : 3 : +GND+ : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +VCCIO3 : AB2 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +GND : AB6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 : +GND+ : AB11 : : : : 3 : +GND+ : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +VCCIO4 : AB21 : power : : 2.5V : 4 : +GND : AB22 : gnd : : : : +C4 : B1 : output : 2.5 V : : 1 : Y +S0 : B2 : output : 2.5 V : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 : +GND+ : B11 : : : : 8 : +GND+ : B12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +S2 : C1 : output : 2.5 V : : 1 : Y +S1 : C2 : output : 2.5 V : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +GND : C5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +GND : C9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 : +GND : C11 : gnd : : : : +GND : C12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +GND : C14 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +GND : C16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +GND : C18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : input : 2.5 V : : 1 : N +A0 : D2 : input : 2.5 V : : 1 : Y +GND : D3 : gnd : : : : +VCCIO1 : D4 : power : : 2.5V : 1 : +VCCIO8 : D5 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +GND : D7 : gnd : : : : +GND : D8 : gnd : : : : +VCCIO8 : D9 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +VCCIO8 : D11 : power : : 2.5V : 8 : +VCCIO7 : D12 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +VCCIO7 : D14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +VCCIO7 : D16 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +VCCIO7 : D18 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +S3 : E1 : output : 2.5 V : : 1 : Y +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N +A2 : E3 : input : 2.5 V : : 1 : Y +A1 : E4 : input : 2.5 V : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : +VCCIO8 : E8 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 : +VCCD_PLL2 : E17 : power : : 1.2V : : +GNDA2 : E18 : gnd : : : : +VCCIO6 : E19 : power : : 2.5V : 6 : +GND : E20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 : +GND : F3 : gnd : : : : +VCCIO1 : F4 : power : : 2.5V : 1 : +GNDA3 : F5 : gnd : : : : +VCCD_PLL3 : F6 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +VCCA2 : F18 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +GND+ : G1 : : : : 1 : +GND+ : G2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 : +B2 : G4 : input : 2.5 V : : 1 : Y +B1 : G5 : input : 2.5 V : : 1 : Y +VCCA3 : G6 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 6 : +VCCIO6 : G19 : power : : 2.5V : 6 : +GND : G20 : gnd : : : : +GND+ : G21 : : : : 6 : +GND+ : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : : : : 1 : +GND : H3 : gnd : : : : +VCCIO1 : H4 : power : : 2.5V : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 : +B3 : H6 : input : 2.5 V : : 1 : Y +A3 : H7 : input : 2.5 V : : 1 : Y +GND : H8 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 : +GND : J5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 : +B0 : J7 : input : 2.5 V : : 1 : Y +VCCINT : J8 : power : : 1.2V : : +GND : J9 : gnd : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +VCCINT : J14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +VCCIO6 : J20 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : input : 2.5 V : : 1 : N +~ALTERA_DCLK~ : K2 : output : 2.5 V : : 1 : N +GND : K3 : gnd : : : : +VCCIO1 : K4 : power : : 2.5V : 1 : +nCONFIG : K5 : : : : 1 : +nSTATUS : K6 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +MSEL3 : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22 : output : 2.5 V : : 6 : N +TMS : L1 : input : : : 1 : +TCK : L2 : input : : : 1 : +nCE : L3 : : : : 1 : +TDO : L4 : output : : : 1 : +TDI : L5 : input : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 : +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 6 : +MSEL2 : L17 : : : : 6 : +MSEL1 : L18 : : : : 6 : +VCCIO6 : L19 : power : : 2.5V : 6 : +GND : L20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M16 : : : : 5 : +MSEL0 : M17 : : : : 6 : +CONF_DONE : M18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +GND : N3 : gnd : : : : +VCCIO2 : N4 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +VCCINT : P9 : power : : 1.2V : : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P17 : : : : 5 : +VCCIO5 : P18 : power : : 2.5V : 5 : +GND : P19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +GND : R3 : gnd : : : : +VCCIO2 : R4 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +GND+ : T1 : : : : 2 : +GND+ : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +VCCA1 : T6 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 4 : +VCCINT : T13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +VCCIO5 : T19 : power : : 2.5V : 5 : +GND : T20 : gnd : : : : +GND+ : T21 : : : : 5 : +GND+ : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +GND : U3 : gnd : : : : +VCCIO2 : U4 : power : : 2.5V : 2 : +GNDA1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCINT : U16 : power : : 1.2V : : +VCCINT : U17 : power : : 1.2V : : +VCCA4 : U18 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +VCCD_PLL4 : V17 : power : : 1.2V : : +GNDA4 : V18 : gnd : : : : +VCCIO5 : V19 : power : : 2.5V : 5 : +GND : V20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +GND : W3 : gnd : : : : +VCCIO2 : W4 : power : : 2.5V : 2 : +VCCIO3 : W5 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +VCCIO3 : W9 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +VCCIO3 : W11 : power : : 2.5V : 3 : +VCCIO4 : W12 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +VCCIO4 : W16 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +VCCIO4 : W18 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +GND : Y5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +GND : Y11 : gnd : : : : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +VCCIO4 : Y14 : power : : 2.5V : 4 : +GND : Y15 : gnd : : : : +GND : Y16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +GND : Y18 : gnd : : : : +VCCIO5 : Y19 : power : : 2.5V : 5 : +GND : Y20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.sof b/CH5/CH5-3/output_files/BCD_adder_7483.sof new file mode 100644 index 00000000..0b951972 Binary files /dev/null and b/CH5/CH5-3/output_files/BCD_adder_7483.sof differ diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.sta.rpt b/CH5/CH5-3/output_files/BCD_adder_7483.sta.rpt new file mode 100644 index 00000000..fb034fea --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.sta.rpt @@ -0,0 +1,730 @@ +TimeQuest Timing Analyzer report for BCD_adder_7483 +Mon Aug 26 23:13:38 2019 +Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Propagation Delay + 13. Minimum Propagation Delay + 14. Slow 1200mV 85C Model Metastability Report + 15. Slow 1200mV 0C Model Fmax Summary + 16. Slow 1200mV 0C Model Setup Summary + 17. Slow 1200mV 0C Model Hold Summary + 18. Slow 1200mV 0C Model Recovery Summary + 19. Slow 1200mV 0C Model Removal Summary + 20. Slow 1200mV 0C Model Minimum Pulse Width Summary + 21. Propagation Delay + 22. Minimum Propagation Delay + 23. Slow 1200mV 0C Model Metastability Report + 24. Fast 1200mV 0C Model Setup Summary + 25. Fast 1200mV 0C Model Hold Summary + 26. Fast 1200mV 0C Model Recovery Summary + 27. Fast 1200mV 0C Model Removal Summary + 28. Fast 1200mV 0C Model Minimum Pulse Width Summary + 29. Propagation Delay + 30. Minimum Propagation Delay + 31. Fast 1200mV 0C Model Metastability Report + 32. Multicorner Timing Analysis Summary + 33. Propagation Delay + 34. Minimum Propagation Delay + 35. Board Trace Model Assignments + 36. Input Transition Times + 37. Slow Corner Signal Integrity Metrics + 38. Fast Corner Signal Integrity Metrics + 39. Clock Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths + 43. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+----------------------------------------------------+ +; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; BCD_adder_7483 ; +; Device Family ; Cyclone III ; +; Device Name ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+----------------------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 7.555 ; 7.543 ; 7.970 ; 7.949 ; +; A0 ; S0 ; 6.285 ; 6.263 ; 6.703 ; 6.672 ; +; A0 ; S1 ; 8.010 ; 7.985 ; 8.424 ; 8.400 ; +; A0 ; S2 ; 8.000 ; 7.975 ; 8.411 ; 8.390 ; +; A0 ; S3 ; 7.357 ; 7.388 ; 7.772 ; 7.801 ; +; A1 ; C4 ; 8.019 ; 8.007 ; 8.416 ; 8.395 ; +; A1 ; S1 ; 8.474 ; 8.449 ; 8.870 ; 8.846 ; +; A1 ; S2 ; 8.464 ; 8.439 ; 8.857 ; 8.836 ; +; A1 ; S3 ; 7.821 ; 7.852 ; 8.218 ; 8.247 ; +; A2 ; C4 ; 7.757 ; 7.712 ; 8.169 ; 8.127 ; +; A2 ; S1 ; 8.211 ; 8.187 ; 8.623 ; 8.599 ; +; A2 ; S2 ; 8.198 ; 8.177 ; 8.610 ; 8.589 ; +; A2 ; S3 ; 7.559 ; 7.588 ; 7.971 ; 8.000 ; +; A3 ; C4 ; 6.456 ; ; ; 6.885 ; +; A3 ; S1 ; 6.910 ; 6.886 ; 7.352 ; 7.319 ; +; A3 ; S2 ; 6.897 ; 6.876 ; 7.342 ; 7.312 ; +; A3 ; S3 ; 6.293 ; 6.290 ; 6.696 ; 6.737 ; +; B0 ; C4 ; 8.021 ; 8.009 ; 8.465 ; 8.444 ; +; B0 ; S0 ; 6.783 ; 6.748 ; 7.206 ; 7.227 ; +; B0 ; S1 ; 8.476 ; 8.451 ; 8.919 ; 8.895 ; +; B0 ; S2 ; 8.466 ; 8.441 ; 8.906 ; 8.885 ; +; B0 ; S3 ; 7.823 ; 7.854 ; 8.267 ; 8.296 ; +; B1 ; C4 ; 7.845 ; 7.833 ; 8.239 ; 8.218 ; +; B1 ; S1 ; 8.300 ; 8.275 ; 8.693 ; 8.669 ; +; B1 ; S2 ; 8.290 ; 8.265 ; 8.680 ; 8.659 ; +; B1 ; S3 ; 7.647 ; 7.678 ; 8.041 ; 8.070 ; +; B2 ; C4 ; 7.581 ; 7.562 ; 8.026 ; 7.975 ; +; B2 ; S1 ; 8.035 ; 8.011 ; 8.480 ; 8.456 ; +; B2 ; S2 ; 8.022 ; 8.001 ; 8.467 ; 8.446 ; +; B2 ; S3 ; 7.383 ; 7.412 ; 7.828 ; 7.857 ; +; B3 ; C4 ; 6.339 ; ; ; 6.758 ; +; B3 ; S1 ; 6.793 ; 6.769 ; 7.225 ; 7.192 ; +; B3 ; S2 ; 6.780 ; 6.759 ; 7.215 ; 7.185 ; +; B3 ; S3 ; 6.140 ; 6.171 ; 6.565 ; 6.564 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 6.475 ; 6.476 ; 6.883 ; 6.875 ; +; A0 ; S0 ; 6.150 ; 6.128 ; 6.556 ; 6.525 ; +; A0 ; S1 ; 6.359 ; 6.375 ; 6.807 ; 6.775 ; +; A0 ; S2 ; 6.622 ; 6.628 ; 7.029 ; 7.035 ; +; A0 ; S3 ; 6.283 ; 6.312 ; 6.689 ; 6.720 ; +; A1 ; C4 ; 7.162 ; 7.164 ; 7.545 ; 7.547 ; +; A1 ; S1 ; 6.850 ; 6.824 ; 7.233 ; 7.207 ; +; A1 ; S2 ; 6.982 ; 6.988 ; 7.408 ; 7.413 ; +; A1 ; S3 ; 6.970 ; 6.999 ; 7.353 ; 7.382 ; +; A2 ; C4 ; 7.130 ; 7.388 ; 7.812 ; 7.494 ; +; A2 ; S1 ; 7.566 ; 7.542 ; 7.942 ; 7.909 ; +; A2 ; S2 ; 6.963 ; 6.940 ; 7.376 ; 7.354 ; +; A2 ; S3 ; 6.925 ; 6.995 ; 7.331 ; 7.311 ; +; A3 ; C4 ; 6.249 ; ; ; 6.688 ; +; A3 ; S1 ; 6.685 ; 6.661 ; 7.136 ; 7.103 ; +; A3 ; S2 ; 6.671 ; 6.650 ; 7.127 ; 7.097 ; +; A3 ; S3 ; 6.087 ; 6.103 ; 6.480 ; 6.519 ; +; B0 ; C4 ; 6.881 ; 6.931 ; 7.352 ; 7.341 ; +; B0 ; S0 ; 6.602 ; 6.567 ; 7.002 ; 7.006 ; +; B0 ; S1 ; 6.570 ; 6.586 ; 7.041 ; 6.996 ; +; B0 ; S2 ; 7.032 ; 7.038 ; 7.475 ; 7.480 ; +; B0 ; S3 ; 6.689 ; 6.718 ; 7.155 ; 7.189 ; +; B1 ; C4 ; 7.236 ; 7.238 ; 7.654 ; 7.656 ; +; B1 ; S1 ; 6.924 ; 6.898 ; 7.342 ; 7.316 ; +; B1 ; S2 ; 6.899 ; 6.905 ; 7.287 ; 7.293 ; +; B1 ; S3 ; 7.044 ; 7.073 ; 7.462 ; 7.491 ; +; B2 ; C4 ; 7.017 ; 7.305 ; 7.756 ; 7.399 ; +; B2 ; S1 ; 7.453 ; 7.429 ; 7.847 ; 7.814 ; +; B2 ; S2 ; 6.880 ; 6.857 ; 7.282 ; 7.259 ; +; B2 ; S3 ; 6.812 ; 6.882 ; 7.236 ; 7.216 ; +; B3 ; C4 ; 6.198 ; ; ; 6.605 ; +; B3 ; S1 ; 6.634 ; 6.610 ; 7.053 ; 7.020 ; +; B3 ; S2 ; 6.620 ; 6.599 ; 7.044 ; 7.014 ; +; B3 ; S3 ; 6.005 ; 6.036 ; 6.419 ; 6.419 ; ++------------+-------------+-------+-------+-------+-------+ + + +---------------------------------------------- +; Slow 1200mV 85C Model Metastability Report ; +---------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 6.990 ; 6.968 ; 7.358 ; 7.328 ; +; A0 ; S0 ; 5.852 ; 5.820 ; 6.216 ; 6.176 ; +; A0 ; S1 ; 7.408 ; 7.365 ; 7.776 ; 7.733 ; +; A0 ; S2 ; 7.397 ; 7.355 ; 7.765 ; 7.723 ; +; A0 ; S3 ; 6.790 ; 6.849 ; 7.158 ; 7.214 ; +; A1 ; C4 ; 7.410 ; 7.388 ; 7.748 ; 7.718 ; +; A1 ; S1 ; 7.828 ; 7.785 ; 8.166 ; 8.123 ; +; A1 ; S2 ; 7.817 ; 7.775 ; 8.155 ; 8.113 ; +; A1 ; S3 ; 7.210 ; 7.269 ; 7.548 ; 7.604 ; +; A2 ; C4 ; 7.171 ; 7.119 ; 7.517 ; 7.469 ; +; A2 ; S1 ; 7.589 ; 7.546 ; 7.935 ; 7.892 ; +; A2 ; S2 ; 7.578 ; 7.536 ; 7.924 ; 7.882 ; +; A2 ; S3 ; 6.971 ; 7.027 ; 7.317 ; 7.373 ; +; A3 ; C4 ; 6.003 ; ; ; 6.358 ; +; A3 ; S1 ; 6.421 ; 6.378 ; 6.779 ; 6.728 ; +; A3 ; S2 ; 6.410 ; 6.368 ; 6.771 ; 6.721 ; +; A3 ; S3 ; 5.831 ; 5.860 ; 6.180 ; 6.245 ; +; B0 ; C4 ; 7.403 ; 7.381 ; 7.777 ; 7.747 ; +; B0 ; S0 ; 6.298 ; 6.254 ; 6.641 ; 6.651 ; +; B0 ; S1 ; 7.821 ; 7.778 ; 8.195 ; 8.152 ; +; B0 ; S2 ; 7.810 ; 7.768 ; 8.184 ; 8.142 ; +; B0 ; S3 ; 7.203 ; 7.262 ; 7.577 ; 7.633 ; +; B1 ; C4 ; 7.251 ; 7.229 ; 7.604 ; 7.574 ; +; B1 ; S1 ; 7.669 ; 7.626 ; 8.022 ; 7.979 ; +; B1 ; S2 ; 7.658 ; 7.616 ; 8.011 ; 7.969 ; +; B1 ; S3 ; 7.051 ; 7.110 ; 7.404 ; 7.460 ; +; B2 ; C4 ; 7.015 ; 6.987 ; 7.393 ; 7.336 ; +; B2 ; S1 ; 7.433 ; 7.390 ; 7.811 ; 7.768 ; +; B2 ; S2 ; 7.422 ; 7.380 ; 7.800 ; 7.758 ; +; B2 ; S3 ; 6.815 ; 6.871 ; 7.193 ; 7.249 ; +; B3 ; C4 ; 5.898 ; ; ; 6.247 ; +; B3 ; S1 ; 6.316 ; 6.273 ; 6.668 ; 6.617 ; +; B3 ; S2 ; 6.305 ; 6.263 ; 6.660 ; 6.610 ; +; B3 ; S3 ; 5.697 ; 5.755 ; 6.067 ; 6.096 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 6.038 ; 6.018 ; 6.392 ; 6.366 ; +; A0 ; S0 ; 5.737 ; 5.706 ; 6.090 ; 6.053 ; +; A0 ; S1 ; 5.929 ; 5.920 ; 6.312 ; 6.263 ; +; A0 ; S2 ; 6.163 ; 6.146 ; 6.515 ; 6.492 ; +; A0 ; S3 ; 5.842 ; 5.897 ; 6.190 ; 6.250 ; +; A1 ; C4 ; 6.663 ; 6.643 ; 6.986 ; 6.966 ; +; A1 ; S1 ; 6.374 ; 6.328 ; 6.697 ; 6.651 ; +; A1 ; S2 ; 6.487 ; 6.474 ; 6.844 ; 6.820 ; +; A1 ; S3 ; 6.467 ; 6.522 ; 6.790 ; 6.845 ; +; A2 ; C4 ; 6.612 ; 6.837 ; 7.204 ; 6.909 ; +; A2 ; S1 ; 7.013 ; 6.969 ; 7.315 ; 7.265 ; +; A2 ; S2 ; 6.468 ; 6.425 ; 6.815 ; 6.773 ; +; A2 ; S3 ; 6.408 ; 6.497 ; 6.753 ; 6.761 ; +; A3 ; C4 ; 5.821 ; ; ; 6.188 ; +; A3 ; S1 ; 6.222 ; 6.178 ; 6.594 ; 6.544 ; +; A3 ; S2 ; 6.210 ; 6.169 ; 6.585 ; 6.538 ; +; A3 ; S3 ; 5.658 ; 5.699 ; 5.994 ; 6.055 ; +; B0 ; C4 ; 6.398 ; 6.424 ; 6.793 ; 6.762 ; +; B0 ; S0 ; 6.141 ; 6.103 ; 6.468 ; 6.465 ; +; B0 ; S1 ; 6.111 ; 6.102 ; 6.500 ; 6.442 ; +; B0 ; S2 ; 6.528 ; 6.515 ; 6.890 ; 6.867 ; +; B0 ; S3 ; 6.203 ; 6.257 ; 6.586 ; 6.646 ; +; B1 ; C4 ; 6.723 ; 6.703 ; 7.084 ; 7.064 ; +; B1 ; S1 ; 6.434 ; 6.388 ; 6.794 ; 6.749 ; +; B1 ; S2 ; 6.413 ; 6.394 ; 6.752 ; 6.739 ; +; B1 ; S3 ; 6.527 ; 6.582 ; 6.888 ; 6.938 ; +; B2 ; C4 ; 6.511 ; 6.765 ; 7.159 ; 6.831 ; +; B2 ; S1 ; 6.912 ; 6.868 ; 7.237 ; 7.187 ; +; B2 ; S2 ; 6.396 ; 6.353 ; 6.738 ; 6.695 ; +; B2 ; S3 ; 6.307 ; 6.396 ; 6.675 ; 6.683 ; +; B3 ; C4 ; 5.778 ; ; ; 6.116 ; +; B3 ; S1 ; 6.179 ; 6.135 ; 6.522 ; 6.472 ; +; B3 ; S2 ; 6.167 ; 6.126 ; 6.513 ; 6.466 ; +; B3 ; S3 ; 5.582 ; 5.638 ; 5.944 ; 5.972 ; ++------------+-------------+-------+-------+-------+-------+ + + +--------------------------------------------- +; Slow 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 4.498 ; 4.507 ; 5.046 ; 5.048 ; +; A0 ; S0 ; 3.795 ; 3.814 ; 4.349 ; 4.361 ; +; A0 ; S1 ; 4.736 ; 4.751 ; 5.277 ; 5.292 ; +; A0 ; S2 ; 4.727 ; 4.743 ; 5.268 ; 5.284 ; +; A0 ; S3 ; 4.386 ; 4.378 ; 4.934 ; 4.926 ; +; A1 ; C4 ; 4.740 ; 4.749 ; 5.301 ; 5.303 ; +; A1 ; S1 ; 4.978 ; 4.993 ; 5.532 ; 5.547 ; +; A1 ; S2 ; 4.969 ; 4.985 ; 5.523 ; 5.539 ; +; A1 ; S3 ; 4.628 ; 4.620 ; 5.189 ; 5.181 ; +; A2 ; C4 ; 4.588 ; 4.580 ; 5.167 ; 5.168 ; +; A2 ; S1 ; 4.812 ; 4.834 ; 5.397 ; 5.413 ; +; A2 ; S2 ; 4.802 ; 4.825 ; 5.388 ; 5.404 ; +; A2 ; S3 ; 4.476 ; 4.468 ; 5.055 ; 5.047 ; +; A3 ; C4 ; 3.872 ; ; ; 4.452 ; +; A3 ; S1 ; 4.096 ; 4.118 ; 4.681 ; 4.696 ; +; A3 ; S2 ; 4.086 ; 4.109 ; 4.672 ; 4.688 ; +; A3 ; S3 ; 3.776 ; 3.754 ; 4.318 ; 4.328 ; +; B0 ; C4 ; 4.743 ; 4.752 ; 5.322 ; 5.324 ; +; B0 ; S0 ; 4.066 ; 4.072 ; 4.639 ; 4.675 ; +; B0 ; S1 ; 4.981 ; 4.996 ; 5.553 ; 5.568 ; +; B0 ; S2 ; 4.972 ; 4.988 ; 5.544 ; 5.560 ; +; B0 ; S3 ; 4.631 ; 4.623 ; 5.210 ; 5.202 ; +; B1 ; C4 ; 4.650 ; 4.659 ; 5.193 ; 5.195 ; +; B1 ; S1 ; 4.888 ; 4.903 ; 5.424 ; 5.439 ; +; B1 ; S2 ; 4.879 ; 4.895 ; 5.415 ; 5.431 ; +; B1 ; S3 ; 4.538 ; 4.530 ; 5.081 ; 5.073 ; +; B2 ; C4 ; 4.505 ; 4.510 ; 5.078 ; 5.065 ; +; B2 ; S1 ; 4.739 ; 4.754 ; 5.302 ; 5.324 ; +; B2 ; S2 ; 4.730 ; 4.746 ; 5.292 ; 5.315 ; +; B2 ; S3 ; 4.393 ; 4.385 ; 4.966 ; 4.958 ; +; B3 ; C4 ; 3.802 ; ; ; 4.379 ; +; B3 ; S1 ; 4.026 ; 4.048 ; 4.608 ; 4.623 ; +; B3 ; S2 ; 4.016 ; 4.039 ; 4.599 ; 4.615 ; +; B3 ; S3 ; 3.687 ; 3.682 ; 4.244 ; 4.221 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 3.887 ; 3.924 ; 4.440 ; 4.470 ; +; A0 ; S0 ; 3.715 ; 3.733 ; 4.264 ; 4.275 ; +; A0 ; S1 ; 3.830 ; 3.868 ; 4.410 ; 4.420 ; +; A0 ; S2 ; 3.958 ; 3.987 ; 4.508 ; 4.537 ; +; A0 ; S3 ; 3.780 ; 3.772 ; 4.333 ; 4.325 ; +; A1 ; C4 ; 4.248 ; 4.281 ; 4.794 ; 4.827 ; +; A1 ; S1 ; 4.078 ; 4.095 ; 4.624 ; 4.641 ; +; A1 ; S2 ; 4.150 ; 4.179 ; 4.727 ; 4.756 ; +; A1 ; S3 ; 4.141 ; 4.133 ; 4.687 ; 4.679 ; +; A2 ; C4 ; 4.238 ; 4.393 ; 4.961 ; 4.808 ; +; A2 ; S1 ; 4.453 ; 4.475 ; 5.028 ; 5.043 ; +; A2 ; S2 ; 4.130 ; 4.147 ; 4.711 ; 4.729 ; +; A2 ; S3 ; 4.116 ; 4.141 ; 4.687 ; 4.658 ; +; A3 ; C4 ; 3.753 ; ; ; 4.341 ; +; A3 ; S1 ; 3.968 ; 3.990 ; 4.561 ; 4.576 ; +; A3 ; S2 ; 3.957 ; 3.979 ; 4.552 ; 4.567 ; +; A3 ; S3 ; 3.654 ; 3.646 ; 4.197 ; 4.200 ; +; B0 ; C4 ; 4.103 ; 4.161 ; 4.703 ; 4.726 ; +; B0 ; S0 ; 3.960 ; 3.965 ; 4.517 ; 4.545 ; +; B0 ; S1 ; 3.934 ; 3.972 ; 4.534 ; 4.539 ; +; B0 ; S2 ; 4.179 ; 4.208 ; 4.757 ; 4.786 ; +; B0 ; S3 ; 3.996 ; 3.988 ; 4.595 ; 4.588 ; +; B1 ; C4 ; 4.295 ; 4.328 ; 4.866 ; 4.899 ; +; B1 ; S1 ; 4.125 ; 4.142 ; 4.696 ; 4.713 ; +; B1 ; S2 ; 4.105 ; 4.134 ; 4.650 ; 4.679 ; +; B1 ; S3 ; 4.188 ; 4.180 ; 4.759 ; 4.750 ; +; B2 ; C4 ; 4.194 ; 4.360 ; 4.921 ; 4.742 ; +; B2 ; S1 ; 4.409 ; 4.431 ; 4.962 ; 4.977 ; +; B2 ; S2 ; 4.097 ; 4.114 ; 4.646 ; 4.663 ; +; B2 ; S3 ; 4.072 ; 4.097 ; 4.621 ; 4.592 ; +; B3 ; C4 ; 3.720 ; ; ; 4.291 ; +; B3 ; S1 ; 3.935 ; 3.957 ; 4.511 ; 4.526 ; +; B3 ; S2 ; 3.924 ; 3.946 ; 4.502 ; 4.517 ; +; B3 ; S3 ; 3.608 ; 3.605 ; 4.160 ; 4.137 ; ++------------+-------------+-------+-------+-------+-------+ + + +--------------------------------------------- +; Fast 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 7.555 ; 7.543 ; 7.970 ; 7.949 ; +; A0 ; S0 ; 6.285 ; 6.263 ; 6.703 ; 6.672 ; +; A0 ; S1 ; 8.010 ; 7.985 ; 8.424 ; 8.400 ; +; A0 ; S2 ; 8.000 ; 7.975 ; 8.411 ; 8.390 ; +; A0 ; S3 ; 7.357 ; 7.388 ; 7.772 ; 7.801 ; +; A1 ; C4 ; 8.019 ; 8.007 ; 8.416 ; 8.395 ; +; A1 ; S1 ; 8.474 ; 8.449 ; 8.870 ; 8.846 ; +; A1 ; S2 ; 8.464 ; 8.439 ; 8.857 ; 8.836 ; +; A1 ; S3 ; 7.821 ; 7.852 ; 8.218 ; 8.247 ; +; A2 ; C4 ; 7.757 ; 7.712 ; 8.169 ; 8.127 ; +; A2 ; S1 ; 8.211 ; 8.187 ; 8.623 ; 8.599 ; +; A2 ; S2 ; 8.198 ; 8.177 ; 8.610 ; 8.589 ; +; A2 ; S3 ; 7.559 ; 7.588 ; 7.971 ; 8.000 ; +; A3 ; C4 ; 6.456 ; ; ; 6.885 ; +; A3 ; S1 ; 6.910 ; 6.886 ; 7.352 ; 7.319 ; +; A3 ; S2 ; 6.897 ; 6.876 ; 7.342 ; 7.312 ; +; A3 ; S3 ; 6.293 ; 6.290 ; 6.696 ; 6.737 ; +; B0 ; C4 ; 8.021 ; 8.009 ; 8.465 ; 8.444 ; +; B0 ; S0 ; 6.783 ; 6.748 ; 7.206 ; 7.227 ; +; B0 ; S1 ; 8.476 ; 8.451 ; 8.919 ; 8.895 ; +; B0 ; S2 ; 8.466 ; 8.441 ; 8.906 ; 8.885 ; +; B0 ; S3 ; 7.823 ; 7.854 ; 8.267 ; 8.296 ; +; B1 ; C4 ; 7.845 ; 7.833 ; 8.239 ; 8.218 ; +; B1 ; S1 ; 8.300 ; 8.275 ; 8.693 ; 8.669 ; +; B1 ; S2 ; 8.290 ; 8.265 ; 8.680 ; 8.659 ; +; B1 ; S3 ; 7.647 ; 7.678 ; 8.041 ; 8.070 ; +; B2 ; C4 ; 7.581 ; 7.562 ; 8.026 ; 7.975 ; +; B2 ; S1 ; 8.035 ; 8.011 ; 8.480 ; 8.456 ; +; B2 ; S2 ; 8.022 ; 8.001 ; 8.467 ; 8.446 ; +; B2 ; S3 ; 7.383 ; 7.412 ; 7.828 ; 7.857 ; +; B3 ; C4 ; 6.339 ; ; ; 6.758 ; +; B3 ; S1 ; 6.793 ; 6.769 ; 7.225 ; 7.192 ; +; B3 ; S2 ; 6.780 ; 6.759 ; 7.215 ; 7.185 ; +; B3 ; S3 ; 6.140 ; 6.171 ; 6.565 ; 6.564 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; A0 ; C4 ; 3.887 ; 3.924 ; 4.440 ; 4.470 ; +; A0 ; S0 ; 3.715 ; 3.733 ; 4.264 ; 4.275 ; +; A0 ; S1 ; 3.830 ; 3.868 ; 4.410 ; 4.420 ; +; A0 ; S2 ; 3.958 ; 3.987 ; 4.508 ; 4.537 ; +; A0 ; S3 ; 3.780 ; 3.772 ; 4.333 ; 4.325 ; +; A1 ; C4 ; 4.248 ; 4.281 ; 4.794 ; 4.827 ; +; A1 ; S1 ; 4.078 ; 4.095 ; 4.624 ; 4.641 ; +; A1 ; S2 ; 4.150 ; 4.179 ; 4.727 ; 4.756 ; +; A1 ; S3 ; 4.141 ; 4.133 ; 4.687 ; 4.679 ; +; A2 ; C4 ; 4.238 ; 4.393 ; 4.961 ; 4.808 ; +; A2 ; S1 ; 4.453 ; 4.475 ; 5.028 ; 5.043 ; +; A2 ; S2 ; 4.130 ; 4.147 ; 4.711 ; 4.729 ; +; A2 ; S3 ; 4.116 ; 4.141 ; 4.687 ; 4.658 ; +; A3 ; C4 ; 3.753 ; ; ; 4.341 ; +; A3 ; S1 ; 3.968 ; 3.990 ; 4.561 ; 4.576 ; +; A3 ; S2 ; 3.957 ; 3.979 ; 4.552 ; 4.567 ; +; A3 ; S3 ; 3.654 ; 3.646 ; 4.197 ; 4.200 ; +; B0 ; C4 ; 4.103 ; 4.161 ; 4.703 ; 4.726 ; +; B0 ; S0 ; 3.960 ; 3.965 ; 4.517 ; 4.545 ; +; B0 ; S1 ; 3.934 ; 3.972 ; 4.534 ; 4.539 ; +; B0 ; S2 ; 4.179 ; 4.208 ; 4.757 ; 4.786 ; +; B0 ; S3 ; 3.996 ; 3.988 ; 4.595 ; 4.588 ; +; B1 ; C4 ; 4.295 ; 4.328 ; 4.866 ; 4.899 ; +; B1 ; S1 ; 4.125 ; 4.142 ; 4.696 ; 4.713 ; +; B1 ; S2 ; 4.105 ; 4.134 ; 4.650 ; 4.679 ; +; B1 ; S3 ; 4.188 ; 4.180 ; 4.759 ; 4.750 ; +; B2 ; C4 ; 4.194 ; 4.360 ; 4.921 ; 4.742 ; +; B2 ; S1 ; 4.409 ; 4.431 ; 4.962 ; 4.977 ; +; B2 ; S2 ; 4.097 ; 4.114 ; 4.646 ; 4.663 ; +; B2 ; S3 ; 4.072 ; 4.097 ; 4.621 ; 4.592 ; +; B3 ; C4 ; 3.720 ; ; ; 4.291 ; +; B3 ; S1 ; 3.935 ; 3.957 ; 4.511 ; 4.526 ; +; B3 ; S2 ; 3.924 ; 3.946 ; 4.502 ; 4.517 ; +; B3 ; S3 ; 3.608 ; 3.605 ; 4.160 ; 4.137 ; ++------------+-------------+-------+-------+-------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; S0 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S1 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S2 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; S3 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; C4 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; A0 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B0 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A1 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B1 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A3 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B3 ; 2.5 V ; 2000 ps ; 2000 ps ; +; A2 ; 2.5 V ; 2000 ps ; 2000 ps ; +; B2 ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; S0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; S3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; C4 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.68e-07 V ; 2.35 V ; -0.0132 V ; 0.2 V ; 0.027 V ; 5.26e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 5.68e-07 V ; 2.35 V ; -0.0132 V ; 0.2 V ; 0.027 V ; 5.26e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.36e-07 V ; 2.35 V ; -0.00444 V ; 0.18 V ; 0.019 V ; 7.23e-10 s ; 9.82e-10 s ; Yes ; Yes ; 2.32 V ; 9.36e-07 V ; 2.35 V ; -0.00444 V ; 0.18 V ; 0.019 V ; 7.23e-10 s ; 9.82e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; S0 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S1 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S2 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; S3 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; C4 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.72 V ; -0.0747 V ; 0.28 V ; 0.169 V ; 3.1e-10 s ; 3.01e-10 s ; No ; Yes ; 2.62 V ; 2.22e-08 V ; 2.72 V ; -0.0747 V ; 0.28 V ; 0.169 V ; 3.1e-10 s ; 3.01e-10 s ; No ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.53e-08 V ; 2.7 V ; -0.0212 V ; 0.204 V ; 0.049 V ; 4.85e-10 s ; 6.73e-10 s ; No ; Yes ; 2.62 V ; 3.53e-08 V ; 2.7 V ; -0.0212 V ; 0.204 V ; 0.049 V ; 4.85e-10 s ; 6.73e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 8 ; 8 ; +; Unconstrained Input Port Paths ; 34 ; 34 ; +; Unconstrained Output Ports ; 5 ; 5 ; +; Unconstrained Output Port Paths ; 34 ; 34 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 32-bit TimeQuest Timing Analyzer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Mon Aug 26 23:13:35 2019 +Info: Command: quartus_sta BCD_adder_7483 -c BCD_adder_7483 +Info: qsta_default_script.tcl version: #1 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'BCD_adder_7483.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 383 megabytes + Info: Processing ended: Mon Aug 26 23:13:38 2019 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/CH5/CH5-3/output_files/BCD_adder_7483.sta.summary b/CH5/CH5-3/output_files/BCD_adder_7483.sta.summary new file mode 100644 index 00000000..33f74363 --- /dev/null +++ b/CH5/CH5-3/output_files/BCD_adder_7483.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D.sft b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D.sft new file mode 100644 index 00000000..1c0f8339 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim-Altera (VHDL)" +set corner_file_list { + {{"Slow -6 1.2V 85 Model"} {BCD_adder_1D_6_1200mv_85c_slow.vho BCD_adder_1D_6_1200mv_85c_vhd_slow.sdo}} + {{"Slow -6 1.2V 0 Model"} {BCD_adder_1D_6_1200mv_0c_slow.vho BCD_adder_1D_6_1200mv_0c_vhd_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {BCD_adder_1D_min_1200mv_0c_fast.vho BCD_adder_1D_min_1200mv_0c_vhd_fast.sdo}} +} diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D.vho new file mode 100644 index 00000000..f8dcf5da --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D.vho @@ -0,0 +1,458 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "09/05/2019 20:29:14" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_1D IS + PORT ( + S0 : OUT std_logic; + A3 : IN std_logic; + B3 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A1 : IN std_logic; + B1 : IN std_logic; + A0 : IN std_logic; + B0 : IN std_logic; + S1 : OUT std_logic; + S2 : OUT std_logic; + S3 : OUT std_logic; + C4 : OUT std_logic + ); +END BCD_adder_1D; + +-- Design Ports Information +-- S0 => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +-- S3 => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +-- C4 => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_H7, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_H6, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_J7, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_1D IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_C4 : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \C4~output_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \inst|inst4|inst|inst~combout\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \inst|inst3|inst1|inst~0_combout\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \inst6~0_combout\ : std_logic; +SIGNAL \inst6~1_combout\ : std_logic; +SIGNAL \inst2|inst3|inst|inst~combout\ : std_logic; +SIGNAL \inst|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst2|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst2|inst|inst1|inst~0_combout\ : std_logic; + +BEGIN + +S0 <= ww_S0; +ww_A3 <= A3; +ww_B3 <= B3; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A1 <= A1; +ww_B1 <= B1; +ww_A0 <= A0; +ww_B0 <= B0; +S1 <= ww_S1; +S2 <= ww_S2; +S3 <= ww_S3; +C4 <= ww_C4; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +-- Location: IOOBUF_X0_Y24_N16 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst4|inst|inst~combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst3|inst|inst~combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y26_N16 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst2|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y27_N9 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y27_N16 +\C4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst6~1_combout\, + devoe => ww_devoe, + o => \C4~output_o\); + +-- Location: IOIBUF_X0_Y25_N22 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X0_Y25_N15 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: LCCOMB_X1_Y24_N16 +\inst|inst4|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst4|inst|inst~combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datac => \A0~input_o\, + combout => \inst|inst4|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y23_N8 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: IOIBUF_X0_Y26_N8 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: LCCOMB_X1_Y24_N10 +\inst|inst3|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst3|inst1|inst~0_combout\ = \B1~input_o\ $ (\A1~input_o\ $ (((\B0~input_o\ & \A0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001010101101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \A1~input_o\, + combout => \inst|inst3|inst1|inst~0_combout\); + +-- Location: IOIBUF_X0_Y25_N1 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y27_N22 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: LCCOMB_X1_Y24_N12 +\inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst3|inst2~0_combout\ = (\B1~input_o\ & ((\A1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\B1~input_o\ & (\B0~input_o\ & (\A0~input_o\ & \A1~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \A1~input_o\, + combout => \inst|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y24_N24 +\inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst2~0_combout\ = (\B2~input_o\ & ((\A2~input_o\) # (\inst|inst3|inst2~0_combout\))) # (!\B2~input_o\ & (\A2~input_o\ & \inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datac => \A2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst|inst2|inst2~0_combout\); + +-- Location: IOIBUF_X0_Y22_N15 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: LCCOMB_X1_Y24_N6 +\inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~0_combout\ = (\inst|inst3|inst1|inst~0_combout\) # (\A2~input_o\ $ (\B2~input_o\ $ (\inst|inst3|inst2~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101110111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datab => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst6~0_combout\); + +-- Location: LCCOMB_X1_Y24_N2 +\inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~1_combout\ = (\A3~input_o\ & ((\inst|inst2|inst2~0_combout\) # ((\B3~input_o\) # (\inst6~0_combout\)))) # (!\A3~input_o\ & ((\inst|inst2|inst2~0_combout\ & ((\B3~input_o\) # (\inst6~0_combout\))) # (!\inst|inst2|inst2~0_combout\ & (\B3~input_o\ & +-- \inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|inst2|inst2~0_combout\, + datac => \B3~input_o\, + datad => \inst6~0_combout\, + combout => \inst6~1_combout\); + +-- Location: LCCOMB_X1_Y24_N4 +\inst2|inst3|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst3|inst|inst~combout\ = \inst|inst3|inst1|inst~0_combout\ $ (\inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101010110101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datad => \inst6~1_combout\, + combout => \inst2|inst3|inst|inst~combout\); + +-- Location: LCCOMB_X1_Y24_N22 +\inst|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst1|inst~0_combout\ = \B2~input_o\ $ (\A2~input_o\ $ (\inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datac => \A2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y24_N0 +\inst2|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst2|inst1|inst~0_combout\ = \inst|inst2|inst1|inst~0_combout\ $ (((!\inst|inst3|inst1|inst~0_combout\ & \inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010111110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst2|inst1|inst~0_combout\, + datad => \inst6~1_combout\, + combout => \inst2|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y24_N26 +\inst2|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst|inst1|inst~0_combout\ = (\A3~input_o\ & (\inst|inst2|inst2~0_combout\ $ (\B3~input_o\ $ (!\inst6~0_combout\)))) # (!\A3~input_o\ & ((\inst|inst2|inst2~0_combout\ & (\B3~input_o\ $ (!\inst6~0_combout\))) # (!\inst|inst2|inst2~0_combout\ & +-- (\B3~input_o\ & !\inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100010010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|inst2|inst2~0_combout\, + datac => \B3~input_o\, + datad => \inst6~0_combout\, + combout => \inst2|inst|inst1|inst~0_combout\); + +ww_S0 <= \S0~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S3 <= \S3~output_o\; + +ww_C4 <= \C4~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_0c_slow.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_0c_slow.vho new file mode 100644 index 00000000..f8dcf5da --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_0c_slow.vho @@ -0,0 +1,458 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "09/05/2019 20:29:14" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_1D IS + PORT ( + S0 : OUT std_logic; + A3 : IN std_logic; + B3 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A1 : IN std_logic; + B1 : IN std_logic; + A0 : IN std_logic; + B0 : IN std_logic; + S1 : OUT std_logic; + S2 : OUT std_logic; + S3 : OUT std_logic; + C4 : OUT std_logic + ); +END BCD_adder_1D; + +-- Design Ports Information +-- S0 => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +-- S3 => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +-- C4 => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_H7, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_H6, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_J7, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_1D IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_C4 : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \C4~output_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \inst|inst4|inst|inst~combout\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \inst|inst3|inst1|inst~0_combout\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \inst6~0_combout\ : std_logic; +SIGNAL \inst6~1_combout\ : std_logic; +SIGNAL \inst2|inst3|inst|inst~combout\ : std_logic; +SIGNAL \inst|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst2|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst2|inst|inst1|inst~0_combout\ : std_logic; + +BEGIN + +S0 <= ww_S0; +ww_A3 <= A3; +ww_B3 <= B3; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A1 <= A1; +ww_B1 <= B1; +ww_A0 <= A0; +ww_B0 <= B0; +S1 <= ww_S1; +S2 <= ww_S2; +S3 <= ww_S3; +C4 <= ww_C4; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +-- Location: IOOBUF_X0_Y24_N16 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst4|inst|inst~combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst3|inst|inst~combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y26_N16 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst2|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y27_N9 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y27_N16 +\C4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst6~1_combout\, + devoe => ww_devoe, + o => \C4~output_o\); + +-- Location: IOIBUF_X0_Y25_N22 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X0_Y25_N15 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: LCCOMB_X1_Y24_N16 +\inst|inst4|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst4|inst|inst~combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datac => \A0~input_o\, + combout => \inst|inst4|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y23_N8 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: IOIBUF_X0_Y26_N8 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: LCCOMB_X1_Y24_N10 +\inst|inst3|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst3|inst1|inst~0_combout\ = \B1~input_o\ $ (\A1~input_o\ $ (((\B0~input_o\ & \A0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001010101101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \A1~input_o\, + combout => \inst|inst3|inst1|inst~0_combout\); + +-- Location: IOIBUF_X0_Y25_N1 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y27_N22 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: LCCOMB_X1_Y24_N12 +\inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst3|inst2~0_combout\ = (\B1~input_o\ & ((\A1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\B1~input_o\ & (\B0~input_o\ & (\A0~input_o\ & \A1~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \A1~input_o\, + combout => \inst|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y24_N24 +\inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst2~0_combout\ = (\B2~input_o\ & ((\A2~input_o\) # (\inst|inst3|inst2~0_combout\))) # (!\B2~input_o\ & (\A2~input_o\ & \inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datac => \A2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst|inst2|inst2~0_combout\); + +-- Location: IOIBUF_X0_Y22_N15 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: LCCOMB_X1_Y24_N6 +\inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~0_combout\ = (\inst|inst3|inst1|inst~0_combout\) # (\A2~input_o\ $ (\B2~input_o\ $ (\inst|inst3|inst2~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101110111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datab => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst6~0_combout\); + +-- Location: LCCOMB_X1_Y24_N2 +\inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~1_combout\ = (\A3~input_o\ & ((\inst|inst2|inst2~0_combout\) # ((\B3~input_o\) # (\inst6~0_combout\)))) # (!\A3~input_o\ & ((\inst|inst2|inst2~0_combout\ & ((\B3~input_o\) # (\inst6~0_combout\))) # (!\inst|inst2|inst2~0_combout\ & (\B3~input_o\ & +-- \inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|inst2|inst2~0_combout\, + datac => \B3~input_o\, + datad => \inst6~0_combout\, + combout => \inst6~1_combout\); + +-- Location: LCCOMB_X1_Y24_N4 +\inst2|inst3|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst3|inst|inst~combout\ = \inst|inst3|inst1|inst~0_combout\ $ (\inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101010110101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datad => \inst6~1_combout\, + combout => \inst2|inst3|inst|inst~combout\); + +-- Location: LCCOMB_X1_Y24_N22 +\inst|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst1|inst~0_combout\ = \B2~input_o\ $ (\A2~input_o\ $ (\inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datac => \A2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y24_N0 +\inst2|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst2|inst1|inst~0_combout\ = \inst|inst2|inst1|inst~0_combout\ $ (((!\inst|inst3|inst1|inst~0_combout\ & \inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010111110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst2|inst1|inst~0_combout\, + datad => \inst6~1_combout\, + combout => \inst2|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y24_N26 +\inst2|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst|inst1|inst~0_combout\ = (\A3~input_o\ & (\inst|inst2|inst2~0_combout\ $ (\B3~input_o\ $ (!\inst6~0_combout\)))) # (!\A3~input_o\ & ((\inst|inst2|inst2~0_combout\ & (\B3~input_o\ $ (!\inst6~0_combout\))) # (!\inst|inst2|inst2~0_combout\ & +-- (\B3~input_o\ & !\inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100010010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|inst2|inst2~0_combout\, + datac => \B3~input_o\, + datad => \inst6~0_combout\, + combout => \inst2|inst|inst1|inst~0_combout\); + +ww_S0 <= \S0~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S3 <= \S3~output_o\; + +ww_C4 <= \C4~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_0c_vhd_slow.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_0c_vhd_slow.sdo new file mode 100644 index 00000000..746e36b6 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_0c_vhd_slow.sdo @@ -0,0 +1,307 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP3C16F484C6, +// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_1D") + (DATE "09/05/2019 20:29:14") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (293:293:293) (287:287:287)) + (IOPATH i o (2246:2246:2246) (2234:2234:2234)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (548:548:548) (546:546:546)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (548:548:548) (539:539:539)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (579:579:579) (591:591:591)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (614:614:614) (625:625:625)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst4\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT datab (2379:2379:2379) (2577:2577:2577)) + (PORT datac (2367:2367:2367) (2549:2549:2549)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst3\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2428:2428:2428) (2632:2632:2632)) + (PORT datab (2379:2379:2379) (2574:2574:2574)) + (PORT datac (2366:2366:2366) (2552:2552:2552)) + (PORT datad (2381:2381:2381) (2588:2588:2588)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (775:775:775) (936:936:936)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst3\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2428:2428:2428) (2632:2632:2632)) + (PORT datab (2379:2379:2379) (2574:2574:2574)) + (PORT datac (2366:2366:2366) (2550:2550:2550)) + (PORT datad (2381:2381:2381) (2588:2588:2588)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2420:2420:2420) (2624:2624:2624)) + (PORT datac (2403:2403:2403) (2610:2610:2610)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (2428:2428:2428) (2633:2633:2633)) + (PORT datac (2392:2392:2392) (2593:2593:2593)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2391:2391:2391) (2580:2580:2580)) + (PORT datab (192:192:192) (231:231:231)) + (PORT datac (2358:2358:2358) (2557:2557:2557)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst3\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (245:245:245)) + (PORT datad (185:185:185) (209:209:209)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2419:2419:2419) (2625:2625:2625)) + (PORT datac (2403:2403:2403) (2610:2610:2610)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst2\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (246:246:246)) + (PORT datac (160:160:160) (191:191:191)) + (PORT datad (185:185:185) (209:209:209)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2386:2386:2386) (2574:2574:2574)) + (PORT datab (190:190:190) (226:226:226)) + (PORT datac (2360:2360:2360) (2559:2559:2559)) + (PORT datad (169:169:169) (193:193:193)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_85c_slow.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_85c_slow.vho new file mode 100644 index 00000000..f8dcf5da --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_85c_slow.vho @@ -0,0 +1,458 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "09/05/2019 20:29:14" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_1D IS + PORT ( + S0 : OUT std_logic; + A3 : IN std_logic; + B3 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A1 : IN std_logic; + B1 : IN std_logic; + A0 : IN std_logic; + B0 : IN std_logic; + S1 : OUT std_logic; + S2 : OUT std_logic; + S3 : OUT std_logic; + C4 : OUT std_logic + ); +END BCD_adder_1D; + +-- Design Ports Information +-- S0 => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +-- S3 => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +-- C4 => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_H7, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_H6, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_J7, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_1D IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_C4 : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \C4~output_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \inst|inst4|inst|inst~combout\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \inst|inst3|inst1|inst~0_combout\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \inst6~0_combout\ : std_logic; +SIGNAL \inst6~1_combout\ : std_logic; +SIGNAL \inst2|inst3|inst|inst~combout\ : std_logic; +SIGNAL \inst|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst2|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst2|inst|inst1|inst~0_combout\ : std_logic; + +BEGIN + +S0 <= ww_S0; +ww_A3 <= A3; +ww_B3 <= B3; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A1 <= A1; +ww_B1 <= B1; +ww_A0 <= A0; +ww_B0 <= B0; +S1 <= ww_S1; +S2 <= ww_S2; +S3 <= ww_S3; +C4 <= ww_C4; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +-- Location: IOOBUF_X0_Y24_N16 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst4|inst|inst~combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst3|inst|inst~combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y26_N16 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst2|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y27_N9 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y27_N16 +\C4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst6~1_combout\, + devoe => ww_devoe, + o => \C4~output_o\); + +-- Location: IOIBUF_X0_Y25_N22 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X0_Y25_N15 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: LCCOMB_X1_Y24_N16 +\inst|inst4|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst4|inst|inst~combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datac => \A0~input_o\, + combout => \inst|inst4|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y23_N8 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: IOIBUF_X0_Y26_N8 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: LCCOMB_X1_Y24_N10 +\inst|inst3|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst3|inst1|inst~0_combout\ = \B1~input_o\ $ (\A1~input_o\ $ (((\B0~input_o\ & \A0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001010101101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \A1~input_o\, + combout => \inst|inst3|inst1|inst~0_combout\); + +-- Location: IOIBUF_X0_Y25_N1 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y27_N22 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: LCCOMB_X1_Y24_N12 +\inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst3|inst2~0_combout\ = (\B1~input_o\ & ((\A1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\B1~input_o\ & (\B0~input_o\ & (\A0~input_o\ & \A1~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \A1~input_o\, + combout => \inst|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y24_N24 +\inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst2~0_combout\ = (\B2~input_o\ & ((\A2~input_o\) # (\inst|inst3|inst2~0_combout\))) # (!\B2~input_o\ & (\A2~input_o\ & \inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datac => \A2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst|inst2|inst2~0_combout\); + +-- Location: IOIBUF_X0_Y22_N15 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: LCCOMB_X1_Y24_N6 +\inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~0_combout\ = (\inst|inst3|inst1|inst~0_combout\) # (\A2~input_o\ $ (\B2~input_o\ $ (\inst|inst3|inst2~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101110111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datab => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst6~0_combout\); + +-- Location: LCCOMB_X1_Y24_N2 +\inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~1_combout\ = (\A3~input_o\ & ((\inst|inst2|inst2~0_combout\) # ((\B3~input_o\) # (\inst6~0_combout\)))) # (!\A3~input_o\ & ((\inst|inst2|inst2~0_combout\ & ((\B3~input_o\) # (\inst6~0_combout\))) # (!\inst|inst2|inst2~0_combout\ & (\B3~input_o\ & +-- \inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|inst2|inst2~0_combout\, + datac => \B3~input_o\, + datad => \inst6~0_combout\, + combout => \inst6~1_combout\); + +-- Location: LCCOMB_X1_Y24_N4 +\inst2|inst3|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst3|inst|inst~combout\ = \inst|inst3|inst1|inst~0_combout\ $ (\inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101010110101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datad => \inst6~1_combout\, + combout => \inst2|inst3|inst|inst~combout\); + +-- Location: LCCOMB_X1_Y24_N22 +\inst|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst1|inst~0_combout\ = \B2~input_o\ $ (\A2~input_o\ $ (\inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datac => \A2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y24_N0 +\inst2|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst2|inst1|inst~0_combout\ = \inst|inst2|inst1|inst~0_combout\ $ (((!\inst|inst3|inst1|inst~0_combout\ & \inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010111110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst2|inst1|inst~0_combout\, + datad => \inst6~1_combout\, + combout => \inst2|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y24_N26 +\inst2|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst|inst1|inst~0_combout\ = (\A3~input_o\ & (\inst|inst2|inst2~0_combout\ $ (\B3~input_o\ $ (!\inst6~0_combout\)))) # (!\A3~input_o\ & ((\inst|inst2|inst2~0_combout\ & (\B3~input_o\ $ (!\inst6~0_combout\))) # (!\inst|inst2|inst2~0_combout\ & +-- (\B3~input_o\ & !\inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100010010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|inst2|inst2~0_combout\, + datac => \B3~input_o\, + datad => \inst6~0_combout\, + combout => \inst2|inst|inst1|inst~0_combout\); + +ww_S0 <= \S0~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S3 <= \S3~output_o\; + +ww_C4 <= \C4~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_85c_vhd_slow.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_85c_vhd_slow.sdo new file mode 100644 index 00000000..1075c651 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_6_1200mv_85c_vhd_slow.sdo @@ -0,0 +1,307 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP3C16F484C6, +// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_1D") + (DATE "09/05/2019 20:29:14") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (321:321:321) (324:324:324)) + (IOPATH i o (2246:2246:2246) (2234:2234:2234)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (599:599:599) (599:599:599)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (598:598:598) (594:594:594)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (633:633:633) (669:669:669)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (669:669:669) (705:705:705)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst4\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT datab (2773:2773:2773) (3030:3030:3030)) + (PORT datac (2755:2755:2755) (3003:3003:3003)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst3\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2823:2823:2823) (3096:3096:3096)) + (PORT datab (2773:2773:2773) (3031:3031:3031)) + (PORT datac (2755:2755:2755) (3004:3004:3004)) + (PORT datad (2771:2771:2771) (3047:3047:3047)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (775:775:775) (936:936:936)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst3\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2824:2824:2824) (3095:3095:3095)) + (PORT datab (2773:2773:2773) (3031:3031:3031)) + (PORT datac (2755:2755:2755) (3003:3003:3003)) + (PORT datad (2771:2771:2771) (3046:3046:3046)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2816:2816:2816) (3091:3091:3091)) + (PORT datac (2800:2800:2800) (3050:3050:3050)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (271:271:271)) + (PORT datab (2826:2826:2826) (3078:3078:3078)) + (PORT datac (2785:2785:2785) (3052:3052:3052)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2778:2778:2778) (3035:3035:3035)) + (PORT datab (212:212:212) (255:255:255)) + (PORT datac (2743:2743:2743) (2994:2994:2994)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst3\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (271:271:271)) + (PORT datad (203:203:203) (231:231:231)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2816:2816:2816) (3091:3091:3091)) + (PORT datac (2800:2800:2800) (3050:3050:3050)) + (PORT datad (190:190:190) (220:220:220)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst2\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (271:271:271)) + (PORT datac (176:176:176) (210:210:210)) + (PORT datad (204:204:204) (232:232:232)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2773:2773:2773) (3029:3029:3029)) + (PORT datab (209:209:209) (251:251:251)) + (PORT datac (2743:2743:2743) (2996:2996:2996)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G.sft b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G.sft new file mode 100644 index 00000000..5244a60e --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim-Altera (VHDL)" +set corner_file_list { + {{"Slow -6 1.2V 85 Model"} {BCD_adder_1D_G_6_1200mv_85c_slow.vho BCD_adder_1D_G_6_1200mv_85c_vhd_slow.sdo}} + {{"Slow -6 1.2V 0 Model"} {BCD_adder_1D_G_6_1200mv_0c_slow.vho BCD_adder_1D_G_6_1200mv_0c_vhd_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {BCD_adder_1D_G_min_1200mv_0c_fast.vho BCD_adder_1D_G_min_1200mv_0c_vhd_fast.sdo}} +} diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G.vho new file mode 100644 index 00000000..e5897f0d --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G.vho @@ -0,0 +1,926 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "09/09/2019 21:06:05" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_1D_G IS + PORT ( + S3 : OUT std_logic; + A3 : IN std_logic; + B3 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A1 : IN std_logic; + B1 : IN std_logic; + A0 : IN std_logic; + B0 : IN std_logic; + S2 : OUT std_logic; + S1 : OUT std_logic; + S0 : OUT std_logic; + S7 : OUT std_logic; + A7 : IN std_logic; + B7 : IN std_logic; + A6 : IN std_logic; + B6 : IN std_logic; + A5 : IN std_logic; + B5 : IN std_logic; + A4 : IN std_logic; + B4 : IN std_logic; + S6 : OUT std_logic; + S5 : OUT std_logic; + S4 : OUT std_logic; + C8 : OUT std_logic + ); +END BCD_adder_1D_G; + +-- Design Ports Information +-- S3 => Location: PIN_R2, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_P4, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_V2, I/O Standard: 2.5 V, Current Strength: Default +-- S0 => Location: PIN_U2, I/O Standard: 2.5 V, Current Strength: Default +-- S7 => Location: PIN_K7, I/O Standard: 2.5 V, Current Strength: Default +-- S6 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S5 => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +-- S4 => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +-- C8 => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_U8, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_AA5, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_R1, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_P5, I/O Standard: 2.5 V, Current Strength: Default +-- B7 => Location: PIN_J4, I/O Standard: 2.5 V, Current Strength: Default +-- A4 => Location: PIN_H5, I/O Standard: 2.5 V, Current Strength: Default +-- B4 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- A5 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +-- B5 => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +-- A6 => Location: PIN_K8, I/O Standard: 2.5 V, Current Strength: Default +-- B6 => Location: PIN_J3, I/O Standard: 2.5 V, Current Strength: Default +-- A7 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_1D_G IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_S7 : std_logic; +SIGNAL ww_A7 : std_logic; +SIGNAL ww_B7 : std_logic; +SIGNAL ww_A6 : std_logic; +SIGNAL ww_B6 : std_logic; +SIGNAL ww_A5 : std_logic; +SIGNAL ww_B5 : std_logic; +SIGNAL ww_A4 : std_logic; +SIGNAL ww_B4 : std_logic; +SIGNAL ww_S6 : std_logic; +SIGNAL ww_S5 : std_logic; +SIGNAL ww_S4 : std_logic; +SIGNAL ww_C8 : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S7~output_o\ : std_logic; +SIGNAL \S6~output_o\ : std_logic; +SIGNAL \S5~output_o\ : std_logic; +SIGNAL \S4~output_o\ : std_logic; +SIGNAL \C8~output_o\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \inst|inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \inst|inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst|inst|inst3|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst6~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst6~1_combout\ : std_logic; +SIGNAL \inst|inst|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst3|inst|inst~combout\ : std_logic; +SIGNAL \inst|inst|inst4|inst|inst~combout\ : std_logic; +SIGNAL \B7~input_o\ : std_logic; +SIGNAL \B6~input_o\ : std_logic; +SIGNAL \A6~input_o\ : std_logic; +SIGNAL \inst4|inst|inst2|inst|inst~combout\ : std_logic; +SIGNAL \A4~input_o\ : std_logic; +SIGNAL \B4~input_o\ : std_logic; +SIGNAL \inst4|inst|inst4|inst2~1_combout\ : std_logic; +SIGNAL \B5~input_o\ : std_logic; +SIGNAL \inst4|inst|inst4|inst2~0_combout\ : std_logic; +SIGNAL \A5~input_o\ : std_logic; +SIGNAL \inst4|inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst|inst3|inst1|inst~combout\ : std_logic; +SIGNAL \A7~input_o\ : std_logic; +SIGNAL \inst4|inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst6~0_combout\ : std_logic; +SIGNAL \inst4|inst6~1_combout\ : std_logic; +SIGNAL \inst4|inst2|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst2|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst|inst|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst4|inst2|inst|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst2|inst2|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst2|inst3|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst|inst4|inst1|inst~combout\ : std_logic; + +BEGIN + +S3 <= ww_S3; +ww_A3 <= A3; +ww_B3 <= B3; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A1 <= A1; +ww_B1 <= B1; +ww_A0 <= A0; +ww_B0 <= B0; +S2 <= ww_S2; +S1 <= ww_S1; +S0 <= ww_S0; +S7 <= ww_S7; +ww_A7 <= A7; +ww_B7 <= B7; +ww_A6 <= A6; +ww_B6 <= B6; +ww_A5 <= A5; +ww_B5 <= B5; +ww_A4 <= A4; +ww_B4 <= B4; +S6 <= ww_S6; +S5 <= ww_S5; +S4 <= ww_S4; +C8 <= ww_C8; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +-- Location: IOOBUF_X0_Y10_N2 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y10_N23 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst2|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y9_N23 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst3|inst|inst~combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y9_N9 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst|inst4|inst|inst~combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y22_N23 +\S7~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst|inst1|inst~combout\, + devoe => ww_devoe, + o => \S7~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S6~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst2|inst1|inst~combout\, + devoe => ww_devoe, + o => \S6~output_o\); + +-- Location: IOOBUF_X1_Y29_N23 +\S5~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst3|inst1|inst~combout\, + devoe => ww_devoe, + o => \S5~output_o\); + +-- Location: IOOBUF_X0_Y22_N2 +\S4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst|inst4|inst1|inst~combout\, + devoe => ww_devoe, + o => \S4~output_o\); + +-- Location: IOOBUF_X0_Y21_N16 +\C8~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst6~1_combout\, + devoe => ww_devoe, + o => \C8~output_o\); + +-- Location: IOIBUF_X0_Y12_N22 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y11_N1 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: IOIBUF_X0_Y10_N15 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: IOIBUF_X0_Y10_N8 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: IOIBUF_X3_Y0_N15 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X9_Y0_N29 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: IOIBUF_X0_Y8_N8 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: LCCOMB_X1_Y10_N24 +\inst|inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst3|inst2~0_combout\ = (\A1~input_o\ & ((\B1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\A1~input_o\ & (\B0~input_o\ & (\A0~input_o\ & \B1~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \B1~input_o\, + combout => \inst|inst|inst3|inst2~0_combout\); + +-- Location: IOIBUF_X3_Y0_N22 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: LCCOMB_X1_Y10_N26 +\inst|inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst2|inst2~0_combout\ = (\B2~input_o\ & ((\inst|inst|inst3|inst2~0_combout\) # (\A2~input_o\))) # (!\B2~input_o\ & (\inst|inst|inst3|inst2~0_combout\ & \A2~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datab => \inst|inst|inst3|inst2~0_combout\, + datad => \A2~input_o\, + combout => \inst|inst|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y10_N12 +\inst|inst|inst3|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst3|inst1|inst~0_combout\ = \A1~input_o\ $ (\B1~input_o\ $ (((\B0~input_o\ & \A0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001010101101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \B1~input_o\, + combout => \inst|inst|inst3|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N6 +\inst|inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst6~0_combout\ = (\inst|inst|inst3|inst1|inst~0_combout\) # (\inst|inst|inst3|inst2~0_combout\ $ (\B2~input_o\ $ (\A2~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101110111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datab => \inst|inst|inst3|inst2~0_combout\, + datac => \B2~input_o\, + datad => \A2~input_o\, + combout => \inst|inst6~0_combout\); + +-- Location: LCCOMB_X1_Y10_N0 +\inst|inst2|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst|inst1|inst~0_combout\ = (\A3~input_o\ & (\B3~input_o\ $ (\inst|inst|inst2|inst2~0_combout\ $ (!\inst|inst6~0_combout\)))) # (!\A3~input_o\ & ((\B3~input_o\ & (\inst|inst|inst2|inst2~0_combout\ $ (!\inst|inst6~0_combout\))) # +-- (!\B3~input_o\ & (\inst|inst|inst2|inst2~0_combout\ & !\inst|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100010010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \B3~input_o\, + datac => \inst|inst|inst2|inst2~0_combout\, + datad => \inst|inst6~0_combout\, + combout => \inst|inst2|inst|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N4 +\inst|inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst6~1_combout\ = (\A3~input_o\ & ((\B3~input_o\) # ((\inst|inst|inst2|inst2~0_combout\) # (\inst|inst6~0_combout\)))) # (!\A3~input_o\ & ((\B3~input_o\ & ((\inst|inst|inst2|inst2~0_combout\) # (\inst|inst6~0_combout\))) # (!\B3~input_o\ & +-- (\inst|inst|inst2|inst2~0_combout\ & \inst|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \B3~input_o\, + datac => \inst|inst|inst2|inst2~0_combout\, + datad => \inst|inst6~0_combout\, + combout => \inst|inst6~1_combout\); + +-- Location: LCCOMB_X1_Y10_N18 +\inst|inst|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst2|inst1|inst~0_combout\ = \B2~input_o\ $ (\inst|inst|inst3|inst2~0_combout\ $ (\A2~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001100101100110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datab => \inst|inst|inst3|inst2~0_combout\, + datad => \A2~input_o\, + combout => \inst|inst|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N14 +\inst|inst2|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst2|inst1|inst~0_combout\ = \inst|inst|inst2|inst1|inst~0_combout\ $ (((!\inst|inst|inst3|inst1|inst~0_combout\ & \inst|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010111101010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst6~1_combout\, + datad => \inst|inst|inst2|inst1|inst~0_combout\, + combout => \inst|inst2|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N16 +\inst|inst2|inst3|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst3|inst|inst~combout\ = \inst|inst|inst3|inst1|inst~0_combout\ $ (\inst|inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst6~1_combout\, + combout => \inst|inst2|inst3|inst|inst~combout\); + +-- Location: LCCOMB_X1_Y10_N2 +\inst|inst|inst4|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst4|inst|inst~combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datac => \A0~input_o\, + combout => \inst|inst|inst4|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y21_N1 +\B7~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B7, + o => \B7~input_o\); + +-- Location: IOIBUF_X0_Y21_N22 +\B6~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B6, + o => \B6~input_o\); + +-- Location: IOIBUF_X0_Y22_N8 +\A6~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A6, + o => \A6~input_o\); + +-- Location: LCCOMB_X1_Y21_N24 +\inst4|inst|inst2|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst2|inst|inst~combout\ = \B6~input_o\ $ (\A6~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datac => \A6~input_o\, + combout => \inst4|inst|inst2|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y27_N1 +\A4~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A4, + o => \A4~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\B4~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B4, + o => \B4~input_o\); + +-- Location: LCCOMB_X1_Y21_N10 +\inst4|inst|inst4|inst2~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst2~1_combout\ = (\B4~input_o\ & ((\A4~input_o\) # (\inst|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111000010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datac => \B4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst2~1_combout\); + +-- Location: IOIBUF_X0_Y21_N8 +\B5~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B5, + o => \B5~input_o\); + +-- Location: LCCOMB_X1_Y21_N8 +\inst4|inst|inst4|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst2~0_combout\ = (\A4~input_o\ & \inst|inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010101000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst2~0_combout\); + +-- Location: IOIBUF_X0_Y23_N8 +\A5~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A5, + o => \A5~input_o\); + +-- Location: LCCOMB_X1_Y21_N28 +\inst4|inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst3|inst2~0_combout\ = (\B5~input_o\ & ((\inst4|inst|inst4|inst2~1_combout\) # ((\inst4|inst|inst4|inst2~0_combout\) # (\A5~input_o\)))) # (!\B5~input_o\ & (\A5~input_o\ & ((\inst4|inst|inst4|inst2~1_combout\) # +-- (\inst4|inst|inst4|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst4|inst2~1_combout\, + datab => \B5~input_o\, + datac => \inst4|inst|inst4|inst2~0_combout\, + datad => \A5~input_o\, + combout => \inst4|inst|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N18 +\inst4|inst|inst3|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst3|inst1|inst~combout\ = \B5~input_o\ $ (\A5~input_o\ $ (((\inst4|inst|inst4|inst2~1_combout\) # (\inst4|inst|inst4|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100100100110110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst4|inst2~1_combout\, + datab => \B5~input_o\, + datac => \inst4|inst|inst4|inst2~0_combout\, + datad => \A5~input_o\, + combout => \inst4|inst|inst3|inst1|inst~combout\); + +-- Location: IOIBUF_X0_Y27_N22 +\A7~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A7, + o => \A7~input_o\); + +-- Location: LCCOMB_X1_Y21_N22 +\inst4|inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst2|inst2~0_combout\ = (\B6~input_o\ & ((\A6~input_o\) # (\inst4|inst|inst3|inst2~0_combout\))) # (!\B6~input_o\ & (\A6~input_o\ & \inst4|inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst2~0_combout\, + combout => \inst4|inst|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N20 +\inst4|inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst6~0_combout\ = (\inst4|inst|inst3|inst1|inst~combout\) # (\B6~input_o\ $ (\inst4|inst|inst3|inst2~0_combout\ $ (\A6~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst1|inst~combout\, + combout => \inst4|inst6~0_combout\); + +-- Location: LCCOMB_X1_Y21_N16 +\inst4|inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst6~1_combout\ = (\B7~input_o\ & ((\A7~input_o\) # ((\inst4|inst|inst2|inst2~0_combout\) # (\inst4|inst6~0_combout\)))) # (!\B7~input_o\ & ((\A7~input_o\ & ((\inst4|inst|inst2|inst2~0_combout\) # (\inst4|inst6~0_combout\))) # (!\A7~input_o\ & +-- (\inst4|inst|inst2|inst2~0_combout\ & \inst4|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B7~input_o\, + datab => \A7~input_o\, + datac => \inst4|inst|inst2|inst2~0_combout\, + datad => \inst4|inst6~0_combout\, + combout => \inst4|inst6~1_combout\); + +-- Location: LCCOMB_X1_Y21_N26 +\inst4|inst2|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst3|inst2~0_combout\ = (\inst|inst6~1_combout\ & ((\inst4|inst|inst3|inst1|inst~combout\) # (\inst4|inst6~1_combout\))) # (!\inst|inst6~1_combout\ & (\inst4|inst|inst3|inst1|inst~combout\ & \inst4|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \inst4|inst|inst3|inst1|inst~combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N4 +\inst4|inst2|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst2|inst2~0_combout\ = (\inst4|inst2|inst3|inst2~0_combout\ & ((\inst4|inst6~1_combout\) # (\inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\)))) # (!\inst4|inst2|inst3|inst2~0_combout\ & (\inst4|inst6~1_combout\ & +-- (\inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111011001100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst2|inst|inst~combout\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \inst4|inst2|inst3|inst2~0_combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N6 +\inst4|inst|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst|inst1|inst~0_combout\ = \A7~input_o\ $ (((\B6~input_o\ & ((\A6~input_o\) # (\inst4|inst|inst3|inst2~0_combout\))) # (!\B6~input_o\ & (\A6~input_o\ & \inst4|inst|inst3|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011011001101100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datab => \A7~input_o\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst2~0_combout\, + combout => \inst4|inst|inst|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y21_N14 +\inst4|inst2|inst|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst|inst1|inst~combout\ = \inst|inst6~1_combout\ $ (\B7~input_o\ $ (\inst4|inst2|inst2|inst2~0_combout\ $ (\inst4|inst|inst|inst1|inst~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \B7~input_o\, + datac => \inst4|inst2|inst2|inst2~0_combout\, + datad => \inst4|inst|inst|inst1|inst~0_combout\, + combout => \inst4|inst2|inst|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N0 +\inst4|inst2|inst2|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst2|inst1|inst~combout\ = \inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\ $ (\inst4|inst2|inst3|inst2~0_combout\ $ (\inst4|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst2|inst|inst~combout\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \inst4|inst2|inst3|inst2~0_combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst2|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N2 +\inst4|inst2|inst3|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst3|inst1|inst~combout\ = \inst|inst6~1_combout\ $ (\inst4|inst|inst3|inst1|inst~combout\ $ (\inst4|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001100101100110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \inst4|inst|inst3|inst1|inst~combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst3|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N12 +\inst4|inst|inst4|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst1|inst~combout\ = \A4~input_o\ $ (\B4~input_o\ $ (\inst|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datac => \B4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst1|inst~combout\); + +ww_S3 <= \S3~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S0 <= \S0~output_o\; + +ww_S7 <= \S7~output_o\; + +ww_S6 <= \S6~output_o\; + +ww_S5 <= \S5~output_o\; + +ww_S4 <= \S4~output_o\; + +ww_C8 <= \C8~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_0c_slow.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_0c_slow.vho new file mode 100644 index 00000000..e5897f0d --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_0c_slow.vho @@ -0,0 +1,926 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "09/09/2019 21:06:05" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_1D_G IS + PORT ( + S3 : OUT std_logic; + A3 : IN std_logic; + B3 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A1 : IN std_logic; + B1 : IN std_logic; + A0 : IN std_logic; + B0 : IN std_logic; + S2 : OUT std_logic; + S1 : OUT std_logic; + S0 : OUT std_logic; + S7 : OUT std_logic; + A7 : IN std_logic; + B7 : IN std_logic; + A6 : IN std_logic; + B6 : IN std_logic; + A5 : IN std_logic; + B5 : IN std_logic; + A4 : IN std_logic; + B4 : IN std_logic; + S6 : OUT std_logic; + S5 : OUT std_logic; + S4 : OUT std_logic; + C8 : OUT std_logic + ); +END BCD_adder_1D_G; + +-- Design Ports Information +-- S3 => Location: PIN_R2, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_P4, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_V2, I/O Standard: 2.5 V, Current Strength: Default +-- S0 => Location: PIN_U2, I/O Standard: 2.5 V, Current Strength: Default +-- S7 => Location: PIN_K7, I/O Standard: 2.5 V, Current Strength: Default +-- S6 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S5 => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +-- S4 => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +-- C8 => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_U8, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_AA5, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_R1, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_P5, I/O Standard: 2.5 V, Current Strength: Default +-- B7 => Location: PIN_J4, I/O Standard: 2.5 V, Current Strength: Default +-- A4 => Location: PIN_H5, I/O Standard: 2.5 V, Current Strength: Default +-- B4 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- A5 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +-- B5 => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +-- A6 => Location: PIN_K8, I/O Standard: 2.5 V, Current Strength: Default +-- B6 => Location: PIN_J3, I/O Standard: 2.5 V, Current Strength: Default +-- A7 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_1D_G IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_S7 : std_logic; +SIGNAL ww_A7 : std_logic; +SIGNAL ww_B7 : std_logic; +SIGNAL ww_A6 : std_logic; +SIGNAL ww_B6 : std_logic; +SIGNAL ww_A5 : std_logic; +SIGNAL ww_B5 : std_logic; +SIGNAL ww_A4 : std_logic; +SIGNAL ww_B4 : std_logic; +SIGNAL ww_S6 : std_logic; +SIGNAL ww_S5 : std_logic; +SIGNAL ww_S4 : std_logic; +SIGNAL ww_C8 : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S7~output_o\ : std_logic; +SIGNAL \S6~output_o\ : std_logic; +SIGNAL \S5~output_o\ : std_logic; +SIGNAL \S4~output_o\ : std_logic; +SIGNAL \C8~output_o\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \inst|inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \inst|inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst|inst|inst3|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst6~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst6~1_combout\ : std_logic; +SIGNAL \inst|inst|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst3|inst|inst~combout\ : std_logic; +SIGNAL \inst|inst|inst4|inst|inst~combout\ : std_logic; +SIGNAL \B7~input_o\ : std_logic; +SIGNAL \B6~input_o\ : std_logic; +SIGNAL \A6~input_o\ : std_logic; +SIGNAL \inst4|inst|inst2|inst|inst~combout\ : std_logic; +SIGNAL \A4~input_o\ : std_logic; +SIGNAL \B4~input_o\ : std_logic; +SIGNAL \inst4|inst|inst4|inst2~1_combout\ : std_logic; +SIGNAL \B5~input_o\ : std_logic; +SIGNAL \inst4|inst|inst4|inst2~0_combout\ : std_logic; +SIGNAL \A5~input_o\ : std_logic; +SIGNAL \inst4|inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst|inst3|inst1|inst~combout\ : std_logic; +SIGNAL \A7~input_o\ : std_logic; +SIGNAL \inst4|inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst6~0_combout\ : std_logic; +SIGNAL \inst4|inst6~1_combout\ : std_logic; +SIGNAL \inst4|inst2|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst2|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst|inst|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst4|inst2|inst|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst2|inst2|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst2|inst3|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst|inst4|inst1|inst~combout\ : std_logic; + +BEGIN + +S3 <= ww_S3; +ww_A3 <= A3; +ww_B3 <= B3; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A1 <= A1; +ww_B1 <= B1; +ww_A0 <= A0; +ww_B0 <= B0; +S2 <= ww_S2; +S1 <= ww_S1; +S0 <= ww_S0; +S7 <= ww_S7; +ww_A7 <= A7; +ww_B7 <= B7; +ww_A6 <= A6; +ww_B6 <= B6; +ww_A5 <= A5; +ww_B5 <= B5; +ww_A4 <= A4; +ww_B4 <= B4; +S6 <= ww_S6; +S5 <= ww_S5; +S4 <= ww_S4; +C8 <= ww_C8; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +-- Location: IOOBUF_X0_Y10_N2 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y10_N23 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst2|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y9_N23 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst3|inst|inst~combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y9_N9 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst|inst4|inst|inst~combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y22_N23 +\S7~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst|inst1|inst~combout\, + devoe => ww_devoe, + o => \S7~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S6~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst2|inst1|inst~combout\, + devoe => ww_devoe, + o => \S6~output_o\); + +-- Location: IOOBUF_X1_Y29_N23 +\S5~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst3|inst1|inst~combout\, + devoe => ww_devoe, + o => \S5~output_o\); + +-- Location: IOOBUF_X0_Y22_N2 +\S4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst|inst4|inst1|inst~combout\, + devoe => ww_devoe, + o => \S4~output_o\); + +-- Location: IOOBUF_X0_Y21_N16 +\C8~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst6~1_combout\, + devoe => ww_devoe, + o => \C8~output_o\); + +-- Location: IOIBUF_X0_Y12_N22 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y11_N1 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: IOIBUF_X0_Y10_N15 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: IOIBUF_X0_Y10_N8 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: IOIBUF_X3_Y0_N15 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X9_Y0_N29 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: IOIBUF_X0_Y8_N8 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: LCCOMB_X1_Y10_N24 +\inst|inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst3|inst2~0_combout\ = (\A1~input_o\ & ((\B1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\A1~input_o\ & (\B0~input_o\ & (\A0~input_o\ & \B1~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \B1~input_o\, + combout => \inst|inst|inst3|inst2~0_combout\); + +-- Location: IOIBUF_X3_Y0_N22 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: LCCOMB_X1_Y10_N26 +\inst|inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst2|inst2~0_combout\ = (\B2~input_o\ & ((\inst|inst|inst3|inst2~0_combout\) # (\A2~input_o\))) # (!\B2~input_o\ & (\inst|inst|inst3|inst2~0_combout\ & \A2~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datab => \inst|inst|inst3|inst2~0_combout\, + datad => \A2~input_o\, + combout => \inst|inst|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y10_N12 +\inst|inst|inst3|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst3|inst1|inst~0_combout\ = \A1~input_o\ $ (\B1~input_o\ $ (((\B0~input_o\ & \A0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001010101101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \B1~input_o\, + combout => \inst|inst|inst3|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N6 +\inst|inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst6~0_combout\ = (\inst|inst|inst3|inst1|inst~0_combout\) # (\inst|inst|inst3|inst2~0_combout\ $ (\B2~input_o\ $ (\A2~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101110111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datab => \inst|inst|inst3|inst2~0_combout\, + datac => \B2~input_o\, + datad => \A2~input_o\, + combout => \inst|inst6~0_combout\); + +-- Location: LCCOMB_X1_Y10_N0 +\inst|inst2|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst|inst1|inst~0_combout\ = (\A3~input_o\ & (\B3~input_o\ $ (\inst|inst|inst2|inst2~0_combout\ $ (!\inst|inst6~0_combout\)))) # (!\A3~input_o\ & ((\B3~input_o\ & (\inst|inst|inst2|inst2~0_combout\ $ (!\inst|inst6~0_combout\))) # +-- (!\B3~input_o\ & (\inst|inst|inst2|inst2~0_combout\ & !\inst|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100010010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \B3~input_o\, + datac => \inst|inst|inst2|inst2~0_combout\, + datad => \inst|inst6~0_combout\, + combout => \inst|inst2|inst|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N4 +\inst|inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst6~1_combout\ = (\A3~input_o\ & ((\B3~input_o\) # ((\inst|inst|inst2|inst2~0_combout\) # (\inst|inst6~0_combout\)))) # (!\A3~input_o\ & ((\B3~input_o\ & ((\inst|inst|inst2|inst2~0_combout\) # (\inst|inst6~0_combout\))) # (!\B3~input_o\ & +-- (\inst|inst|inst2|inst2~0_combout\ & \inst|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \B3~input_o\, + datac => \inst|inst|inst2|inst2~0_combout\, + datad => \inst|inst6~0_combout\, + combout => \inst|inst6~1_combout\); + +-- Location: LCCOMB_X1_Y10_N18 +\inst|inst|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst2|inst1|inst~0_combout\ = \B2~input_o\ $ (\inst|inst|inst3|inst2~0_combout\ $ (\A2~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001100101100110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datab => \inst|inst|inst3|inst2~0_combout\, + datad => \A2~input_o\, + combout => \inst|inst|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N14 +\inst|inst2|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst2|inst1|inst~0_combout\ = \inst|inst|inst2|inst1|inst~0_combout\ $ (((!\inst|inst|inst3|inst1|inst~0_combout\ & \inst|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010111101010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst6~1_combout\, + datad => \inst|inst|inst2|inst1|inst~0_combout\, + combout => \inst|inst2|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N16 +\inst|inst2|inst3|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst3|inst|inst~combout\ = \inst|inst|inst3|inst1|inst~0_combout\ $ (\inst|inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst6~1_combout\, + combout => \inst|inst2|inst3|inst|inst~combout\); + +-- Location: LCCOMB_X1_Y10_N2 +\inst|inst|inst4|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst4|inst|inst~combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datac => \A0~input_o\, + combout => \inst|inst|inst4|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y21_N1 +\B7~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B7, + o => \B7~input_o\); + +-- Location: IOIBUF_X0_Y21_N22 +\B6~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B6, + o => \B6~input_o\); + +-- Location: IOIBUF_X0_Y22_N8 +\A6~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A6, + o => \A6~input_o\); + +-- Location: LCCOMB_X1_Y21_N24 +\inst4|inst|inst2|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst2|inst|inst~combout\ = \B6~input_o\ $ (\A6~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datac => \A6~input_o\, + combout => \inst4|inst|inst2|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y27_N1 +\A4~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A4, + o => \A4~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\B4~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B4, + o => \B4~input_o\); + +-- Location: LCCOMB_X1_Y21_N10 +\inst4|inst|inst4|inst2~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst2~1_combout\ = (\B4~input_o\ & ((\A4~input_o\) # (\inst|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111000010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datac => \B4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst2~1_combout\); + +-- Location: IOIBUF_X0_Y21_N8 +\B5~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B5, + o => \B5~input_o\); + +-- Location: LCCOMB_X1_Y21_N8 +\inst4|inst|inst4|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst2~0_combout\ = (\A4~input_o\ & \inst|inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010101000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst2~0_combout\); + +-- Location: IOIBUF_X0_Y23_N8 +\A5~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A5, + o => \A5~input_o\); + +-- Location: LCCOMB_X1_Y21_N28 +\inst4|inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst3|inst2~0_combout\ = (\B5~input_o\ & ((\inst4|inst|inst4|inst2~1_combout\) # ((\inst4|inst|inst4|inst2~0_combout\) # (\A5~input_o\)))) # (!\B5~input_o\ & (\A5~input_o\ & ((\inst4|inst|inst4|inst2~1_combout\) # +-- (\inst4|inst|inst4|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst4|inst2~1_combout\, + datab => \B5~input_o\, + datac => \inst4|inst|inst4|inst2~0_combout\, + datad => \A5~input_o\, + combout => \inst4|inst|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N18 +\inst4|inst|inst3|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst3|inst1|inst~combout\ = \B5~input_o\ $ (\A5~input_o\ $ (((\inst4|inst|inst4|inst2~1_combout\) # (\inst4|inst|inst4|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100100100110110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst4|inst2~1_combout\, + datab => \B5~input_o\, + datac => \inst4|inst|inst4|inst2~0_combout\, + datad => \A5~input_o\, + combout => \inst4|inst|inst3|inst1|inst~combout\); + +-- Location: IOIBUF_X0_Y27_N22 +\A7~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A7, + o => \A7~input_o\); + +-- Location: LCCOMB_X1_Y21_N22 +\inst4|inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst2|inst2~0_combout\ = (\B6~input_o\ & ((\A6~input_o\) # (\inst4|inst|inst3|inst2~0_combout\))) # (!\B6~input_o\ & (\A6~input_o\ & \inst4|inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst2~0_combout\, + combout => \inst4|inst|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N20 +\inst4|inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst6~0_combout\ = (\inst4|inst|inst3|inst1|inst~combout\) # (\B6~input_o\ $ (\inst4|inst|inst3|inst2~0_combout\ $ (\A6~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst1|inst~combout\, + combout => \inst4|inst6~0_combout\); + +-- Location: LCCOMB_X1_Y21_N16 +\inst4|inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst6~1_combout\ = (\B7~input_o\ & ((\A7~input_o\) # ((\inst4|inst|inst2|inst2~0_combout\) # (\inst4|inst6~0_combout\)))) # (!\B7~input_o\ & ((\A7~input_o\ & ((\inst4|inst|inst2|inst2~0_combout\) # (\inst4|inst6~0_combout\))) # (!\A7~input_o\ & +-- (\inst4|inst|inst2|inst2~0_combout\ & \inst4|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B7~input_o\, + datab => \A7~input_o\, + datac => \inst4|inst|inst2|inst2~0_combout\, + datad => \inst4|inst6~0_combout\, + combout => \inst4|inst6~1_combout\); + +-- Location: LCCOMB_X1_Y21_N26 +\inst4|inst2|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst3|inst2~0_combout\ = (\inst|inst6~1_combout\ & ((\inst4|inst|inst3|inst1|inst~combout\) # (\inst4|inst6~1_combout\))) # (!\inst|inst6~1_combout\ & (\inst4|inst|inst3|inst1|inst~combout\ & \inst4|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \inst4|inst|inst3|inst1|inst~combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N4 +\inst4|inst2|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst2|inst2~0_combout\ = (\inst4|inst2|inst3|inst2~0_combout\ & ((\inst4|inst6~1_combout\) # (\inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\)))) # (!\inst4|inst2|inst3|inst2~0_combout\ & (\inst4|inst6~1_combout\ & +-- (\inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111011001100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst2|inst|inst~combout\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \inst4|inst2|inst3|inst2~0_combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N6 +\inst4|inst|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst|inst1|inst~0_combout\ = \A7~input_o\ $ (((\B6~input_o\ & ((\A6~input_o\) # (\inst4|inst|inst3|inst2~0_combout\))) # (!\B6~input_o\ & (\A6~input_o\ & \inst4|inst|inst3|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011011001101100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datab => \A7~input_o\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst2~0_combout\, + combout => \inst4|inst|inst|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y21_N14 +\inst4|inst2|inst|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst|inst1|inst~combout\ = \inst|inst6~1_combout\ $ (\B7~input_o\ $ (\inst4|inst2|inst2|inst2~0_combout\ $ (\inst4|inst|inst|inst1|inst~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \B7~input_o\, + datac => \inst4|inst2|inst2|inst2~0_combout\, + datad => \inst4|inst|inst|inst1|inst~0_combout\, + combout => \inst4|inst2|inst|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N0 +\inst4|inst2|inst2|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst2|inst1|inst~combout\ = \inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\ $ (\inst4|inst2|inst3|inst2~0_combout\ $ (\inst4|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst2|inst|inst~combout\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \inst4|inst2|inst3|inst2~0_combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst2|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N2 +\inst4|inst2|inst3|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst3|inst1|inst~combout\ = \inst|inst6~1_combout\ $ (\inst4|inst|inst3|inst1|inst~combout\ $ (\inst4|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001100101100110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \inst4|inst|inst3|inst1|inst~combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst3|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N12 +\inst4|inst|inst4|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst1|inst~combout\ = \A4~input_o\ $ (\B4~input_o\ $ (\inst|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datac => \B4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst1|inst~combout\); + +ww_S3 <= \S3~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S0 <= \S0~output_o\; + +ww_S7 <= \S7~output_o\; + +ww_S6 <= \S6~output_o\; + +ww_S5 <= \S5~output_o\; + +ww_S4 <= \S4~output_o\; + +ww_C8 <= \C8~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_0c_vhd_slow.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_0c_vhd_slow.sdo new file mode 100644 index 00000000..b9956632 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_0c_vhd_slow.sdo @@ -0,0 +1,641 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP3C16F484C6, +// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_1D_G") + (DATE "09/09/2019 21:06:05") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (299:299:299) (295:295:295)) + (IOPATH i o (2236:2236:2236) (2224:2224:2224)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (295:295:295) (292:292:292)) + (IOPATH i o (2226:2226:2226) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (552:552:552) (543:543:543)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (570:570:570) (567:567:567)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S7\~output\\) + (DELAY + (ABSOLUTE + (PORT i (526:526:526) (508:508:508)) + (IOPATH i o (2226:2226:2226) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S6\~output\\) + (DELAY + (ABSOLUTE + (PORT i (709:709:709) (692:692:692)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S5\~output\\) + (DELAY + (ABSOLUTE + (PORT i (745:745:745) (752:752:752)) + (IOPATH i o (2060:2060:2060) (2009:2009:2009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (553:553:553) (538:538:538)) + (IOPATH i o (2226:2226:2226) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C8\~output\\) + (DELAY + (ABSOLUTE + (PORT i (313:313:313) (305:305:305)) + (IOPATH i o (2236:2236:2236) (2224:2224:2224)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (745:745:745) (906:906:906)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (715:715:715) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (715:715:715) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (745:745:745) (906:906:906)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (679:679:679) (842:842:842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (739:739:739) (902:902:902)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst\|inst3\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2168:2168:2168) (2366:2366:2366)) + (PORT datab (2807:2807:2807) (3030:3030:3030)) + (PORT datac (2750:2750:2750) (2950:2950:2950)) + (PORT datad (2395:2395:2395) (2599:2599:2599)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (689:689:689) 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(197:197:197) (226:226:226)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst2\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (350:350:350)) + (PORT datab (211:211:211) (261:261:261)) + (PORT datac (165:165:165) (199:199:199)) + (PORT datad (199:199:199) (229:229:229)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2154:2154:2154) (2372:2372:2372)) + (PORT datab (2679:2679:2679) (2895:2895:2895)) + (PORT datac (2353:2353:2353) (2546:2546:2546)) + (PORT datad (185:185:185) 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(202:202:202)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst3\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (995:995:995)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (200:200:200) (228:228:228)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst4\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (2673:2673:2673) (2877:2877:2877)) + (PORT datac (2582:2582:2582) (2772:2772:2772)) + (PORT datad (967:967:967) (961:961:961)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_85c_slow.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_85c_slow.vho new file mode 100644 index 00000000..e5897f0d --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_85c_slow.vho @@ -0,0 +1,926 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "09/09/2019 21:06:05" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_1D_G IS + PORT ( + S3 : OUT std_logic; + A3 : IN std_logic; + B3 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A1 : IN std_logic; + B1 : IN std_logic; + A0 : IN std_logic; + B0 : IN std_logic; + S2 : OUT std_logic; + S1 : OUT std_logic; + S0 : OUT std_logic; + S7 : OUT std_logic; + A7 : IN std_logic; + B7 : IN std_logic; + A6 : IN std_logic; + B6 : IN std_logic; + A5 : IN std_logic; + B5 : IN std_logic; + A4 : IN std_logic; + B4 : IN std_logic; + S6 : OUT std_logic; + S5 : OUT std_logic; + S4 : OUT std_logic; + C8 : OUT std_logic + ); +END BCD_adder_1D_G; + +-- Design Ports Information +-- S3 => Location: PIN_R2, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_P4, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_V2, I/O Standard: 2.5 V, Current Strength: Default +-- S0 => Location: PIN_U2, I/O Standard: 2.5 V, Current Strength: Default +-- S7 => Location: PIN_K7, I/O Standard: 2.5 V, Current Strength: Default +-- S6 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S5 => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +-- S4 => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +-- C8 => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_U8, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_AA5, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_R1, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_P5, I/O Standard: 2.5 V, Current Strength: Default +-- B7 => Location: PIN_J4, I/O Standard: 2.5 V, Current Strength: Default +-- A4 => Location: PIN_H5, I/O Standard: 2.5 V, Current Strength: Default +-- B4 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- A5 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +-- B5 => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +-- A6 => Location: PIN_K8, I/O Standard: 2.5 V, Current Strength: Default +-- B6 => Location: PIN_J3, I/O Standard: 2.5 V, Current Strength: Default +-- A7 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_1D_G IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_S7 : std_logic; +SIGNAL ww_A7 : std_logic; +SIGNAL ww_B7 : std_logic; +SIGNAL ww_A6 : std_logic; +SIGNAL ww_B6 : std_logic; +SIGNAL ww_A5 : std_logic; +SIGNAL ww_B5 : std_logic; +SIGNAL ww_A4 : std_logic; +SIGNAL ww_B4 : std_logic; +SIGNAL ww_S6 : std_logic; +SIGNAL ww_S5 : std_logic; +SIGNAL ww_S4 : std_logic; +SIGNAL ww_C8 : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S7~output_o\ : std_logic; +SIGNAL \S6~output_o\ : std_logic; +SIGNAL \S5~output_o\ : std_logic; +SIGNAL \S4~output_o\ : std_logic; +SIGNAL \C8~output_o\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \inst|inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \inst|inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst|inst|inst3|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst6~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst6~1_combout\ : std_logic; +SIGNAL \inst|inst|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst3|inst|inst~combout\ : std_logic; +SIGNAL \inst|inst|inst4|inst|inst~combout\ : std_logic; +SIGNAL \B7~input_o\ : std_logic; +SIGNAL \B6~input_o\ : std_logic; +SIGNAL \A6~input_o\ : std_logic; +SIGNAL \inst4|inst|inst2|inst|inst~combout\ : std_logic; +SIGNAL \A4~input_o\ : std_logic; +SIGNAL \B4~input_o\ : std_logic; +SIGNAL \inst4|inst|inst4|inst2~1_combout\ : std_logic; +SIGNAL \B5~input_o\ : std_logic; +SIGNAL \inst4|inst|inst4|inst2~0_combout\ : std_logic; +SIGNAL \A5~input_o\ : std_logic; +SIGNAL \inst4|inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst|inst3|inst1|inst~combout\ : std_logic; +SIGNAL \A7~input_o\ : std_logic; +SIGNAL \inst4|inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst6~0_combout\ : std_logic; +SIGNAL \inst4|inst6~1_combout\ : std_logic; +SIGNAL \inst4|inst2|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst2|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst|inst|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst4|inst2|inst|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst2|inst2|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst2|inst3|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst|inst4|inst1|inst~combout\ : std_logic; + +BEGIN + +S3 <= ww_S3; +ww_A3 <= A3; +ww_B3 <= B3; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A1 <= A1; +ww_B1 <= B1; +ww_A0 <= A0; +ww_B0 <= B0; +S2 <= ww_S2; +S1 <= ww_S1; +S0 <= ww_S0; +S7 <= ww_S7; +ww_A7 <= A7; +ww_B7 <= B7; +ww_A6 <= A6; +ww_B6 <= B6; +ww_A5 <= A5; +ww_B5 <= B5; +ww_A4 <= A4; +ww_B4 <= B4; +S6 <= ww_S6; +S5 <= ww_S5; +S4 <= ww_S4; +C8 <= ww_C8; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +-- Location: IOOBUF_X0_Y10_N2 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y10_N23 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst2|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y9_N23 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst3|inst|inst~combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y9_N9 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst|inst4|inst|inst~combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y22_N23 +\S7~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst|inst1|inst~combout\, + devoe => ww_devoe, + o => \S7~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S6~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst2|inst1|inst~combout\, + devoe => ww_devoe, + o => \S6~output_o\); + +-- Location: IOOBUF_X1_Y29_N23 +\S5~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst3|inst1|inst~combout\, + devoe => ww_devoe, + o => \S5~output_o\); + +-- Location: IOOBUF_X0_Y22_N2 +\S4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst|inst4|inst1|inst~combout\, + devoe => ww_devoe, + o => \S4~output_o\); + +-- Location: IOOBUF_X0_Y21_N16 +\C8~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst6~1_combout\, + devoe => ww_devoe, + o => \C8~output_o\); + +-- Location: IOIBUF_X0_Y12_N22 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y11_N1 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: IOIBUF_X0_Y10_N15 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: IOIBUF_X0_Y10_N8 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: IOIBUF_X3_Y0_N15 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X9_Y0_N29 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: IOIBUF_X0_Y8_N8 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: LCCOMB_X1_Y10_N24 +\inst|inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst3|inst2~0_combout\ = (\A1~input_o\ & ((\B1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\A1~input_o\ & (\B0~input_o\ & (\A0~input_o\ & \B1~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \B1~input_o\, + combout => \inst|inst|inst3|inst2~0_combout\); + +-- Location: IOIBUF_X3_Y0_N22 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: LCCOMB_X1_Y10_N26 +\inst|inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst2|inst2~0_combout\ = (\B2~input_o\ & ((\inst|inst|inst3|inst2~0_combout\) # (\A2~input_o\))) # (!\B2~input_o\ & (\inst|inst|inst3|inst2~0_combout\ & \A2~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datab => \inst|inst|inst3|inst2~0_combout\, + datad => \A2~input_o\, + combout => \inst|inst|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y10_N12 +\inst|inst|inst3|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst3|inst1|inst~0_combout\ = \A1~input_o\ $ (\B1~input_o\ $ (((\B0~input_o\ & \A0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001010101101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \B1~input_o\, + combout => \inst|inst|inst3|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N6 +\inst|inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst6~0_combout\ = (\inst|inst|inst3|inst1|inst~0_combout\) # (\inst|inst|inst3|inst2~0_combout\ $ (\B2~input_o\ $ (\A2~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101110111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datab => \inst|inst|inst3|inst2~0_combout\, + datac => \B2~input_o\, + datad => \A2~input_o\, + combout => \inst|inst6~0_combout\); + +-- Location: LCCOMB_X1_Y10_N0 +\inst|inst2|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst|inst1|inst~0_combout\ = (\A3~input_o\ & (\B3~input_o\ $ (\inst|inst|inst2|inst2~0_combout\ $ (!\inst|inst6~0_combout\)))) # (!\A3~input_o\ & ((\B3~input_o\ & (\inst|inst|inst2|inst2~0_combout\ $ (!\inst|inst6~0_combout\))) # +-- (!\B3~input_o\ & (\inst|inst|inst2|inst2~0_combout\ & !\inst|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100010010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \B3~input_o\, + datac => \inst|inst|inst2|inst2~0_combout\, + datad => \inst|inst6~0_combout\, + combout => \inst|inst2|inst|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N4 +\inst|inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst6~1_combout\ = (\A3~input_o\ & ((\B3~input_o\) # ((\inst|inst|inst2|inst2~0_combout\) # (\inst|inst6~0_combout\)))) # (!\A3~input_o\ & ((\B3~input_o\ & ((\inst|inst|inst2|inst2~0_combout\) # (\inst|inst6~0_combout\))) # (!\B3~input_o\ & +-- (\inst|inst|inst2|inst2~0_combout\ & \inst|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \B3~input_o\, + datac => \inst|inst|inst2|inst2~0_combout\, + datad => \inst|inst6~0_combout\, + combout => \inst|inst6~1_combout\); + +-- Location: LCCOMB_X1_Y10_N18 +\inst|inst|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst2|inst1|inst~0_combout\ = \B2~input_o\ $ (\inst|inst|inst3|inst2~0_combout\ $ (\A2~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001100101100110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datab => \inst|inst|inst3|inst2~0_combout\, + datad => \A2~input_o\, + combout => \inst|inst|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N14 +\inst|inst2|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst2|inst1|inst~0_combout\ = \inst|inst|inst2|inst1|inst~0_combout\ $ (((!\inst|inst|inst3|inst1|inst~0_combout\ & \inst|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010111101010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst6~1_combout\, + datad => \inst|inst|inst2|inst1|inst~0_combout\, + combout => \inst|inst2|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N16 +\inst|inst2|inst3|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst3|inst|inst~combout\ = \inst|inst|inst3|inst1|inst~0_combout\ $ (\inst|inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst6~1_combout\, + combout => \inst|inst2|inst3|inst|inst~combout\); + +-- Location: LCCOMB_X1_Y10_N2 +\inst|inst|inst4|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst4|inst|inst~combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datac => \A0~input_o\, + combout => \inst|inst|inst4|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y21_N1 +\B7~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B7, + o => \B7~input_o\); + +-- Location: IOIBUF_X0_Y21_N22 +\B6~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B6, + o => \B6~input_o\); + +-- Location: IOIBUF_X0_Y22_N8 +\A6~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A6, + o => \A6~input_o\); + +-- Location: LCCOMB_X1_Y21_N24 +\inst4|inst|inst2|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst2|inst|inst~combout\ = \B6~input_o\ $ (\A6~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datac => \A6~input_o\, + combout => \inst4|inst|inst2|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y27_N1 +\A4~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A4, + o => \A4~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\B4~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B4, + o => \B4~input_o\); + +-- Location: LCCOMB_X1_Y21_N10 +\inst4|inst|inst4|inst2~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst2~1_combout\ = (\B4~input_o\ & ((\A4~input_o\) # (\inst|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111000010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datac => \B4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst2~1_combout\); + +-- Location: IOIBUF_X0_Y21_N8 +\B5~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B5, + o => \B5~input_o\); + +-- Location: LCCOMB_X1_Y21_N8 +\inst4|inst|inst4|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst2~0_combout\ = (\A4~input_o\ & \inst|inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010101000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst2~0_combout\); + +-- Location: IOIBUF_X0_Y23_N8 +\A5~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A5, + o => \A5~input_o\); + +-- Location: LCCOMB_X1_Y21_N28 +\inst4|inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst3|inst2~0_combout\ = (\B5~input_o\ & ((\inst4|inst|inst4|inst2~1_combout\) # ((\inst4|inst|inst4|inst2~0_combout\) # (\A5~input_o\)))) # (!\B5~input_o\ & (\A5~input_o\ & ((\inst4|inst|inst4|inst2~1_combout\) # +-- (\inst4|inst|inst4|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst4|inst2~1_combout\, + datab => \B5~input_o\, + datac => \inst4|inst|inst4|inst2~0_combout\, + datad => \A5~input_o\, + combout => \inst4|inst|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N18 +\inst4|inst|inst3|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst3|inst1|inst~combout\ = \B5~input_o\ $ (\A5~input_o\ $ (((\inst4|inst|inst4|inst2~1_combout\) # (\inst4|inst|inst4|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100100100110110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst4|inst2~1_combout\, + datab => \B5~input_o\, + datac => \inst4|inst|inst4|inst2~0_combout\, + datad => \A5~input_o\, + combout => \inst4|inst|inst3|inst1|inst~combout\); + +-- Location: IOIBUF_X0_Y27_N22 +\A7~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A7, + o => \A7~input_o\); + +-- Location: LCCOMB_X1_Y21_N22 +\inst4|inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst2|inst2~0_combout\ = (\B6~input_o\ & ((\A6~input_o\) # (\inst4|inst|inst3|inst2~0_combout\))) # (!\B6~input_o\ & (\A6~input_o\ & \inst4|inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst2~0_combout\, + combout => \inst4|inst|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N20 +\inst4|inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst6~0_combout\ = (\inst4|inst|inst3|inst1|inst~combout\) # (\B6~input_o\ $ (\inst4|inst|inst3|inst2~0_combout\ $ (\A6~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst1|inst~combout\, + combout => \inst4|inst6~0_combout\); + +-- Location: LCCOMB_X1_Y21_N16 +\inst4|inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst6~1_combout\ = (\B7~input_o\ & ((\A7~input_o\) # ((\inst4|inst|inst2|inst2~0_combout\) # (\inst4|inst6~0_combout\)))) # (!\B7~input_o\ & ((\A7~input_o\ & ((\inst4|inst|inst2|inst2~0_combout\) # (\inst4|inst6~0_combout\))) # (!\A7~input_o\ & +-- (\inst4|inst|inst2|inst2~0_combout\ & \inst4|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B7~input_o\, + datab => \A7~input_o\, + datac => \inst4|inst|inst2|inst2~0_combout\, + datad => \inst4|inst6~0_combout\, + combout => \inst4|inst6~1_combout\); + +-- Location: LCCOMB_X1_Y21_N26 +\inst4|inst2|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst3|inst2~0_combout\ = (\inst|inst6~1_combout\ & ((\inst4|inst|inst3|inst1|inst~combout\) # (\inst4|inst6~1_combout\))) # (!\inst|inst6~1_combout\ & (\inst4|inst|inst3|inst1|inst~combout\ & \inst4|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \inst4|inst|inst3|inst1|inst~combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N4 +\inst4|inst2|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst2|inst2~0_combout\ = (\inst4|inst2|inst3|inst2~0_combout\ & ((\inst4|inst6~1_combout\) # (\inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\)))) # (!\inst4|inst2|inst3|inst2~0_combout\ & (\inst4|inst6~1_combout\ & +-- (\inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111011001100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst2|inst|inst~combout\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \inst4|inst2|inst3|inst2~0_combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N6 +\inst4|inst|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst|inst1|inst~0_combout\ = \A7~input_o\ $ (((\B6~input_o\ & ((\A6~input_o\) # (\inst4|inst|inst3|inst2~0_combout\))) # (!\B6~input_o\ & (\A6~input_o\ & \inst4|inst|inst3|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011011001101100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datab => \A7~input_o\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst2~0_combout\, + combout => \inst4|inst|inst|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y21_N14 +\inst4|inst2|inst|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst|inst1|inst~combout\ = \inst|inst6~1_combout\ $ (\B7~input_o\ $ (\inst4|inst2|inst2|inst2~0_combout\ $ (\inst4|inst|inst|inst1|inst~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \B7~input_o\, + datac => \inst4|inst2|inst2|inst2~0_combout\, + datad => \inst4|inst|inst|inst1|inst~0_combout\, + combout => \inst4|inst2|inst|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N0 +\inst4|inst2|inst2|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst2|inst1|inst~combout\ = \inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\ $ (\inst4|inst2|inst3|inst2~0_combout\ $ (\inst4|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst2|inst|inst~combout\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \inst4|inst2|inst3|inst2~0_combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst2|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N2 +\inst4|inst2|inst3|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst3|inst1|inst~combout\ = \inst|inst6~1_combout\ $ (\inst4|inst|inst3|inst1|inst~combout\ $ (\inst4|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001100101100110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \inst4|inst|inst3|inst1|inst~combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst3|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N12 +\inst4|inst|inst4|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst1|inst~combout\ = \A4~input_o\ $ (\B4~input_o\ $ (\inst|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datac => \B4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst1|inst~combout\); + +ww_S3 <= \S3~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S0 <= \S0~output_o\; + +ww_S7 <= \S7~output_o\; + +ww_S6 <= \S6~output_o\; + +ww_S5 <= \S5~output_o\; + +ww_S4 <= \S4~output_o\; + +ww_C8 <= \C8~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_85c_vhd_slow.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_85c_vhd_slow.sdo new file mode 100644 index 00000000..9b2c3be3 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_6_1200mv_85c_vhd_slow.sdo @@ -0,0 +1,641 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP3C16F484C6, +// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_1D_G") + (DATE "09/09/2019 21:06:05") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (327:327:327) (333:333:333)) + (IOPATH i o (2236:2236:2236) (2224:2224:2224)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (324:324:324) (328:328:328)) + (IOPATH i o (2226:2226:2226) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (603:603:603) (611:611:611)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (624:624:624) (638:638:638)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S7\~output\\) + (DELAY + (ABSOLUTE + (PORT i (575:575:575) (572:572:572)) + (IOPATH i o (2226:2226:2226) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S6\~output\\) + (DELAY + (ABSOLUTE + (PORT i (759:759:759) (781:781:781)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S5\~output\\) + (DELAY + (ABSOLUTE + (PORT i (807:807:807) (804:804:804)) + (IOPATH i o (2060:2060:2060) (2009:2009:2009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (597:597:597) (606:606:606)) + (IOPATH i o (2226:2226:2226) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C8\~output\\) + (DELAY + (ABSOLUTE + (PORT i (342:342:342) (344:344:344)) + (IOPATH i o (2236:2236:2236) (2224:2224:2224)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (745:745:745) (906:906:906)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (715:715:715) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (715:715:715) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (745:745:745) (906:906:906)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (679:679:679) (842:842:842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (739:739:739) (902:902:902)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst\|inst3\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2541:2541:2541) (2795:2795:2795)) + (PORT datab (3236:3236:3236) (3536:3536:3536)) + (PORT datac (3167:3167:3167) (3450:3450:3450)) + (PORT datad (2787:2787:2787) (3039:3039:3039)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (689:689:689) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst\|inst2\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2506:2506:2506) (2775:2775:2775)) + (PORT datab (218:218:218) (262:262:262)) + (PORT datad (3142:3142:3142) (3432:3432:3432)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst\|inst3\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2539:2539:2539) (2796:2796:2796)) + (PORT datab (3239:3239:3239) (3541:3541:3541)) + (PORT datac (3165:3165:3165) (3451:3451:3451)) + (PORT datad (2786:2786:2786) (3040:3040:3040)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (271:271:271)) + (PORT datab (218:218:218) (264:264:264)) + (PORT datac (2490:2490:2490) (2740:2740:2740)) + (PORT datad (3145:3145:3145) (3433:3433:3433)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2809:2809:2809) (3059:3059:3059)) + (PORT datab (2796:2796:2796) (3069:3069:3069)) + (PORT datac (185:185:185) (223:223:223)) + (PORT datad (182:182:182) (210:210:210)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst6\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2810:2810:2810) (3060:3060:3060)) + (PORT datab (2796:2796:2796) (3066:3066:3066)) + (PORT datac (183:183:183) (220:220:220)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst\|inst2\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2503:2503:2503) (2775:2775:2775)) + (PORT datab (219:219:219) (265:265:265)) + (PORT datad (3143:3143:3143) (3435:3435:3435)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE 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combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B7\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (715:715:715) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B6\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A6\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (745:745:745) (906:906:906)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst2\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (2528:2528:2528) (2799:2799:2799)) + (PORT datac (2736:2736:2736) (2986:2986:2986)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A4\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B4\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst4\|inst2\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (3090:3090:3090) (3387:3387:3387)) + (PORT datac (2985:2985:2985) (3248:3248:3248)) + (PORT datad (1039:1039:1039) (1077:1077:1077)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B5\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst4\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (3090:3090:3090) (3384:3384:3384)) + (PORT datad (1038:1038:1038) (1078:1078:1078)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A5\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst3\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (263:263:263)) + (PORT datab (2535:2535:2535) (2789:2789:2789)) + (PORT datac (184:184:184) (222:222:222)) + (PORT datad (2819:2819:2819) (3101:3101:3101)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst3\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (263:263:263)) + (PORT datab (2536:2536:2536) (2792:2792:2792)) + (PORT datac (183:183:183) (221:221:221)) + (PORT datad (2818:2818:2818) (3100:3100:3100)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A7\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst2\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2528:2528:2528) (2799:2799:2799)) + (PORT datac (2736:2736:2736) (2986:2986:2986)) + (PORT datad (204:204:204) (241:241:241)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2525:2525:2525) (2804:2804:2804)) + (PORT datab (232:232:232) (285:285:285)) + (PORT datac (2738:2738:2738) (2987:2987:2987)) + (PORT datad (192:192:192) (226:226:226)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst6\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2529:2529:2529) (2783:2783:2783)) + (PORT datab (3095:3095:3095) (3393:3393:3393)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst3\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1129:1129:1129)) + (PORT datab (218:218:218) (261:261:261)) + (PORT datad (216:216:216) (251:251:251)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst2\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (393:393:393)) + (PORT datab (234:234:234) (288:288:288)) + (PORT datac (183:183:183) (220:220:220)) + (PORT datad (218:218:218) (254:254:254)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2525:2525:2525) (2798:2798:2798)) + (PORT datab (3093:3093:3093) (3390:3390:3390)) + (PORT datac (2741:2741:2741) (2988:2988:2988)) + (PORT datad (207:207:207) (246:246:246)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1127:1127:1127)) + (PORT datab (2492:2492:2492) (2754:2754:2754)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst2\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (393:393:393)) + (PORT datab (238:238:238) (289:289:289)) + (PORT datac (185:185:185) (223:223:223)) + (PORT datad (220:220:220) (254:254:254)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst3\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1121:1121:1121)) + (PORT datab (219:219:219) (264:264:264)) + (PORT datad (219:219:219) (253:253:253)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst4\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (3089:3089:3089) (3387:3387:3387)) + (PORT datac (2985:2985:2985) (3247:3247:3247)) + (PORT datad (1040:1040:1040) (1080:1080:1080)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_min_1200mv_0c_fast.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_min_1200mv_0c_fast.vho new file mode 100644 index 00000000..e5897f0d --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_min_1200mv_0c_fast.vho @@ -0,0 +1,926 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "09/09/2019 21:06:05" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_1D_G IS + PORT ( + S3 : OUT std_logic; + A3 : IN std_logic; + B3 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A1 : IN std_logic; + B1 : IN std_logic; + A0 : IN std_logic; + B0 : IN std_logic; + S2 : OUT std_logic; + S1 : OUT std_logic; + S0 : OUT std_logic; + S7 : OUT std_logic; + A7 : IN std_logic; + B7 : IN std_logic; + A6 : IN std_logic; + B6 : IN std_logic; + A5 : IN std_logic; + B5 : IN std_logic; + A4 : IN std_logic; + B4 : IN std_logic; + S6 : OUT std_logic; + S5 : OUT std_logic; + S4 : OUT std_logic; + C8 : OUT std_logic + ); +END BCD_adder_1D_G; + +-- Design Ports Information +-- S3 => Location: PIN_R2, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_P4, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_V2, I/O Standard: 2.5 V, Current Strength: Default +-- S0 => Location: PIN_U2, I/O Standard: 2.5 V, Current Strength: Default +-- S7 => Location: PIN_K7, I/O Standard: 2.5 V, Current Strength: Default +-- S6 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S5 => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +-- S4 => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +-- C8 => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_U8, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_AA5, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_R1, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_P5, I/O Standard: 2.5 V, Current Strength: Default +-- B7 => Location: PIN_J4, I/O Standard: 2.5 V, Current Strength: Default +-- A4 => Location: PIN_H5, I/O Standard: 2.5 V, Current Strength: Default +-- B4 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- A5 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +-- B5 => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +-- A6 => Location: PIN_K8, I/O Standard: 2.5 V, Current Strength: Default +-- B6 => Location: PIN_J3, I/O Standard: 2.5 V, Current Strength: Default +-- A7 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_1D_G IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_S7 : std_logic; +SIGNAL ww_A7 : std_logic; +SIGNAL ww_B7 : std_logic; +SIGNAL ww_A6 : std_logic; +SIGNAL ww_B6 : std_logic; +SIGNAL ww_A5 : std_logic; +SIGNAL ww_B5 : std_logic; +SIGNAL ww_A4 : std_logic; +SIGNAL ww_B4 : std_logic; +SIGNAL ww_S6 : std_logic; +SIGNAL ww_S5 : std_logic; +SIGNAL ww_S4 : std_logic; +SIGNAL ww_C8 : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S7~output_o\ : std_logic; +SIGNAL \S6~output_o\ : std_logic; +SIGNAL \S5~output_o\ : std_logic; +SIGNAL \S4~output_o\ : std_logic; +SIGNAL \C8~output_o\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \inst|inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \inst|inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst|inst|inst3|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst6~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst6~1_combout\ : std_logic; +SIGNAL \inst|inst|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst3|inst|inst~combout\ : std_logic; +SIGNAL \inst|inst|inst4|inst|inst~combout\ : std_logic; +SIGNAL \B7~input_o\ : std_logic; +SIGNAL \B6~input_o\ : std_logic; +SIGNAL \A6~input_o\ : std_logic; +SIGNAL \inst4|inst|inst2|inst|inst~combout\ : std_logic; +SIGNAL \A4~input_o\ : std_logic; +SIGNAL \B4~input_o\ : std_logic; +SIGNAL \inst4|inst|inst4|inst2~1_combout\ : std_logic; +SIGNAL \B5~input_o\ : std_logic; +SIGNAL \inst4|inst|inst4|inst2~0_combout\ : std_logic; +SIGNAL \A5~input_o\ : std_logic; +SIGNAL \inst4|inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst|inst3|inst1|inst~combout\ : std_logic; +SIGNAL \A7~input_o\ : std_logic; +SIGNAL \inst4|inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst6~0_combout\ : std_logic; +SIGNAL \inst4|inst6~1_combout\ : std_logic; +SIGNAL \inst4|inst2|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst2|inst2|inst2~0_combout\ : std_logic; +SIGNAL \inst4|inst|inst|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst4|inst2|inst|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst2|inst2|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst2|inst3|inst1|inst~combout\ : std_logic; +SIGNAL \inst4|inst|inst4|inst1|inst~combout\ : std_logic; + +BEGIN + +S3 <= ww_S3; +ww_A3 <= A3; +ww_B3 <= B3; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A1 <= A1; +ww_B1 <= B1; +ww_A0 <= A0; +ww_B0 <= B0; +S2 <= ww_S2; +S1 <= ww_S1; +S0 <= ww_S0; +S7 <= ww_S7; +ww_A7 <= A7; +ww_B7 <= B7; +ww_A6 <= A6; +ww_B6 <= B6; +ww_A5 <= A5; +ww_B5 <= B5; +ww_A4 <= A4; +ww_B4 <= B4; +S6 <= ww_S6; +S5 <= ww_S5; +S4 <= ww_S4; +C8 <= ww_C8; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +-- Location: IOOBUF_X0_Y10_N2 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y10_N23 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst2|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y9_N23 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst2|inst3|inst|inst~combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y9_N9 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst|inst4|inst|inst~combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y22_N23 +\S7~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst|inst1|inst~combout\, + devoe => ww_devoe, + o => \S7~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S6~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst2|inst1|inst~combout\, + devoe => ww_devoe, + o => \S6~output_o\); + +-- Location: IOOBUF_X1_Y29_N23 +\S5~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst2|inst3|inst1|inst~combout\, + devoe => ww_devoe, + o => \S5~output_o\); + +-- Location: IOOBUF_X0_Y22_N2 +\S4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst|inst4|inst1|inst~combout\, + devoe => ww_devoe, + o => \S4~output_o\); + +-- Location: IOOBUF_X0_Y21_N16 +\C8~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4|inst6~1_combout\, + devoe => ww_devoe, + o => \C8~output_o\); + +-- Location: IOIBUF_X0_Y12_N22 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y11_N1 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: IOIBUF_X0_Y10_N15 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: IOIBUF_X0_Y10_N8 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: IOIBUF_X3_Y0_N15 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X9_Y0_N29 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: IOIBUF_X0_Y8_N8 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: LCCOMB_X1_Y10_N24 +\inst|inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst3|inst2~0_combout\ = (\A1~input_o\ & ((\B1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\A1~input_o\ & (\B0~input_o\ & (\A0~input_o\ & \B1~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \B1~input_o\, + combout => \inst|inst|inst3|inst2~0_combout\); + +-- Location: IOIBUF_X3_Y0_N22 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: LCCOMB_X1_Y10_N26 +\inst|inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst2|inst2~0_combout\ = (\B2~input_o\ & ((\inst|inst|inst3|inst2~0_combout\) # (\A2~input_o\))) # (!\B2~input_o\ & (\inst|inst|inst3|inst2~0_combout\ & \A2~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datab => \inst|inst|inst3|inst2~0_combout\, + datad => \A2~input_o\, + combout => \inst|inst|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y10_N12 +\inst|inst|inst3|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst3|inst1|inst~0_combout\ = \A1~input_o\ $ (\B1~input_o\ $ (((\B0~input_o\ & \A0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001010101101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \B1~input_o\, + combout => \inst|inst|inst3|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N6 +\inst|inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst6~0_combout\ = (\inst|inst|inst3|inst1|inst~0_combout\) # (\inst|inst|inst3|inst2~0_combout\ $ (\B2~input_o\ $ (\A2~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101110111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datab => \inst|inst|inst3|inst2~0_combout\, + datac => \B2~input_o\, + datad => \A2~input_o\, + combout => \inst|inst6~0_combout\); + +-- Location: LCCOMB_X1_Y10_N0 +\inst|inst2|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst|inst1|inst~0_combout\ = (\A3~input_o\ & (\B3~input_o\ $ (\inst|inst|inst2|inst2~0_combout\ $ (!\inst|inst6~0_combout\)))) # (!\A3~input_o\ & ((\B3~input_o\ & (\inst|inst|inst2|inst2~0_combout\ $ (!\inst|inst6~0_combout\))) # +-- (!\B3~input_o\ & (\inst|inst|inst2|inst2~0_combout\ & !\inst|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100010010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \B3~input_o\, + datac => \inst|inst|inst2|inst2~0_combout\, + datad => \inst|inst6~0_combout\, + combout => \inst|inst2|inst|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N4 +\inst|inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst6~1_combout\ = (\A3~input_o\ & ((\B3~input_o\) # ((\inst|inst|inst2|inst2~0_combout\) # (\inst|inst6~0_combout\)))) # (!\A3~input_o\ & ((\B3~input_o\ & ((\inst|inst|inst2|inst2~0_combout\) # (\inst|inst6~0_combout\))) # (!\B3~input_o\ & +-- (\inst|inst|inst2|inst2~0_combout\ & \inst|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \B3~input_o\, + datac => \inst|inst|inst2|inst2~0_combout\, + datad => \inst|inst6~0_combout\, + combout => \inst|inst6~1_combout\); + +-- Location: LCCOMB_X1_Y10_N18 +\inst|inst|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst2|inst1|inst~0_combout\ = \B2~input_o\ $ (\inst|inst|inst3|inst2~0_combout\ $ (\A2~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001100101100110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datab => \inst|inst|inst3|inst2~0_combout\, + datad => \A2~input_o\, + combout => \inst|inst|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N14 +\inst|inst2|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst2|inst1|inst~0_combout\ = \inst|inst|inst2|inst1|inst~0_combout\ $ (((!\inst|inst|inst3|inst1|inst~0_combout\ & \inst|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010111101010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst6~1_combout\, + datad => \inst|inst|inst2|inst1|inst~0_combout\, + combout => \inst|inst2|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y10_N16 +\inst|inst2|inst3|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst3|inst|inst~combout\ = \inst|inst|inst3|inst1|inst~0_combout\ $ (\inst|inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst6~1_combout\, + combout => \inst|inst2|inst3|inst|inst~combout\); + +-- Location: LCCOMB_X1_Y10_N2 +\inst|inst|inst4|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst|inst4|inst|inst~combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datac => \A0~input_o\, + combout => \inst|inst|inst4|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y21_N1 +\B7~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B7, + o => \B7~input_o\); + +-- Location: IOIBUF_X0_Y21_N22 +\B6~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B6, + o => \B6~input_o\); + +-- Location: IOIBUF_X0_Y22_N8 +\A6~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A6, + o => \A6~input_o\); + +-- Location: LCCOMB_X1_Y21_N24 +\inst4|inst|inst2|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst2|inst|inst~combout\ = \B6~input_o\ $ (\A6~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datac => \A6~input_o\, + combout => \inst4|inst|inst2|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y27_N1 +\A4~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A4, + o => \A4~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\B4~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B4, + o => \B4~input_o\); + +-- Location: LCCOMB_X1_Y21_N10 +\inst4|inst|inst4|inst2~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst2~1_combout\ = (\B4~input_o\ & ((\A4~input_o\) # (\inst|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111000010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datac => \B4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst2~1_combout\); + +-- Location: IOIBUF_X0_Y21_N8 +\B5~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B5, + o => \B5~input_o\); + +-- Location: LCCOMB_X1_Y21_N8 +\inst4|inst|inst4|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst2~0_combout\ = (\A4~input_o\ & \inst|inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010101000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst2~0_combout\); + +-- Location: IOIBUF_X0_Y23_N8 +\A5~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A5, + o => \A5~input_o\); + +-- Location: LCCOMB_X1_Y21_N28 +\inst4|inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst3|inst2~0_combout\ = (\B5~input_o\ & ((\inst4|inst|inst4|inst2~1_combout\) # ((\inst4|inst|inst4|inst2~0_combout\) # (\A5~input_o\)))) # (!\B5~input_o\ & (\A5~input_o\ & ((\inst4|inst|inst4|inst2~1_combout\) # +-- (\inst4|inst|inst4|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst4|inst2~1_combout\, + datab => \B5~input_o\, + datac => \inst4|inst|inst4|inst2~0_combout\, + datad => \A5~input_o\, + combout => \inst4|inst|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N18 +\inst4|inst|inst3|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst3|inst1|inst~combout\ = \B5~input_o\ $ (\A5~input_o\ $ (((\inst4|inst|inst4|inst2~1_combout\) # (\inst4|inst|inst4|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100100100110110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst4|inst2~1_combout\, + datab => \B5~input_o\, + datac => \inst4|inst|inst4|inst2~0_combout\, + datad => \A5~input_o\, + combout => \inst4|inst|inst3|inst1|inst~combout\); + +-- Location: IOIBUF_X0_Y27_N22 +\A7~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A7, + o => \A7~input_o\); + +-- Location: LCCOMB_X1_Y21_N22 +\inst4|inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst2|inst2~0_combout\ = (\B6~input_o\ & ((\A6~input_o\) # (\inst4|inst|inst3|inst2~0_combout\))) # (!\B6~input_o\ & (\A6~input_o\ & \inst4|inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst2~0_combout\, + combout => \inst4|inst|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N20 +\inst4|inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst6~0_combout\ = (\inst4|inst|inst3|inst1|inst~combout\) # (\B6~input_o\ $ (\inst4|inst|inst3|inst2~0_combout\ $ (\A6~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst1|inst~combout\, + combout => \inst4|inst6~0_combout\); + +-- Location: LCCOMB_X1_Y21_N16 +\inst4|inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst6~1_combout\ = (\B7~input_o\ & ((\A7~input_o\) # ((\inst4|inst|inst2|inst2~0_combout\) # (\inst4|inst6~0_combout\)))) # (!\B7~input_o\ & ((\A7~input_o\ & ((\inst4|inst|inst2|inst2~0_combout\) # (\inst4|inst6~0_combout\))) # (!\A7~input_o\ & +-- (\inst4|inst|inst2|inst2~0_combout\ & \inst4|inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B7~input_o\, + datab => \A7~input_o\, + datac => \inst4|inst|inst2|inst2~0_combout\, + datad => \inst4|inst6~0_combout\, + combout => \inst4|inst6~1_combout\); + +-- Location: LCCOMB_X1_Y21_N26 +\inst4|inst2|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst3|inst2~0_combout\ = (\inst|inst6~1_combout\ & ((\inst4|inst|inst3|inst1|inst~combout\) # (\inst4|inst6~1_combout\))) # (!\inst|inst6~1_combout\ & (\inst4|inst|inst3|inst1|inst~combout\ & \inst4|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \inst4|inst|inst3|inst1|inst~combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N4 +\inst4|inst2|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst2|inst2~0_combout\ = (\inst4|inst2|inst3|inst2~0_combout\ & ((\inst4|inst6~1_combout\) # (\inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\)))) # (!\inst4|inst2|inst3|inst2~0_combout\ & (\inst4|inst6~1_combout\ & +-- (\inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111011001100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst2|inst|inst~combout\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \inst4|inst2|inst3|inst2~0_combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst2|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y21_N6 +\inst4|inst|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst|inst1|inst~0_combout\ = \A7~input_o\ $ (((\B6~input_o\ & ((\A6~input_o\) # (\inst4|inst|inst3|inst2~0_combout\))) # (!\B6~input_o\ & (\A6~input_o\ & \inst4|inst|inst3|inst2~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011011001101100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B6~input_o\, + datab => \A7~input_o\, + datac => \A6~input_o\, + datad => \inst4|inst|inst3|inst2~0_combout\, + combout => \inst4|inst|inst|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y21_N14 +\inst4|inst2|inst|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst|inst1|inst~combout\ = \inst|inst6~1_combout\ $ (\B7~input_o\ $ (\inst4|inst2|inst2|inst2~0_combout\ $ (\inst4|inst|inst|inst1|inst~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \B7~input_o\, + datac => \inst4|inst2|inst2|inst2~0_combout\, + datad => \inst4|inst|inst|inst1|inst~0_combout\, + combout => \inst4|inst2|inst|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N0 +\inst4|inst2|inst2|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst2|inst1|inst~combout\ = \inst4|inst|inst2|inst|inst~combout\ $ (\inst4|inst|inst3|inst2~0_combout\ $ (\inst4|inst2|inst3|inst2~0_combout\ $ (\inst4|inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst4|inst|inst2|inst|inst~combout\, + datab => \inst4|inst|inst3|inst2~0_combout\, + datac => \inst4|inst2|inst3|inst2~0_combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst2|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N2 +\inst4|inst2|inst3|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst2|inst3|inst1|inst~combout\ = \inst|inst6~1_combout\ $ (\inst4|inst|inst3|inst1|inst~combout\ $ (\inst4|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001100101100110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst6~1_combout\, + datab => \inst4|inst|inst3|inst1|inst~combout\, + datad => \inst4|inst6~1_combout\, + combout => \inst4|inst2|inst3|inst1|inst~combout\); + +-- Location: LCCOMB_X1_Y21_N12 +\inst4|inst|inst4|inst1|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst4|inst|inst4|inst1|inst~combout\ = \A4~input_o\ $ (\B4~input_o\ $ (\inst|inst6~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A4~input_o\, + datac => \B4~input_o\, + datad => \inst|inst6~1_combout\, + combout => \inst4|inst|inst4|inst1|inst~combout\); + +ww_S3 <= \S3~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S0 <= \S0~output_o\; + +ww_S7 <= \S7~output_o\; + +ww_S6 <= \S6~output_o\; + +ww_S5 <= \S5~output_o\; + +ww_S4 <= \S4~output_o\; + +ww_C8 <= \C8~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_min_1200mv_0c_vhd_fast.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_min_1200mv_0c_vhd_fast.sdo new file mode 100644 index 00000000..7197e0f9 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_min_1200mv_0c_vhd_fast.sdo @@ -0,0 +1,641 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Fast Corner delays for the design using part EP3C16F484C6, +// with speed grade M, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_1D_G") + (DATE "09/09/2019 21:06:05") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (164:164:164) (186:186:186)) + (IOPATH i o (1476:1476:1476) (1460:1460:1460)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (162:162:162) (183:183:183)) + (IOPATH i o (1466:1466:1466) (1450:1450:1450)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (321:321:321) (363:363:363)) + (IOPATH i o (1506:1506:1506) (1490:1490:1490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (333:333:333) (380:380:380)) + (IOPATH i o (1496:1496:1496) (1480:1480:1480)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S7\~output\\) + (DELAY + (ABSOLUTE + (PORT i (304:304:304) (341:341:341)) + (IOPATH i o (1466:1466:1466) (1450:1450:1450)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S6\~output\\) + (DELAY + (ABSOLUTE + (PORT i (415:415:415) (462:462:462)) + (IOPATH i o (1496:1496:1496) (1480:1480:1480)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S5\~output\\) + (DELAY + (ABSOLUTE + (PORT i (454:454:454) (516:516:516)) + (IOPATH i o (1300:1300:1300) (1291:1291:1291)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (321:321:321) (361:361:361)) + (IOPATH i o (1466:1466:1466) (1450:1450:1450)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C8\~output\\) + (DELAY + (ABSOLUTE + (PORT i (174:174:174) (192:192:192)) + (IOPATH i o (1476:1476:1476) (1460:1460:1460)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (401:401:401) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (371:371:371) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (371:371:371) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (401:401:401) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (352:352:352) (734:734:734)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (412:412:412) (794:794:794)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (381:381:381) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst\|inst3\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1646:1646:1646)) + (PORT datab (1863:1863:1863) (2103:2103:2103)) + (PORT datac (1826:1826:1826) (2052:2052:2052)) + (PORT datad (1626:1626:1626) (1810:1810:1810)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (362:362:362) (744:744:744)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst\|inst2\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1462:1462:1462) (1636:1636:1636)) + (PORT datab (113:113:113) (144:144:144)) + (PORT datad (1832:1832:1832) (2055:2055:2055)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst\|inst3\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1472:1472:1472) (1644:1644:1644)) + (PORT datab (1867:1867:1867) (2107:2107:2107)) + (PORT datac (1824:1824:1824) (2053:2053:2053)) + (PORT datad (1625:1625:1625) (1809:1809:1809)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (149:149:149)) + (PORT datab (116:116:116) (147:147:147)) + (PORT datac (1449:1449:1449) (1615:1615:1615)) + (PORT datad (1834:1834:1834) (2056:2056:2056)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1632:1632:1632) (1822:1822:1822)) + (PORT datab (1626:1626:1626) (1822:1822:1822)) + (PORT datac (98:98:98) (123:123:123)) + (PORT datad (95:95:95) (113:113:113)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst6\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (1633:1633:1633) (1823:1823:1823)) + (PORT datab (1624:1624:1624) (1819:1819:1819)) + (PORT datac (98:98:98) (120:120:120)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst\|inst2\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1461:1461:1461) (1635:1635:1635)) + (PORT datab (113:113:113) (147:147:147)) + (PORT datad (1833:1833:1833) (2055:2055:2055)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst2\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (150:150:150)) + (PORT datac (108:108:108) (131:131:131)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst3\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (150:150:150)) + (PORT datac (108:108:108) (132:132:132)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst\|inst4\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT datab (1868:1868:1868) (2108:2108:2108)) + (PORT datac (1823:1823:1823) (2050:2050:2050)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B7\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (371:371:371) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B6\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (391:391:391) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A6\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (401:401:401) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst2\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1651:1651:1651)) + (PORT datac (1589:1589:1589) (1776:1776:1776)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A4\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (381:381:381) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B4\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (391:391:391) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst4\|inst2\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (1803:1803:1803) (2016:2016:2016)) + (PORT datac (1743:1743:1743) (1941:1941:1941)) + (PORT datad (588:588:588) (658:658:658)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B5\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (391:391:391) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst4\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1803:1803:1803) (2014:2014:2014)) + (PORT datad (589:589:589) (658:658:658)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A5\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (391:391:391) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst3\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (147:147:147)) + (PORT datab (1473:1473:1473) (1643:1643:1643)) + (PORT datac (98:98:98) (122:122:122)) + (PORT datad (1640:1640:1640) (1846:1846:1846)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst3\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (145:145:145)) + (PORT datab (1473:1473:1473) (1643:1643:1643)) + (PORT datac (95:95:95) (121:121:121)) + (PORT datad (1639:1639:1639) (1845:1845:1845)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A7\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (381:381:381) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst2\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1651:1651:1651)) + (PORT datac (1589:1589:1589) (1776:1776:1776)) + (PORT datad (108:108:108) (132:132:132)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1476:1476:1476) (1654:1654:1654)) + (PORT datab (121:121:121) (157:157:157)) + (PORT datac (1590:1590:1590) (1776:1776:1776)) + (PORT datad (100:100:100) (121:121:121)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst6\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (1468:1468:1468) (1637:1637:1637)) + (PORT datab (1805:1805:1805) (2028:2028:2028)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst3\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (690:690:690)) + (PORT datab (113:113:113) (145:145:145)) + (PORT datad (115:115:115) (136:136:136)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst2\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (225:225:225)) + (PORT datab (126:126:126) (163:163:163)) + (PORT datac (98:98:98) (120:120:120)) + (PORT datad (118:118:118) (139:139:139)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1472:1472:1472) (1649:1649:1649)) + (PORT datab (1804:1804:1804) (2027:2027:2027)) + (PORT datac (1591:1591:1591) (1778:1778:1778)) + (PORT datad (112:112:112) (138:138:138)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (687:687:687)) + (PORT datab (1452:1452:1452) (1621:1621:1621)) + (PORT datac (91:91:91) (112:112:112)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst2\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (224:224:224)) + (PORT datab (127:127:127) (164:164:164)) + (PORT datac (98:98:98) (123:123:123)) + (PORT datad (118:118:118) (139:139:139)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst3\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (681:681:681)) + (PORT datab (115:115:115) (148:148:148)) + (PORT datad (117:117:117) (139:139:139)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst4\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (1803:1803:1803) (2016:2016:2016)) + (PORT datac (1743:1743:1743) (1941:1941:1941)) + (PORT datad (590:590:590) (659:659:659)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_modelsim.xrf b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_modelsim.xrf new file mode 100644 index 00000000..4498bb8c --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_modelsim.xrf @@ -0,0 +1,61 @@ +vendor_name = ModelSim +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.vwf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/db/BCD_adder_1D_G.cbx.xml +design_name = BCD_adder_1D_G +instance = comp, \S3~output\, S3~output, BCD_adder_1D_G, 1 +instance = comp, \S2~output\, S2~output, BCD_adder_1D_G, 1 +instance = comp, \S1~output\, S1~output, BCD_adder_1D_G, 1 +instance = comp, \S0~output\, S0~output, BCD_adder_1D_G, 1 +instance = comp, \S7~output\, S7~output, BCD_adder_1D_G, 1 +instance = comp, \S6~output\, S6~output, BCD_adder_1D_G, 1 +instance = comp, \S5~output\, S5~output, BCD_adder_1D_G, 1 +instance = comp, \S4~output\, S4~output, BCD_adder_1D_G, 1 +instance = comp, \C8~output\, C8~output, BCD_adder_1D_G, 1 +instance = comp, \A3~input\, A3~input, BCD_adder_1D_G, 1 +instance = comp, \B3~input\, B3~input, BCD_adder_1D_G, 1 +instance = comp, \B2~input\, B2~input, BCD_adder_1D_G, 1 +instance = comp, \A1~input\, A1~input, BCD_adder_1D_G, 1 +instance = comp, \B0~input\, B0~input, BCD_adder_1D_G, 1 +instance = comp, \A0~input\, A0~input, BCD_adder_1D_G, 1 +instance = comp, \B1~input\, B1~input, BCD_adder_1D_G, 1 +instance = comp, \inst|inst|inst3|inst2~0\, inst|inst|inst3|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \A2~input\, A2~input, BCD_adder_1D_G, 1 +instance = comp, \inst|inst|inst2|inst2~0\, inst|inst|inst2|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst|inst3|inst1|inst~0\, inst|inst|inst3|inst1|inst~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst6~0\, inst|inst6~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst2|inst|inst1|inst~0\, inst|inst2|inst|inst1|inst~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst6~1\, inst|inst6~1, BCD_adder_1D_G, 1 +instance = comp, \inst|inst|inst2|inst1|inst~0\, inst|inst|inst2|inst1|inst~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst2|inst2|inst1|inst~0\, inst|inst2|inst2|inst1|inst~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst2|inst3|inst|inst\, inst|inst2|inst3|inst|inst, BCD_adder_1D_G, 1 +instance = comp, \inst|inst|inst4|inst|inst\, inst|inst|inst4|inst|inst, BCD_adder_1D_G, 1 +instance = comp, \B7~input\, B7~input, BCD_adder_1D_G, 1 +instance = comp, \B6~input\, B6~input, BCD_adder_1D_G, 1 +instance = comp, \A6~input\, A6~input, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst2|inst|inst\, inst4|inst|inst2|inst|inst, BCD_adder_1D_G, 1 +instance = comp, \A4~input\, A4~input, BCD_adder_1D_G, 1 +instance = comp, \B4~input\, B4~input, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst4|inst2~1\, inst4|inst|inst4|inst2~1, BCD_adder_1D_G, 1 +instance = comp, \B5~input\, B5~input, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst4|inst2~0\, inst4|inst|inst4|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \A5~input\, A5~input, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst3|inst2~0\, inst4|inst|inst3|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst3|inst1|inst\, inst4|inst|inst3|inst1|inst, BCD_adder_1D_G, 1 +instance = comp, \A7~input\, A7~input, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst2|inst2~0\, inst4|inst|inst2|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst6~0\, inst4|inst6~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst6~1\, inst4|inst6~1, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst2|inst3|inst2~0\, inst4|inst2|inst3|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst2|inst2|inst2~0\, inst4|inst2|inst2|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst|inst1|inst~0\, inst4|inst|inst|inst1|inst~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst2|inst|inst1|inst\, inst4|inst2|inst|inst1|inst, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst2|inst2|inst1|inst\, inst4|inst2|inst2|inst1|inst, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst2|inst3|inst1|inst\, inst4|inst2|inst3|inst1|inst, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst4|inst1|inst\, inst4|inst|inst4|inst1|inst, BCD_adder_1D_G, 1 diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_vhd.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_vhd.sdo new file mode 100644 index 00000000..9b2c3be3 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_G_vhd.sdo @@ -0,0 +1,641 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP3C16F484C6, +// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_1D_G") + (DATE "09/09/2019 21:06:05") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (327:327:327) (333:333:333)) + (IOPATH i o (2236:2236:2236) (2224:2224:2224)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (324:324:324) (328:328:328)) + (IOPATH i o (2226:2226:2226) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (603:603:603) (611:611:611)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (624:624:624) (638:638:638)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S7\~output\\) + (DELAY + (ABSOLUTE + (PORT i (575:575:575) (572:572:572)) + (IOPATH i o (2226:2226:2226) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S6\~output\\) + (DELAY + (ABSOLUTE + (PORT i (759:759:759) (781:781:781)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S5\~output\\) + (DELAY + (ABSOLUTE + (PORT i (807:807:807) (804:804:804)) + (IOPATH i o (2060:2060:2060) (2009:2009:2009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (597:597:597) (606:606:606)) + (IOPATH i o (2226:2226:2226) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C8\~output\\) + (DELAY + (ABSOLUTE + (PORT i (342:342:342) (344:344:344)) + (IOPATH i o (2236:2236:2236) (2224:2224:2224)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (745:745:745) (906:906:906)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (715:715:715) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (715:715:715) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (745:745:745) (906:906:906)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + 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(185:185:185) (223:223:223)) + (PORT datad (220:220:220) (254:254:254)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst2\|inst3\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1121:1121:1121)) + (PORT datab (219:219:219) (264:264:264)) + (PORT datad (219:219:219) (253:253:253)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst4\|inst\|inst4\|inst1\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (3089:3089:3089) (3387:3387:3387)) + (PORT datac (2985:2985:2985) (3247:3247:3247)) + (PORT datad (1040:1040:1040) (1080:1080:1080)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_min_1200mv_0c_fast.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_min_1200mv_0c_fast.vho new file mode 100644 index 00000000..f8dcf5da --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_min_1200mv_0c_fast.vho @@ -0,0 +1,458 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "09/05/2019 20:29:14" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_1D IS + PORT ( + S0 : OUT std_logic; + A3 : IN std_logic; + B3 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A1 : IN std_logic; + B1 : IN std_logic; + A0 : IN std_logic; + B0 : IN std_logic; + S1 : OUT std_logic; + S2 : OUT std_logic; + S3 : OUT std_logic; + C4 : OUT std_logic + ); +END BCD_adder_1D; + +-- Design Ports Information +-- S0 => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +-- S3 => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +-- C4 => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_H7, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_H6, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_J7, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_1D IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_C4 : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \C4~output_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \inst|inst4|inst|inst~combout\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \inst|inst3|inst1|inst~0_combout\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \inst|inst3|inst2~0_combout\ : std_logic; +SIGNAL \inst|inst2|inst2~0_combout\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \inst6~0_combout\ : std_logic; +SIGNAL \inst6~1_combout\ : std_logic; +SIGNAL \inst2|inst3|inst|inst~combout\ : std_logic; +SIGNAL \inst|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst2|inst2|inst1|inst~0_combout\ : std_logic; +SIGNAL \inst2|inst|inst1|inst~0_combout\ : std_logic; + +BEGIN + +S0 <= ww_S0; +ww_A3 <= A3; +ww_B3 <= B3; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A1 <= A1; +ww_B1 <= B1; +ww_A0 <= A0; +ww_B0 <= B0; +S1 <= ww_S1; +S2 <= ww_S2; +S3 <= ww_S3; +C4 <= ww_C4; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +-- Location: IOOBUF_X0_Y24_N16 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|inst4|inst|inst~combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst3|inst|inst~combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y26_N16 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst2|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y27_N9 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2|inst|inst1|inst~0_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y27_N16 +\C4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst6~1_combout\, + devoe => ww_devoe, + o => \C4~output_o\); + +-- Location: IOIBUF_X0_Y25_N22 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X0_Y25_N15 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: LCCOMB_X1_Y24_N16 +\inst|inst4|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst4|inst|inst~combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datac => \A0~input_o\, + combout => \inst|inst4|inst|inst~combout\); + +-- Location: IOIBUF_X0_Y23_N8 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: IOIBUF_X0_Y26_N8 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: LCCOMB_X1_Y24_N10 +\inst|inst3|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst3|inst1|inst~0_combout\ = \B1~input_o\ $ (\A1~input_o\ $ (((\B0~input_o\ & \A0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001010101101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \A1~input_o\, + combout => \inst|inst3|inst1|inst~0_combout\); + +-- Location: IOIBUF_X0_Y25_N1 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y27_N22 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: LCCOMB_X1_Y24_N12 +\inst|inst3|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst3|inst2~0_combout\ = (\B1~input_o\ & ((\A1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\B1~input_o\ & (\B0~input_o\ & (\A0~input_o\ & \A1~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B1~input_o\, + datab => \B0~input_o\, + datac => \A0~input_o\, + datad => \A1~input_o\, + combout => \inst|inst3|inst2~0_combout\); + +-- Location: LCCOMB_X1_Y24_N24 +\inst|inst2|inst2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst2~0_combout\ = (\B2~input_o\ & ((\A2~input_o\) # (\inst|inst3|inst2~0_combout\))) # (!\B2~input_o\ & (\A2~input_o\ & \inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datac => \A2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst|inst2|inst2~0_combout\); + +-- Location: IOIBUF_X0_Y22_N15 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: LCCOMB_X1_Y24_N6 +\inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~0_combout\ = (\inst|inst3|inst1|inst~0_combout\) # (\A2~input_o\ $ (\B2~input_o\ $ (\inst|inst3|inst2~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110101110111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datab => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst6~0_combout\); + +-- Location: LCCOMB_X1_Y24_N2 +\inst6~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~1_combout\ = (\A3~input_o\ & ((\inst|inst2|inst2~0_combout\) # ((\B3~input_o\) # (\inst6~0_combout\)))) # (!\A3~input_o\ & ((\inst|inst2|inst2~0_combout\ & ((\B3~input_o\) # (\inst6~0_combout\))) # (!\inst|inst2|inst2~0_combout\ & (\B3~input_o\ & +-- \inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011101000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|inst2|inst2~0_combout\, + datac => \B3~input_o\, + datad => \inst6~0_combout\, + combout => \inst6~1_combout\); + +-- Location: LCCOMB_X1_Y24_N4 +\inst2|inst3|inst|inst\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst3|inst|inst~combout\ = \inst|inst3|inst1|inst~0_combout\ $ (\inst6~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101010110101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datad => \inst6~1_combout\, + combout => \inst2|inst3|inst|inst~combout\); + +-- Location: LCCOMB_X1_Y24_N22 +\inst|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|inst2|inst1|inst~0_combout\ = \B2~input_o\ $ (\A2~input_o\ $ (\inst|inst3|inst2~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \B2~input_o\, + datac => \A2~input_o\, + datad => \inst|inst3|inst2~0_combout\, + combout => \inst|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y24_N0 +\inst2|inst2|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst2|inst1|inst~0_combout\ = \inst|inst2|inst1|inst~0_combout\ $ (((!\inst|inst3|inst1|inst~0_combout\ & \inst6~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010111110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|inst3|inst1|inst~0_combout\, + datac => \inst|inst2|inst1|inst~0_combout\, + datad => \inst6~1_combout\, + combout => \inst2|inst2|inst1|inst~0_combout\); + +-- Location: LCCOMB_X1_Y24_N26 +\inst2|inst|inst1|inst~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|inst|inst1|inst~0_combout\ = (\A3~input_o\ & (\inst|inst2|inst2~0_combout\ $ (\B3~input_o\ $ (!\inst6~0_combout\)))) # (!\A3~input_o\ & ((\inst|inst2|inst2~0_combout\ & (\B3~input_o\ $ (!\inst6~0_combout\))) # (!\inst|inst2|inst2~0_combout\ & +-- (\B3~input_o\ & !\inst6~0_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100010010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|inst2|inst2~0_combout\, + datac => \B3~input_o\, + datad => \inst6~0_combout\, + combout => \inst2|inst|inst1|inst~0_combout\); + +ww_S0 <= \S0~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S3 <= \S3~output_o\; + +ww_C4 <= \C4~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_min_1200mv_0c_vhd_fast.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_min_1200mv_0c_vhd_fast.sdo new file mode 100644 index 00000000..2d27e958 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_min_1200mv_0c_vhd_fast.sdo @@ -0,0 +1,307 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Fast Corner delays for the design using part EP3C16F484C6, +// with speed grade M, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_1D") + (DATE "09/05/2019 20:29:14") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (161:161:161) (181:181:181)) + (IOPATH i o (1486:1486:1486) (1470:1470:1470)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (324:324:324) (364:364:364)) + (IOPATH i o (1496:1496:1496) (1480:1480:1480)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (325:325:325) (356:356:356)) + (IOPATH i o (1506:1506:1506) (1490:1490:1490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (353:353:353) (396:396:396)) + (IOPATH i o (1506:1506:1506) (1490:1490:1490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (374:374:374) (416:416:416)) + (IOPATH i o (1506:1506:1506) (1490:1490:1490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (381:381:381) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (381:381:381) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst4\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT datab (1611:1611:1611) (1801:1801:1801)) + (PORT datac (1604:1604:1604) (1780:1780:1780)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (391:391:391) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (391:391:391) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst3\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1639:1639:1639) (1835:1835:1835)) + (PORT datab (1610:1610:1610) (1801:1801:1801)) + (PORT datac (1606:1606:1606) (1783:1783:1783)) + (PORT datad (1620:1620:1620) (1805:1805:1805)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (431:431:431) (813:813:813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (381:381:381) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (391:391:391) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst3\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1638:1638:1638) (1835:1835:1835)) + (PORT datab (1610:1610:1610) (1801:1801:1801)) + (PORT datac (1606:1606:1606) (1783:1783:1783)) + (PORT datad (1619:1619:1619) (1805:1805:1805)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1640:1640:1640) (1829:1829:1829)) + (PORT datac (1635:1635:1635) (1818:1818:1818)) + (PORT datad (101:101:101) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (381:381:381) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (150:150:150)) + (PORT datab (1645:1645:1645) (1835:1835:1835)) + (PORT datac (1625:1625:1625) (1805:1805:1805)) + (PORT datad (98:98:98) (117:117:117)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (1616:1616:1616) (1802:1802:1802)) + (PORT datab (111:111:111) (143:143:143)) + (PORT datac (1607:1607:1607) (1782:1782:1782)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst3\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (151:151:151)) + (PORT datad (107:107:107) (125:125:125)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1641:1641:1641) (1829:1829:1829)) + (PORT datac (1635:1635:1635) (1818:1818:1818)) + (PORT datad (101:101:101) (120:120:120)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst2\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (151:151:151)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (107:107:107) (125:125:125)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1611:1611:1611) (1796:1796:1796)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (1609:1609:1609) (1785:1785:1785)) + (PORT datad (97:97:97) (116:116:116)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_modelsim.xrf b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_modelsim.xrf new file mode 100644 index 00000000..ee59a269 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_modelsim.xrf @@ -0,0 +1,32 @@ +vendor_name = ModelSim +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/db/BCD_adder_1D.cbx.xml +design_name = BCD_adder_1D +instance = comp, \S0~output\, S0~output, BCD_adder_1D, 1 +instance = comp, \S1~output\, S1~output, BCD_adder_1D, 1 +instance = comp, \S2~output\, S2~output, BCD_adder_1D, 1 +instance = comp, \S3~output\, S3~output, BCD_adder_1D, 1 +instance = comp, \C4~output\, C4~output, BCD_adder_1D, 1 +instance = comp, \B0~input\, B0~input, BCD_adder_1D, 1 +instance = comp, \A0~input\, A0~input, BCD_adder_1D, 1 +instance = comp, \inst|inst4|inst|inst\, inst|inst4|inst|inst, BCD_adder_1D, 1 +instance = comp, \B1~input\, B1~input, BCD_adder_1D, 1 +instance = comp, \A1~input\, A1~input, BCD_adder_1D, 1 +instance = comp, \inst|inst3|inst1|inst~0\, inst|inst3|inst1|inst~0, BCD_adder_1D, 1 +instance = comp, \A3~input\, A3~input, BCD_adder_1D, 1 +instance = comp, \B2~input\, B2~input, BCD_adder_1D, 1 +instance = comp, \A2~input\, A2~input, BCD_adder_1D, 1 +instance = comp, \inst|inst3|inst2~0\, inst|inst3|inst2~0, BCD_adder_1D, 1 +instance = comp, \inst|inst2|inst2~0\, inst|inst2|inst2~0, BCD_adder_1D, 1 +instance = comp, \B3~input\, B3~input, BCD_adder_1D, 1 +instance = comp, \inst6~0\, inst6~0, BCD_adder_1D, 1 +instance = comp, \inst6~1\, inst6~1, BCD_adder_1D, 1 +instance = comp, \inst2|inst3|inst|inst\, inst2|inst3|inst|inst, BCD_adder_1D, 1 +instance = comp, \inst|inst2|inst1|inst~0\, inst|inst2|inst1|inst~0, BCD_adder_1D, 1 +instance = comp, \inst2|inst2|inst1|inst~0\, inst2|inst2|inst1|inst~0, BCD_adder_1D, 1 +instance = comp, \inst2|inst|inst1|inst~0\, inst2|inst|inst1|inst~0, BCD_adder_1D, 1 diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_vhd.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_vhd.sdo new file mode 100644 index 00000000..1075c651 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_1D_vhd.sdo @@ -0,0 +1,307 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP3C16F484C6, +// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_1D") + (DATE "09/05/2019 20:29:14") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (321:321:321) (324:324:324)) + (IOPATH i o (2246:2246:2246) (2234:2234:2234)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (599:599:599) (599:599:599)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (598:598:598) (594:594:594)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (633:633:633) (669:669:669)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (669:669:669) (705:705:705)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst4\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT datab (2773:2773:2773) (3030:3030:3030)) + (PORT datac (2755:2755:2755) (3003:3003:3003)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst3\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2823:2823:2823) (3096:3096:3096)) + (PORT datab (2773:2773:2773) (3031:3031:3031)) + (PORT datac (2755:2755:2755) (3004:3004:3004)) + (PORT datad (2771:2771:2771) (3047:3047:3047)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (775:775:775) (936:936:936)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst3\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2824:2824:2824) (3095:3095:3095)) + (PORT datab (2773:2773:2773) (3031:3031:3031)) + (PORT datac (2755:2755:2755) (3003:3003:3003)) + (PORT datad (2771:2771:2771) (3046:3046:3046)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2816:2816:2816) (3091:3091:3091)) + (PORT datac (2800:2800:2800) (3050:3050:3050)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (271:271:271)) + (PORT datab (2826:2826:2826) (3078:3078:3078)) + (PORT datac (2785:2785:2785) (3052:3052:3052)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2778:2778:2778) (3035:3035:3035)) + (PORT datab (212:212:212) (255:255:255)) + (PORT datac (2743:2743:2743) (2994:2994:2994)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst3\|inst\|inst\\) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (271:271:271)) + (PORT datad (203:203:203) (231:231:231)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|inst2\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2816:2816:2816) (3091:3091:3091)) + (PORT datac (2800:2800:2800) (3050:3050:3050)) + (PORT datad (190:190:190) (220:220:220)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst2\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (271:271:271)) + (PORT datac (176:176:176) (210:210:210)) + (PORT datad (204:204:204) (232:232:232)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|inst\|inst1\|inst\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2773:2773:2773) (3029:3029:3029)) + (PORT datab (209:209:209) (251:251:251)) + (PORT datac (2743:2743:2743) (2996:2996:2996)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_7483.sft b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483.sft new file mode 100644 index 00000000..aac84deb --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim-Altera (VHDL)" +set corner_file_list { + {{"Slow -6 1.2V 85 Model"} {BCD_adder_7483_6_1200mv_85c_slow.vho BCD_adder_7483_6_1200mv_85c_vhd_slow.sdo}} + {{"Slow -6 1.2V 0 Model"} {BCD_adder_7483_6_1200mv_0c_slow.vho BCD_adder_7483_6_1200mv_0c_vhd_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {BCD_adder_7483_min_1200mv_0c_fast.vho BCD_adder_7483_min_1200mv_0c_vhd_fast.sdo}} +} diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_7483.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483.vho new file mode 100644 index 00000000..b2cb9178 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483.vho @@ -0,0 +1,495 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "08/26/2019 23:13:45" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_7483 IS + PORT ( + S0 : OUT std_logic; + B3 : IN std_logic; + A0 : IN std_logic; + A1 : IN std_logic; + B0 : IN std_logic; + B1 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A3 : IN std_logic; + S1 : OUT std_logic; + S2 : OUT std_logic; + S3 : OUT std_logic; + C4 : OUT std_logic + ); +END BCD_adder_7483; + +-- Design Ports Information +-- S0 => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S3 => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +-- C4 => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_J7, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_H7, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_H6, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_7483 IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_C4 : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \C4~output_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \inst|27~0_combout\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \inst|29~0_combout\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \inst|51~1_combout\ : std_logic; +SIGNAL \inst|1~0_combout\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \inst|51~0_combout\ : std_logic; +SIGNAL \inst|44~0_combout\ : std_logic; +SIGNAL \inst1|45~0_combout\ : std_logic; +SIGNAL \inst6~0_combout\ : std_logic; +SIGNAL \inst1|29~0_combout\ : std_logic; +SIGNAL \inst1|51~0_combout\ : std_logic; +SIGNAL \inst1|44~0_combout\ : std_logic; +SIGNAL \inst1|45~1_combout\ : std_logic; +SIGNAL \inst1|ALT_INV_45~1_combout\ : std_logic; + +BEGIN + +S0 <= ww_S0; +ww_B3 <= B3; +ww_A0 <= A0; +ww_A1 <= A1; +ww_B0 <= B0; +ww_B1 <= B1; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A3 <= A3; +S1 <= ww_S1; +S2 <= ww_S2; +S3 <= ww_S3; +C4 <= ww_C4; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +\inst1|ALT_INV_45~1_combout\ <= NOT \inst1|45~1_combout\; + +-- Location: IOOBUF_X0_Y27_N9 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|27~0_combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y26_N16 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|29~0_combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|44~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y24_N16 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|ALT_INV_45~1_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y27_N16 +\C4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst6~0_combout\, + devoe => ww_devoe, + o => \C4~output_o\); + +-- Location: IOIBUF_X0_Y22_N15 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X0_Y25_N1 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: LCCOMB_X1_Y25_N0 +\inst|27~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|27~0_combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011001111001100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datad => \A0~input_o\, + combout => \inst|27~0_combout\); + +-- Location: IOIBUF_X0_Y27_N22 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: LCCOMB_X1_Y25_N26 +\inst|29~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|29~0_combout\ = \B1~input_o\ $ (\A1~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B1~input_o\, + datac => \A1~input_o\, + combout => \inst|29~0_combout\); + +-- Location: IOIBUF_X0_Y25_N15 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y26_N8 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: IOIBUF_X0_Y23_N8 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: LCCOMB_X1_Y25_N2 +\inst|51~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|51~1_combout\ = (\A1~input_o\ & ((\B1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\A1~input_o\ & (\B0~input_o\ & (\B1~input_o\ & \A0~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110100010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst|51~1_combout\); + +-- Location: LCCOMB_X1_Y25_N28 +\inst|1~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|1~0_combout\ = (\A2~input_o\ & (!\B2~input_o\ & !\inst|51~1_combout\)) # (!\A2~input_o\ & ((!\inst|51~1_combout\) # (!\B2~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000010101011111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|51~1_combout\, + combout => \inst|1~0_combout\); + +-- Location: IOIBUF_X0_Y25_N22 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: LCCOMB_X1_Y25_N20 +\inst|51~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|51~0_combout\ = (\A1~input_o\ & (!\B1~input_o\ & ((!\A0~input_o\) # (!\B0~input_o\)))) # (!\A1~input_o\ & (((!\A0~input_o\) # (!\B1~input_o\)) # (!\B0~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001011101011111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst|51~0_combout\); + +-- Location: LCCOMB_X1_Y25_N22 +\inst|44~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|44~0_combout\ = \A2~input_o\ $ (\B2~input_o\ $ (\inst|51~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|51~0_combout\, + combout => \inst|44~0_combout\); + +-- Location: LCCOMB_X1_Y25_N16 +\inst1|45~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|45~0_combout\ = (\inst|29~0_combout\ $ (((\B0~input_o\ & \A0~input_o\)))) # (!\inst|44~0_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0111110111110101", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|44~0_combout\, + datab => \B0~input_o\, + datac => \inst|29~0_combout\, + datad => \A0~input_o\, + combout => \inst1|45~0_combout\); + +-- Location: LCCOMB_X1_Y25_N14 +\inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~0_combout\ = (\A3~input_o\ & (((\B3~input_o\) # (\inst1|45~0_combout\)) # (!\inst|1~0_combout\))) # (!\A3~input_o\ & ((\inst|1~0_combout\ & (\B3~input_o\ & \inst1|45~0_combout\)) # (!\inst|1~0_combout\ & ((\B3~input_o\) # (\inst1|45~0_combout\))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101110110010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|1~0_combout\, + datac => \B3~input_o\, + datad => \inst1|45~0_combout\, + combout => \inst6~0_combout\); + +-- Location: LCCOMB_X1_Y25_N24 +\inst1|29~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|29~0_combout\ = \inst|29~0_combout\ $ (\inst6~0_combout\ $ (((\A0~input_o\ & \B0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000011101111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A0~input_o\, + datab => \B0~input_o\, + datac => \inst|29~0_combout\, + datad => \inst6~0_combout\, + combout => \inst1|29~0_combout\); + +-- Location: LCCOMB_X1_Y25_N10 +\inst1|51~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|51~0_combout\ = \A1~input_o\ $ (\B1~input_o\ $ (((!\A0~input_o\) # (!\B0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110100101", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst1|51~0_combout\); + +-- Location: LCCOMB_X1_Y25_N12 +\inst1|44~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|44~0_combout\ = \inst|44~0_combout\ $ (((!\inst6~0_combout\) # (!\inst1|51~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010100001111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|51~0_combout\, + datac => \inst|44~0_combout\, + datad => \inst6~0_combout\, + combout => \inst1|44~0_combout\); + +-- Location: LCCOMB_X1_Y25_N30 +\inst1|45~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|45~1_combout\ = (\A3~input_o\ & (\inst|1~0_combout\ $ (\B3~input_o\ $ (!\inst1|45~0_combout\)))) # (!\A3~input_o\ & ((\inst|1~0_combout\ & ((\inst1|45~0_combout\) # (!\B3~input_o\))) # (!\inst|1~0_combout\ & (\B3~input_o\ $ +-- (\inst1|45~0_combout\))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110110110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|1~0_combout\, + datac => \B3~input_o\, + datad => \inst1|45~0_combout\, + combout => \inst1|45~1_combout\); + +ww_S0 <= \S0~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S3 <= \S3~output_o\; + +ww_C4 <= \C4~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_0c_slow.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_0c_slow.vho new file mode 100644 index 00000000..b2cb9178 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_0c_slow.vho @@ -0,0 +1,495 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "08/26/2019 23:13:45" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_7483 IS + PORT ( + S0 : OUT std_logic; + B3 : IN std_logic; + A0 : IN std_logic; + A1 : IN std_logic; + B0 : IN std_logic; + B1 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A3 : IN std_logic; + S1 : OUT std_logic; + S2 : OUT std_logic; + S3 : OUT std_logic; + C4 : OUT std_logic + ); +END BCD_adder_7483; + +-- Design Ports Information +-- S0 => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S3 => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +-- C4 => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_J7, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_H7, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_H6, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_7483 IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_C4 : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \C4~output_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \inst|27~0_combout\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \inst|29~0_combout\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \inst|51~1_combout\ : std_logic; +SIGNAL \inst|1~0_combout\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \inst|51~0_combout\ : std_logic; +SIGNAL \inst|44~0_combout\ : std_logic; +SIGNAL \inst1|45~0_combout\ : std_logic; +SIGNAL \inst6~0_combout\ : std_logic; +SIGNAL \inst1|29~0_combout\ : std_logic; +SIGNAL \inst1|51~0_combout\ : std_logic; +SIGNAL \inst1|44~0_combout\ : std_logic; +SIGNAL \inst1|45~1_combout\ : std_logic; +SIGNAL \inst1|ALT_INV_45~1_combout\ : std_logic; + +BEGIN + +S0 <= ww_S0; +ww_B3 <= B3; +ww_A0 <= A0; +ww_A1 <= A1; +ww_B0 <= B0; +ww_B1 <= B1; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A3 <= A3; +S1 <= ww_S1; +S2 <= ww_S2; +S3 <= ww_S3; +C4 <= ww_C4; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +\inst1|ALT_INV_45~1_combout\ <= NOT \inst1|45~1_combout\; + +-- Location: IOOBUF_X0_Y27_N9 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|27~0_combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y26_N16 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|29~0_combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|44~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y24_N16 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|ALT_INV_45~1_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y27_N16 +\C4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst6~0_combout\, + devoe => ww_devoe, + o => \C4~output_o\); + +-- Location: IOIBUF_X0_Y22_N15 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X0_Y25_N1 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: LCCOMB_X1_Y25_N0 +\inst|27~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|27~0_combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011001111001100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datad => \A0~input_o\, + combout => \inst|27~0_combout\); + +-- Location: IOIBUF_X0_Y27_N22 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: LCCOMB_X1_Y25_N26 +\inst|29~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|29~0_combout\ = \B1~input_o\ $ (\A1~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B1~input_o\, + datac => \A1~input_o\, + combout => \inst|29~0_combout\); + +-- Location: IOIBUF_X0_Y25_N15 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y26_N8 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: IOIBUF_X0_Y23_N8 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: LCCOMB_X1_Y25_N2 +\inst|51~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|51~1_combout\ = (\A1~input_o\ & ((\B1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\A1~input_o\ & (\B0~input_o\ & (\B1~input_o\ & \A0~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110100010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst|51~1_combout\); + +-- Location: LCCOMB_X1_Y25_N28 +\inst|1~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|1~0_combout\ = (\A2~input_o\ & (!\B2~input_o\ & !\inst|51~1_combout\)) # (!\A2~input_o\ & ((!\inst|51~1_combout\) # (!\B2~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000010101011111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|51~1_combout\, + combout => \inst|1~0_combout\); + +-- Location: IOIBUF_X0_Y25_N22 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: LCCOMB_X1_Y25_N20 +\inst|51~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|51~0_combout\ = (\A1~input_o\ & (!\B1~input_o\ & ((!\A0~input_o\) # (!\B0~input_o\)))) # (!\A1~input_o\ & (((!\A0~input_o\) # (!\B1~input_o\)) # (!\B0~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001011101011111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst|51~0_combout\); + +-- Location: LCCOMB_X1_Y25_N22 +\inst|44~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|44~0_combout\ = \A2~input_o\ $ (\B2~input_o\ $ (\inst|51~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|51~0_combout\, + combout => \inst|44~0_combout\); + +-- Location: LCCOMB_X1_Y25_N16 +\inst1|45~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|45~0_combout\ = (\inst|29~0_combout\ $ (((\B0~input_o\ & \A0~input_o\)))) # (!\inst|44~0_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0111110111110101", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|44~0_combout\, + datab => \B0~input_o\, + datac => \inst|29~0_combout\, + datad => \A0~input_o\, + combout => \inst1|45~0_combout\); + +-- Location: LCCOMB_X1_Y25_N14 +\inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~0_combout\ = (\A3~input_o\ & (((\B3~input_o\) # (\inst1|45~0_combout\)) # (!\inst|1~0_combout\))) # (!\A3~input_o\ & ((\inst|1~0_combout\ & (\B3~input_o\ & \inst1|45~0_combout\)) # (!\inst|1~0_combout\ & ((\B3~input_o\) # (\inst1|45~0_combout\))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101110110010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|1~0_combout\, + datac => \B3~input_o\, + datad => \inst1|45~0_combout\, + combout => \inst6~0_combout\); + +-- Location: LCCOMB_X1_Y25_N24 +\inst1|29~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|29~0_combout\ = \inst|29~0_combout\ $ (\inst6~0_combout\ $ (((\A0~input_o\ & \B0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000011101111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A0~input_o\, + datab => \B0~input_o\, + datac => \inst|29~0_combout\, + datad => \inst6~0_combout\, + combout => \inst1|29~0_combout\); + +-- Location: LCCOMB_X1_Y25_N10 +\inst1|51~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|51~0_combout\ = \A1~input_o\ $ (\B1~input_o\ $ (((!\A0~input_o\) # (!\B0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110100101", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst1|51~0_combout\); + +-- Location: LCCOMB_X1_Y25_N12 +\inst1|44~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|44~0_combout\ = \inst|44~0_combout\ $ (((!\inst6~0_combout\) # (!\inst1|51~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010100001111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|51~0_combout\, + datac => \inst|44~0_combout\, + datad => \inst6~0_combout\, + combout => \inst1|44~0_combout\); + +-- Location: LCCOMB_X1_Y25_N30 +\inst1|45~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|45~1_combout\ = (\A3~input_o\ & (\inst|1~0_combout\ $ (\B3~input_o\ $ (!\inst1|45~0_combout\)))) # (!\A3~input_o\ & ((\inst|1~0_combout\ & ((\inst1|45~0_combout\) # (!\B3~input_o\))) # (!\inst|1~0_combout\ & (\B3~input_o\ $ +-- (\inst1|45~0_combout\))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110110110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|1~0_combout\, + datac => \B3~input_o\, + datad => \inst1|45~0_combout\, + combout => \inst1|45~1_combout\); + +ww_S0 <= \S0~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S3 <= \S3~output_o\; + +ww_C4 <= \C4~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_0c_vhd_slow.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_0c_vhd_slow.sdo new file mode 100644 index 00000000..607b4bb7 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_0c_vhd_slow.sdo @@ -0,0 +1,339 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP3C16F484C6, +// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_7483") + (DATE "08/26/2019 23:13:46") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (538:538:538) (531:531:531)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (545:545:545) (527:527:527)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (546:546:546) (529:529:529)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (403:403:403) (434:434:434)) + (IOPATH i o (2234:2234:2234) (2246:2246:2246)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (559:559:559) (564:564:564)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (775:775:775) (936:936:936)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|27\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (2450:2450:2450) (2656:2656:2656)) + (PORT datad (2154:2154:2154) (2360:2360:2360)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|29\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (2401:2401:2401) (2604:2604:2604)) + (PORT datac (2371:2371:2371) (2559:2559:2559)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|51\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2401:2401:2401) (2595:2595:2595)) + (PORT datab (2449:2449:2449) (2655:2655:2655)) + (PORT datac (2369:2369:2369) (2571:2571:2571)) + (PORT datad (2155:2155:2155) (2360:2360:2360)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|1\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2437:2437:2437) (2626:2626:2626)) + (PORT datac (2402:2402:2402) (2609:2609:2609)) + (PORT datad (163:163:163) (185:185:185)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|51\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2399:2399:2399) (2594:2594:2594)) + (PORT datab (2444:2444:2444) (2656:2656:2656)) + (PORT datac (2372:2372:2372) (2576:2576:2576)) + (PORT datad (2160:2160:2160) (2366:2366:2366)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|44\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2436:2436:2436) (2625:2625:2625)) + (PORT datac (2402:2402:2402) (2608:2608:2608)) + (PORT datad (161:161:161) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|45\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (233:233:233)) + (PORT datab (2446:2446:2446) (2655:2655:2655)) + (PORT datac (165:165:165) (199:199:199)) + (PORT datad (2159:2159:2159) (2366:2366:2366)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2135:2135:2135) (2347:2347:2347)) + (PORT datab (191:191:191) (229:229:229)) + (PORT datac (2128:2128:2128) (2327:2327:2327)) + (PORT datad (167:167:167) (192:192:192)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|29\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2208:2208:2208) (2411:2411:2411)) + (PORT datab (2444:2444:2444) (2650:2650:2650)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (313:313:313) (312:312:312)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|51\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2398:2398:2398) (2595:2595:2595)) + (PORT datab (2447:2447:2447) (2654:2654:2654)) + (PORT datac (2370:2370:2370) (2574:2574:2574)) + (PORT datad (2157:2157:2157) (2360:2360:2360)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|44\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (224:224:224)) + (PORT datac (166:166:166) (203:203:203)) + (PORT datad (311:311:311) (313:313:313)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|45\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2137:2137:2137) (2350:2350:2350)) + (PORT datab (189:189:189) (226:226:226)) + (PORT datac (2130:2130:2130) (2328:2328:2328)) + (PORT datad (168:168:168) (190:190:190)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_85c_slow.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_85c_slow.vho new file mode 100644 index 00000000..b2cb9178 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_85c_slow.vho @@ -0,0 +1,495 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "08/26/2019 23:13:45" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_7483 IS + PORT ( + S0 : OUT std_logic; + B3 : IN std_logic; + A0 : IN std_logic; + A1 : IN std_logic; + B0 : IN std_logic; + B1 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A3 : IN std_logic; + S1 : OUT std_logic; + S2 : OUT std_logic; + S3 : OUT std_logic; + C4 : OUT std_logic + ); +END BCD_adder_7483; + +-- Design Ports Information +-- S0 => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S3 => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +-- C4 => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_J7, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_H7, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_H6, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_7483 IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_C4 : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \C4~output_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \inst|27~0_combout\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \inst|29~0_combout\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \inst|51~1_combout\ : std_logic; +SIGNAL \inst|1~0_combout\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \inst|51~0_combout\ : std_logic; +SIGNAL \inst|44~0_combout\ : std_logic; +SIGNAL \inst1|45~0_combout\ : std_logic; +SIGNAL \inst6~0_combout\ : std_logic; +SIGNAL \inst1|29~0_combout\ : std_logic; +SIGNAL \inst1|51~0_combout\ : std_logic; +SIGNAL \inst1|44~0_combout\ : std_logic; +SIGNAL \inst1|45~1_combout\ : std_logic; +SIGNAL \inst1|ALT_INV_45~1_combout\ : std_logic; + +BEGIN + +S0 <= ww_S0; +ww_B3 <= B3; +ww_A0 <= A0; +ww_A1 <= A1; +ww_B0 <= B0; +ww_B1 <= B1; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A3 <= A3; +S1 <= ww_S1; +S2 <= ww_S2; +S3 <= ww_S3; +C4 <= ww_C4; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +\inst1|ALT_INV_45~1_combout\ <= NOT \inst1|45~1_combout\; + +-- Location: IOOBUF_X0_Y27_N9 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|27~0_combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y26_N16 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|29~0_combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|44~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y24_N16 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|ALT_INV_45~1_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y27_N16 +\C4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst6~0_combout\, + devoe => ww_devoe, + o => \C4~output_o\); + +-- Location: IOIBUF_X0_Y22_N15 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X0_Y25_N1 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: LCCOMB_X1_Y25_N0 +\inst|27~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|27~0_combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011001111001100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datad => \A0~input_o\, + combout => \inst|27~0_combout\); + +-- Location: IOIBUF_X0_Y27_N22 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: LCCOMB_X1_Y25_N26 +\inst|29~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|29~0_combout\ = \B1~input_o\ $ (\A1~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B1~input_o\, + datac => \A1~input_o\, + combout => \inst|29~0_combout\); + +-- Location: IOIBUF_X0_Y25_N15 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y26_N8 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: IOIBUF_X0_Y23_N8 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: LCCOMB_X1_Y25_N2 +\inst|51~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|51~1_combout\ = (\A1~input_o\ & ((\B1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\A1~input_o\ & (\B0~input_o\ & (\B1~input_o\ & \A0~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110100010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst|51~1_combout\); + +-- Location: LCCOMB_X1_Y25_N28 +\inst|1~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|1~0_combout\ = (\A2~input_o\ & (!\B2~input_o\ & !\inst|51~1_combout\)) # (!\A2~input_o\ & ((!\inst|51~1_combout\) # (!\B2~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000010101011111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|51~1_combout\, + combout => \inst|1~0_combout\); + +-- Location: IOIBUF_X0_Y25_N22 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: LCCOMB_X1_Y25_N20 +\inst|51~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|51~0_combout\ = (\A1~input_o\ & (!\B1~input_o\ & ((!\A0~input_o\) # (!\B0~input_o\)))) # (!\A1~input_o\ & (((!\A0~input_o\) # (!\B1~input_o\)) # (!\B0~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001011101011111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst|51~0_combout\); + +-- Location: LCCOMB_X1_Y25_N22 +\inst|44~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|44~0_combout\ = \A2~input_o\ $ (\B2~input_o\ $ (\inst|51~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|51~0_combout\, + combout => \inst|44~0_combout\); + +-- Location: LCCOMB_X1_Y25_N16 +\inst1|45~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|45~0_combout\ = (\inst|29~0_combout\ $ (((\B0~input_o\ & \A0~input_o\)))) # (!\inst|44~0_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0111110111110101", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|44~0_combout\, + datab => \B0~input_o\, + datac => \inst|29~0_combout\, + datad => \A0~input_o\, + combout => \inst1|45~0_combout\); + +-- Location: LCCOMB_X1_Y25_N14 +\inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~0_combout\ = (\A3~input_o\ & (((\B3~input_o\) # (\inst1|45~0_combout\)) # (!\inst|1~0_combout\))) # (!\A3~input_o\ & ((\inst|1~0_combout\ & (\B3~input_o\ & \inst1|45~0_combout\)) # (!\inst|1~0_combout\ & ((\B3~input_o\) # (\inst1|45~0_combout\))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101110110010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|1~0_combout\, + datac => \B3~input_o\, + datad => \inst1|45~0_combout\, + combout => \inst6~0_combout\); + +-- Location: LCCOMB_X1_Y25_N24 +\inst1|29~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|29~0_combout\ = \inst|29~0_combout\ $ (\inst6~0_combout\ $ (((\A0~input_o\ & \B0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000011101111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A0~input_o\, + datab => \B0~input_o\, + datac => \inst|29~0_combout\, + datad => \inst6~0_combout\, + combout => \inst1|29~0_combout\); + +-- Location: LCCOMB_X1_Y25_N10 +\inst1|51~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|51~0_combout\ = \A1~input_o\ $ (\B1~input_o\ $ (((!\A0~input_o\) # (!\B0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110100101", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst1|51~0_combout\); + +-- Location: LCCOMB_X1_Y25_N12 +\inst1|44~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|44~0_combout\ = \inst|44~0_combout\ $ (((!\inst6~0_combout\) # (!\inst1|51~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010100001111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|51~0_combout\, + datac => \inst|44~0_combout\, + datad => \inst6~0_combout\, + combout => \inst1|44~0_combout\); + +-- Location: LCCOMB_X1_Y25_N30 +\inst1|45~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|45~1_combout\ = (\A3~input_o\ & (\inst|1~0_combout\ $ (\B3~input_o\ $ (!\inst1|45~0_combout\)))) # (!\A3~input_o\ & ((\inst|1~0_combout\ & ((\inst1|45~0_combout\) # (!\B3~input_o\))) # (!\inst|1~0_combout\ & (\B3~input_o\ $ +-- (\inst1|45~0_combout\))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110110110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|1~0_combout\, + datac => \B3~input_o\, + datad => \inst1|45~0_combout\, + combout => \inst1|45~1_combout\); + +ww_S0 <= \S0~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S3 <= \S3~output_o\; + +ww_C4 <= \C4~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_85c_vhd_slow.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_85c_vhd_slow.sdo new file mode 100644 index 00000000..bdafd46d --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_6_1200mv_85c_vhd_slow.sdo @@ -0,0 +1,339 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP3C16F484C6, +// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_7483") + (DATE "08/26/2019 23:13:45") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (587:587:587) (587:587:587)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (597:597:597) (595:595:595)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (596:596:596) (597:597:597)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (452:452:452) (459:459:459)) + (IOPATH i o (2234:2234:2234) (2246:2246:2246)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (608:608:608) (623:623:623)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (775:775:775) (936:936:936)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|27\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (2850:2850:2850) (3131:3131:3131)) + (PORT datad (2527:2527:2527) (2785:2785:2785)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|29\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (2792:2792:2792) (3052:3052:3052)) + (PORT datac (2756:2756:2756) (3008:3008:3008)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|51\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2791:2791:2791) (3052:3052:3052)) + (PORT datab (2849:2849:2849) (3130:3130:3130)) + (PORT datac (2758:2758:2758) (3013:3013:3013)) + (PORT datad (2527:2527:2527) (2785:2785:2785)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|1\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2837:2837:2837) (3088:3088:3088)) + (PORT datac (2798:2798:2798) (3070:3070:3070)) + (PORT datad (177:177:177) (204:204:204)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|51\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2788:2788:2788) (3051:3051:3051)) + (PORT datab (2843:2843:2843) (3130:3130:3130)) + (PORT datac (2761:2761:2761) (3018:3018:3018)) + (PORT datad (2532:2532:2532) (2792:2792:2792)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|44\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2836:2836:2836) (3088:3088:3088)) + (PORT datac (2797:2797:2797) (3070:3070:3070)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|45\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (260:260:260)) + (PORT datab (2845:2845:2845) (3128:3128:3128)) + (PORT datac (182:182:182) (220:220:220)) + (PORT datad (2532:2532:2532) (2791:2791:2791)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2503:2503:2503) (2773:2773:2773)) + (PORT datab (210:210:210) (254:254:254)) + (PORT datac (2497:2497:2497) (2753:2753:2753)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|29\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2576:2576:2576) (2841:2841:2841)) + (PORT datab (2844:2844:2844) (3125:3125:3125)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (335:335:335) (352:352:352)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|51\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2788:2788:2788) (3051:3051:3051)) + (PORT datab (2847:2847:2847) (3132:3132:3132)) + (PORT datac (2759:2759:2759) (3017:3017:3017)) + (PORT datad (2529:2529:2529) (2787:2787:2787)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|44\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datac (183:183:183) (222:222:222)) + (PORT datad (333:333:333) (353:353:353)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|45\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2506:2506:2506) (2775:2775:2775)) + (PORT datab (209:209:209) (251:251:251)) + (PORT datac (2498:2498:2498) (2751:2751:2751)) + (PORT datad (183:183:183) (210:210:210)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_min_1200mv_0c_fast.vho b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_min_1200mv_0c_fast.vho new file mode 100644 index 00000000..b2cb9178 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_min_1200mv_0c_fast.vho @@ -0,0 +1,495 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 32-bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "08/26/2019 23:13:45" + +-- +-- Device: Altera EP3C16F484C6 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIII; +LIBRARY IEEE; +USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY BCD_adder_7483 IS + PORT ( + S0 : OUT std_logic; + B3 : IN std_logic; + A0 : IN std_logic; + A1 : IN std_logic; + B0 : IN std_logic; + B1 : IN std_logic; + A2 : IN std_logic; + B2 : IN std_logic; + A3 : IN std_logic; + S1 : OUT std_logic; + S2 : OUT std_logic; + S3 : OUT std_logic; + C4 : OUT std_logic + ); +END BCD_adder_7483; + +-- Design Ports Information +-- S0 => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +-- S1 => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +-- S2 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +-- S3 => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +-- C4 => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +-- A0 => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +-- B0 => Location: PIN_J7, I/O Standard: 2.5 V, Current Strength: Default +-- A1 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +-- B1 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +-- A3 => Location: PIN_H7, I/O Standard: 2.5 V, Current Strength: Default +-- B3 => Location: PIN_H6, I/O Standard: 2.5 V, Current Strength: Default +-- A2 => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +-- B2 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF BCD_adder_7483 IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_S0 : std_logic; +SIGNAL ww_B3 : std_logic; +SIGNAL ww_A0 : std_logic; +SIGNAL ww_A1 : std_logic; +SIGNAL ww_B0 : std_logic; +SIGNAL ww_B1 : std_logic; +SIGNAL ww_A2 : std_logic; +SIGNAL ww_B2 : std_logic; +SIGNAL ww_A3 : std_logic; +SIGNAL ww_S1 : std_logic; +SIGNAL ww_S2 : std_logic; +SIGNAL ww_S3 : std_logic; +SIGNAL ww_C4 : std_logic; +SIGNAL \S0~output_o\ : std_logic; +SIGNAL \S1~output_o\ : std_logic; +SIGNAL \S2~output_o\ : std_logic; +SIGNAL \S3~output_o\ : std_logic; +SIGNAL \C4~output_o\ : std_logic; +SIGNAL \B0~input_o\ : std_logic; +SIGNAL \A0~input_o\ : std_logic; +SIGNAL \inst|27~0_combout\ : std_logic; +SIGNAL \B1~input_o\ : std_logic; +SIGNAL \A1~input_o\ : std_logic; +SIGNAL \inst|29~0_combout\ : std_logic; +SIGNAL \A3~input_o\ : std_logic; +SIGNAL \A2~input_o\ : std_logic; +SIGNAL \B2~input_o\ : std_logic; +SIGNAL \inst|51~1_combout\ : std_logic; +SIGNAL \inst|1~0_combout\ : std_logic; +SIGNAL \B3~input_o\ : std_logic; +SIGNAL \inst|51~0_combout\ : std_logic; +SIGNAL \inst|44~0_combout\ : std_logic; +SIGNAL \inst1|45~0_combout\ : std_logic; +SIGNAL \inst6~0_combout\ : std_logic; +SIGNAL \inst1|29~0_combout\ : std_logic; +SIGNAL \inst1|51~0_combout\ : std_logic; +SIGNAL \inst1|44~0_combout\ : std_logic; +SIGNAL \inst1|45~1_combout\ : std_logic; +SIGNAL \inst1|ALT_INV_45~1_combout\ : std_logic; + +BEGIN + +S0 <= ww_S0; +ww_B3 <= B3; +ww_A0 <= A0; +ww_A1 <= A1; +ww_B0 <= B0; +ww_B1 <= B1; +ww_A2 <= A2; +ww_B2 <= B2; +ww_A3 <= A3; +S1 <= ww_S1; +S2 <= ww_S2; +S3 <= ww_S3; +C4 <= ww_C4; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +\inst1|ALT_INV_45~1_combout\ <= NOT \inst1|45~1_combout\; + +-- Location: IOOBUF_X0_Y27_N9 +\S0~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|27~0_combout\, + devoe => ww_devoe, + o => \S0~output_o\); + +-- Location: IOOBUF_X0_Y26_N16 +\S1~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|29~0_combout\, + devoe => ww_devoe, + o => \S1~output_o\); + +-- Location: IOOBUF_X0_Y26_N23 +\S2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|44~0_combout\, + devoe => ww_devoe, + o => \S2~output_o\); + +-- Location: IOOBUF_X0_Y24_N16 +\S3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|ALT_INV_45~1_combout\, + devoe => ww_devoe, + o => \S3~output_o\); + +-- Location: IOOBUF_X0_Y27_N16 +\C4~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst6~0_combout\, + devoe => ww_devoe, + o => \C4~output_o\); + +-- Location: IOIBUF_X0_Y22_N15 +\B0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B0, + o => \B0~input_o\); + +-- Location: IOIBUF_X0_Y25_N1 +\A0~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A0, + o => \A0~input_o\); + +-- Location: LCCOMB_X1_Y25_N0 +\inst|27~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|27~0_combout\ = \B0~input_o\ $ (\A0~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011001111001100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B0~input_o\, + datad => \A0~input_o\, + combout => \inst|27~0_combout\); + +-- Location: IOIBUF_X0_Y27_N22 +\B1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B1, + o => \B1~input_o\); + +-- Location: IOIBUF_X0_Y26_N1 +\A1~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A1, + o => \A1~input_o\); + +-- Location: LCCOMB_X1_Y25_N26 +\inst|29~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|29~0_combout\ = \B1~input_o\ $ (\A1~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \B1~input_o\, + datac => \A1~input_o\, + combout => \inst|29~0_combout\); + +-- Location: IOIBUF_X0_Y25_N15 +\A3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A3, + o => \A3~input_o\); + +-- Location: IOIBUF_X0_Y26_N8 +\A2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_A2, + o => \A2~input_o\); + +-- Location: IOIBUF_X0_Y23_N8 +\B2~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B2, + o => \B2~input_o\); + +-- Location: LCCOMB_X1_Y25_N2 +\inst|51~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|51~1_combout\ = (\A1~input_o\ & ((\B1~input_o\) # ((\B0~input_o\ & \A0~input_o\)))) # (!\A1~input_o\ & (\B0~input_o\ & (\B1~input_o\ & \A0~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110100010100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst|51~1_combout\); + +-- Location: LCCOMB_X1_Y25_N28 +\inst|1~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|1~0_combout\ = (\A2~input_o\ & (!\B2~input_o\ & !\inst|51~1_combout\)) # (!\A2~input_o\ & ((!\inst|51~1_combout\) # (!\B2~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000010101011111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|51~1_combout\, + combout => \inst|1~0_combout\); + +-- Location: IOIBUF_X0_Y25_N22 +\B3~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_B3, + o => \B3~input_o\); + +-- Location: LCCOMB_X1_Y25_N20 +\inst|51~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|51~0_combout\ = (\A1~input_o\ & (!\B1~input_o\ & ((!\A0~input_o\) # (!\B0~input_o\)))) # (!\A1~input_o\ & (((!\A0~input_o\) # (!\B1~input_o\)) # (!\B0~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0001011101011111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst|51~0_combout\); + +-- Location: LCCOMB_X1_Y25_N22 +\inst|44~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst|44~0_combout\ = \A2~input_o\ $ (\B2~input_o\ $ (\inst|51~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010101011010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A2~input_o\, + datac => \B2~input_o\, + datad => \inst|51~0_combout\, + combout => \inst|44~0_combout\); + +-- Location: LCCOMB_X1_Y25_N16 +\inst1|45~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|45~0_combout\ = (\inst|29~0_combout\ $ (((\B0~input_o\ & \A0~input_o\)))) # (!\inst|44~0_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0111110111110101", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|44~0_combout\, + datab => \B0~input_o\, + datac => \inst|29~0_combout\, + datad => \A0~input_o\, + combout => \inst1|45~0_combout\); + +-- Location: LCCOMB_X1_Y25_N14 +\inst6~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst6~0_combout\ = (\A3~input_o\ & (((\B3~input_o\) # (\inst1|45~0_combout\)) # (!\inst|1~0_combout\))) # (!\A3~input_o\ & ((\inst|1~0_combout\ & (\B3~input_o\ & \inst1|45~0_combout\)) # (!\inst|1~0_combout\ & ((\B3~input_o\) # (\inst1|45~0_combout\))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101110110010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|1~0_combout\, + datac => \B3~input_o\, + datad => \inst1|45~0_combout\, + combout => \inst6~0_combout\); + +-- Location: LCCOMB_X1_Y25_N24 +\inst1|29~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|29~0_combout\ = \inst|29~0_combout\ $ (\inst6~0_combout\ $ (((\A0~input_o\ & \B0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000011101111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A0~input_o\, + datab => \B0~input_o\, + datac => \inst|29~0_combout\, + datad => \inst6~0_combout\, + combout => \inst1|29~0_combout\); + +-- Location: LCCOMB_X1_Y25_N10 +\inst1|51~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|51~0_combout\ = \A1~input_o\ $ (\B1~input_o\ $ (((!\A0~input_o\) # (!\B0~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110100110100101", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A1~input_o\, + datab => \B0~input_o\, + datac => \B1~input_o\, + datad => \A0~input_o\, + combout => \inst1|51~0_combout\); + +-- Location: LCCOMB_X1_Y25_N12 +\inst1|44~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|44~0_combout\ = \inst|44~0_combout\ $ (((!\inst6~0_combout\) # (!\inst1|51~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010100001111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|51~0_combout\, + datac => \inst|44~0_combout\, + datad => \inst6~0_combout\, + combout => \inst1|44~0_combout\); + +-- Location: LCCOMB_X1_Y25_N30 +\inst1|45~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst1|45~1_combout\ = (\A3~input_o\ & (\inst|1~0_combout\ $ (\B3~input_o\ $ (!\inst1|45~0_combout\)))) # (!\A3~input_o\ & ((\inst|1~0_combout\ & ((\inst1|45~0_combout\) # (!\B3~input_o\))) # (!\inst|1~0_combout\ & (\B3~input_o\ $ +-- (\inst1|45~0_combout\))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0110110110010110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \A3~input_o\, + datab => \inst|1~0_combout\, + datac => \B3~input_o\, + datad => \inst1|45~0_combout\, + combout => \inst1|45~1_combout\); + +ww_S0 <= \S0~output_o\; + +ww_S1 <= \S1~output_o\; + +ww_S2 <= \S2~output_o\; + +ww_S3 <= \S3~output_o\; + +ww_C4 <= \C4~output_o\; +END structure; + + diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_min_1200mv_0c_vhd_fast.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_min_1200mv_0c_vhd_fast.sdo new file mode 100644 index 00000000..27933b0a --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_min_1200mv_0c_vhd_fast.sdo @@ -0,0 +1,339 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Fast Corner delays for the design using part EP3C16F484C6, +// with speed grade M, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_7483") + (DATE "08/26/2019 23:13:46") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (318:318:318) (355:355:355)) + (IOPATH i o (1506:1506:1506) (1490:1490:1490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (317:317:317) (357:357:357)) + (IOPATH i o (1506:1506:1506) (1490:1490:1490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (317:317:317) (358:358:358)) + (IOPATH i o (1496:1496:1496) (1480:1480:1480)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (256:256:256) (230:230:230)) + (IOPATH i o (1470:1470:1470) (1486:1486:1486)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (331:331:331) (373:373:373)) + (IOPATH i o (1506:1506:1506) (1490:1490:1490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (381:381:381) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (431:431:431) (813:813:813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|27\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (1665:1665:1665) (1860:1860:1860)) + (PORT datad (1472:1472:1472) (1640:1640:1640)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (381:381:381) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (391:391:391) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|29\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (1634:1634:1634) (1821:1821:1821)) + (PORT datac (1606:1606:1606) (1786:1786:1786)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (381:381:381) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (391:391:391) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (391:391:391) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|51\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (1625:1625:1625) (1815:1815:1815)) + (PORT datab (1664:1664:1664) (1860:1860:1860)) + (PORT datac (1615:1615:1615) (1794:1794:1794)) + (PORT datad (1471:1471:1471) (1642:1642:1642)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|1\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1639:1639:1639) (1836:1836:1836)) + (PORT datac (1634:1634:1634) (1817:1817:1817)) + (PORT datad (94:94:94) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (381:381:381) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|51\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1621:1621:1621) (1811:1811:1811)) + (PORT datab (1660:1660:1660) (1855:1855:1855)) + (PORT datac (1619:1619:1619) (1798:1798:1798)) + (PORT datad (1476:1476:1476) (1649:1649:1649)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|44\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1639:1639:1639) (1835:1835:1835)) + (PORT datac (1634:1634:1634) (1817:1817:1817)) + (PORT datad (91:91:91) (107:107:107)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|45\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (1660:1660:1660) (1855:1855:1855)) + (PORT datac (96:96:96) (118:118:118)) + (PORT datad (1476:1476:1476) (1648:1648:1648)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1459:1459:1459) (1633:1633:1633)) + (PORT datab (109:109:109) (141:141:141)) + (PORT datac (1454:1454:1454) (1620:1620:1620)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|29\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1679:1679:1679)) + (PORT datab (1659:1659:1659) (1854:1854:1854)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (170:170:170) (197:197:197)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|51\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1814:1814:1814)) + (PORT datab (1663:1663:1663) (1858:1858:1858)) + (PORT datac (1616:1616:1616) (1795:1795:1795)) + (PORT datad (1473:1473:1473) (1642:1642:1642)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|44\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datac (97:97:97) (119:119:119)) + (PORT datad (170:170:170) (198:198:198)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|45\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (1462:1462:1462) (1636:1636:1636)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (1455:1455:1455) (1622:1622:1622)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_modelsim.xrf b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_modelsim.xrf new file mode 100644 index 00000000..af849624 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_modelsim.xrf @@ -0,0 +1,30 @@ +vendor_name = ModelSim +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/db/BCD_adder_7483.cbx.xml +source_file = 1, /home/timmy/altera/13.1/quartus/libraries/others/maxplus2/7483.bdf +design_name = BCD_adder_7483 +instance = comp, \S0~output\, S0~output, BCD_adder_7483, 1 +instance = comp, \S1~output\, S1~output, BCD_adder_7483, 1 +instance = comp, \S2~output\, S2~output, BCD_adder_7483, 1 +instance = comp, \S3~output\, S3~output, BCD_adder_7483, 1 +instance = comp, \C4~output\, C4~output, BCD_adder_7483, 1 +instance = comp, \B0~input\, B0~input, BCD_adder_7483, 1 +instance = comp, \A0~input\, A0~input, BCD_adder_7483, 1 +instance = comp, \inst|27~0\, inst|27~0, BCD_adder_7483, 1 +instance = comp, \B1~input\, B1~input, BCD_adder_7483, 1 +instance = comp, \A1~input\, A1~input, BCD_adder_7483, 1 +instance = comp, \inst|29~0\, inst|29~0, BCD_adder_7483, 1 +instance = comp, \A3~input\, A3~input, BCD_adder_7483, 1 +instance = comp, \A2~input\, A2~input, BCD_adder_7483, 1 +instance = comp, \B2~input\, B2~input, BCD_adder_7483, 1 +instance = comp, \inst|51~1\, inst|51~1, BCD_adder_7483, 1 +instance = comp, \inst|1~0\, inst|1~0, BCD_adder_7483, 1 +instance = comp, \B3~input\, B3~input, BCD_adder_7483, 1 +instance = comp, \inst|51~0\, inst|51~0, BCD_adder_7483, 1 +instance = comp, \inst|44~0\, inst|44~0, BCD_adder_7483, 1 +instance = comp, \inst1|45~0\, inst1|45~0, BCD_adder_7483, 1 +instance = comp, \inst6~0\, inst6~0, BCD_adder_7483, 1 +instance = comp, \inst1|29~0\, inst1|29~0, BCD_adder_7483, 1 +instance = comp, \inst1|51~0\, inst1|51~0, BCD_adder_7483, 1 +instance = comp, \inst1|44~0\, inst1|44~0, BCD_adder_7483, 1 +instance = comp, \inst1|45~1\, inst1|45~1, BCD_adder_7483, 1 diff --git a/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_vhd.sdo b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_vhd.sdo new file mode 100644 index 00000000..144cc1b0 --- /dev/null +++ b/CH5/CH5-3/simulation/modelsim/BCD_adder_7483_vhd.sdo @@ -0,0 +1,339 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP3C16F484C6, +// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "BCD_adder_7483") + (DATE "08/26/2019 23:13:46") + (VENDOR "Altera") + (PROGRAM "Quartus II 32-bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (587:587:587) (587:587:587)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (597:597:597) (595:595:595)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (596:596:596) (597:597:597)) + (IOPATH i o (2256:2256:2256) (2244:2244:2244)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\S3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (452:452:452) (459:459:459)) + (IOPATH i o (2234:2234:2234) (2246:2246:2246)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\C4\~output\\) + (DELAY + (ABSOLUTE + (PORT i (608:608:608) (623:623:623)) + (IOPATH i o (2266:2266:2266) (2254:2254:2254)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (775:775:775) (936:936:936)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|27\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (2850:2850:2850) (3131:3131:3131)) + (PORT datad (2527:2527:2527) (2785:2785:2785)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|29\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (2792:2792:2792) (3052:3052:3052)) + (PORT datac (2756:2756:2756) (3008:3008:3008)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\A2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B2\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (735:735:735) (896:896:896)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|51\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2791:2791:2791) (3052:3052:3052)) + (PORT datab (2849:2849:2849) (3130:3130:3130)) + (PORT datac (2758:2758:2758) (3013:3013:3013)) + (PORT datad (2527:2527:2527) (2785:2785:2785)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|1\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2837:2837:2837) (3088:3088:3088)) + (PORT datac (2798:2798:2798) (3070:3070:3070)) + (PORT datad (177:177:177) (204:204:204)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\B3\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (725:725:725) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|51\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2788:2788:2788) (3051:3051:3051)) + (PORT datab (2843:2843:2843) (3130:3130:3130)) + (PORT datac (2761:2761:2761) (3018:3018:3018)) + (PORT datad (2532:2532:2532) (2792:2792:2792)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\|44\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2836:2836:2836) (3088:3088:3088)) + (PORT datac (2797:2797:2797) (3070:3070:3070)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|45\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (260:260:260)) + (PORT datab (2845:2845:2845) (3128:3128:3128)) + (PORT datac (182:182:182) (220:220:220)) + (PORT datad (2532:2532:2532) (2791:2791:2791)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst6\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2503:2503:2503) (2773:2773:2773)) + (PORT datab (210:210:210) (254:254:254)) + (PORT datac (2497:2497:2497) (2753:2753:2753)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|29\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2576:2576:2576) (2841:2841:2841)) + (PORT datab (2844:2844:2844) (3125:3125:3125)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (335:335:335) (352:352:352)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|51\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2788:2788:2788) (3051:3051:3051)) + (PORT datab (2847:2847:2847) (3132:3132:3132)) + (PORT datac (2759:2759:2759) (3017:3017:3017)) + (PORT datad (2529:2529:2529) (2787:2787:2787)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|44\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datac (183:183:183) (222:222:222)) + (PORT datad (333:333:333) (353:353:353)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst1\|45\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2506:2506:2506) (2775:2775:2775)) + (PORT datab (209:209:209) (251:251:251)) + (PORT datac (2498:2498:2498) (2751:2751:2751)) + (PORT datad (183:183:183) (210:210:210)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) +) diff --git a/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.do b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.do new file mode 100644 index 00000000..be78ed01 --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.do @@ -0,0 +1,10 @@ +onerror {exit -code 1} +vlib work +vlog -work work BCD_adder_1D_G.vo +vlog -work work BCD_adder_1D_G.vwf.vt +vsim -novopt -c -t 1ps -L cycloneiii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.BCD_adder_1D_G_vlg_vec_tst -voptargs="+acc" +vcd file -direction BCD_adder_1D_G.msim.vcd +vcd add -internal BCD_adder_1D_G_vlg_vec_tst/* +vcd add -internal BCD_adder_1D_G_vlg_vec_tst/i1/* +run -all +quit -f diff --git a/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.msim.vcd b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.msim.vcd new file mode 100644 index 00000000..5772ca4e --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.msim.vcd @@ -0,0 +1,186 @@ +$comment + File created using the following command: + vcd file BCD_adder_1D_G.msim.vcd -direction +$end +$date + Mon Sep 9 21:07:10 2019 +$end +$version + ModelSim Version 10.1d +$end +$timescale + 1ps +$end +$scope module BCD_adder_1D_G_vlg_vec_tst $end +$var reg 1 ! A0 $end +$var reg 1 " A1 $end +$var reg 1 # A2 $end +$var reg 1 $ A3 $end +$var reg 1 % A4 $end +$var reg 1 & A5 $end +$var reg 1 ' A6 $end +$var reg 1 ( A7 $end +$var reg 1 ) B0 $end +$var reg 1 * B1 $end +$var reg 1 + B2 $end +$var reg 1 , B3 $end +$var reg 1 - B4 $end +$var reg 1 . B5 $end +$var reg 1 / B6 $end +$var reg 1 0 B7 $end +$var wire 1 1 C8 $end +$var wire 1 2 S0 $end +$var wire 1 3 S1 $end +$var wire 1 4 S2 $end +$var wire 1 5 S3 $end +$var wire 1 6 S4 $end +$var wire 1 7 S5 $end +$var wire 1 8 S6 $end +$var wire 1 9 S7 $end +$var wire 1 : sampler $end +$scope module i1 $end +$var wire 1 ; gnd $end +$var wire 1 < vcc $end +$var wire 1 = unknown $end +$var tri1 1 > devclrn $end +$var tri1 1 ? devpor $end +$var tri1 1 @ devoe $end +$var wire 1 A S3~output_o $end +$var wire 1 B S2~output_o $end +$var wire 1 C S1~output_o $end +$var wire 1 D S0~output_o $end +$var wire 1 E S7~output_o $end +$var wire 1 F S6~output_o $end +$var wire 1 G S5~output_o $end +$var wire 1 H S4~output_o $end +$var wire 1 I C8~output_o $end +$var wire 1 J A3~input_o $end +$var wire 1 K B3~input_o $end +$var wire 1 L B2~input_o $end +$var wire 1 M A1~input_o $end +$var wire 1 N B0~input_o $end +$var wire 1 O A0~input_o $end +$var wire 1 P B1~input_o $end +$var wire 1 Q inst|inst|inst3|inst2~0_combout $end +$var wire 1 R A2~input_o $end +$var wire 1 S inst|inst|inst2|inst2~0_combout $end +$var wire 1 T inst|inst|inst3|inst1|inst~0_combout $end +$var wire 1 U inst|inst6~0_combout $end +$var wire 1 V inst|inst2|inst|inst1|inst~0_combout $end +$var wire 1 W inst|inst6~1_combout $end +$var wire 1 X inst|inst|inst2|inst1|inst~0_combout $end +$var wire 1 Y inst|inst2|inst2|inst1|inst~0_combout $end +$var wire 1 Z inst|inst2|inst3|inst|inst~combout $end +$var wire 1 [ inst|inst|inst4|inst|inst~combout $end +$var wire 1 \ B7~input_o $end +$var wire 1 ] B6~input_o $end +$var wire 1 ^ A6~input_o $end +$var wire 1 _ inst4|inst|inst2|inst|inst~combout $end +$var wire 1 ` A4~input_o $end +$var wire 1 a B4~input_o $end +$var wire 1 b inst4|inst|inst4|inst2~1_combout $end +$var wire 1 c B5~input_o $end +$var wire 1 d inst4|inst|inst4|inst2~0_combout $end +$var wire 1 e A5~input_o $end +$var wire 1 f inst4|inst|inst3|inst2~0_combout $end +$var wire 1 g inst4|inst|inst3|inst1|inst~combout $end +$var wire 1 h A7~input_o $end +$var wire 1 i inst4|inst|inst2|inst2~0_combout $end +$var wire 1 j inst4|inst6~0_combout $end +$var wire 1 k inst4|inst6~1_combout $end +$var wire 1 l inst4|inst2|inst3|inst2~0_combout $end +$var wire 1 m inst4|inst2|inst2|inst2~0_combout $end +$var wire 1 n inst4|inst|inst|inst1|inst~0_combout $end +$var wire 1 o inst4|inst2|inst|inst1|inst~combout $end +$var wire 1 p inst4|inst2|inst2|inst1|inst~combout $end +$var wire 1 q inst4|inst2|inst3|inst1|inst~combout $end +$var wire 1 r inst4|inst|inst4|inst1|inst~combout $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +1! +0" +0# +0$ +1% +0& +0' +0( +0) +0* +1+ +0, +1- +1. +0/ +00 +01 +12 +03 +14 +05 +06 +07 +18 +09 +x: +0; +1< +x= +1> +1? +1@ +0A +1B +0C +1D +0E +1F +0G +0H +0I +0J +0K +1L +0M +0N +1O +0P +0Q +0R +0S +0T +1U +0V +0W +1X +1Y +0Z +1[ +0\ +0] +0^ +0_ +1` +1a +1b +1c +0d +0e +1f +0g +0h +0i +1j +0k +0l +0m +0n +0o +1p +0q +0r +$end +#1000000 diff --git a/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.sft b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.sft new file mode 100644 index 00000000..06a2ca45 --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (Verilog)" diff --git a/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.sim.vwf b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.sim.vwf new file mode 100644 index 00000000..1ac49616 --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.sim.vwf @@ -0,0 +1,909 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("A0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A5") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A6") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("A7") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B5") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B6") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B7") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("C8") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S5") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S6") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("S7") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +GROUP("A") +{ + MEMBERS = "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7"; +} + +GROUP("B") +{ + MEMBERS = "B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7"; +} + +GROUP("S") +{ + MEMBERS = "S0", "S1", "S2", "S3", "S4", "S5", "S6", "S7"; +} + +TRANSITION_LIST("A0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("A1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("A2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("A3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("A4") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("A5") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("A6") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("A7") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("B0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("B1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("B2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("B3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("B4") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("B5") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("B6") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("B7") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("C8") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("S0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("S1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("S2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("S3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("S4") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("S5") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("S6") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("S7") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "A"; + EXPAND_STATUS = EXPANDED; + RADIX = Unsigned; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8; +} + +DISPLAY_LINE +{ + CHANNEL = "A0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A5"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A6"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "A7"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "B"; + EXPAND_STATUS = EXPANDED; + RADIX = Unsigned; + TREE_INDEX = 9; + TREE_LEVEL = 0; + CHILDREN = 10, 11, 12, 13, 14, 15, 16, 17; +} + +DISPLAY_LINE +{ + CHANNEL = "B0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B5"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B6"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "B7"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "C8"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "S"; + EXPAND_STATUS = EXPANDED; + RADIX = Unsigned; + TREE_INDEX = 19; + TREE_LEVEL = 0; + CHILDREN = 20, 21, 22, 23, 24, 25, 26, 27; +} + +DISPLAY_LINE +{ + CHANNEL = "S0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 22; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 23; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 24; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S5"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 25; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S6"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 26; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "S7"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 27; + TREE_LEVEL = 1; + PARENT = 19; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.vo b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.vo new file mode 100644 index 00000000..7760a485 --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.vo @@ -0,0 +1,899 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 32-bit" +// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +// DATE "09/09/2019 21:07:09" + +// +// Device: Altera EP3C16F484C6 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module BCD_adder_1D_G ( + S3, + A3, + B3, + A2, + B2, + A1, + B1, + A0, + B0, + S2, + S1, + S0, + S7, + A7, + B7, + A6, + B6, + A5, + B5, + A4, + B4, + S6, + S5, + S4, + C8); +output S3; +input A3; +input B3; +input A2; +input B2; +input A1; +input B1; +input A0; +input B0; +output S2; +output S1; +output S0; +output S7; +input A7; +input B7; +input A6; +input B6; +input A5; +input B5; +input A4; +input B4; +output S6; +output S5; +output S4; +output C8; + +// Design Ports Information +// S3 => Location: PIN_R2, I/O Standard: 2.5 V, Current Strength: Default +// S2 => Location: PIN_P4, I/O Standard: 2.5 V, Current Strength: Default +// S1 => Location: PIN_V2, I/O Standard: 2.5 V, Current Strength: Default +// S0 => Location: PIN_U2, I/O Standard: 2.5 V, Current Strength: Default +// S7 => Location: PIN_K7, I/O Standard: 2.5 V, Current Strength: Default +// S6 => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// S5 => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +// S4 => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +// C8 => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// B3 => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default +// A3 => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +// A2 => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default +// B2 => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default +// B0 => Location: PIN_U8, I/O Standard: 2.5 V, Current Strength: Default +// A0 => Location: PIN_AA5, I/O Standard: 2.5 V, Current Strength: Default +// A1 => Location: PIN_R1, I/O Standard: 2.5 V, Current Strength: Default +// B1 => Location: PIN_P5, I/O Standard: 2.5 V, Current Strength: Default +// B7 => Location: PIN_J4, I/O Standard: 2.5 V, Current Strength: Default +// A4 => Location: PIN_H5, I/O Standard: 2.5 V, Current Strength: Default +// B4 => Location: PIN_E4, I/O Standard: 2.5 V, Current Strength: Default +// A5 => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +// B5 => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// A6 => Location: PIN_K8, I/O Standard: 2.5 V, Current Strength: Default +// B6 => Location: PIN_J3, I/O Standard: 2.5 V, Current Strength: Default +// A7 => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \S3~output_o ; +wire \S2~output_o ; +wire \S1~output_o ; +wire \S0~output_o ; +wire \S7~output_o ; +wire \S6~output_o ; +wire \S5~output_o ; +wire \S4~output_o ; +wire \C8~output_o ; +wire \A3~input_o ; +wire \B3~input_o ; +wire \B2~input_o ; +wire \A1~input_o ; +wire \B0~input_o ; +wire \A0~input_o ; +wire \B1~input_o ; +wire \inst|inst|inst3|inst2~0_combout ; +wire \A2~input_o ; +wire \inst|inst|inst2|inst2~0_combout ; +wire \inst|inst|inst3|inst1|inst~0_combout ; +wire \inst|inst6~0_combout ; +wire \inst|inst2|inst|inst1|inst~0_combout ; +wire \inst|inst6~1_combout ; +wire \inst|inst|inst2|inst1|inst~0_combout ; +wire \inst|inst2|inst2|inst1|inst~0_combout ; +wire \inst|inst2|inst3|inst|inst~combout ; +wire \inst|inst|inst4|inst|inst~combout ; +wire \B7~input_o ; +wire \B6~input_o ; +wire \A6~input_o ; +wire \inst4|inst|inst2|inst|inst~combout ; +wire \A4~input_o ; +wire \B4~input_o ; +wire \inst4|inst|inst4|inst2~1_combout ; +wire \B5~input_o ; +wire \inst4|inst|inst4|inst2~0_combout ; +wire \A5~input_o ; +wire \inst4|inst|inst3|inst2~0_combout ; +wire \inst4|inst|inst3|inst1|inst~combout ; +wire \A7~input_o ; +wire \inst4|inst|inst2|inst2~0_combout ; +wire \inst4|inst6~0_combout ; +wire \inst4|inst6~1_combout ; +wire \inst4|inst2|inst3|inst2~0_combout ; +wire \inst4|inst2|inst2|inst2~0_combout ; +wire \inst4|inst|inst|inst1|inst~0_combout ; +wire \inst4|inst2|inst|inst1|inst~combout ; +wire \inst4|inst2|inst2|inst1|inst~combout ; +wire \inst4|inst2|inst3|inst1|inst~combout ; +wire \inst4|inst|inst4|inst1|inst~combout ; + + +// Location: IOOBUF_X0_Y10_N2 +cycloneiii_io_obuf \S3~output ( + .i(\inst|inst2|inst|inst1|inst~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\S3~output_o ), + .obar()); +// synopsys translate_off +defparam \S3~output .bus_hold = "false"; +defparam \S3~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N23 +cycloneiii_io_obuf \S2~output ( + .i(\inst|inst2|inst2|inst1|inst~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\S2~output_o ), + .obar()); +// synopsys translate_off +defparam \S2~output .bus_hold = "false"; +defparam \S2~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N23 +cycloneiii_io_obuf \S1~output ( + .i(\inst|inst2|inst3|inst|inst~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\S1~output_o ), + .obar()); +// synopsys translate_off +defparam \S1~output .bus_hold = "false"; +defparam \S1~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N9 +cycloneiii_io_obuf \S0~output ( + .i(\inst|inst|inst4|inst|inst~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\S0~output_o ), + .obar()); +// synopsys translate_off +defparam \S0~output .bus_hold = "false"; +defparam \S0~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y22_N23 +cycloneiii_io_obuf \S7~output ( + .i(\inst4|inst2|inst|inst1|inst~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\S7~output_o ), + .obar()); +// synopsys translate_off +defparam \S7~output .bus_hold = "false"; +defparam \S7~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N23 +cycloneiii_io_obuf \S6~output ( + .i(\inst4|inst2|inst2|inst1|inst~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\S6~output_o ), + .obar()); +// synopsys translate_off +defparam \S6~output .bus_hold = "false"; +defparam \S6~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N23 +cycloneiii_io_obuf \S5~output ( + .i(\inst4|inst2|inst3|inst1|inst~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\S5~output_o ), + .obar()); +// synopsys translate_off +defparam \S5~output .bus_hold = "false"; +defparam \S5~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y22_N2 +cycloneiii_io_obuf \S4~output ( + .i(\inst4|inst|inst4|inst1|inst~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\S4~output_o ), + .obar()); +// synopsys translate_off +defparam \S4~output .bus_hold = "false"; +defparam \S4~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N16 +cycloneiii_io_obuf \C8~output ( + .i(\inst4|inst6~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\C8~output_o ), + .obar()); +// synopsys translate_off +defparam \C8~output .bus_hold = "false"; +defparam \C8~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y12_N22 +cycloneiii_io_ibuf \A3~input ( + .i(A3), + .ibar(gnd), + .o(\A3~input_o )); +// synopsys translate_off +defparam \A3~input .bus_hold = "false"; +defparam \A3~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N1 +cycloneiii_io_ibuf \B3~input ( + .i(B3), + .ibar(gnd), + .o(\B3~input_o )); +// synopsys translate_off +defparam \B3~input .bus_hold = "false"; +defparam \B3~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N15 +cycloneiii_io_ibuf \B2~input ( + .i(B2), + .ibar(gnd), + .o(\B2~input_o )); +// synopsys translate_off +defparam \B2~input .bus_hold = "false"; +defparam \B2~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N8 +cycloneiii_io_ibuf \A1~input ( + .i(A1), + .ibar(gnd), + .o(\A1~input_o )); +// synopsys translate_off +defparam \A1~input .bus_hold = "false"; +defparam \A1~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y0_N15 +cycloneiii_io_ibuf \B0~input ( + .i(B0), + .ibar(gnd), + .o(\B0~input_o )); +// synopsys translate_off +defparam \B0~input .bus_hold = "false"; +defparam \B0~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y0_N29 +cycloneiii_io_ibuf \A0~input ( + .i(A0), + .ibar(gnd), + .o(\A0~input_o )); +// synopsys translate_off +defparam \A0~input .bus_hold = "false"; +defparam \A0~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N8 +cycloneiii_io_ibuf \B1~input ( + .i(B1), + .ibar(gnd), + .o(\B1~input_o )); +// synopsys translate_off +defparam \B1~input .bus_hold = "false"; +defparam \B1~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y10_N24 +cycloneiii_lcell_comb \inst|inst|inst3|inst2~0 ( +// Equation(s): +// \inst|inst|inst3|inst2~0_combout = (\A1~input_o & ((\B1~input_o ) # ((\B0~input_o & \A0~input_o )))) # (!\A1~input_o & (\B0~input_o & (\A0~input_o & \B1~input_o ))) + + .dataa(\A1~input_o ), + .datab(\B0~input_o ), + .datac(\A0~input_o ), + .datad(\B1~input_o ), + .cin(gnd), + .combout(\inst|inst|inst3|inst2~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|inst|inst3|inst2~0 .lut_mask = 16'hEA80; +defparam \inst|inst|inst3|inst2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y0_N22 +cycloneiii_io_ibuf \A2~input ( + .i(A2), + .ibar(gnd), + .o(\A2~input_o )); +// synopsys translate_off +defparam \A2~input .bus_hold = "false"; +defparam \A2~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y10_N26 +cycloneiii_lcell_comb \inst|inst|inst2|inst2~0 ( +// Equation(s): +// \inst|inst|inst2|inst2~0_combout = (\B2~input_o & ((\inst|inst|inst3|inst2~0_combout ) # (\A2~input_o ))) # (!\B2~input_o & (\inst|inst|inst3|inst2~0_combout & \A2~input_o )) + + .dataa(\B2~input_o ), + .datab(\inst|inst|inst3|inst2~0_combout ), + .datac(gnd), + .datad(\A2~input_o ), + .cin(gnd), + .combout(\inst|inst|inst2|inst2~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|inst|inst2|inst2~0 .lut_mask = 16'hEE88; +defparam \inst|inst|inst2|inst2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y10_N12 +cycloneiii_lcell_comb \inst|inst|inst3|inst1|inst~0 ( +// Equation(s): +// \inst|inst|inst3|inst1|inst~0_combout = \A1~input_o $ (\B1~input_o $ (((\B0~input_o & \A0~input_o )))) + + .dataa(\A1~input_o ), + .datab(\B0~input_o ), + .datac(\A0~input_o ), + .datad(\B1~input_o ), + .cin(gnd), + .combout(\inst|inst|inst3|inst1|inst~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|inst|inst3|inst1|inst~0 .lut_mask = 16'h956A; +defparam \inst|inst|inst3|inst1|inst~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y10_N6 +cycloneiii_lcell_comb \inst|inst6~0 ( +// Equation(s): +// \inst|inst6~0_combout = (\inst|inst|inst3|inst1|inst~0_combout ) # (\inst|inst|inst3|inst2~0_combout $ (\B2~input_o $ (\A2~input_o ))) + + .dataa(\inst|inst|inst3|inst1|inst~0_combout ), + .datab(\inst|inst|inst3|inst2~0_combout ), + .datac(\B2~input_o ), + .datad(\A2~input_o ), + .cin(gnd), + .combout(\inst|inst6~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|inst6~0 .lut_mask = 16'hEBBE; +defparam \inst|inst6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y10_N0 +cycloneiii_lcell_comb \inst|inst2|inst|inst1|inst~0 ( +// Equation(s): +// \inst|inst2|inst|inst1|inst~0_combout = (\A3~input_o & (\B3~input_o $ (\inst|inst|inst2|inst2~0_combout $ (!\inst|inst6~0_combout )))) # (!\A3~input_o & ((\B3~input_o & (\inst|inst|inst2|inst2~0_combout $ (!\inst|inst6~0_combout ))) # (!\B3~input_o +// & (\inst|inst|inst2|inst2~0_combout & !\inst|inst6~0_combout )))) + + .dataa(\A3~input_o ), + .datab(\B3~input_o ), + .datac(\inst|inst|inst2|inst2~0_combout ), + .datad(\inst|inst6~0_combout ), + .cin(gnd), + .combout(\inst|inst2|inst|inst1|inst~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|inst2|inst|inst1|inst~0 .lut_mask = 16'h6896; +defparam \inst|inst2|inst|inst1|inst~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y10_N4 +cycloneiii_lcell_comb \inst|inst6~1 ( +// Equation(s): +// \inst|inst6~1_combout = (\A3~input_o & ((\B3~input_o ) # ((\inst|inst|inst2|inst2~0_combout ) # (\inst|inst6~0_combout )))) # (!\A3~input_o & ((\B3~input_o & ((\inst|inst|inst2|inst2~0_combout ) # (\inst|inst6~0_combout ))) # (!\B3~input_o & +// (\inst|inst|inst2|inst2~0_combout & \inst|inst6~0_combout )))) + + .dataa(\A3~input_o ), + .datab(\B3~input_o ), + .datac(\inst|inst|inst2|inst2~0_combout ), + .datad(\inst|inst6~0_combout ), + .cin(gnd), + .combout(\inst|inst6~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst|inst6~1 .lut_mask = 16'hFEE8; +defparam \inst|inst6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y10_N18 +cycloneiii_lcell_comb \inst|inst|inst2|inst1|inst~0 ( +// Equation(s): +// \inst|inst|inst2|inst1|inst~0_combout = \B2~input_o $ (\inst|inst|inst3|inst2~0_combout $ (\A2~input_o )) + + .dataa(\B2~input_o ), + .datab(\inst|inst|inst3|inst2~0_combout ), + .datac(gnd), + .datad(\A2~input_o ), + .cin(gnd), + .combout(\inst|inst|inst2|inst1|inst~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|inst|inst2|inst1|inst~0 .lut_mask = 16'h9966; +defparam \inst|inst|inst2|inst1|inst~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y10_N14 +cycloneiii_lcell_comb \inst|inst2|inst2|inst1|inst~0 ( +// Equation(s): +// \inst|inst2|inst2|inst1|inst~0_combout = \inst|inst|inst2|inst1|inst~0_combout $ (((!\inst|inst|inst3|inst1|inst~0_combout & \inst|inst6~1_combout ))) + + .dataa(\inst|inst|inst3|inst1|inst~0_combout ), + .datab(gnd), + .datac(\inst|inst6~1_combout ), + .datad(\inst|inst|inst2|inst1|inst~0_combout ), + .cin(gnd), + .combout(\inst|inst2|inst2|inst1|inst~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|inst2|inst2|inst1|inst~0 .lut_mask = 16'hAF50; +defparam \inst|inst2|inst2|inst1|inst~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y10_N16 +cycloneiii_lcell_comb \inst|inst2|inst3|inst|inst ( +// Equation(s): +// \inst|inst2|inst3|inst|inst~combout = \inst|inst|inst3|inst1|inst~0_combout $ (\inst|inst6~1_combout ) + + .dataa(\inst|inst|inst3|inst1|inst~0_combout ), + .datab(gnd), + .datac(\inst|inst6~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\inst|inst2|inst3|inst|inst~combout ), + .cout()); +// synopsys translate_off +defparam \inst|inst2|inst3|inst|inst .lut_mask = 16'h5A5A; +defparam \inst|inst2|inst3|inst|inst .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y10_N2 +cycloneiii_lcell_comb \inst|inst|inst4|inst|inst ( +// Equation(s): +// \inst|inst|inst4|inst|inst~combout = \B0~input_o $ (\A0~input_o ) + + .dataa(gnd), + .datab(\B0~input_o ), + .datac(\A0~input_o ), + .datad(gnd), + .cin(gnd), + .combout(\inst|inst|inst4|inst|inst~combout ), + .cout()); +// synopsys translate_off +defparam \inst|inst|inst4|inst|inst .lut_mask = 16'h3C3C; +defparam \inst|inst|inst4|inst|inst .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N1 +cycloneiii_io_ibuf \B7~input ( + .i(B7), + .ibar(gnd), + .o(\B7~input_o )); +// synopsys translate_off +defparam \B7~input .bus_hold = "false"; +defparam \B7~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N22 +cycloneiii_io_ibuf \B6~input ( + .i(B6), + .ibar(gnd), + .o(\B6~input_o )); +// synopsys translate_off +defparam \B6~input .bus_hold = "false"; +defparam \B6~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y22_N8 +cycloneiii_io_ibuf \A6~input ( + .i(A6), + .ibar(gnd), + .o(\A6~input_o )); +// synopsys translate_off +defparam \A6~input .bus_hold = "false"; +defparam \A6~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N24 +cycloneiii_lcell_comb \inst4|inst|inst2|inst|inst ( +// Equation(s): +// \inst4|inst|inst2|inst|inst~combout = \B6~input_o $ (\A6~input_o ) + + .dataa(\B6~input_o ), + .datab(gnd), + .datac(\A6~input_o ), + .datad(gnd), + .cin(gnd), + .combout(\inst4|inst|inst2|inst|inst~combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst|inst2|inst|inst .lut_mask = 16'h5A5A; +defparam \inst4|inst|inst2|inst|inst .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y27_N1 +cycloneiii_io_ibuf \A4~input ( + .i(A4), + .ibar(gnd), + .o(\A4~input_o )); +// synopsys translate_off +defparam \A4~input .bus_hold = "false"; +defparam \A4~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y26_N1 +cycloneiii_io_ibuf \B4~input ( + .i(B4), + .ibar(gnd), + .o(\B4~input_o )); +// synopsys translate_off +defparam \B4~input .bus_hold = "false"; +defparam \B4~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N10 +cycloneiii_lcell_comb \inst4|inst|inst4|inst2~1 ( +// Equation(s): +// \inst4|inst|inst4|inst2~1_combout = (\B4~input_o & ((\A4~input_o ) # (\inst|inst6~1_combout ))) + + .dataa(\A4~input_o ), + .datab(gnd), + .datac(\B4~input_o ), + .datad(\inst|inst6~1_combout ), + .cin(gnd), + .combout(\inst4|inst|inst4|inst2~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst|inst4|inst2~1 .lut_mask = 16'hF0A0; +defparam \inst4|inst|inst4|inst2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N8 +cycloneiii_io_ibuf \B5~input ( + .i(B5), + .ibar(gnd), + .o(\B5~input_o )); +// synopsys translate_off +defparam \B5~input .bus_hold = "false"; +defparam \B5~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N8 +cycloneiii_lcell_comb \inst4|inst|inst4|inst2~0 ( +// Equation(s): +// \inst4|inst|inst4|inst2~0_combout = (\A4~input_o & \inst|inst6~1_combout ) + + .dataa(\A4~input_o ), + .datab(gnd), + .datac(gnd), + .datad(\inst|inst6~1_combout ), + .cin(gnd), + .combout(\inst4|inst|inst4|inst2~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst|inst4|inst2~0 .lut_mask = 16'hAA00; +defparam \inst4|inst|inst4|inst2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N8 +cycloneiii_io_ibuf \A5~input ( + .i(A5), + .ibar(gnd), + .o(\A5~input_o )); +// synopsys translate_off +defparam \A5~input .bus_hold = "false"; +defparam \A5~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N28 +cycloneiii_lcell_comb \inst4|inst|inst3|inst2~0 ( +// Equation(s): +// \inst4|inst|inst3|inst2~0_combout = (\B5~input_o & ((\inst4|inst|inst4|inst2~1_combout ) # ((\inst4|inst|inst4|inst2~0_combout ) # (\A5~input_o )))) # (!\B5~input_o & (\A5~input_o & ((\inst4|inst|inst4|inst2~1_combout ) # +// (\inst4|inst|inst4|inst2~0_combout )))) + + .dataa(\inst4|inst|inst4|inst2~1_combout ), + .datab(\B5~input_o ), + .datac(\inst4|inst|inst4|inst2~0_combout ), + .datad(\A5~input_o ), + .cin(gnd), + .combout(\inst4|inst|inst3|inst2~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst|inst3|inst2~0 .lut_mask = 16'hFEC8; +defparam \inst4|inst|inst3|inst2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N18 +cycloneiii_lcell_comb \inst4|inst|inst3|inst1|inst ( +// Equation(s): +// \inst4|inst|inst3|inst1|inst~combout = \B5~input_o $ (\A5~input_o $ (((\inst4|inst|inst4|inst2~1_combout ) # (\inst4|inst|inst4|inst2~0_combout )))) + + .dataa(\inst4|inst|inst4|inst2~1_combout ), + .datab(\B5~input_o ), + .datac(\inst4|inst|inst4|inst2~0_combout ), + .datad(\A5~input_o ), + .cin(gnd), + .combout(\inst4|inst|inst3|inst1|inst~combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst|inst3|inst1|inst .lut_mask = 16'hC936; +defparam \inst4|inst|inst3|inst1|inst .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y27_N22 +cycloneiii_io_ibuf \A7~input ( + .i(A7), + .ibar(gnd), + .o(\A7~input_o )); +// synopsys translate_off +defparam \A7~input .bus_hold = "false"; +defparam \A7~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N22 +cycloneiii_lcell_comb \inst4|inst|inst2|inst2~0 ( +// Equation(s): +// \inst4|inst|inst2|inst2~0_combout = (\B6~input_o & ((\A6~input_o ) # (\inst4|inst|inst3|inst2~0_combout ))) # (!\B6~input_o & (\A6~input_o & \inst4|inst|inst3|inst2~0_combout )) + + .dataa(\B6~input_o ), + .datab(gnd), + .datac(\A6~input_o ), + .datad(\inst4|inst|inst3|inst2~0_combout ), + .cin(gnd), + .combout(\inst4|inst|inst2|inst2~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst|inst2|inst2~0 .lut_mask = 16'hFAA0; +defparam \inst4|inst|inst2|inst2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N20 +cycloneiii_lcell_comb \inst4|inst6~0 ( +// Equation(s): +// \inst4|inst6~0_combout = (\inst4|inst|inst3|inst1|inst~combout ) # (\B6~input_o $ (\inst4|inst|inst3|inst2~0_combout $ (\A6~input_o ))) + + .dataa(\B6~input_o ), + .datab(\inst4|inst|inst3|inst2~0_combout ), + .datac(\A6~input_o ), + .datad(\inst4|inst|inst3|inst1|inst~combout ), + .cin(gnd), + .combout(\inst4|inst6~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst6~0 .lut_mask = 16'hFF96; +defparam \inst4|inst6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N16 +cycloneiii_lcell_comb \inst4|inst6~1 ( +// Equation(s): +// \inst4|inst6~1_combout = (\B7~input_o & ((\A7~input_o ) # ((\inst4|inst|inst2|inst2~0_combout ) # (\inst4|inst6~0_combout )))) # (!\B7~input_o & ((\A7~input_o & ((\inst4|inst|inst2|inst2~0_combout ) # (\inst4|inst6~0_combout ))) # (!\A7~input_o & +// (\inst4|inst|inst2|inst2~0_combout & \inst4|inst6~0_combout )))) + + .dataa(\B7~input_o ), + .datab(\A7~input_o ), + .datac(\inst4|inst|inst2|inst2~0_combout ), + .datad(\inst4|inst6~0_combout ), + .cin(gnd), + .combout(\inst4|inst6~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst6~1 .lut_mask = 16'hFEE8; +defparam \inst4|inst6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N26 +cycloneiii_lcell_comb \inst4|inst2|inst3|inst2~0 ( +// Equation(s): +// \inst4|inst2|inst3|inst2~0_combout = (\inst|inst6~1_combout & ((\inst4|inst|inst3|inst1|inst~combout ) # (\inst4|inst6~1_combout ))) # (!\inst|inst6~1_combout & (\inst4|inst|inst3|inst1|inst~combout & \inst4|inst6~1_combout )) + + .dataa(\inst|inst6~1_combout ), + .datab(\inst4|inst|inst3|inst1|inst~combout ), + .datac(gnd), + .datad(\inst4|inst6~1_combout ), + .cin(gnd), + .combout(\inst4|inst2|inst3|inst2~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst2|inst3|inst2~0 .lut_mask = 16'hEE88; +defparam \inst4|inst2|inst3|inst2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N4 +cycloneiii_lcell_comb \inst4|inst2|inst2|inst2~0 ( +// Equation(s): +// \inst4|inst2|inst2|inst2~0_combout = (\inst4|inst2|inst3|inst2~0_combout & ((\inst4|inst6~1_combout ) # (\inst4|inst|inst2|inst|inst~combout $ (\inst4|inst|inst3|inst2~0_combout )))) # (!\inst4|inst2|inst3|inst2~0_combout & (\inst4|inst6~1_combout & +// (\inst4|inst|inst2|inst|inst~combout $ (\inst4|inst|inst3|inst2~0_combout )))) + + .dataa(\inst4|inst|inst2|inst|inst~combout ), + .datab(\inst4|inst|inst3|inst2~0_combout ), + .datac(\inst4|inst2|inst3|inst2~0_combout ), + .datad(\inst4|inst6~1_combout ), + .cin(gnd), + .combout(\inst4|inst2|inst2|inst2~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst2|inst2|inst2~0 .lut_mask = 16'hF660; +defparam \inst4|inst2|inst2|inst2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N6 +cycloneiii_lcell_comb \inst4|inst|inst|inst1|inst~0 ( +// Equation(s): +// \inst4|inst|inst|inst1|inst~0_combout = \A7~input_o $ (((\B6~input_o & ((\A6~input_o ) # (\inst4|inst|inst3|inst2~0_combout ))) # (!\B6~input_o & (\A6~input_o & \inst4|inst|inst3|inst2~0_combout )))) + + .dataa(\B6~input_o ), + .datab(\A7~input_o ), + .datac(\A6~input_o ), + .datad(\inst4|inst|inst3|inst2~0_combout ), + .cin(gnd), + .combout(\inst4|inst|inst|inst1|inst~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst|inst|inst1|inst~0 .lut_mask = 16'h366C; +defparam \inst4|inst|inst|inst1|inst~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N14 +cycloneiii_lcell_comb \inst4|inst2|inst|inst1|inst ( +// Equation(s): +// \inst4|inst2|inst|inst1|inst~combout = \inst|inst6~1_combout $ (\B7~input_o $ (\inst4|inst2|inst2|inst2~0_combout $ (\inst4|inst|inst|inst1|inst~0_combout ))) + + .dataa(\inst|inst6~1_combout ), + .datab(\B7~input_o ), + .datac(\inst4|inst2|inst2|inst2~0_combout ), + .datad(\inst4|inst|inst|inst1|inst~0_combout ), + .cin(gnd), + .combout(\inst4|inst2|inst|inst1|inst~combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst2|inst|inst1|inst .lut_mask = 16'h6996; +defparam \inst4|inst2|inst|inst1|inst .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N0 +cycloneiii_lcell_comb \inst4|inst2|inst2|inst1|inst ( +// Equation(s): +// \inst4|inst2|inst2|inst1|inst~combout = \inst4|inst|inst2|inst|inst~combout $ (\inst4|inst|inst3|inst2~0_combout $ (\inst4|inst2|inst3|inst2~0_combout $ (\inst4|inst6~1_combout ))) + + .dataa(\inst4|inst|inst2|inst|inst~combout ), + .datab(\inst4|inst|inst3|inst2~0_combout ), + .datac(\inst4|inst2|inst3|inst2~0_combout ), + .datad(\inst4|inst6~1_combout ), + .cin(gnd), + .combout(\inst4|inst2|inst2|inst1|inst~combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst2|inst2|inst1|inst .lut_mask = 16'h6996; +defparam \inst4|inst2|inst2|inst1|inst .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N2 +cycloneiii_lcell_comb \inst4|inst2|inst3|inst1|inst ( +// Equation(s): +// \inst4|inst2|inst3|inst1|inst~combout = \inst|inst6~1_combout $ (\inst4|inst|inst3|inst1|inst~combout $ (\inst4|inst6~1_combout )) + + .dataa(\inst|inst6~1_combout ), + .datab(\inst4|inst|inst3|inst1|inst~combout ), + .datac(gnd), + .datad(\inst4|inst6~1_combout ), + .cin(gnd), + .combout(\inst4|inst2|inst3|inst1|inst~combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst2|inst3|inst1|inst .lut_mask = 16'h9966; +defparam \inst4|inst2|inst3|inst1|inst .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N12 +cycloneiii_lcell_comb \inst4|inst|inst4|inst1|inst ( +// Equation(s): +// \inst4|inst|inst4|inst1|inst~combout = \A4~input_o $ (\B4~input_o $ (\inst|inst6~1_combout )) + + .dataa(\A4~input_o ), + .datab(gnd), + .datac(\B4~input_o ), + .datad(\inst|inst6~1_combout ), + .cin(gnd), + .combout(\inst4|inst|inst4|inst1|inst~combout ), + .cout()); +// synopsys translate_off +defparam \inst4|inst|inst4|inst1|inst .lut_mask = 16'hA55A; +defparam \inst4|inst|inst4|inst1|inst .sum_lutc_input = "datac"; +// synopsys translate_on + +assign S3 = \S3~output_o ; + +assign S2 = \S2~output_o ; + +assign S1 = \S1~output_o ; + +assign S0 = \S0~output_o ; + +assign S7 = \S7~output_o ; + +assign S6 = \S6~output_o ; + +assign S5 = \S5~output_o ; + +assign S4 = \S4~output_o ; + +assign C8 = \C8~output_o ; + +endmodule diff --git a/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.vwf.vt b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.vwf.vt new file mode 100644 index 00000000..fb3863d3 --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G.vwf.vt @@ -0,0 +1,589 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "09/09/2019 21:07:04" + +// Verilog Self-Checking Test Bench (with test vectors) for design : BCD_adder_1D_G +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module BCD_adder_1D_G_vlg_sample_tst( + A0, + A1, + A2, + A3, + A4, + A5, + A6, + A7, + B0, + B1, + B2, + B3, + B4, + B5, + B6, + B7, + sampler_tx +); +input A0; +input A1; +input A2; +input A3; +input A4; +input A5; +input A6; +input A7; +input B0; +input B1; +input B2; +input B3; +input B4; +input B5; +input B6; +input B7; +output sampler_tx; + +reg sample; +time current_time; +always @(A0 or A1 or A2 or A3 or A4 or A5 or A6 or A7 or B0 or B1 or B2 or B3 or B4 or B5 or B6 or B7) + +begin + if ($realtime > 0) + begin + if ($realtime == 0 || $realtime != current_time) + begin + if (sample === 1'bx) + sample = 0; + else + sample = ~sample; + end + current_time = $realtime; + end +end + +assign sampler_tx = sample; +endmodule + +module BCD_adder_1D_G_vlg_check_tst ( + C8, + S0, + S1, + S2, + S3, + S4, + S5, + S6, + S7, + sampler_rx +); +input C8; +input S0; +input S1; +input S2; +input S3; +input S4; +input S5; +input S6; +input S7; +input sampler_rx; + +reg C8_expected; +reg S0_expected; +reg S1_expected; +reg S2_expected; +reg S3_expected; +reg S4_expected; +reg S5_expected; +reg S6_expected; +reg S7_expected; + +reg C8_prev; +reg S0_prev; +reg S1_prev; +reg S2_prev; +reg S3_prev; +reg S4_prev; +reg S5_prev; +reg S6_prev; +reg S7_prev; + +reg C8_expected_prev; +reg S0_expected_prev; +reg S1_expected_prev; +reg S2_expected_prev; +reg S3_expected_prev; +reg S4_expected_prev; +reg S5_expected_prev; +reg S6_expected_prev; +reg S7_expected_prev; + +reg last_C8_exp; +reg last_S0_exp; +reg last_S1_exp; +reg last_S2_exp; +reg last_S3_exp; +reg last_S4_exp; +reg last_S5_exp; +reg last_S6_exp; +reg last_S7_exp; + +reg trigger; + +integer i; +integer nummismatches; + +reg [1:9] on_first_change ; + + +initial +begin +trigger = 0; +i = 0; +nummismatches = 0; +on_first_change = 9'b1; +end + +// update real /o prevs + +always @(trigger) +begin + C8_prev = C8; + S0_prev = S0; + S1_prev = S1; + S2_prev = S2; + S3_prev = S3; + S4_prev = S4; + S5_prev = S5; + S6_prev = S6; + S7_prev = S7; +end + +// update expected /o prevs + +always @(trigger) +begin + C8_expected_prev = C8_expected; + S0_expected_prev = S0_expected; + S1_expected_prev = S1_expected; + S2_expected_prev = S2_expected; + S3_expected_prev = S3_expected; + S4_expected_prev = S4_expected; + S5_expected_prev = S5_expected; + S6_expected_prev = S6_expected; + S7_expected_prev = S7_expected; +end + + + +// expected C8 +initial +begin + C8_expected = 1'bX; +end + +// expected S0 +initial +begin + S0_expected = 1'bX; +end + +// expected S1 +initial +begin + S1_expected = 1'bX; +end + +// expected S2 +initial +begin + S2_expected = 1'bX; +end + +// expected S3 +initial +begin + S3_expected = 1'bX; +end + +// expected S4 +initial +begin + S4_expected = 1'bX; +end + +// expected S5 +initial +begin + S5_expected = 1'bX; +end + +// expected S6 +initial +begin + S6_expected = 1'bX; +end + +// expected S7 +initial +begin + S7_expected = 1'bX; +end +// generate trigger +always @(C8_expected or C8 or S0_expected or S0 or S1_expected or S1 or S2_expected or S2 or S3_expected or S3 or S4_expected or S4 or S5_expected or S5 or S6_expected or S6 or S7_expected or S7) +begin + trigger <= ~trigger; +end + +always @(posedge sampler_rx or negedge sampler_rx) +begin +`ifdef debug_tbench + $display("Scanning pattern %d @time = %t",i,$realtime ); + i = i + 1; + $display("| expected C8 = %b | expected S0 = %b | expected S1 = %b | expected S2 = %b | expected S3 = %b | expected S4 = %b | expected S5 = %b | expected S6 = %b | expected S7 = %b | ",C8_expected_prev,S0_expected_prev,S1_expected_prev,S2_expected_prev,S3_expected_prev,S4_expected_prev,S5_expected_prev,S6_expected_prev,S7_expected_prev); + $display("| real C8 = %b | real S0 = %b | real S1 = %b | real S2 = %b | real S3 = %b | real S4 = %b | real S5 = %b | real S6 = %b | real S7 = %b | ",C8_prev,S0_prev,S1_prev,S2_prev,S3_prev,S4_prev,S5_prev,S6_prev,S7_prev); +`endif + if ( + ( C8_expected_prev !== 1'bx ) && ( C8_prev !== C8_expected_prev ) + && ((C8_expected_prev !== last_C8_exp) || + on_first_change[1]) + ) + begin + $display ("ERROR! Vector Mismatch for output port C8 :: @time = %t", $realtime); + $display (" Expected value = %b", C8_expected_prev); + $display (" Real value = %b", C8_prev); + nummismatches = nummismatches + 1; + on_first_change[1] = 1'b0; + last_C8_exp = C8_expected_prev; + end + if ( + ( S0_expected_prev !== 1'bx ) && ( S0_prev !== S0_expected_prev ) + && ((S0_expected_prev !== last_S0_exp) || + on_first_change[2]) + ) + begin + $display ("ERROR! Vector Mismatch for output port S0 :: @time = %t", $realtime); + $display (" Expected value = %b", S0_expected_prev); + $display (" Real value = %b", S0_prev); + nummismatches = nummismatches + 1; + on_first_change[2] = 1'b0; + last_S0_exp = S0_expected_prev; + end + if ( + ( S1_expected_prev !== 1'bx ) && ( S1_prev !== S1_expected_prev ) + && ((S1_expected_prev !== last_S1_exp) || + on_first_change[3]) + ) + begin + $display ("ERROR! Vector Mismatch for output port S1 :: @time = %t", $realtime); + $display (" Expected value = %b", S1_expected_prev); + $display (" Real value = %b", S1_prev); + nummismatches = nummismatches + 1; + on_first_change[3] = 1'b0; + last_S1_exp = S1_expected_prev; + end + if ( + ( S2_expected_prev !== 1'bx ) && ( S2_prev !== S2_expected_prev ) + && ((S2_expected_prev !== last_S2_exp) || + on_first_change[4]) + ) + begin + $display ("ERROR! Vector Mismatch for output port S2 :: @time = %t", $realtime); + $display (" Expected value = %b", S2_expected_prev); + $display (" Real value = %b", S2_prev); + nummismatches = nummismatches + 1; + on_first_change[4] = 1'b0; + last_S2_exp = S2_expected_prev; + end + if ( + ( S3_expected_prev !== 1'bx ) && ( S3_prev !== S3_expected_prev ) + && ((S3_expected_prev !== last_S3_exp) || + on_first_change[5]) + ) + begin + $display ("ERROR! Vector Mismatch for output port S3 :: @time = %t", $realtime); + $display (" Expected value = %b", S3_expected_prev); + $display (" Real value = %b", S3_prev); + nummismatches = nummismatches + 1; + on_first_change[5] = 1'b0; + last_S3_exp = S3_expected_prev; + end + if ( + ( S4_expected_prev !== 1'bx ) && ( S4_prev !== S4_expected_prev ) + && ((S4_expected_prev !== last_S4_exp) || + on_first_change[6]) + ) + begin + $display ("ERROR! Vector Mismatch for output port S4 :: @time = %t", $realtime); + $display (" Expected value = %b", S4_expected_prev); + $display (" Real value = %b", S4_prev); + nummismatches = nummismatches + 1; + on_first_change[6] = 1'b0; + last_S4_exp = S4_expected_prev; + end + if ( + ( S5_expected_prev !== 1'bx ) && ( S5_prev !== S5_expected_prev ) + && ((S5_expected_prev !== last_S5_exp) || + on_first_change[7]) + ) + begin + $display ("ERROR! Vector Mismatch for output port S5 :: @time = %t", $realtime); + $display (" Expected value = %b", S5_expected_prev); + $display (" Real value = %b", S5_prev); + nummismatches = nummismatches + 1; + on_first_change[7] = 1'b0; + last_S5_exp = S5_expected_prev; + end + if ( + ( S6_expected_prev !== 1'bx ) && ( S6_prev !== S6_expected_prev ) + && ((S6_expected_prev !== last_S6_exp) || + on_first_change[8]) + ) + begin + $display ("ERROR! Vector Mismatch for output port S6 :: @time = %t", $realtime); + $display (" Expected value = %b", S6_expected_prev); + $display (" Real value = %b", S6_prev); + nummismatches = nummismatches + 1; + on_first_change[8] = 1'b0; + last_S6_exp = S6_expected_prev; + end + if ( + ( S7_expected_prev !== 1'bx ) && ( S7_prev !== S7_expected_prev ) + && ((S7_expected_prev !== last_S7_exp) || + on_first_change[9]) + ) + begin + $display ("ERROR! Vector Mismatch for output port S7 :: @time = %t", $realtime); + $display (" Expected value = %b", S7_expected_prev); + $display (" Real value = %b", S7_prev); + nummismatches = nummismatches + 1; + on_first_change[9] = 1'b0; + last_S7_exp = S7_expected_prev; + end + + trigger <= ~trigger; +end +initial + +begin +$timeformat(-12,3," ps",6); +#1000000; +if (nummismatches > 0) + $display ("%d mismatched vectors : Simulation failed !",nummismatches); +else + $display ("Simulation passed !"); +$finish; +end +endmodule + +module BCD_adder_1D_G_vlg_vec_tst(); +// constants +// general purpose registers +reg A0; +reg A1; +reg A2; +reg A3; +reg A4; +reg A5; +reg A6; +reg A7; +reg B0; +reg B1; +reg B2; +reg B3; +reg B4; +reg B5; +reg B6; +reg B7; +// wires +wire C8; +wire S0; +wire S1; +wire S2; +wire S3; +wire S4; +wire S5; +wire S6; +wire S7; + +wire sampler; + +// assign statements (if any) +BCD_adder_1D_G i1 ( +// port map - connection between master ports and signals/registers + .A0(A0), + .A1(A1), + .A2(A2), + .A3(A3), + .A4(A4), + .A5(A5), + .A6(A6), + .A7(A7), + .B0(B0), + .B1(B1), + .B2(B2), + .B3(B3), + .B4(B4), + .B5(B5), + .B6(B6), + .B7(B7), + .C8(C8), + .S0(S0), + .S1(S1), + .S2(S2), + .S3(S3), + .S4(S4), + .S5(S5), + .S6(S6), + .S7(S7) +); + +// A0 +initial +begin + A0 = 1'b1; +end + +// A1 +initial +begin + A1 = 1'b0; +end + +// A2 +initial +begin + A2 = 1'b0; +end + +// A3 +initial +begin + A3 = 1'b0; +end + +// A4 +initial +begin + A4 = 1'b1; +end + +// A5 +initial +begin + A5 = 1'b0; +end + +// A6 +initial +begin + A6 = 1'b0; +end + +// A7 +initial +begin + A7 = 1'b0; +end + +// B0 +initial +begin + B0 = 1'b0; +end + +// B1 +initial +begin + B1 = 1'b0; +end + +// B2 +initial +begin + B2 = 1'b1; +end + +// B3 +initial +begin + B3 = 1'b0; +end + +// B4 +initial +begin + B4 = 1'b1; +end + +// B5 +initial +begin + B5 = 1'b1; +end + +// B6 +initial +begin + B6 = 1'b0; +end + +// B7 +initial +begin + B7 = 1'b0; +end + +BCD_adder_1D_G_vlg_sample_tst tb_sample ( + .A0(A0), + .A1(A1), + .A2(A2), + .A3(A3), + .A4(A4), + .A5(A5), + .A6(A6), + .A7(A7), + .B0(B0), + .B1(B1), + .B2(B2), + .B3(B3), + .B4(B4), + .B5(B5), + .B6(B6), + .B7(B7), + .sampler_tx(sampler) +); + +BCD_adder_1D_G_vlg_check_tst tb_out( + .C8(C8), + .S0(S0), + .S1(S1), + .S2(S2), + .S3(S3), + .S4(S4), + .S5(S5), + .S6(S6), + .S7(S7), + .sampler_rx(sampler) +); +endmodule + diff --git a/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G_modelsim.xrf b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G_modelsim.xrf new file mode 100644 index 00000000..a428fc1f --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/BCD_adder_1D_G_modelsim.xrf @@ -0,0 +1,61 @@ +vendor_name = ModelSim +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/eight_bit_adder.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Full_adder_S.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/Half_adder.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-1/four_bir_adder.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_7483.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.bdf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/BCD_adder_1D_G.vwf +source_file = 1, /home/timmy/Git/Learn-VHDL/CH5/CH5-3/db/BCD_adder_1D_G.cbx.xml +design_name = BCD_adder_1D_G +instance = comp, \S3~output , S3~output, BCD_adder_1D_G, 1 +instance = comp, \S2~output , S2~output, BCD_adder_1D_G, 1 +instance = comp, \S1~output , S1~output, BCD_adder_1D_G, 1 +instance = comp, \S0~output , S0~output, BCD_adder_1D_G, 1 +instance = comp, \S7~output , S7~output, BCD_adder_1D_G, 1 +instance = comp, \S6~output , S6~output, BCD_adder_1D_G, 1 +instance = comp, \S5~output , S5~output, BCD_adder_1D_G, 1 +instance = comp, \S4~output , S4~output, BCD_adder_1D_G, 1 +instance = comp, \C8~output , C8~output, BCD_adder_1D_G, 1 +instance = comp, \A3~input , A3~input, BCD_adder_1D_G, 1 +instance = comp, \B3~input , B3~input, BCD_adder_1D_G, 1 +instance = comp, \B2~input , B2~input, BCD_adder_1D_G, 1 +instance = comp, \A1~input , A1~input, BCD_adder_1D_G, 1 +instance = comp, \B0~input , B0~input, BCD_adder_1D_G, 1 +instance = comp, \A0~input , A0~input, BCD_adder_1D_G, 1 +instance = comp, \B1~input , B1~input, BCD_adder_1D_G, 1 +instance = comp, \inst|inst|inst3|inst2~0 , inst|inst|inst3|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \A2~input , A2~input, BCD_adder_1D_G, 1 +instance = comp, \inst|inst|inst2|inst2~0 , inst|inst|inst2|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst|inst3|inst1|inst~0 , inst|inst|inst3|inst1|inst~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst6~0 , inst|inst6~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst2|inst|inst1|inst~0 , inst|inst2|inst|inst1|inst~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst6~1 , inst|inst6~1, BCD_adder_1D_G, 1 +instance = comp, \inst|inst|inst2|inst1|inst~0 , inst|inst|inst2|inst1|inst~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst2|inst2|inst1|inst~0 , inst|inst2|inst2|inst1|inst~0, BCD_adder_1D_G, 1 +instance = comp, \inst|inst2|inst3|inst|inst , inst|inst2|inst3|inst|inst, BCD_adder_1D_G, 1 +instance = comp, \inst|inst|inst4|inst|inst , inst|inst|inst4|inst|inst, BCD_adder_1D_G, 1 +instance = comp, \B7~input , B7~input, BCD_adder_1D_G, 1 +instance = comp, \B6~input , B6~input, BCD_adder_1D_G, 1 +instance = comp, \A6~input , A6~input, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst2|inst|inst , inst4|inst|inst2|inst|inst, BCD_adder_1D_G, 1 +instance = comp, \A4~input , A4~input, BCD_adder_1D_G, 1 +instance = comp, \B4~input , B4~input, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst4|inst2~1 , inst4|inst|inst4|inst2~1, BCD_adder_1D_G, 1 +instance = comp, \B5~input , B5~input, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst4|inst2~0 , inst4|inst|inst4|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \A5~input , A5~input, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst3|inst2~0 , inst4|inst|inst3|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst3|inst1|inst , inst4|inst|inst3|inst1|inst, BCD_adder_1D_G, 1 +instance = comp, \A7~input , A7~input, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst2|inst2~0 , inst4|inst|inst2|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst6~0 , inst4|inst6~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst6~1 , inst4|inst6~1, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst2|inst3|inst2~0 , inst4|inst2|inst3|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst2|inst2|inst2~0 , inst4|inst2|inst2|inst2~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst|inst1|inst~0 , inst4|inst|inst|inst1|inst~0, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst2|inst|inst1|inst , inst4|inst2|inst|inst1|inst, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst2|inst2|inst1|inst , inst4|inst2|inst2|inst1|inst, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst2|inst3|inst1|inst , inst4|inst2|inst3|inst1|inst, BCD_adder_1D_G, 1 +instance = comp, \inst4|inst|inst4|inst1|inst , inst4|inst|inst4|inst1|inst, BCD_adder_1D_G, 1 diff --git a/CH5/CH5-3/simulation/qsim/transcript b/CH5/CH5-3/simulation/qsim/transcript new file mode 100644 index 00000000..f199030a --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/transcript @@ -0,0 +1,24 @@ +# do BCD_adder_1D_G.do +# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 +# -- Compiling module BCD_adder_1D_G +# +# Top level modules: +# BCD_adder_1D_G +# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 +# -- Compiling module BCD_adder_1D_G_vlg_sample_tst +# -- Compiling module BCD_adder_1D_G_vlg_check_tst +# -- Compiling module BCD_adder_1D_G_vlg_vec_tst +# +# Top level modules: +# BCD_adder_1D_G_vlg_vec_tst +# vsim -L cycloneiii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate -c -voptargs=\"+acc\" -t 1ps -novopt work.BCD_adder_1D_G_vlg_vec_tst +# Loading work.BCD_adder_1D_G_vlg_vec_tst +# Loading work.BCD_adder_1D_G +# Loading cycloneiii_ver.cycloneiii_io_obuf +# Loading cycloneiii_ver.cycloneiii_io_ibuf +# Loading cycloneiii_ver.cycloneiii_lcell_comb +# Loading work.BCD_adder_1D_G_vlg_sample_tst +# Loading work.BCD_adder_1D_G_vlg_check_tst +# Simulation passed ! +# ** Note: $finish : BCD_adder_1D_G.vwf.vt(394) +# Time: 1 us Iteration: 0 Instance: /BCD_adder_1D_G_vlg_vec_tst/tb_out diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/_primary.dat b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/_primary.dat new file mode 100644 index 00000000..beef19bc Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/_primary.dat differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/_primary.dbs b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/_primary.dbs new file mode 100644 index 00000000..2f3c8b5c Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/_primary.dbs differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/_primary.vhd b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/_primary.vhd new file mode 100644 index 00000000..1c9f0713 --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/_primary.vhd @@ -0,0 +1,31 @@ +library verilog; +use verilog.vl_types.all; +entity BCD_adder_1D_G is + port( + S3 : out vl_logic; + A3 : in vl_logic; + B3 : in vl_logic; + A2 : in vl_logic; + B2 : in vl_logic; + A1 : in vl_logic; + B1 : in vl_logic; + A0 : in vl_logic; + B0 : in vl_logic; + S2 : out vl_logic; + S1 : out vl_logic; + S0 : out vl_logic; + S7 : out vl_logic; + A7 : in vl_logic; + B7 : in vl_logic; + A6 : in vl_logic; + B6 : in vl_logic; + A5 : in vl_logic; + B5 : in vl_logic; + A4 : in vl_logic; + B4 : in vl_logic; + S6 : out vl_logic; + S5 : out vl_logic; + S4 : out vl_logic; + C8 : out vl_logic + ); +end BCD_adder_1D_G; diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/verilog.prw b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/verilog.prw new file mode 100644 index 00000000..f5528f99 Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/verilog.prw differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/verilog.psm b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/verilog.psm new file mode 100644 index 00000000..ef24a453 Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g/verilog.psm differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/_primary.dat b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/_primary.dat new file mode 100644 index 00000000..aa2c0c60 Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/_primary.dat differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/_primary.dbs b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/_primary.dbs new file mode 100644 index 00000000..c5b44a38 Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/_primary.dbs differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/_primary.vhd b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/_primary.vhd new file mode 100644 index 00000000..bf55f5d3 --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/_primary.vhd @@ -0,0 +1,16 @@ +library verilog; +use verilog.vl_types.all; +entity BCD_adder_1D_G_vlg_check_tst is + port( + C8 : in vl_logic; + S0 : in vl_logic; + S1 : in vl_logic; + S2 : in vl_logic; + S3 : in vl_logic; + S4 : in vl_logic; + S5 : in vl_logic; + S6 : in vl_logic; + S7 : in vl_logic; + sampler_rx : in vl_logic + ); +end BCD_adder_1D_G_vlg_check_tst; diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/verilog.prw b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/verilog.prw new file mode 100644 index 00000000..ffe2c5da Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/verilog.prw differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/verilog.psm b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/verilog.psm new file mode 100644 index 00000000..61fa6e06 Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_check_tst/verilog.psm differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/_primary.dat b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/_primary.dat new file mode 100644 index 00000000..027c68b1 Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/_primary.dat differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/_primary.dbs b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/_primary.dbs new file mode 100644 index 00000000..111ba07f Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/_primary.dbs differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/_primary.vhd b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/_primary.vhd new file mode 100644 index 00000000..49c2510b --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/_primary.vhd @@ -0,0 +1,23 @@ +library verilog; +use verilog.vl_types.all; +entity BCD_adder_1D_G_vlg_sample_tst is + port( + A0 : in vl_logic; + A1 : in vl_logic; + A2 : in vl_logic; + A3 : in vl_logic; + A4 : in vl_logic; + A5 : in vl_logic; + A6 : in vl_logic; + A7 : in vl_logic; + B0 : in vl_logic; + B1 : in vl_logic; + B2 : in vl_logic; + B3 : in vl_logic; + B4 : in vl_logic; + B5 : in vl_logic; + B6 : in vl_logic; + B7 : in vl_logic; + sampler_tx : out vl_logic + ); +end BCD_adder_1D_G_vlg_sample_tst; diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/verilog.prw b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/verilog.prw new file mode 100644 index 00000000..10568e2b Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/verilog.prw differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/verilog.psm b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/verilog.psm new file mode 100644 index 00000000..5ad5ae95 Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_sample_tst/verilog.psm differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_vec_tst/_primary.dat b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_vec_tst/_primary.dat new file mode 100644 index 00000000..78727864 Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_vec_tst/_primary.dat differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_vec_tst/_primary.dbs b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_vec_tst/_primary.dbs new file mode 100644 index 00000000..f7386d3e Binary files /dev/null and b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_vec_tst/_primary.dbs differ diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_vec_tst/_primary.vhd b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_vec_tst/_primary.vhd new file mode 100644 index 00000000..bb762a8a --- /dev/null +++ b/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_vec_tst/_primary.vhd @@ -0,0 +1,4 @@ +library verilog; +use verilog.vl_types.all; +entity BCD_adder_1D_G_vlg_vec_tst is +end BCD_adder_1D_G_vlg_vec_tst; diff --git a/CH5/CH5-3/simulation/qsim/work/@b@c@d_adder_1@d_@g_vlg_vec_tst/verilog.prw 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