如果採用，此拉請求將完成加法器與減法器實習 5-3 BCD加法器的實習所有工作項目

CH5/CH5-3/BCD_adder_1D.bsf

@@ -0,0 +1,127 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 112 208)
+	(text "BCD_adder_1D" (rect 5 0 98 12)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 178 25 188)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "A3" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "A3" (rect 21 27 38 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "B3" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "B3" (rect 21 43 38 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "A2" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "A2" (rect 21 59 38 71)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "B2" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "B2" (rect 21 75 38 87)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "A1" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "A1" (rect 21 91 38 103)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "B1" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "B1" (rect 21 107 38 119)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 16 112))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "A0" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "A0" (rect 21 123 38 135)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 16 128))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "B0" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "B0" (rect 21 139 38 151)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 16 144))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "C0" (rect 0 0 18 12)(font "Arial" (font_size 8)))
+		(text "C0" (rect 21 155 39 167)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 16 160))
+	)
+	(port
+		(pt 96 32)
+		(output)
+		(text "S3" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "S3" (rect 58 27 75 39)(font "Arial" (font_size 8)))
+		(line (pt 96 32)(pt 80 32))
+	)
+	(port
+		(pt 96 48)
+		(output)
+		(text "S2" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "S2" (rect 58 43 75 55)(font "Arial" (font_size 8)))
+		(line (pt 96 48)(pt 80 48))
+	)
+	(port
+		(pt 96 64)
+		(output)
+		(text "S1" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "S1" (rect 58 59 75 71)(font "Arial" (font_size 8)))
+		(line (pt 96 64)(pt 80 64))
+	)
+	(port
+		(pt 96 80)
+		(output)
+		(text "S0" (rect 0 0 17 12)(font "Arial" (font_size 8)))
+		(text "S0" (rect 58 75 75 87)(font "Arial" (font_size 8)))
+		(line (pt 96 80)(pt 80 80))
+	)
+	(port
+		(pt 96 96)
+		(output)
+		(text "C4" (rect 0 0 18 12)(font "Arial" (font_size 8)))
+		(text "C4" (rect 57 91 75 103)(font "Arial" (font_size 8)))
+		(line (pt 96 96)(pt 80 96))
+	)
+	(drawing
+		(rectangle (rect 16 16 80 176))
+	)
+)

CH5/CH5-3/BCD_adder_1D.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 19:10:01  September 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "19:10:01  September 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "BCD_adder_1D"

CH5/CH5-3/BCD_adder_1D.qsf

@@ -0,0 +1,75 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 19:10:01  September 05, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		BCD_adder_1D_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY BCD_adder_1D
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:10:01  SEPTEMBER 05, 2019"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name BDF_FILE BCD_adder_7483.bdf
+set_global_assignment -name BDF_FILE "../CH5-1/Full_adder_S.bdf"
+set_global_assignment -name BDF_FILE "../CH5-1/four_bir_adder.bdf"
+set_global_assignment -name BDF_FILE "../CH5-1/eight_bit_adder.bdf"
+set_global_assignment -name BDF_FILE "../CH5-1/Half_adder.bdf"
+set_global_assignment -name BDF_FILE BCD_adder_1D.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_H7 -to A0
+set_location_assignment PIN_E3 -to A1
+set_location_assignment PIN_E4 -to A2
+set_location_assignment PIN_D2 -to A3
+set_location_assignment PIN_H6 -to B0
+set_location_assignment PIN_G4 -to B1
+set_location_assignment PIN_G5 -to B2
+set_location_assignment PIN_J7 -to B3
+set_location_assignment PIN_B1 -to C4
+set_location_assignment PIN_E1 -to S0
+set_location_assignment PIN_C1 -to S1
+set_location_assignment PIN_C2 -to S2
+set_location_assignment PIN_B2 -to S3
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top