From 28d11c1fefa2ecd9a3ce8fbd8e8671eb60388cd3 Mon Sep 17 00:00:00 2001
From: Wu Chenzhi <38396747+timmy61109@users.noreply.github.com>
Date: Thu, 24 Oct 2019 22:38:55 +0800
Subject: [PATCH] =?UTF-8?q?Revert=20"=E5=AE=8C=E6=88=90=E7=AC=AC=E5=85=AD?=
 =?UTF-8?q?=E7=AB=A0=E7=AC=AC=E4=B8=80=E7=AF=80"?=
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Content-Transfer-Encoding: 8bit

---
 .gitignore                                    |  109 --
 CH6/CH6-1/BCD_to_decimal_decoder.bdf          | 1333 ----------------
 CH6/CH6-1/BCD_to_decimal_decoder.qpf          |   30 -
 CH6/CH6-1/BCD_to_decimal_decoder.qsf          |   59 -
 CH6/CH6-1/BCD_to_decimal_decoder.vwf          |  458 ------
 .../Ten_line_to_four_line_BCD_encoder.bdf     |  621 --------
 .../Ten_line_to_four_line_BCD_encoder.qpf     |   30 -
 .../Ten_line_to_four_line_BCD_encoder.qsf     |   72 -
 ...r_line_BCD_encoder_assignment_defaults.qdf |  728 ---------
 CH6/CH6-1/db/.cmp.kpt                         |  Bin 225 -> 0 bytes
 .../db/BCD_to_decimal_decoder.(0).cnf.cdb     |  Bin 1474 -> 0 bytes
 .../db/BCD_to_decimal_decoder.(0).cnf.hdb     |  Bin 829 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.asm.qmsg  |    6 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.asm.rdb   |  Bin 1359 -> 0 bytes
 .../db/BCD_to_decimal_decoder.asm_labs.ddb    |  Bin 9975 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.cbx.xml   |    5 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.bpm   |  Bin 738 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.cdb   |  Bin 5294 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.hdb   |  Bin 10834 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.idb   |  Bin 1185 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.logdb |   56 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.rdb   |  Bin 22371 -> 0 bytes
 .../db/BCD_to_decimal_decoder.cmp_merge.kpt   |  Bin 223 -> 0 bytes
 ...da_io_sim_cache.31um_ff_1200mv_0c_fast.hsd |  Bin 388256 -> 0 bytes
 ...a_io_sim_cache.31um_tt_1200mv_85c_slow.hsd |  Bin 382865 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.eda.qmsg  |    5 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.fit.qmsg  |   48 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.hier_info |   32 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.hif       |  Bin 345 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.ipinfo    |  Bin 162 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.lpc.html  |   18 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.lpc.rdb   |  Bin 399 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.lpc.txt   |    5 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.map.ammdb |  Bin 128 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.map.bpm   |  Bin 707 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.map.cdb   |  Bin 2823 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.map.hdb   |  Bin 10082 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.map.kpt   |  Bin 222 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.map.logdb |    1 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.map.qmsg  |   10 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.map.rdb   |  Bin 1309 -> 0 bytes
 .../db/BCD_to_decimal_decoder.map_bb.cdb      |  Bin 1892 -> 0 bytes
 .../db/BCD_to_decimal_decoder.map_bb.hdb      |  Bin 9139 -> 0 bytes
 .../db/BCD_to_decimal_decoder.map_bb.logdb    |    1 -
 .../db/BCD_to_decimal_decoder.pre_map.hdb     |  Bin 10039 -> 0 bytes
 .../db/BCD_to_decimal_decoder.pti_db_list.ddb |  Bin 245 -> 0 bytes
 ...imal_decoder.root_partition.map.reg_db.cdb |  Bin 232 -> 0 bytes
 .../db/BCD_to_decimal_decoder.routing.rdb     |  Bin 4595 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.rtlv.hdb  |  Bin 10008 -> 0 bytes
 .../db/BCD_to_decimal_decoder.rtlv_sg.cdb     |  Bin 1302 -> 0 bytes
 .../BCD_to_decimal_decoder.rtlv_sg_swap.cdb   |  Bin 203 -> 0 bytes
 .../db/BCD_to_decimal_decoder.sgdiff.cdb      |  Bin 2409 -> 0 bytes
 .../db/BCD_to_decimal_decoder.sgdiff.hdb      |  Bin 10158 -> 0 bytes
 ...CD_to_decimal_decoder.sld_design_entry.sci |  Bin 276 -> 0 bytes
 ...o_decimal_decoder.sld_design_entry_dsc.sci |  Bin 276 -> 0 bytes
 .../BCD_to_decimal_decoder.smart_action.txt   |    1 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.sta.qmsg  |   49 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.sta.rdb   |  Bin 10221 -> 0 bytes
 ...imal_decoder.sta_cmp.6_slow_1200mv_85c.tdb |  Bin 4388 -> 0 bytes
 .../db/BCD_to_decimal_decoder.tis_db_list.ddb |  Bin 301 -> 0 bytes
 ..._decimal_decoder.tiscmp.fast_1200mv_0c.ddb |  Bin 106380 -> 0 bytes
 ..._decimal_decoder.tiscmp.slow_1200mv_0c.ddb |  Bin 106930 -> 0 bytes
 ...decimal_decoder.tiscmp.slow_1200mv_85c.ddb |  Bin 106894 -> 0 bytes
 CH6/CH6-1/db/BCD_to_decimal_decoder.tmw_info  |    5 -
 CH6/CH6-1/db/BCD_to_decimal_decoder.vpr.ammdb |  Bin 313 -> 0 bytes
 .../Ten_line_to_four_line_BCD_encoder.db_info |    3 -
 ...o_sixteen_line_decimal_decoder.(0).cnf.cdb |  Bin 1233 -> 0 bytes
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 ...e_to_sixteen_line_decimal_decoder.asm.qmsg |    6 -
 ...ne_to_sixteen_line_decimal_decoder.asm.rdb |  Bin 1374 -> 0 bytes
 ..._sixteen_line_decimal_decoder.asm_labs.ddb |  Bin 10304 -> 0 bytes
 ...ne_to_sixteen_line_decimal_decoder.cbx.xml |    5 -
 ...ne_to_sixteen_line_decimal_decoder.cmp.bpm |  Bin 807 -> 0 bytes
 ...ne_to_sixteen_line_decimal_decoder.cmp.cdb |  Bin 6012 -> 0 bytes
 ...ne_to_sixteen_line_decimal_decoder.cmp.hdb |  Bin 11368 -> 0 bytes
 ...ne_to_sixteen_line_decimal_decoder.cmp.idb |  Bin 1372 -> 0 bytes
 ..._to_sixteen_line_decimal_decoder.cmp.logdb |   62 -
 ...ne_to_sixteen_line_decimal_decoder.cmp.rdb |  Bin 23324 -> 0 bytes
 ...sixteen_line_decimal_decoder.cmp_merge.kpt |  Bin 232 -> 0 bytes
 ...da_io_sim_cache.31um_ff_1200mv_0c_fast.hsd |  Bin 388822 -> 0 bytes
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 ...e_to_sixteen_line_decimal_decoder.eda.qmsg |    5 -
 ...e_to_sixteen_line_decimal_decoder.fit.qmsg |   48 -
 ..._to_sixteen_line_decimal_decoder.hier_info |   61 -
 ...r_line_to_sixteen_line_decimal_decoder.hif |  Bin 414 -> 0 bytes
 ...ine_to_sixteen_line_decimal_decoder.ipinfo |  Bin 162 -> 0 bytes
 ...e_to_sixteen_line_decimal_decoder.lpc.html |   18 -
 ...ne_to_sixteen_line_decimal_decoder.lpc.rdb |  Bin 399 -> 0 bytes
 ...ne_to_sixteen_line_decimal_decoder.lpc.txt |    5 -
 ..._to_sixteen_line_decimal_decoder.map.ammdb |  Bin 128 -> 0 bytes
 ...ne_to_sixteen_line_decimal_decoder.map.bpm |  Bin 768 -> 0 bytes
 ...ne_to_sixteen_line_decimal_decoder.map.cdb |  Bin 2837 -> 0 bytes
 ...ne_to_sixteen_line_decimal_decoder.map.hdb |  Bin 10125 -> 0 bytes
 ...ne_to_sixteen_line_decimal_decoder.map.kpt |  Bin 229 -> 0 bytes
 ..._to_sixteen_line_decimal_decoder.map.logdb |    1 -
 ...e_to_sixteen_line_decimal_decoder.map.qmsg |   12 -
 ...ne_to_sixteen_line_decimal_decoder.map.rdb |  Bin 1322 -> 0 bytes
 ...to_sixteen_line_decimal_decoder.map_bb.cdb |  Bin 1930 -> 0 bytes
 ...to_sixteen_line_decimal_decoder.map_bb.hdb |  Bin 8944 -> 0 bytes
 ..._sixteen_line_decimal_decoder.map_bb.logdb |    1 -
 ...o_sixteen_line_decimal_decoder.pre_map.hdb |  Bin 10338 -> 0 bytes
 ...xteen_line_decimal_decoder.pti_db_list.ddb |  Bin 245 -> 0 bytes
 ...imal_decoder.root_partition.map.reg_db.cdb |  Bin 248 -> 0 bytes
 ...o_sixteen_line_decimal_decoder.routing.rdb |  Bin 5166 -> 0 bytes
 ...e_to_sixteen_line_decimal_decoder.rtlv.hdb |  Bin 10271 -> 0 bytes
 ...o_sixteen_line_decimal_decoder.rtlv_sg.cdb |  Bin 2121 -> 0 bytes
 ...teen_line_decimal_decoder.rtlv_sg_swap.cdb |  Bin 658 -> 0 bytes
 ...to_sixteen_line_decimal_decoder.sgdiff.cdb |  Bin 2433 -> 0 bytes
 ...to_sixteen_line_decimal_decoder.sgdiff.hdb |  Bin 10083 -> 0 bytes
 ..._line_decimal_decoder.sld_design_entry.sci |  Bin 276 -> 0 bytes
 ...e_decimal_decoder.sld_design_entry_dsc.sci |  Bin 276 -> 0 bytes
 ...teen_line_decimal_decoder.smart_action.txt |    1 -
 ...e_to_sixteen_line_decimal_decoder.sta.qmsg |   49 -
 ...ne_to_sixteen_line_decimal_decoder.sta.rdb |  Bin 13326 -> 0 bytes
 ...imal_decoder.sta_cmp.6_slow_1200mv_85c.tdb |  Bin 5854 -> 0 bytes
 ...xteen_line_decimal_decoder.tis_db_list.ddb |  Bin 301 -> 0 bytes
 ..._decimal_decoder.tiscmp.fast_1200mv_0c.ddb |  Bin 109061 -> 0 bytes
 ..._decimal_decoder.tiscmp.slow_1200mv_0c.ddb |  Bin 109417 -> 0 bytes
 ...decimal_decoder.tiscmp.slow_1200mv_85c.ddb |  Bin 109322 -> 0 bytes
 ..._to_sixteen_line_decimal_decoder.vpr.ammdb |  Bin 313 -> 0 bytes
 CH6/CH6-1/db/logic_util_heursitic.dat         |  Bin 2948 -> 0 bytes
 .../db/prev_cmp_BCD_to_decimal_decoder.qmsg   |  126 --
 ...cmp_Ten_line_to_four_line_BCD_encoder.qmsg |  135 --
 ...ine_to_four_line_BCD_priority_encoder.qmsg |  125 --
 ...p_three_line_to_eight_decimal_decoder.qmsg |  128 --
 ...four_line_BCD_priority_encoder.(0).cnf.cdb |  Bin 1104 -> 0 bytes
 ...four_line_BCD_priority_encoder.(0).cnf.hdb |  Bin 793 -> 0 bytes
 ...four_line_BCD_priority_encoder.(1).cnf.cdb |  Bin 1820 -> 0 bytes
 ...four_line_BCD_priority_encoder.(1).cnf.hdb |  Bin 1161 -> 0 bytes
 ...to_four_line_BCD_priority_encoder.asm.qmsg |    6 -
 ..._to_four_line_BCD_priority_encoder.asm.rdb |  Bin 1381 -> 0 bytes
 ...our_line_BCD_priority_encoder.asm_labs.ddb |  Bin 10258 -> 0 bytes
 ..._to_four_line_BCD_priority_encoder.cbx.xml |    5 -
 ..._to_four_line_BCD_priority_encoder.cmp.bpm |  Bin 752 -> 0 bytes
 ..._to_four_line_BCD_priority_encoder.cmp.cdb |  Bin 5283 -> 0 bytes
 ..._to_four_line_BCD_priority_encoder.cmp.hdb |  Bin 11585 -> 0 bytes
 ..._to_four_line_BCD_priority_encoder.cmp.idb |  Bin 1200 -> 0 bytes
 ...o_four_line_BCD_priority_encoder.cmp.logdb |   54 -
 ..._to_four_line_BCD_priority_encoder.cmp.rdb |  Bin 22385 -> 0 bytes
 ...ur_line_BCD_priority_encoder.cmp_merge.kpt |  Bin 233 -> 0 bytes
 ...da_io_sim_cache.31um_ff_1200mv_0c_fast.hsd |  Bin 388256 -> 0 bytes
 ...a_io_sim_cache.31um_tt_1200mv_85c_slow.hsd |  Bin 382865 -> 0 bytes
 ...to_four_line_BCD_priority_encoder.eda.qmsg |    5 -
 ...to_four_line_BCD_priority_encoder.fit.qmsg |   45 -
 ...o_four_line_BCD_priority_encoder.hier_info |   31 -
 ...line_to_four_line_BCD_priority_encoder.hif |  Bin 414 -> 0 bytes
 ...e_to_four_line_BCD_priority_encoder.ipinfo |  Bin 162 -> 0 bytes
 ...to_four_line_BCD_priority_encoder.lpc.html |   18 -
 ..._to_four_line_BCD_priority_encoder.lpc.rdb |  Bin 399 -> 0 bytes
 ..._to_four_line_BCD_priority_encoder.lpc.txt |    5 -
 ...o_four_line_BCD_priority_encoder.map.ammdb |  Bin 128 -> 0 bytes
 ..._to_four_line_BCD_priority_encoder.map.bpm |  Bin 726 -> 0 bytes
 ..._to_four_line_BCD_priority_encoder.map.cdb |  Bin 2908 -> 0 bytes
 ..._to_four_line_BCD_priority_encoder.map.hdb |  Bin 10763 -> 0 bytes
 ..._to_four_line_BCD_priority_encoder.map.kpt |  Bin 231 -> 0 bytes
 ...o_four_line_BCD_priority_encoder.map.logdb |    1 -
 ...to_four_line_BCD_priority_encoder.map.qmsg |   12 -
 ..._to_four_line_BCD_priority_encoder.map.rdb |  Bin 1321 -> 0 bytes
 ..._four_line_BCD_priority_encoder.map_bb.cdb |  Bin 1898 -> 0 bytes
 ..._four_line_BCD_priority_encoder.map_bb.hdb |  Bin 9694 -> 0 bytes
 ...our_line_BCD_priority_encoder.map_bb.logdb |    1 -
 ...to_four_line_BCD_priority_encoder.pplq.rdb |  Bin 295 -> 0 bytes
 ...four_line_BCD_priority_encoder.pre_map.hdb |  Bin 11390 -> 0 bytes
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 ...rity_encoder.root_partition.map.reg_db.cdb |  Bin 250 -> 0 bytes
 ...four_line_BCD_priority_encoder.routing.rdb |  Bin 4434 -> 0 bytes
 ...to_four_line_BCD_priority_encoder.rtlv.hdb |  Bin 11331 -> 0 bytes
 ...four_line_BCD_priority_encoder.rtlv_sg.cdb |  Bin 2597 -> 0 bytes
 ...line_BCD_priority_encoder.rtlv_sg_swap.cdb |  Bin 564 -> 0 bytes
 ..._four_line_BCD_priority_encoder.sgdiff.cdb |  Bin 2745 -> 0 bytes
 ..._four_line_BCD_priority_encoder.sgdiff.hdb |  Bin 11161 -> 0 bytes
 ..._BCD_priority_encoder.sld_design_entry.sci |  Bin 276 -> 0 bytes
 ..._priority_encoder.sld_design_entry_dsc.sci |  Bin 276 -> 0 bytes
 ...line_BCD_priority_encoder.smart_action.txt |    1 -
 ...to_four_line_BCD_priority_encoder.sta.qmsg |   49 -
 ..._to_four_line_BCD_priority_encoder.sta.rdb |  Bin 8172 -> 0 bytes
 ...rity_encoder.sta_cmp.6_slow_1200mv_85c.tdb |  Bin 3672 -> 0 bytes
 ..._line_BCD_priority_encoder.tis_db_list.ddb |  Bin 301 -> 0 bytes
 ...priority_encoder.tiscmp.fast_1200mv_0c.ddb |  Bin 101996 -> 0 bytes
 ...priority_encoder.tiscmp.slow_1200mv_0c.ddb |  Bin 102377 -> 0 bytes
 ...riority_encoder.tiscmp.slow_1200mv_85c.ddb |  Bin 102335 -> 0 bytes
 ...to_four_line_BCD_priority_encoder.tmw_info |    5 -
 ...o_four_line_BCD_priority_encoder.vpr.ammdb |  Bin 292 -> 0 bytes
 ..._line_to_eight_decimal_decoder.(0).cnf.cdb |  Bin 1078 -> 0 bytes
 ..._line_to_eight_decimal_decoder.(0).cnf.hdb |  Bin 708 -> 0 bytes
 ..._line_to_eight_decimal_decoder.(1).cnf.cdb |  Bin 1400 -> 0 bytes
 ..._line_to_eight_decimal_decoder.(1).cnf.hdb |  Bin 981 -> 0 bytes
 ...ree_line_to_eight_decimal_decoder.asm.qmsg |    6 -
 ...hree_line_to_eight_decimal_decoder.asm.rdb |  Bin 1372 -> 0 bytes
 ...line_to_eight_decimal_decoder.asm_labs.ddb |  Bin 9914 -> 0 bytes
 ...hree_line_to_eight_decimal_decoder.cbx.xml |    5 -
 ...hree_line_to_eight_decimal_decoder.cmp.bpm |  Bin 717 -> 0 bytes
 ...hree_line_to_eight_decimal_decoder.cmp.cdb |  Bin 4737 -> 0 bytes
 ...hree_line_to_eight_decimal_decoder.cmp.hdb |  Bin 11357 -> 0 bytes
 ...hree_line_to_eight_decimal_decoder.cmp.idb |  Bin 1185 -> 0 bytes
 ...ee_line_to_eight_decimal_decoder.cmp.logdb |   53 -
 ...hree_line_to_eight_decimal_decoder.cmp.rdb |  Bin 22168 -> 0 bytes
 ...ine_to_eight_decimal_decoder.cmp_merge.kpt |  Bin 229 -> 0 bytes
 ...da_io_sim_cache.31um_ff_1200mv_0c_fast.hsd |  Bin 388822 -> 0 bytes
 ...a_io_sim_cache.31um_tt_1200mv_85c_slow.hsd |  Bin 382423 -> 0 bytes
 ...ree_line_to_eight_decimal_decoder.eda.qmsg |    5 -
 ...ree_line_to_eight_decimal_decoder.fit.qmsg |   45 -
 ...ee_line_to_eight_decimal_decoder.hier_info |   34 -
 .../three_line_to_eight_decimal_decoder.hif   |  Bin 411 -> 0 bytes
 ...three_line_to_eight_decimal_decoder.ipinfo |  Bin 162 -> 0 bytes
 ...ree_line_to_eight_decimal_decoder.lpc.html |   18 -
 ...hree_line_to_eight_decimal_decoder.lpc.rdb |  Bin 399 -> 0 bytes
 ...hree_line_to_eight_decimal_decoder.lpc.txt |    5 -
 ...ee_line_to_eight_decimal_decoder.map.ammdb |  Bin 128 -> 0 bytes
 ...hree_line_to_eight_decimal_decoder.map.bpm |  Bin 694 -> 0 bytes
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 ...hree_line_to_eight_decimal_decoder.map.hdb |  Bin 10611 -> 0 bytes
 ...hree_line_to_eight_decimal_decoder.map.kpt |  Bin 228 -> 0 bytes
 ...ee_line_to_eight_decimal_decoder.map.logdb |    1 -
 ...ree_line_to_eight_decimal_decoder.map.qmsg |   12 -
 ...hree_line_to_eight_decimal_decoder.map.rdb |  Bin 1316 -> 0 bytes
 ...e_line_to_eight_decimal_decoder.map_bb.cdb |  Bin 1883 -> 0 bytes
 ...e_line_to_eight_decimal_decoder.map_bb.hdb |  Bin 9595 -> 0 bytes
 ...line_to_eight_decimal_decoder.map_bb.logdb |    1 -
 ...ree_line_to_eight_decimal_decoder.pplq.rdb |  Bin 295 -> 0 bytes
 ..._line_to_eight_decimal_decoder.pre_map.hdb |  Bin 11042 -> 0 bytes
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 ..._to_eight_decimal_decoder.smart_action.txt |    1 -
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 ...ree_line_to_eight_decimal_decoder.tmw_info |    5 -
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 ...r_line_to_sixteen_line_decimal_decoder.bdf |  779 ----------
 ...r_line_to_sixteen_line_decimal_decoder.qpf |   30 -
 ...r_line_to_sixteen_line_decimal_decoder.qsf |   59 -
 ...r_line_to_sixteen_line_decimal_decoder.vwf |  646 --------
 CH6/CH6-1/incremental_db/README               |   11 -
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 .../Ten_line_to_four_line_BCD_encoder.db_info |    3 -
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 ...ecimal_decoder.root_partition.map.hbdb.sig |    1 -
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diff --git a/CH6/CH6-1/BCD_to_decimal_decoder.qpf b/CH6/CH6-1/BCD_to_decimal_decoder.qpf
deleted file mode 100644
index 883b35a1..00000000
--- a/CH6/CH6-1/BCD_to_decimal_decoder.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
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-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
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-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
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-# -------------------------------------------------------------------------- #
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-DATE = "21:53:56  October 17, 2019"
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-# Revisions
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diff --git a/CH6/CH6-1/BCD_to_decimal_decoder.qsf b/CH6/CH6-1/BCD_to_decimal_decoder.qsf
deleted file mode 100644
index 6e874912..00000000
--- a/CH6/CH6-1/BCD_to_decimal_decoder.qsf
+++ /dev/null
@@ -1,59 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
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-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
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-# -------------------------------------------------------------------------- #
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-# Quartus II 32-bit
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-# Date created = 21:53:56  October 17, 2019
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-# -------------------------------------------------------------------------- #
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-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VECTOR_WAVEFORM_FILE BCD_to_decimal_decoder.vwf
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diff --git a/CH6/CH6-1/BCD_to_decimal_decoder.vwf b/CH6/CH6-1/BCD_to_decimal_decoder.vwf
deleted file mode 100644
index 7baad12e..00000000
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-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
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-Agreement, or other applicable license agreement, including, 
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diff --git a/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.bdf b/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.bdf
deleted file mode 100644
index ee3417bb..00000000
--- a/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.bdf
+++ /dev/null
@@ -1,621 +0,0 @@
-/*
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-/*
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
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-(junction (pt 288 312))
-(junction (pt 320 152))
-(junction (pt 304 232))
-(junction (pt 288 248))
-(junction (pt 336 392))
diff --git a/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.qpf b/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.qpf
deleted file mode 100644
index 1bb62655..00000000
--- a/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 23:05:27  September 30, 2019
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "23:05:27  September 30, 2019"
-
-# Revisions
-
-PROJECT_REVISION = "Ten_line_to_four_line_BCD_encoder"
diff --git a/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.qsf b/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.qsf
deleted file mode 100644
index 8f9191e5..00000000
--- a/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.qsf
+++ /dev/null
@@ -1,72 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 23:05:27  September 30, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		Ten_line_to_four_line_BCD_encoder_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE EP3C16F484C6
-set_global_assignment -name TOP_LEVEL_ENTITY Ten_line_to_four_line_BCD_encoder
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:05:27  SEPTEMBER 30, 2019"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name BDF_FILE Ten_line_to_four_line_BCD_encoder.bdf
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_location_assignment PIN_C1 -to A
-set_location_assignment PIN_C2 -to B
-set_location_assignment PIN_B2 -to C
-set_location_assignment PIN_B1 -to D
-set_location_assignment PIN_D2 -to I0
-set_location_assignment PIN_E3 -to I2
-set_location_assignment PIN_H7 -to I3
-set_location_assignment PIN_J7 -to I4
-set_location_assignment PIN_G5 -to I5
-set_location_assignment PIN_G4 -to I6
-set_location_assignment PIN_H6 -to I7
-set_location_assignment PIN_H5 -to I8
-set_location_assignment PIN_J6 -to I9
-set_global_assignment -name CDF_FILE output_files/Chain1.cdf
-set_location_assignment PIN_E4 -to I1
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder_assignment_defaults.qdf b/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder_assignment_defaults.qdf
deleted file mode 100644
index d4b9e098..00000000
--- a/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder_assignment_defaults.qdf
+++ /dev/null
@@ -1,728 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, the Altera Quartus II License Agreement,
-# the Altera MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Altera and sold by Altera or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
-# Date created = 19:21:34  October 03, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Note:
-#
-# 1) Do not modify this file. This file was generated
-#    automatically by the Quartus II software and is used
-#    to preserve global assignments across Quartus II versions.
-#
-# -------------------------------------------------------------------------- #
-
-set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
-set_global_assignment -name IP_COMPONENT_INTERNAL Off
-set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
-set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
-set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
-set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
-set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
-set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
-set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
-set_global_assignment -name HC_OUTPUT_DIR hc_output
-set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
-set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
-set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
-set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
-set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
-set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
-set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
-set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
-set_global_assignment -name REVISION_TYPE Base
-set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
-set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
-set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
-set_global_assignment -name DO_COMBINED_ANALYSIS Off
-set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
-set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
-set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
-set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
-set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
-set_global_assignment -name OPTIMIZATION_MODE Balanced
-set_global_assignment -name ALLOW_REGISTER_MERGING On
-set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
-set_global_assignment -name TIMEQUEST2 on -family "Arria 10"
-set_global_assignment -name TIMEQUEST2 OFF -family "Stratix V"
-set_global_assignment -name MUX_RESTRUCTURE Auto
-set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
-set_global_assignment -name ENABLE_IP_DEBUG Off
-set_global_assignment -name SAVE_DISK_SPACE On
-set_global_assignment -name DISABLE_OCP_HW_EVAL Off
-set_global_assignment -name DEVICE_FILTER_PACKAGE Any
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
-set_global_assignment -name FAMILY -value "Cyclone V"
-set_global_assignment -name TRUE_WYSIWYG_FLOW Off
-set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
-set_global_assignment -name STATE_MACHINE_PROCESSING Auto
-set_global_assignment -name SAFE_STATE_MACHINE Off
-set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
-set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
-set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
-set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
-set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
-set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
-set_global_assignment -name PARALLEL_SYNTHESIS On
-set_global_assignment -name DSP_BLOCK_BALANCING Auto
-set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
-set_global_assignment -name NOT_GATE_PUSH_BACK On
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
-set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
-set_global_assignment -name IGNORE_CARRY_BUFFERS Off
-set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
-set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_LCELL_BUFFERS Off
-set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
-set_global_assignment -name IGNORE_SOFT_BUFFERS On
-set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
-set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
-set_global_assignment -name AUTO_GLOBAL_OE_MAX On
-set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
-set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
-set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name ALLOW_XOR_GATE_USAGE On
-set_global_assignment -name AUTO_LCELL_INSERTION On
-set_global_assignment -name CARRY_CHAIN_LENGTH 48
-set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
-set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name CASCADE_CHAIN_LENGTH 2
-set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
-set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
-set_global_assignment -name AUTO_CARRY_CHAINS On
-set_global_assignment -name AUTO_CASCADE_CHAINS On
-set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
-set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
-set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
-set_global_assignment -name AUTO_ROM_RECOGNITION On
-set_global_assignment -name AUTO_RAM_RECOGNITION On
-set_global_assignment -name AUTO_DSP_RECOGNITION On
-set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
-set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
-set_global_assignment -name STRICT_RAM_RECOGNITION Off
-set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
-set_global_assignment -name FORCE_SYNCH_CLEAR Off
-set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
-set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
-set_global_assignment -name AUTO_RESOURCE_SHARING Off
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name MAX7000_FANIN_PER_CELL 100
-set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
-set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
-set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
-set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
-set_global_assignment -name REPORT_PARAMETER_SETTINGS On
-set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
-set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
-set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
-set_global_assignment -name HDL_MESSAGE_LEVEL Level2
-set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
-set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
-set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
-set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
-set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
-set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
-set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
-set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
-set_global_assignment -name BLOCK_DESIGN_NAMING Auto
-set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
-set_global_assignment -name SYNTHESIS_EFFORT Auto
-set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
-set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
-set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
-set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
-set_global_assignment -name MAX_LABS "-1 (Unlimited)"
-set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
-set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
-set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
-set_global_assignment -name PRPOF_ID Off
-set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
-set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
-set_global_assignment -name AUTO_MERGE_PLLS On
-set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
-set_global_assignment -name TXPMA_SLEW_RATE Low
-set_global_assignment -name ADCE_ENABLED Auto
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
-set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
-set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
-set_global_assignment -name DEVICE AUTO
-set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
-set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
-set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
-set_global_assignment -name ENABLE_NCEO_OUTPUT Off
-set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
-set_global_assignment -name STRATIX_UPDATE_MODE Standard
-set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
-set_global_assignment -name CVP_MODE Off
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name USER_START_UP_CLOCK Off
-set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
-set_global_assignment -name ENABLE_VREFA_PIN Off
-set_global_assignment -name ENABLE_VREFB_PIN Off
-set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
-set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
-set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
-set_global_assignment -name INIT_DONE_OPEN_DRAIN On
-set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name ENABLE_CONFIGURATION_PINS On
-set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
-set_global_assignment -name ENABLE_NCE_PIN Off
-set_global_assignment -name ENABLE_BOOT_SEL_PIN On
-set_global_assignment -name CRC_ERROR_CHECKING Off
-set_global_assignment -name INTERNAL_SCRUBBING Off
-set_global_assignment -name PR_ERROR_OPEN_DRAIN On
-set_global_assignment -name PR_READY_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CVP_CONFDONE Off
-set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
-set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
-set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
-set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
-set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
-set_global_assignment -name OPTIMIZE_SSN Off
-set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
-set_global_assignment -name ECO_OPTIMIZE_TIMING Off
-set_global_assignment -name ECO_REGENERATE_REPORT Off
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
-set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
-set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
-set_global_assignment -name SEED 1
-set_global_assignment -name SLOW_SLEW_RATE Off
-set_global_assignment -name PCI_IO Off
-set_global_assignment -name TURBO_BIT On
-set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
-set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
-set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
-set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
-set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
-set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
-set_global_assignment -name NORMAL_LCELL_INSERT On
-set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
-set_global_assignment -name AUTO_DELAY_CHAINS Off -family "Arria 10"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
-set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
-set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
-set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
-set_global_assignment -name AUTO_TURBO_BIT ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
-set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
-set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
-set_global_assignment -name FITTER_EFFORT "Auto Fit"
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
-set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
-set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
-set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK On
-set_global_assignment -name AUTO_GLOBAL_OE On
-set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
-set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
-set_global_assignment -name ENABLE_HOLD_BACK_OFF On
-set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
-set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
-set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
-set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
-set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
-set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
-set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
-set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
-set_global_assignment -name PR_DONE_OPEN_DRAIN On
-set_global_assignment -name NCEO_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
-set_global_assignment -name ENABLE_PR_PINS Off
-set_global_assignment -name PR_PINS_OPEN_DRAIN Off
-set_global_assignment -name CLAMPING_DIODE Off
-set_global_assignment -name TRI_STATE_SPI_PINS Off
-set_global_assignment -name UNUSED_TSD_PINS_GND Off
-set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
-set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
-set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
-set_global_assignment -name COMPRESSION_MODE Off
-set_global_assignment -name CLOCK_SOURCE Internal
-set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
-set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
-set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
-set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
-set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
-set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
-set_global_assignment -name SECURITY_BIT Off
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
-set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
-set_global_assignment -name GENERATE_TTF_FILE Off
-set_global_assignment -name GENERATE_RBF_FILE Off
-set_global_assignment -name GENERATE_HEX_FILE Off
-set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
-set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
-set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
-set_global_assignment -name AUTO_RESTART_CONFIGURATION On
-set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
-set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
-set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
-set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
-set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
-set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
-set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
-set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
-set_global_assignment -name POR_SCHEME "Instant ON"
-set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
-set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
-set_global_assignment -name POF_VERIFY_PROTECT Off
-set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
-set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
-set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
-set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
-set_global_assignment -name START_TIME 0ns
-set_global_assignment -name SIMULATION_MODE TIMING
-set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
-set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
-set_global_assignment -name SETUP_HOLD_DETECTION Off
-set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
-set_global_assignment -name CHECK_OUTPUTS Off
-set_global_assignment -name SIMULATION_COVERAGE On
-set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name GLITCH_DETECTION Off
-set_global_assignment -name GLITCH_INTERVAL 1ns
-set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
-set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
-set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
-set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
-set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
-set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
-set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
-set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
-set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
-set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
-set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
-set_global_assignment -name DRC_TOP_FANOUT 50
-set_global_assignment -name DRC_FANOUT_EXCEEDING 30
-set_global_assignment -name DRC_GATED_CLOCK_FEED 30
-set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
-set_global_assignment -name ENABLE_DRC_SETTINGS Off
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
-set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
-set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
-set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
-set_global_assignment -name MERGE_HEX_FILE Off
-set_global_assignment -name GENERATE_SVF_FILE Off
-set_global_assignment -name GENERATE_ISC_FILE Off
-set_global_assignment -name GENERATE_JAM_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
-set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
-set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
-set_global_assignment -name HPS_EARLY_IO_RELEASE Off
-set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
-set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
-set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_USE_PVA On
-set_global_assignment -name POWER_USE_INPUT_FILE "No File"
-set_global_assignment -name POWER_USE_INPUT_FILES Off
-set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
-set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
-set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
-set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
-set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
-set_global_assignment -name POWER_TJ_VALUE 25
-set_global_assignment -name POWER_USE_TA_VALUE 25
-set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
-set_global_assignment -name POWER_BOARD_TEMPERATURE 25
-set_global_assignment -name POWER_HPS_ENABLE Off
-set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
-set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
-set_global_assignment -name IGNORE_PARTITIONS Off
-set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
-set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
-set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
-set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
-set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
-set_global_assignment -name RTLV_GROUP_RELATED_NODES On
-set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
-set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
-set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
-set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
-set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
-set_global_assignment -name EQC_BBOX_MERGE On
-set_global_assignment -name EQC_LVDS_MERGE On
-set_global_assignment -name EQC_RAM_UNMERGING On
-set_global_assignment -name EQC_DFF_SS_EMULATION On
-set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
-set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
-set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
-set_global_assignment -name EQC_STRUCTURE_MATCHING On
-set_global_assignment -name EQC_AUTO_BREAK_CONE On
-set_global_assignment -name EQC_POWER_UP_COMPARE Off
-set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
-set_global_assignment -name EQC_AUTO_INVERSION On
-set_global_assignment -name EQC_AUTO_TERMINATE On
-set_global_assignment -name EQC_SUB_CONE_REPORT Off
-set_global_assignment -name EQC_RENAMING_RULES On
-set_global_assignment -name EQC_PARAMETER_CHECK On
-set_global_assignment -name EQC_AUTO_PORTSWAP On
-set_global_assignment -name EQC_DETECT_DONT_CARES On
-set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
-set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
-set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
-set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
-set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
-set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
-set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
-set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
-set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
-set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
-set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
-set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
-set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
-set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
-set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
-set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
-set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
-set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
-set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
-set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
-set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
-set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
-set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
-set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
-set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
-set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
-set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
-set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
-set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
-set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
-set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
-set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
-set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
-set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
-set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
-set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
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-set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
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-set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
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-set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
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-set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
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diff --git a/CH6/CH6-1/db/.cmp.kpt b/CH6/CH6-1/db/.cmp.kpt
deleted file mode 100644
index b952d1f5b9f245235efb07b9051d45a12dc14c28..0000000000000000000000000000000000000000
GIT binary patch
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deleted file mode 100644
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GIT binary patch
literal 0
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.(0).cnf.hdb b/CH6/CH6-1/db/BCD_to_decimal_decoder.(0).cnf.hdb
deleted file mode 100644
index d29700b9e8329c94aecd81b65623ceb430e05cc4..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.asm.qmsg b/CH6/CH6-1/db/BCD_to_decimal_decoder.asm.qmsg
deleted file mode 100644
index febe3fa7..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.asm.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571325895356 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571325895359 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 23:24:55 2019 " "Processing started: Thu Oct 17 23:24:55 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571325895359 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571325895359 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571325895360 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1571325896915 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571325896955 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571325897445 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 23:24:57 2019 " "Processing ended: Thu Oct 17 23:24:57 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571325897445 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571325897445 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571325897445 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571325897445 ""}
diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.asm.rdb b/CH6/CH6-1/db/BCD_to_decimal_decoder.asm.rdb
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GIT binary patch
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.asm_labs.ddb b/CH6/CH6-1/db/BCD_to_decimal_decoder.asm_labs.ddb
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GIT binary patch
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index c3b8db08..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.idb b/CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.idb
deleted file mode 100644
index ca3ac77666f591bc97db7aa903877ffc37668ecb..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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z7Zs_3`GR7<qNdSd9xyx2F0<P_XdW^Tn>}W)iC5@yeMoJv&!j%)N6lU4F>|+>n)tx}
z<K|xTgt^Z=X||c%C+E>Kc-q8g=4VWNWPaAfZ{~Og@f=<-FPWFkE9O<R-yARp%^`Ex
z95Lww-q8m<qYrpRAMl7i;0=9974!iw=mQ?m2kxCdaL;Jb1GMlSEj&jHuhGKeRDri>
z;VD{pi54EBg?IQyjgT54H9~5H)Cj2&QX`~BNR5yh@t++3(S_(jbRoJBU5GA37orQ%
zh3L{pa{7oaL>Hn9(S_(jbRoJBU5GA3x7j(*1G*4hh%Q7Iq6^W5=t6WMx)9wK=R8k5
zOFTzBLj#I_#h_wHF`^h&EGUvhKb$-^p3cpe%9Eu>lXL0pgK|1MUAi|lGgY2X@Rz~0
z*iJC0p*W}JI6tqPdx>+U#la`+hT?->1M(;tZhBXxmSj2aNeFDw01qc>*PgxzAH9^V
zX9vcl@n$ub%UAV#x1Mb!|H}b9&)T;9B!sl0_G!?r*Xq!?J5+D@X75nEk;v?B^%LhS
z*#jI`HwGJah%ep08Y|DQk5<3-gz3+{;mcBYcze4oRPVQk$9FoyQnf2QTkH$3W;)-m
z_j-A4-&^&q|CXIoeEZ3h-yNu5;Zr@^>`CR;`tIOmd<56nKC!yS1|LRmBkXNd?ee=u
zt6OV-=K$|Y{>Q7Ywf=}h7}XoLn19Km<gc%wkNkWfo{;?q#7S|}pB?xC00960cmZsY
z%SyvQ6o#i4wbnw>g11#c7cTk&mM}1B#u}V-N*cR#Oe<=zHrS@VgAXD?-Kl%mE=6$b
zE4bB_=S&l^)WBhq^M5&)e+nc;jtL>z;`eI`&NRd(gl(D1VjeSDi>sz<x0%OvB25Y)
zzn8{uaFAt)B1D3#mM2}FAv=(JczpUq4a=^^Oq<sL(1j*wmTZIc6<$9hhOrT&rj$Y<
z|A(F<IZ%@a={y8B-?O=}=1CSl@5WaKB8ZkCP{y%XohyfX`_fv_+|m7QJ88NWbFi*m
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zpBdeAe^8l{F{7e^A4Ef~(u%_!=q?l!Le>}zJ;|48nJ&%@g3jS`{|{2<4dsG;G(WQ~
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.logdb b/CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.logdb
deleted file mode 100644
index 02c37c81..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.logdb
+++ /dev/null
@@ -1,56 +0,0 @@
-v1
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;0;0;0;0;14;0;0;14;14;0;10;0;0;4;0;10;4;0;0;0;10;0;0;0;0;0;14;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,14;14;14;14;14;0;14;14;0;0;14;4;14;14;10;14;4;10;14;14;14;4;14;14;14;14;14;0;14;14,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Y0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y4,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y5,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y6,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y7,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y8,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y9,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,A,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,D,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,B,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,C,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.rdb b/CH6/CH6-1/db/BCD_to_decimal_decoder.cmp.rdb
deleted file mode 100644
index 4d10daea91d7841a061c63aaee07342e6ca58176..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.eda.qmsg b/CH6/CH6-1/db/BCD_to_decimal_decoder.eda.qmsg
deleted file mode 100644
index 6338b006..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.eda.qmsg
+++ /dev/null
@@ -1,5 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571325908268 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571325908270 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 23:25:07 2019 " "Processing started: Thu Oct 17 23:25:07 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571325908270 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571325908270 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571325908271 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_to_decimal_decoder.vo /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim// simulation " "Generated file BCD_to_decimal_decoder.vo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1571325908860 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "348 " "Peak virtual memory: 348 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571325908927 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 23:25:08 2019 " "Processing ended: Thu Oct 17 23:25:08 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571325908927 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571325908927 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571325908927 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571325908927 ""}
diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.fit.qmsg b/CH6/CH6-1/db/BCD_to_decimal_decoder.fit.qmsg
deleted file mode 100644
index d9d29642..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571325880315 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "BCD_to_decimal_decoder EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"BCD_to_decimal_decoder\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571325880323 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571325880444 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571325880446 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571325880446 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1571325880608 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1571325880630 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571325881054 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571325881054 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571325881054 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1571325881054 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 45 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571325881066 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 47 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571325881066 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 49 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571325881066 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 51 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571325881066 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 53 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571325881066 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1571325881066 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1571325881072 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "14 14 " "No exact pin location assignment(s) for 14 pins of 14 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Pin Y0 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y0 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 296 704 880 312 "Y0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 3 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Pin Y1 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y1 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 384 704 880 400 "Y1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 8 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Pin Y2 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y2 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 472 704 880 488 "Y2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 9 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Pin Y3 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y3 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 560 704 880 576 "Y3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 10 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Pin Y4 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y4 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 648 704 880 664 "Y4" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 11 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Pin Y5 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y5 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 736 704 880 752 "Y5" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 12 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Pin Y6 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y6 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 824 704 880 840 "Y6" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 13 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Pin Y7 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y7 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 912 704 880 928 "Y7" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 14 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y8 " "Pin Y8 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y8 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 1000 704 880 1016 "Y8" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y8 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 15 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y9 " "Pin Y9 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y9 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 1088 704 880 1104 "Y9" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y9 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 16 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A " "Pin A not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 56 120 288 72 "A" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 4 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D " "Pin D not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { D } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 248 120 288 264 "D" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { D } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 7 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B " "Pin B not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 120 120 288 136 "B" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 5 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C " "Pin C not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { C } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 184 120 288 200 "C" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { C } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 6 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325883042 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1571325883042 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_to_decimal_decoder.sdc " "Synopsys Design Constraints File file not found: 'BCD_to_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1571325883317 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1571325883319 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1571325883320 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1571325883322 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1571325883324 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1571325883324 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1571325883325 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1571325883333 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571325883334 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571325883335 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571325883337 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571325883338 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1571325883339 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1571325883339 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1571325883339 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1571325883340 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1571325883340 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1571325883340 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "14 unused 2.5V 4 10 0 " "Number of I/O pins in group: 14 (unused VREF, 2.5V VCCIO, 4 input, 10 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1571325883346 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1571325883346 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1571325883346 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 29 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  29 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325883351 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325883351 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325883351 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325883351 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325883351 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325883351 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325883351 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325883351 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1571325883351 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1571325883351 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571325883398 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1571325885062 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571325885162 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1571325885176 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1571325885533 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571325885533 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1571325885814 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X9_Y9 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9" {  } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9"} 0 0 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1571325886777 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1571325886777 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571325886865 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1571325886866 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1571325886866 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1571325886866 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.18 " "Total time spent on timing analysis during the Fitter is 0.18 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1571325886879 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571325886949 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571325887510 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571325887579 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571325888220 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571325888869 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1571325890619 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571325890899 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 23:24:50 2019 " "Processing ended: Thu Oct 17 23:24:50 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571325890899 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571325890899 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571325890899 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571325890899 ""}
diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.hier_info b/CH6/CH6-1/db/BCD_to_decimal_decoder.hier_info
deleted file mode 100644
index 44d1d8c5..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.hier_info
+++ /dev/null
@@ -1,32 +0,0 @@
-|BCD_to_decimal_decoder
-Y0 <= inst.DB_MAX_OUTPUT_PORT_TYPE
-A => inst10.IN0
-A => inst1.IN0
-A => inst3.IN0
-A => inst5.IN0
-A => inst7.IN0
-A => inst9.IN0
-B => inst11.IN0
-B => inst2.IN1
-B => inst3.IN1
-B => inst6.IN1
-B => inst7.IN1
-C => inst12.IN0
-C => inst4.IN2
-C => inst5.IN2
-C => inst6.IN2
-C => inst7.IN2
-D => inst13.IN0
-D => inst8.IN3
-D => inst9.IN3
-Y1 <= inst1.DB_MAX_OUTPUT_PORT_TYPE
-Y2 <= inst2.DB_MAX_OUTPUT_PORT_TYPE
-Y3 <= inst3.DB_MAX_OUTPUT_PORT_TYPE
-Y4 <= inst4.DB_MAX_OUTPUT_PORT_TYPE
-Y5 <= inst5.DB_MAX_OUTPUT_PORT_TYPE
-Y6 <= inst6.DB_MAX_OUTPUT_PORT_TYPE
-Y7 <= inst7.DB_MAX_OUTPUT_PORT_TYPE
-Y8 <= inst8.DB_MAX_OUTPUT_PORT_TYPE
-Y9 <= inst9.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.hif b/CH6/CH6-1/db/BCD_to_decimal_decoder.hif
deleted file mode 100644
index c9cca5161da9e415d91477e92f7410b627ef2c44..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.ipinfo b/CH6/CH6-1/db/BCD_to_decimal_decoder.ipinfo
deleted file mode 100644
index b19e3be175f30fec0abce2c24772f0962e31a465..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 162
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z8Y={QDTJpcDY&L&mH?G<fb}ylltF0?C=H?(LD?0INr??$_W%Dtc1l8uKte)-N7v8l
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.lpc.html b/CH6/CH6-1/db/BCD_to_decimal_decoder.lpc.html
deleted file mode 100644
index fbc5ab50..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.lpc.html
+++ /dev/null
@@ -1,18 +0,0 @@
-<TABLE>
-<TR  bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-</TABLE>
diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.lpc.rdb b/CH6/CH6-1/db/BCD_to_decimal_decoder.lpc.rdb
deleted file mode 100644
index 45b47e5f2e16cf9ff5fed3788e2a3eca5ffb8b5c..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 399
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z8Y={QDTJpcDY&L&mH?G*ff&Fb1EuGJ&4UpAP_YWeIsLv|hYSQ-XZLnJcz-GMT#};*
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.lpc.txt b/CH6/CH6-1/db/BCD_to_decimal_decoder.lpc.txt
deleted file mode 100644
index a4638048..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.lpc.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.map.ammdb b/CH6/CH6-1/db/BCD_to_decimal_decoder.map.ammdb
deleted file mode 100644
index e93ac1af1fe66612e97c409c5531b892acdf5bb1..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 128
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.map.bpm b/CH6/CH6-1/db/BCD_to_decimal_decoder.map.bpm
deleted file mode 100644
index 5dbb5ff789f336755349efc0a98e687aa3ff7cfa..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.map.kpt b/CH6/CH6-1/db/BCD_to_decimal_decoder.map.kpt
deleted file mode 100644
index d6f3f41530cebcced7b1c75eeb4c93da2a77b7f2..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.map.logdb b/CH6/CH6-1/db/BCD_to_decimal_decoder.map.logdb
deleted file mode 100644
index 626799f0..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.map.qmsg b/CH6/CH6-1/db/BCD_to_decimal_decoder.map.qmsg
deleted file mode 100644
index 95db19ca..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.map.qmsg
+++ /dev/null
@@ -1,10 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571325873980 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571325873982 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 23:24:33 2019 " "Processing started: Thu Oct 17 23:24:33 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571325873982 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571325873982 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571325873983 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571325874354 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_to_decimal_decoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_to_decimal_decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_to_decimal_decoder " "Found entity 1: BCD_to_decimal_decoder" {  } { { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571325874508 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571325874508 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "BCD_to_decimal_decoder " "Elaborating entity \"BCD_to_decimal_decoder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571325874606 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1571325875755 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1571325876206 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571325876206 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "24 " "Implemented 24 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571325876303 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571325876303 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10 " "Implemented 10 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1571325876303 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571325876303 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571325876321 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 23:24:36 2019 " "Processing ended: Thu Oct 17 23:24:36 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571325876321 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571325876321 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571325876321 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571325876321 ""}
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.map_bb.logdb b/CH6/CH6-1/db/BCD_to_decimal_decoder.map_bb.logdb
deleted file mode 100644
index 626799f0..00000000
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+++ /dev/null
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.pre_map.hdb b/CH6/CH6-1/db/BCD_to_decimal_decoder.pre_map.hdb
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.smart_action.txt b/CH6/CH6-1/db/BCD_to_decimal_decoder.smart_action.txt
deleted file mode 100644
index c8e8a135..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.sta.qmsg b/CH6/CH6-1/db/BCD_to_decimal_decoder.sta.qmsg
deleted file mode 100644
index b8f5a7ff..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571325901221 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571325901223 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 23:25:00 2019 " "Processing started: Thu Oct 17 23:25:00 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571325901223 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571325901223 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta BCD_to_decimal_decoder -c BCD_to_decimal_decoder " "Command: quartus_sta BCD_to_decimal_decoder -c BCD_to_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571325901224 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571325901288 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571325901499 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571325901503 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571325901616 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571325901616 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_to_decimal_decoder.sdc " "Synopsys Design Constraints File file not found: 'BCD_to_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571325901919 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571325901920 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571325901922 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571325901923 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1571325901924 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571325901924 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571325901926 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1571325901937 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1571325901938 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325901940 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325901945 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325901946 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325901947 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325901948 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325901949 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571325901960 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571325902011 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571325902911 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571325902943 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571325902943 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571325902944 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571325902944 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325902944 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325902947 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325902948 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325902950 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325902951 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325902952 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571325902959 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571325903104 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571325903105 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571325903105 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571325903105 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325903107 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325903109 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325903110 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325903112 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325903113 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571325903314 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571325903314 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "373 " "Peak virtual memory: 373 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571325903359 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 23:25:03 2019 " "Processing ended: Thu Oct 17 23:25:03 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571325903359 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571325903359 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571325903359 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571325903359 ""}
diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.sta.rdb b/CH6/CH6-1/db/BCD_to_decimal_decoder.sta.rdb
deleted file mode 100644
index 8101d1a3dfe453239b5bd7ecd36f4dd5b21f7286..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.sta_cmp.6_slow_1200mv_85c.tdb b/CH6/CH6-1/db/BCD_to_decimal_decoder.sta_cmp.6_slow_1200mv_85c.tdb
deleted file mode 100644
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.tiscmp.slow_1200mv_0c.ddb b/CH6/CH6-1/db/BCD_to_decimal_decoder.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.tiscmp.slow_1200mv_85c.ddb b/CH6/CH6-1/db/BCD_to_decimal_decoder.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
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diff --git a/CH6/CH6-1/db/BCD_to_decimal_decoder.tmw_info b/CH6/CH6-1/db/BCD_to_decimal_decoder.tmw_info
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index 3d302b91..00000000
--- a/CH6/CH6-1/db/BCD_to_decimal_decoder.tmw_info
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diff --git a/CH6/CH6-1/db/Ten_line_to_four_line_BCD_encoder.db_info b/CH6/CH6-1/db/Ten_line_to_four_line_BCD_encoder.db_info
deleted file mode 100644
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.asm.qmsg b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.asm.qmsg
deleted file mode 100644
index dd2ad3af..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.asm.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571926291773 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571926291775 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 22:11:31 2019 " "Processing started: Thu Oct 24 22:11:31 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571926291775 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571926291775 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571926291775 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1571926293386 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571926293426 ""}
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deleted file mode 100644
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GIT binary patch
literal 0
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.asm_labs.ddb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.asm_labs.ddb
deleted file mode 100644
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GIT binary patch
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cbx.xml b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cbx.xml
deleted file mode 100644
index 2cda874c..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
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GIT binary patch
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cmp.hdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cmp.hdb
deleted file mode 100644
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zz-_##`hi7v?oe2)?VvT4=9?WP7x?w7&X{~yx1&aRmrY_Onyc@mQ$K{SIJGt6)6~Ry
z?2B9znf_+&xc-G?w4MDCd#$IJZ7i-tIY-)IB9Z0d7pNNS<NdHI$1M*gsjbs;<;)Vt
zc)S`2s{kcI5v)zfi8i#1)q%scN(`2gVvn@ssJFq>upR!@1CHhV{G6kda%eV05tZBx
zz}6VOW}m7k%|Gw87LM60Y?+rrgneI4yFO+F+95zcDH5?n5!7@<*tXJ#oPD4)SA40v
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zkQ;l*YfLcQ!V*$<_j+LGtX_>RY;<6FKGY1!A5-3{Ejyq(5CyNtk^s|$d4mpdC(4c$
zoI5C9XJ{dV;hs3i_cI`m9;Wv0dAHJ06iay{8=H$=&HnjKQjiRBYI*PJW(4XRhdN02
zLE@6vjFQ^a?YYxJIctxZfuxwrK){vs2GEH2Lc<-w1;;=Ih#Ny6gHY$|<35}Hl@_n+
ztw6B+$=KR}b3;!z`dT<m1B|3ZR{I2gWXrMwm1YCJ$#4FWhb%^g0K|EnH8+}2crJ}X
zJY*urw;s_A%qD&n8uL>8{-d%=3YpoIZt<Ije_2}5Fb#xsk)a9RSg(I7Brp`(X(Vbe
zMa7&iTfBSkC9()YR4A1|w&r)i7J`#nkK_66_xQeylm(s48t0w}2KV&mrjray;n#Te
z2R)|9M8;U{=tg$GEQ|AM<285ES$ddj84VMx(dH4N5pOz?Q~+n1d12ps&HIhc()BQR
zt>A4A%Yd3Xy7No24V?MDRcW$UY&`~NOJTOniLlpo=Lqdlot3sGrse1UZ6?bT!*7kv
jc4Y9Ak1zXAxr~M{CZ}O(;+=8nwVsKeb|0MoV=Vs<gNEo`

diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cmp.idb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cmp.idb
deleted file mode 100644
index da3a8afb86510852a844b16b5a83289d11cd7908..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 1372
zcmYjRdo<Gv9N*G(<lSOYn8|W;>|sOmHl#et<4DxjO~^bF<JxIyjYM0wm$F1llsxj-
zQ3)y4{De}9&CTYO$MOglG2wT2>zwL*&iOpP-|zYU_x)~!Kp^F+Pz6IEQ3?<gx-UF|
zPK!H+#1k-h3=T<7qQ!(E@z$0|JPvC~z*^$)1Z03GGAKM0=^jQ)RE&;n_`U!#t@J~~
z*Zk1``5^3vXFw--4&DKNdT00EUQ-V1SxO^!aX~a%Lrou60_s}n>9AVKI?8ZUon2eJ
z&!^RwZLZsam;IU7>2gFO$up3K3EjAT0lfj(kHSbR{mI>q{8{>x19ocRW{>q)o>$0X
zcGaH3RC#d|N_B*$t-5q+WOQ?9263deCOE}aUb}iiv}|=>E}y3Q+?G$%L&&rEc>>TF
zn%1Ptjn!qtKGC=uTvGH+l$b!ZsL&R3*xjZTa52}O_sxcrD|~~}-`}_W%LX}kz0U$@
zGK?2=n-8jrr?d|=ISPDUbG(ENDALesN~os<Thyd9=s%PH*xP<92BFC{7n+3DUxx>A
zR#0;CTffT(EgjKUjsnf@QKx5AX6`UN?JYDoM}^gcq?sqz5gBe{sS;nr(3v_Uq7z2S
z$4v9<8fP0((JqvJd=k5+6UO&PFm_Y=jg#2Pir|M}xKsMInE~(#AB!p*tH$0TenSh1
znKgbNMv90_XzLxi+R$Rk%yRvTPM+{-@6J6aupx!UCAd<jA%jq%Qsz1>O{8I?vrq|O
zKxTd`IooHJ>~+XjD)<Ryl&xOj&-A@s=$<mBW$+6)t&Zn<zvcfsZ^i;Z+38<kXKDby
z(svi>e`^*9{*)IF><G%kx9c2@dWDL^$7-MJHgX$PPCeK1qI=ijlVK<`s=g|Rr;6~X
zJb%GwXTc-y1L4ny*Zv)%cCm!wv{Tb+vRR~Fqr7=8#J)znHU-?3{HZO_boSvu8l`c|
z6g>MCi9TnLOf}&5#4}qP3J%fK6287}zAJAI()|*2Vt$X5{j3cd^?_GQH=2Z-*j76m
z2d=y;J>eWkAra?Gsr?_Yn;3M571x!;ES8Eq-L}kjT3Xs0JpZWACiscyn!yu(Vlov?
z*=sutVDCuExBamYQQDO>dIU3THe#6AENxhbU#N2!h_L%8sc(Pa74!D-1b4CemR}JV
z|5t@z8EOr-3>ygrk4gu#CVSHV-O76Zbb31hWR6B0iq(*mcXSN+PksZv-WHDlJ@>jI
z#_22(wAXYs7r39a2n{&)b)0Bfh!vm0EH{Nzmdfu|B9_&MD~C^MJ(V@<Ix21x1R2nn
z%Wa-7oj0Dnhj=I=ccj(?x*#x1YqD`T8laz-=&4_y=xrWVW!+u$G))slmX<KZ8297j
z=8wCsje5fcosEaD%(6&4*7~jP7gUV@8C-~7-%b>w&&1}mh8hxrxn)JsH95^mD4+Gn
zXFMS8_@(enlv`?9_BION*zOXOadOE`y{!W9&J{!6rK2OWW76hys7@wl1=@v0SINd;
z2H%9_o3-w<{aWk3>e{N2-MWrbK#(#jGaKm(2=?DJ&tQIgAM#Gpu@Y-XtJ9@dRZzSl
zO=KQK50OioM9<`bvfL~p{pz|5ADE#^h5Z*Ij1gvLE<1D{(}lAw*=M(klf4*6%5H6v
z(pkPaSMY@eY$G?<^7ovV1~SY>I9a5p=Fq~U<zU*?Qria-Ku!Nq_2JYMqEofSu`^D4
w;(AnG8d7esSyM+^Z+xK2JRanK=9Nn|i;Ld`pY!TbzgVx1o*Q0KygU&64@sGSM*si-

diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cmp.logdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cmp.logdb
deleted file mode 100644
index 90ff211d..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cmp.logdb
+++ /dev/null
@@ -1,62 +0,0 @@
-v1
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;0;0;0;0;20;0;0;20;20;0;16;0;0;4;0;16;4;0;0;0;16;0;0;0;0;0;20;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,20;20;20;20;20;0;20;20;0;0;20;4;20;20;16;20;4;16;20;20;20;4;20;20;20;20;20;0;20;20,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Y0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y4,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y5,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y6,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y7,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y8,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y9,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y10,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y11,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y12,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y13,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y14,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y15,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,D,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,C,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,B,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,A,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cmp.rdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cmp.rdb
deleted file mode 100644
index 20c392f7f7082fde681643a29a6c5ca03591be5a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 23324
zcmeEtQ<o+|vu@kA-P6;yHEr8(+qP}nwr$(C&1u{2J^S0|YM(!FF3zg8DkEZLMrCDX
z=97U!0|El7h6Vn22LiJAcQOAfRgE1S&24Rn7@6r9=@^Ivoz1O`h#1+Jh!`2@nV9LB
z7#Nv}lq8ANj17oHjLe<>RegH|`Huz{jsFxtTmQrUhr!eQADJ8QWw(Ya-gxpaan;Js
zj<sfS$>xfV6r07FBq$JMAOR+^iW)s2qWGa-G({X-DjfcPptm!Bz|dgR=jP|rOW(jB
zFps@`rn_dkrZ&5z`JV<K&3a}pGd7(OW0Rr!lCgcDLekr5S8KF8Gikr0JzuWBIKRK)
zzhAd{eQ!2j%UkGb4@9eRTQf}fJ1m+zcmJHzulhF6NWZuLq=tDz`uYa;_RfA{5A{;|
z@(<DfVEO*`^$pN%5(jE2cmNDuHg(wZ3O3!e|LDfIZ*+9njGka>Kh(XKQ}X)i0DjXa
zr^pn~M{lqySvLb$1i$xps@7V2WREq?IOzNo8Oj#QdhM`mt5(jt8{t$xwAsvfOmlr~
zF(O(_D=nVu2wN|jXFKyRZN%#*7@0C$yGR>*+Rkb%Z*2c!>fj<EOXg`Hx0tqEJa?}3
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cmp_merge.kpt b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cmp_merge.kpt
deleted file mode 100644
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.eda.qmsg b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.eda.qmsg
deleted file mode 100644
index a872cdb7..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.eda.qmsg
+++ /dev/null
@@ -1,5 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571927092997 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 1991-2013 Altera Corporation. All rights reserved. " "Copyright (C) 1991-2013 Altera Corporation. All rights reserved." {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Altera Corporation's design tools, logic functions  " "Your use of Altera Corporation's design tools, logic functions " {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic  " "and other software and tools, and its AMPP partner logic " {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing  " "functions, and any output files from any of the foregoing " {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any  " "(including device programming or simulation files), and any " {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject  " "associated documentation or information are expressly subject " {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Altera Program License  " "to the terms and conditions of the Altera Program License " {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, Altera MegaCore Function License  " "Subscription Agreement, Altera MegaCore Function License " {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Agreement, or other applicable license agreement, including,  " "Agreement, or other applicable license agreement, including, " {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "without limitation, that your use is for the sole purpose of  " "without limitation, that your use is for the sole purpose of " {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "programming logic devices manufactured by Altera and sold by  " "programming logic devices manufactured by Altera and sold by " {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Altera or its authorized distributors.  Please refer to the  " "Altera or its authorized distributors.  Please refer to the " {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "applicable agreement for further details. " "applicable agreement for further details." {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 22:24:52 2019 " "Processing started: Thu Oct 24 22:24:52 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571927092999 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/ four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder " "Command: quartus_eda --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/ four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571927093001 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "four_line_to_sixteen_line_decimal_decoder.vo /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim// simulation " "Generated file four_line_to_sixteen_line_decimal_decoder.vo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1571927093526 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "348 " "Peak virtual memory: 348 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571927093579 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 22:24:53 2019 " "Processing ended: Thu Oct 24 22:24:53 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571927093579 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571927093579 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571927093579 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571927093579 ""}
diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.fit.qmsg b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.fit.qmsg
deleted file mode 100644
index 8951ebfe..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571926277237 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "four_line_to_sixteen_line_decimal_decoder EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"four_line_to_sixteen_line_decimal_decoder\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571926277245 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571926277363 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571926277364 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571926277365 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1571926277514 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1571926277538 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571926277935 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571926277935 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571926277935 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1571926277935 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 82 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571926277946 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 84 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571926277946 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 86 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571926277946 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 88 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571926277946 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 90 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571926277946 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1571926277946 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1571926277951 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "20 20 " "No exact pin location assignment(s) for 20 pins of 20 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Pin Y0 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y0 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 128 600 776 144 "Y0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 5 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Pin Y1 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y1 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 144 600 776 160 "Y1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 10 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Pin Y2 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y2 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 160 600 776 176 "Y2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 11 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Pin Y3 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y3 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 176 600 776 192 "Y3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 12 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Pin Y4 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y4 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 192 600 776 208 "Y4" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 13 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Pin Y5 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y5 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 208 600 776 224 "Y5" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 14 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Pin Y6 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y6 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 224 600 776 240 "Y6" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 15 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Pin Y7 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y7 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 240 600 776 256 "Y7" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 16 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y8 " "Pin Y8 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y8 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 288 600 776 304 "Y8" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y8 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 17 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y9 " "Pin Y9 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y9 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 304 600 776 320 "Y9" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y9 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 18 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y10 " "Pin Y10 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y10 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 320 600 776 336 "Y10" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y10 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 19 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y11 " "Pin Y11 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y11 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 336 600 776 352 "Y11" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y11 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 20 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y12 " "Pin Y12 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y12 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 352 600 776 368 "Y12" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 21 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y13 " "Pin Y13 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y13 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 368 600 776 384 "Y13" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y13 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 22 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y14 " "Pin Y14 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y14 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 384 600 776 400 "Y14" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y14 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 23 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y15 " "Pin Y15 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y15 } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 400 600 776 416 "Y15" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y15 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 24 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D " "Pin D not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { D } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 208 184 352 224 "D" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { D } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 9 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C " "Pin C not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { C } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 176 184 352 192 "C" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { C } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 8 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B " "Pin B not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 160 184 352 176 "B" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 7 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A " "Pin A not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A } } } { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 144 184 352 160 "A" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 6 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571926279844 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1571926279844 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "four_line_to_sixteen_line_decimal_decoder.sdc " "Synopsys Design Constraints File file not found: 'four_line_to_sixteen_line_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1571926280129 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1571926280130 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1571926280132 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1571926280133 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1571926280136 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1571926280136 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1571926280137 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1571926280145 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571926280147 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571926280147 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571926280150 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571926280151 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1571926280152 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1571926280152 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1571926280152 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1571926280152 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1571926280153 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1571926280153 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "20 unused 2.5V 4 16 0 " "Number of I/O pins in group: 20 (unused VREF, 2.5V VCCIO, 4 input, 16 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1571926280160 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1571926280160 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1571926280160 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 29 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  29 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571926280165 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571926280165 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571926280165 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571926280165 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571926280165 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571926280165 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571926280165 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571926280165 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1571926280165 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1571926280165 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571926280222 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1571926281718 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571926281820 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1571926281835 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1571926282259 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571926282259 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1571926282535 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X9_Y9 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9" {  } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9"} 0 0 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1571926283592 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1571926283592 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571926283654 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1571926283654 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1571926283654 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1571926283654 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.22 " "Total time spent on timing analysis during the Fitter is 0.22 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1571926283670 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571926283738 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571926284312 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571926284373 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571926284981 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571926285621 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1571926287372 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571926287648 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 22:11:27 2019 " "Processing ended: Thu Oct 24 22:11:27 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571926287648 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571926287648 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571926287648 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571926287648 ""}
diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.hier_info b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.hier_info
deleted file mode 100644
index d7345b33..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.hier_info
+++ /dev/null
@@ -1,61 +0,0 @@
-|four_line_to_sixteen_line_decimal_decoder
-Y0 <= 74138:inst.Y0N
-A => 74138:inst.A
-A => 74138:inst6.A
-B => 74138:inst.B
-B => 74138:inst6.B
-C => 74138:inst.C
-C => 74138:inst6.C
-D => 74138:inst.G2AN
-D => 74138:inst6.G1
-Y1 <= 74138:inst.Y1N
-Y2 <= 74138:inst.Y2N
-Y3 <= 74138:inst.Y3N
-Y4 <= 74138:inst.Y4N
-Y5 <= 74138:inst.Y5N
-Y6 <= 74138:inst.Y6N
-Y7 <= 74138:inst.Y7N
-Y8 <= 74138:inst6.Y0N
-Y9 <= 74138:inst6.Y1N
-Y10 <= 74138:inst6.Y2N
-Y11 <= 74138:inst6.Y3N
-Y12 <= 74138:inst6.Y4N
-Y13 <= 74138:inst6.Y5N
-Y14 <= 74138:inst6.Y6N
-Y15 <= 74138:inst6.Y7N
-
-
-|four_line_to_sixteen_line_decimal_decoder|74138:inst
-Y7N <= 22.DB_MAX_OUTPUT_PORT_TYPE
-G1 => 8.IN0
-G2BN => 1.IN1
-G2AN => 1.IN2
-B => 10.IN0
-A => 9.IN0
-C => 11.IN0
-Y6N <= 21.DB_MAX_OUTPUT_PORT_TYPE
-Y5N <= 20.DB_MAX_OUTPUT_PORT_TYPE
-Y4N <= 19.DB_MAX_OUTPUT_PORT_TYPE
-Y3N <= 18.DB_MAX_OUTPUT_PORT_TYPE
-Y2N <= 17.DB_MAX_OUTPUT_PORT_TYPE
-Y1N <= 16.DB_MAX_OUTPUT_PORT_TYPE
-Y0N <= 15.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|four_line_to_sixteen_line_decimal_decoder|74138:inst6
-Y7N <= 22.DB_MAX_OUTPUT_PORT_TYPE
-G1 => 8.IN0
-G2BN => 1.IN1
-G2AN => 1.IN2
-B => 10.IN0
-A => 9.IN0
-C => 11.IN0
-Y6N <= 21.DB_MAX_OUTPUT_PORT_TYPE
-Y5N <= 20.DB_MAX_OUTPUT_PORT_TYPE
-Y4N <= 19.DB_MAX_OUTPUT_PORT_TYPE
-Y3N <= 18.DB_MAX_OUTPUT_PORT_TYPE
-Y2N <= 17.DB_MAX_OUTPUT_PORT_TYPE
-Y1N <= 16.DB_MAX_OUTPUT_PORT_TYPE
-Y0N <= 15.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.hif b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.hif
deleted file mode 100644
index 50a600a35296325b741c7c7f04e60c15c8f55a86..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 414
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.ipinfo b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.ipinfo
deleted file mode 100644
index b19e3be175f30fec0abce2c24772f0962e31a465..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 162
zcmWe(U|?9w%?KnJ7_xxS7)Xbu78Pga=P4K(>lx}9C^(g7=A<YXni(k=8t5At>l+yu
z8Y={QDTJpcDY&L&mH?G<fb}ylltF0?C=H?(LD?0INr??$_W%Dtc1l8uKte)-N7v8l
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.lpc.html b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.lpc.html
deleted file mode 100644
index fbc5ab50..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.lpc.html
+++ /dev/null
@@ -1,18 +0,0 @@
-<TABLE>
-<TR  bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-</TABLE>
diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.lpc.rdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.lpc.rdb
deleted file mode 100644
index 45b47e5f2e16cf9ff5fed3788e2a3eca5ffb8b5c..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 399
zcmWe(U|?9w%?KnJ7_xxS7)Xbu78Pga=P4K(>lx}9C^(g7=A<YXni(k=8t5At>l+yu
z8Y={QDTJpcDY&L&mH?G*ff&Fb1EuGJ&4UpAP_YWeIsLv|hYSQ-XZLnJcz-GMT#};*
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.lpc.txt b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.lpc.txt
deleted file mode 100644
index a4638048..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.lpc.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.ammdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.ammdb
deleted file mode 100644
index e93ac1af1fe66612e97c409c5531b892acdf5bb1..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 128
zcmWe(U|?9w%?KnJ7_xxS7)Xbu78Pga=P4K(>lx}9C^(g7=A<YXni(k=8t5At>l+yu
w8Y={QDTJpcDY&L&mH?Hqfb}ylltF1GC=H?-pzI39q=bY75a<7Y5F5e*0MIuV<NyEw

diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.bpm b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.bpm
deleted file mode 100644
index 79eb4e41f54d49634b0390b90278eb10788a5d9f..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 768
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.kpt b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.kpt
deleted file mode 100644
index 13e9816e48a919c3cb5295223e55f70464a42fe1..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.logdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.logdb
deleted file mode 100644
index 626799f0..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.qmsg b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.qmsg
deleted file mode 100644
index a0da6fde..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.qmsg
+++ /dev/null
@@ -1,12 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571926271377 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571926271380 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 22:11:11 2019 " "Processing started: Thu Oct 24 22:11:11 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571926271380 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571926271380 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571926271380 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571926271772 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "four_line_to_sixteen_line_decimal_decoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file four_line_to_sixteen_line_decimal_decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 four_line_to_sixteen_line_decimal_decoder " "Found entity 1: four_line_to_sixteen_line_decimal_decoder" {  } { { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571926271928 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571926271928 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "four_line_to_sixteen_line_decimal_decoder " "Elaborating entity \"four_line_to_sixteen_line_decimal_decoder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571926272036 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74138 74138:inst " "Elaborating entity \"74138\" for hierarchy \"74138:inst\"" {  } { { "four_line_to_sixteen_line_decimal_decoder.bdf" "inst" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 112 448 568 272 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571926272046 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "74138:inst " "Elaborated megafunction instantiation \"74138:inst\"" {  } { { "four_line_to_sixteen_line_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf" { { 112 448 568 272 "inst" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571926272047 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1571926273016 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1571926273420 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571926273420 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "36 " "Implemented 36 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571926273527 ""} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Implemented 16 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571926273527 ""} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Implemented 16 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1571926273527 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571926273527 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "371 " "Peak virtual memory: 371 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571926273542 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 22:11:13 2019 " "Processing ended: Thu Oct 24 22:11:13 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571926273542 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571926273542 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571926273542 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571926273542 ""}
diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.rdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map.rdb
deleted file mode 100644
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literal 0
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deleted file mode 100644
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map_bb.hdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map_bb.hdb
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map_bb.logdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map_bb.logdb
deleted file mode 100644
index 626799f0..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.pre_map.hdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.pre_map.hdb
deleted file mode 100644
index 12676eb2f2ca160a38054d55731d153a40bccbaa..0000000000000000000000000000000000000000
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.sld_design_entry.sci b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.sld_design_entry.sci
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.smart_action.txt b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.smart_action.txt
deleted file mode 100644
index 11b531f9..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-SOURCE
diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.sta.qmsg b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.sta.qmsg
deleted file mode 100644
index 9ffb14e1..00000000
--- a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571926298032 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571926298034 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 22:11:37 2019 " "Processing started: Thu Oct 24 22:11:37 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571926298034 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571926298034 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder " "Command: quartus_sta four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571926298035 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571926298100 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571926298359 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571926298365 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571926298511 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571926298512 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "four_line_to_sixteen_line_decimal_decoder.sdc " "Synopsys Design Constraints File file not found: 'four_line_to_sixteen_line_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571926298858 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571926298859 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571926298860 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571926298861 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1571926298862 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571926298862 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571926298864 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1571926298873 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1571926298874 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926298876 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926298881 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926298882 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926298884 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926298885 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926298886 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571926298897 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571926298942 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571926299883 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571926299917 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571926299917 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571926299917 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571926299918 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926299918 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926299921 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926299922 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926299923 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926299925 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926299926 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571926299934 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571926300081 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571926300081 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571926300082 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571926300082 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926300084 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926300086 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926300088 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926300090 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571926300091 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571926300329 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571926300329 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571926300379 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 22:11:40 2019 " "Processing ended: Thu Oct 24 22:11:40 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571926300379 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571926300379 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571926300379 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571926300379 ""}
diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.sta.rdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.sta.rdb
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GIT binary patch
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.sta_cmp.6_slow_1200mv_85c.tdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.sta_cmp.6_slow_1200mv_85c.tdb
deleted file mode 100644
index c80c38da4e0c5ffbc7eb3da08fbd15cfc0608102..0000000000000000000000000000000000000000
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.tiscmp.slow_1200mv_0c.ddb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
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diff --git a/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.vpr.ammdb b/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.vpr.ammdb
deleted file mode 100644
index ab977887fad0b7ad79cdc947429998896c2cd684..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 313
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diff --git a/CH6/CH6-1/db/logic_util_heursitic.dat b/CH6/CH6-1/db/logic_util_heursitic.dat
deleted file mode 100644
index 3a875fb9b16c9e679b4fe1a931fe479706309766..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2948
zcmb8lXF`Di007YM5SfwW3T2fY*&{2Q!AR)(uJFD0`#l8VMZ(u03O5Ef4mSZe3HK3h
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diff --git a/CH6/CH6-1/db/prev_cmp_BCD_to_decimal_decoder.qmsg b/CH6/CH6-1/db/prev_cmp_BCD_to_decimal_decoder.qmsg
deleted file mode 100644
index 68fc0b7b..00000000
--- a/CH6/CH6-1/db/prev_cmp_BCD_to_decimal_decoder.qmsg
+++ /dev/null
@@ -1,126 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571325538436 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571325538438 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 23:18:58 2019 " "Processing started: Thu Oct 17 23:18:58 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571325538438 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571325538438 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571325538439 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571325538811 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD_to_decimal_decoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file BCD_to_decimal_decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BCD_to_decimal_decoder " "Found entity 1: BCD_to_decimal_decoder" {  } { { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571325538964 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571325538964 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "BCD_to_decimal_decoder " "Elaborating entity \"BCD_to_decimal_decoder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571325539069 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1571325540083 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1571325540528 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571325540528 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "24 " "Implemented 24 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571325540630 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571325540630 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10 " "Implemented 10 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1571325540630 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571325540630 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "371 " "Peak virtual memory: 371 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571325540645 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 23:19:00 2019 " "Processing ended: Thu Oct 17 23:19:00 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571325540645 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571325540645 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571325540645 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571325540645 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571325544188 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571325544190 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 23:19:02 2019 " "Processing started: Thu Oct 17 23:19:02 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571325544190 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1571325544190 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder " "Command: quartus_fit --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1571325544190 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1571325544274 ""}
-{ "Info" "0" "" "Project  = BCD_to_decimal_decoder" {  } {  } 0 0 "Project  = BCD_to_decimal_decoder" 0 0 "Fitter" 0 0 1571325544276 ""}
-{ "Info" "0" "" "Revision = BCD_to_decimal_decoder" {  } {  } 0 0 "Revision = BCD_to_decimal_decoder" 0 0 "Fitter" 0 0 1571325544276 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571325544407 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "BCD_to_decimal_decoder EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"BCD_to_decimal_decoder\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571325544417 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571325544552 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571325544555 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571325544555 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1571325544743 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1571325544776 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571325545174 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571325545174 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571325545174 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1571325545174 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 45 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571325545185 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 47 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571325545185 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 49 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571325545185 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 51 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571325545185 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 53 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571325545185 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1571325545185 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1571325545189 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "14 14 " "No exact pin location assignment(s) for 14 pins of 14 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Pin Y0 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y0 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 296 704 880 312 "Y0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 3 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Pin Y1 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y1 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 384 704 880 400 "Y1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 8 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Pin Y2 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y2 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 472 704 880 488 "Y2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 9 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Pin Y3 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y3 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 560 704 880 576 "Y3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 10 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Pin Y4 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y4 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 648 704 880 664 "Y4" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 11 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Pin Y5 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y5 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 736 704 880 752 "Y5" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 12 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Pin Y6 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y6 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 824 704 880 840 "Y6" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 13 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Pin Y7 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y7 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 912 704 880 928 "Y7" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 14 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y8 " "Pin Y8 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y8 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 1000 704 880 1016 "Y8" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y8 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 15 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y9 " "Pin Y9 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y9 } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 1088 704 880 1104 "Y9" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y9 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 16 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A " "Pin A not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 56 120 288 72 "A" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 4 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D " "Pin D not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { D } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 248 120 288 264 "D" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { D } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 7 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B " "Pin B not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 120 120 288 136 "B" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 5 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C " "Pin C not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { C } } } { "BCD_to_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf" { { 184 120 288 200 "C" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { C } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 6 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571325547020 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1571325547020 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_to_decimal_decoder.sdc " "Synopsys Design Constraints File file not found: 'BCD_to_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1571325547297 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1571325547298 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1571325547299 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1571325547301 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1571325547302 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1571325547302 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1571325547303 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1571325547311 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571325547312 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571325547313 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571325547315 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571325547316 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1571325547317 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1571325547317 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1571325547317 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1571325547318 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1571325547319 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1571325547319 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "14 unused 2.5V 4 10 0 " "Number of I/O pins in group: 14 (unused VREF, 2.5V VCCIO, 4 input, 10 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1571325547324 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1571325547324 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1571325547324 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 29 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  29 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325547327 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325547327 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325547327 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325547327 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325547327 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325547327 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325547327 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571325547327 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1571325547327 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1571325547327 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571325547366 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1571325548848 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571325548951 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1571325548965 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1571325549311 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571325549312 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1571325549576 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X9_Y9 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9" {  } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9"} 0 0 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1571325550512 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1571325550512 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571325550593 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1571325550593 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1571325550593 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1571325550593 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.14 " "Total time spent on timing analysis during the Fitter is 0.14 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1571325550607 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571325550671 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571325551200 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571325551250 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571325551832 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571325552451 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1571325554209 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571325554488 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 23:19:14 2019 " "Processing ended: Thu Oct 17 23:19:14 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571325554488 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571325554488 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571325554488 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571325554488 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1571325558977 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571325558979 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 23:19:18 2019 " "Processing started: Thu Oct 17 23:19:18 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571325558979 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571325558979 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571325558981 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1571325560551 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571325560610 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571325561166 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 23:19:21 2019 " "Processing ended: Thu Oct 17 23:19:21 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571325561166 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571325561166 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571325561166 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571325561166 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1571325561318 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1571325564732 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571325564734 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 23:19:24 2019 " "Processing started: Thu Oct 17 23:19:24 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571325564734 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571325564734 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta BCD_to_decimal_decoder -c BCD_to_decimal_decoder " "Command: quartus_sta BCD_to_decimal_decoder -c BCD_to_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571325564735 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571325564806 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571325565020 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571325565024 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571325565134 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571325565134 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "BCD_to_decimal_decoder.sdc " "Synopsys Design Constraints File file not found: 'BCD_to_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571325565452 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571325565453 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571325565454 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571325565455 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1571325565456 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571325565457 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571325565459 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1571325565472 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1571325565474 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325565476 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325565482 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325565484 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325565486 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325565487 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325565489 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571325565504 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571325565570 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571325566716 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571325566750 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571325566750 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571325566750 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571325566751 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325566751 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325566754 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325566755 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325566756 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325566758 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325566759 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571325566766 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571325566908 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571325566908 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571325566909 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571325566909 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325566911 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325566912 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325566914 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325566916 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571325566917 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571325567124 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571325567124 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "373 " "Peak virtual memory: 373 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571325567171 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 23:19:27 2019 " "Processing ended: Thu Oct 17 23:19:27 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571325567171 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571325567171 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571325567171 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571325567171 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571325571714 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571325571717 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 23:19:31 2019 " "Processing started: Thu Oct 17 23:19:31 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571325571717 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571325571717 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571325571718 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_to_decimal_decoder.vo /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim// simulation " "Generated file BCD_to_decimal_decoder.vo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1571325572271 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "348 " "Peak virtual memory: 348 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571325572342 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 23:19:32 2019 " "Processing ended: Thu Oct 17 23:19:32 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571325572342 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571325572342 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571325572342 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571325572342 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 12 s " "Quartus II Full Compilation was successful. 0 errors, 12 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571325572482 ""}
diff --git a/CH6/CH6-1/db/prev_cmp_Ten_line_to_four_line_BCD_encoder.qmsg b/CH6/CH6-1/db/prev_cmp_Ten_line_to_four_line_BCD_encoder.qmsg
deleted file mode 100644
index ae1235e0..00000000
--- a/CH6/CH6-1/db/prev_cmp_Ten_line_to_four_line_BCD_encoder.qmsg
+++ /dev/null
@@ -1,135 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1569859760120 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1569859760122 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct  1 00:09:19 2019 " "Processing started: Tue Oct  1 00:09:19 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1569859760122 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1569859760122 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1569859760123 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1569859760512 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Ten_line_to_four_line_BCD_encoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Ten_line_to_four_line_BCD_encoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Ten_line_to_four_line_BCD_encoder " "Found entity 1: Ten_line_to_four_line_BCD_encoder" {  } { { "Ten_line_to_four_line_BCD_encoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1569859760651 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1569859760651 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "Ten_line_to_four_line_BCD_encoder " "Elaborating entity \"Ten_line_to_four_line_BCD_encoder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1569859760754 ""}
-{ "Warning" "WGDFX_PIN_IGNORED" "I0 " "Pin \"I0\" not connected" {  } { { "Ten_line_to_four_line_BCD_encoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.bdf" { { 16 104 272 32 "I0" "" } } } }  } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Quartus II" 0 -1 1569859760761 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1569859761947 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1569859762422 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1569859762422 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "I0 " "No output dependent on input pin \"I0\"" {  } { { "Ten_line_to_four_line_BCD_encoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.bdf" { { 16 104 272 32 "I0" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1569859762522 "|Ten_line_to_four_line_BCD_encoder|I0"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1569859762522 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1569859762522 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1569859762522 ""} { "Info" "ICUT_CUT_TM_LCELLS" "5 " "Implemented 5 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1569859762522 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1569859762522 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "371 " "Peak virtual memory: 371 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1569859762540 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct  1 00:09:22 2019 " "Processing ended: Tue Oct  1 00:09:22 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1569859762540 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1569859762540 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1569859762540 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1569859762540 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1569859766002 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1569859766003 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct  1 00:09:24 2019 " "Processing started: Tue Oct  1 00:09:24 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1569859766003 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1569859766003 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder " "Command: quartus_fit --read_settings_files=off --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1569859766004 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1569859766055 ""}
-{ "Info" "0" "" "Project  = Ten_line_to_four_line_BCD_encoder" {  } {  } 0 0 "Project  = Ten_line_to_four_line_BCD_encoder" 0 0 "Fitter" 0 0 1569859766057 ""}
-{ "Info" "0" "" "Revision = Ten_line_to_four_line_BCD_encoder" {  } {  } 0 0 "Revision = Ten_line_to_four_line_BCD_encoder" 0 0 "Fitter" 0 0 1569859766057 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1569859766152 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "Ten_line_to_four_line_BCD_encoder EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"Ten_line_to_four_line_BCD_encoder\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1569859766159 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1569859766285 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1569859766286 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1569859766287 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1569859766434 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1569859766458 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1569859766868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1569859766868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1569859766868 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1569859766868 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 42 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1569859766883 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 44 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1569859766883 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 46 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1569859766883 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 48 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1569859766883 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 50 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1569859766883 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1569859766883 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1569859766889 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 14 " "No exact pin location assignment(s) for 1 pins of 14 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I1 " "Pin I1 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { I1 } } } { "Ten_line_to_four_line_BCD_encoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.bdf" { { 64 104 272 80 "I1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 4 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1569859768747 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1569859768747 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Ten_line_to_four_line_BCD_encoder.sdc " "Synopsys Design Constraints File file not found: 'Ten_line_to_four_line_BCD_encoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1569859768989 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1569859768991 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1569859768992 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1569859768993 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1569859768994 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1569859768995 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1569859768995 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1569859769000 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1569859769001 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1569859769002 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1569859769003 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1569859769004 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1569859769004 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1569859769004 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1569859769005 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1569859769005 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1569859769006 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1569859769006 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 2.5V 1 0 0 " "Number of I/O pins in group: 1 (unused VREF, 2.5V VCCIO, 1 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1569859769013 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1569859769013 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1569859769013 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 2.5V 17 16 " "I/O bank number 1 does not use VREF pins and has 2.5V VCCIO pins. 17 total pin(s) used --  16 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1569859769016 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1569859769016 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1569859769016 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1569859769016 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1569859769016 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1569859769016 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1569859769016 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1569859769016 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1569859769016 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1569859769016 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1569859769038 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1569859770556 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1569859770658 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1569859770673 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1569859771034 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1569859771034 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1569859771305 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1569859772241 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1569859772241 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1569859772321 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1569859772322 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1569859772322 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1569859772322 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.20 " "Total time spent on timing analysis during the Fitter is 0.20 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1569859772335 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1569859772402 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1569859772922 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1569859772973 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1569859773553 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1569859774182 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1569859776032 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1569859776312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct  1 00:09:36 2019 " "Processing ended: Tue Oct  1 00:09:36 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1569859776312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1569859776312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1569859776312 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1569859776312 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1569859780604 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1569859780606 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct  1 00:09:40 2019 " "Processing started: Tue Oct  1 00:09:40 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1569859780606 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1569859780606 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1569859780607 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1569859782374 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1569859782421 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1569859782903 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct  1 00:09:42 2019 " "Processing ended: Tue Oct  1 00:09:42 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1569859782903 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1569859782903 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1569859782903 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1569859782903 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1569859783037 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1569859786472 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1569859786473 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct  1 00:09:46 2019 " "Processing started: Tue Oct  1 00:09:46 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1569859786473 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1569859786473 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder " "Command: quartus_sta Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1569859786474 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1569859786534 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1569859786745 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1569859786749 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1569859786864 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1569859786864 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Ten_line_to_four_line_BCD_encoder.sdc " "Synopsys Design Constraints File file not found: 'Ten_line_to_four_line_BCD_encoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1569859787153 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1569859787154 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1569859787155 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1569859787155 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1569859787156 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1569859787156 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1569859787157 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1569859787165 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1569859787167 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859787168 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859787173 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859787174 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859787175 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859787176 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859787177 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1569859787189 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1569859787247 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1569859788155 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1569859788189 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1569859788190 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1569859788190 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1569859788191 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859788192 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859788194 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859788196 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859788197 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859788199 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859788200 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1569859788206 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1569859788338 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1569859788338 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1569859788338 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1569859788338 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859788340 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859788342 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859788343 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859788345 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1569859788346 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1569859788540 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1569859788540 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1569859788577 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct  1 00:09:48 2019 " "Processing ended: Tue Oct  1 00:09:48 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1569859788577 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1569859788577 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1569859788577 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1569859788577 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1569859793065 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1569859793067 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct  1 00:09:52 2019 " "Processing started: Tue Oct  1 00:09:52 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1569859793067 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1569859793067 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1569859793068 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_slow.vho /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/ simulation " "Generated file Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1569859793749 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_slow.vho /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/ simulation " "Generated file Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1569859793786 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_fast.vho /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/ simulation " "Generated file Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_fast.vho in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1569859793823 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "Ten_line_to_four_line_BCD_encoder.vho /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/ simulation " "Generated file Ten_line_to_four_line_BCD_encoder.vho in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1569859793854 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/ simulation " "Generated file Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1569859793895 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/ simulation " "Generated file Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1569859793933 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_vhd_fast.sdo /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/ simulation " "Generated file Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_vhd_fast.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1569859793963 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "Ten_line_to_four_line_BCD_encoder_vhd.sdo /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/ simulation " "Generated file Ten_line_to_four_line_BCD_encoder_vhd.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1569859793993 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Peak virtual memory: 344 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1569859794060 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct  1 00:09:54 2019 " "Processing ended: Tue Oct  1 00:09:54 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1569859794060 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1569859794060 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1569859794060 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1569859794060 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus II Full Compilation was successful. 0 errors, 15 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1569859794215 ""}
diff --git a/CH6/CH6-1/db/prev_cmp_ten_line_to_four_line_BCD_priority_encoder.qmsg b/CH6/CH6-1/db/prev_cmp_ten_line_to_four_line_BCD_priority_encoder.qmsg
deleted file mode 100644
index f38b4d39..00000000
--- a/CH6/CH6-1/db/prev_cmp_ten_line_to_four_line_BCD_priority_encoder.qmsg
+++ /dev/null
@@ -1,125 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571318545953 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571318545956 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 21:22:25 2019 " "Processing started: Thu Oct 17 21:22:25 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571318545956 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571318545956 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571318545957 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571318546301 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ten_line_to_four_line_BCD_priority_encoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ten_line_to_four_line_BCD_priority_encoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_line_to_four_line_BCD_priority_encoder " "Found entity 1: ten_line_to_four_line_BCD_priority_encoder" {  } { { "ten_line_to_four_line_BCD_priority_encoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571318546459 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571318546459 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ten_line_to_four_line_BCD_priority_encoder " "Elaborating entity \"ten_line_to_four_line_BCD_priority_encoder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571318546561 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74147 74147:inst " "Elaborating entity \"74147\" for hierarchy \"74147:inst\"" {  } { { "ten_line_to_four_line_BCD_priority_encoder.bdf" "inst" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf" { { 56 296 416 232 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571318546571 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "74147:inst " "Elaborated megafunction instantiation \"74147:inst\"" {  } { { "ten_line_to_four_line_BCD_priority_encoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf" { { 56 296 416 232 "inst" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571318546572 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1571318547628 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1571318548041 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571318548041 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571318548139 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571318548139 ""} { "Info" "ICUT_CUT_TM_LCELLS" "7 " "Implemented 7 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1571318548139 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571318548139 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571318548156 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 21:22:28 2019 " "Processing ended: Thu Oct 17 21:22:28 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571318548156 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571318548156 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571318548156 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571318548156 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571318551618 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571318551620 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 21:22:30 2019 " "Processing started: Thu Oct 17 21:22:30 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571318551620 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1571318551620 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1571318551621 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1571318551689 ""}
-{ "Info" "0" "" "Project  = ten_line_to_four_line_BCD_priority_encoder" {  } {  } 0 0 "Project  = ten_line_to_four_line_BCD_priority_encoder" 0 0 "Fitter" 0 0 1571318551690 ""}
-{ "Info" "0" "" "Revision = ten_line_to_four_line_BCD_priority_encoder" {  } {  } 0 0 "Revision = ten_line_to_four_line_BCD_priority_encoder" 0 0 "Fitter" 0 0 1571318551690 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571318551799 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ten_line_to_four_line_BCD_priority_encoder EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"ten_line_to_four_line_BCD_priority_encoder\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571318551806 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571318551920 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571318551923 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571318551923 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1571318552094 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1571318552122 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571318552546 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571318552546 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571318552546 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1571318552546 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 42 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571318552558 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 44 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571318552558 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 46 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571318552558 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 48 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571318552558 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 50 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571318552558 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1571318552558 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1571318552562 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_line_to_four_line_BCD_priority_encoder.sdc " "Synopsys Design Constraints File file not found: 'ten_line_to_four_line_BCD_priority_encoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1571318554566 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1571318554567 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1571318554568 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1571318554569 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1571318554571 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1571318554571 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1571318554572 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1571318554577 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571318554578 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571318554578 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571318554580 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571318554581 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1571318554581 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1571318554581 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1571318554581 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1571318554582 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1571318554582 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1571318554582 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571318554607 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1571318556128 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571318556233 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1571318556247 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1571318556610 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571318556610 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1571318556869 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1571318557822 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1571318557822 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571318557883 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1571318557883 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1571318557883 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1571318557883 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.22 " "Total time spent on timing analysis during the Fitter is 0.22 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1571318557896 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571318557964 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571318558470 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571318558522 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571318559082 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571318559695 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1571318561524 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571318561890 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 21:22:41 2019 " "Processing ended: Thu Oct 17 21:22:41 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571318561890 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571318561890 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571318561890 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571318561890 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1571318566118 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571318566121 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 21:22:45 2019 " "Processing started: Thu Oct 17 21:22:45 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571318566121 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571318566121 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571318566122 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1571318567787 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571318567845 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571318568326 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 21:22:48 2019 " "Processing ended: Thu Oct 17 21:22:48 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571318568326 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571318568326 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571318568326 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571318568326 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1571318568481 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1571318572182 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571318572184 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 21:22:51 2019 " "Processing started: Thu Oct 17 21:22:51 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571318572184 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571318572184 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder " "Command: quartus_sta ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571318572184 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571318572247 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571318572462 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571318572466 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571318572579 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571318572579 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_line_to_four_line_BCD_priority_encoder.sdc " "Synopsys Design Constraints File file not found: 'ten_line_to_four_line_BCD_priority_encoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571318572877 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571318572878 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571318572880 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571318572881 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1571318572882 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571318572882 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571318572884 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1571318572894 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1571318572895 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318572897 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318572901 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318572903 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318572904 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318572905 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318572906 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571318572916 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571318572969 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571318573971 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571318574004 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571318574004 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571318574005 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571318574005 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318574006 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318574008 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318574010 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318574011 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318574012 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318574014 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571318574020 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571318574153 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571318574153 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571318574154 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571318574155 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318574157 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318574159 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318574161 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318574162 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318574164 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571318574354 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571318574354 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571318574398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 21:22:54 2019 " "Processing ended: Thu Oct 17 21:22:54 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571318574398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571318574398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571318574398 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571318574398 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571318579110 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571318579113 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 21:22:58 2019 " "Processing started: Thu Oct 17 21:22:58 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571318579113 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571318579113 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571318579114 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_line_to_four_line_BCD_priority_encoder.vo /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim// simulation " "Generated file ten_line_to_four_line_BCD_priority_encoder.vo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1571318579704 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "348 " "Peak virtual memory: 348 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571318579781 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 21:22:59 2019 " "Processing ended: Thu Oct 17 21:22:59 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571318579781 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571318579781 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571318579781 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571318579781 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 11 s " "Quartus II Full Compilation was successful. 0 errors, 11 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571318579940 ""}
diff --git a/CH6/CH6-1/db/prev_cmp_three_line_to_eight_decimal_decoder.qmsg b/CH6/CH6-1/db/prev_cmp_three_line_to_eight_decimal_decoder.qmsg
deleted file mode 100644
index 9e996975..00000000
--- a/CH6/CH6-1/db/prev_cmp_three_line_to_eight_decimal_decoder.qmsg
+++ /dev/null
@@ -1,128 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571925340686 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571925340688 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 21:55:40 2019 " "Processing started: Thu Oct 24 21:55:40 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571925340688 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571925340688 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571925340689 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571925341029 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "three_line_to_eight_decimal_decoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file three_line_to_eight_decimal_decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 three_line_to_eight_decimal_decoder " "Found entity 1: three_line_to_eight_decimal_decoder" {  } { { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571925341172 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571925341172 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "three_line_to_eight_decimal_decoder " "Elaborating entity \"three_line_to_eight_decimal_decoder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571925341320 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74139 74139:inst " "Elaborating entity \"74139\" for hierarchy \"74139:inst\"" {  } { { "three_line_to_eight_decimal_decoder.bdf" "inst" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 112 480 600 272 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571925341337 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "74139:inst " "Elaborated megafunction instantiation \"74139:inst\"" {  } { { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 112 480 600 272 "inst" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571925341338 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1571925342622 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1571925343044 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571925343044 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571925343146 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571925343146 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1571925343146 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571925343146 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "371 " "Peak virtual memory: 371 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571925343162 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 21:55:43 2019 " "Processing ended: Thu Oct 24 21:55:43 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571925343162 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571925343162 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571925343162 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571925343162 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571925346652 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571925346653 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 21:55:45 2019 " "Processing started: Thu Oct 24 21:55:45 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571925346653 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1571925346653 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder " "Command: quartus_fit --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1571925346654 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1571925346738 ""}
-{ "Info" "0" "" "Project  = three_line_to_eight_decimal_decoder" {  } {  } 0 0 "Project  = three_line_to_eight_decimal_decoder" 0 0 "Fitter" 0 0 1571925346740 ""}
-{ "Info" "0" "" "Revision = three_line_to_eight_decimal_decoder" {  } {  } 0 0 "Revision = three_line_to_eight_decimal_decoder" 0 0 "Fitter" 0 0 1571925346740 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571925346870 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "three_line_to_eight_decimal_decoder EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"three_line_to_eight_decimal_decoder\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571925346882 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571925347018 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571925347021 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571925347021 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1571925347223 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1571925347255 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571925347699 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571925347699 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571925347699 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1571925347699 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 47 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571925347715 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 49 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571925347715 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 51 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571925347715 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 53 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571925347715 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 55 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571925347715 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1571925347715 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1571925347721 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "11 11 " "No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Pin Y0 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y0 } } } { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 128 632 808 144 "Y0" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 4 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571925349655 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Pin Y1 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y1 } } } { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 144 632 808 160 "Y1" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 8 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571925349655 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Pin Y2 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y2 } } } { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 160 632 808 176 "Y2" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 9 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571925349655 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Pin Y3 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y3 } } } { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 176 632 808 192 "Y3" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 10 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571925349655 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Pin Y4 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y4 } } } { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 192 632 808 208 "Y4" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 11 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571925349655 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Pin Y5 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y5 } } } { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 208 632 808 224 "Y5" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 12 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571925349655 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Pin Y6 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y6 } } } { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 224 632 808 240 "Y6" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 13 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571925349655 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Pin Y7 not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { Y7 } } } { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 240 632 808 256 "Y7" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 14 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571925349655 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C " "Pin C not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { C } } } { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 208 232 400 224 "C" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { C } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 7 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571925349655 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A " "Pin A not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { A } } } { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 144 232 400 160 "A" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { A } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 5 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571925349655 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B " "Pin B not assigned to an exact location on the device" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { B } } } { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 160 232 400 176 "B" "" } } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { B } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 6 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1571925349655 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1571925349655 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "three_line_to_eight_decimal_decoder.sdc " "Synopsys Design Constraints File file not found: 'three_line_to_eight_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1571925349932 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1571925349933 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1571925349935 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1571925349936 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1571925349938 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1571925349938 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1571925349938 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1571925349944 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571925349944 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571925349945 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571925349947 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571925349947 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1571925349948 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1571925349948 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1571925349948 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1571925349948 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1571925349949 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1571925349949 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 2.5V 3 8 0 " "Number of I/O pins in group: 11 (unused VREF, 2.5V VCCIO, 3 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1571925349954 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1571925349954 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1571925349954 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 29 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  29 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571925349958 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571925349958 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571925349958 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571925349958 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571925349958 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571925349958 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571925349958 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1571925349958 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1571925349958 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1571925349958 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571925349982 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1571925351590 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571925351719 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1571925351741 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1571925352117 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571925352117 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1571925352399 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X9_Y9 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9" {  } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9"} 0 0 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1571925353404 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1571925353404 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571925353481 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1571925353481 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1571925353481 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1571925353481 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.20 " "Total time spent on timing analysis during the Fitter is 0.20 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1571925353499 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571925353588 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571925354174 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571925354232 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571925354824 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571925355506 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1571925357349 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571925357718 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 21:55:57 2019 " "Processing ended: Thu Oct 24 21:55:57 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571925357718 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571925357718 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571925357718 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571925357718 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1571925362578 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571925362581 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 21:56:02 2019 " "Processing started: Thu Oct 24 21:56:02 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571925362581 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571925362581 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571925362582 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1571925364248 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571925364306 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571925364786 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 21:56:04 2019 " "Processing ended: Thu Oct 24 21:56:04 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571925364786 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571925364786 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571925364786 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571925364786 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1571925364923 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1571925368766 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571925368767 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 21:56:08 2019 " "Processing started: Thu Oct 24 21:56:08 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571925368767 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571925368767 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder " "Command: quartus_sta three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571925368768 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571925368837 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571925369082 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571925369088 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571925369235 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571925369235 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "three_line_to_eight_decimal_decoder.sdc " "Synopsys Design Constraints File file not found: 'three_line_to_eight_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571925369571 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571925369572 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571925369573 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571925369573 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1571925369574 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571925369574 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571925369576 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1571925369585 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1571925369586 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925369587 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925369592 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925369594 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925369596 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925369598 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925369599 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571925369613 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571925369662 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571925370583 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571925370621 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571925370621 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571925370622 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571925370622 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925370623 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925370626 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925370627 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925370629 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925370631 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925370632 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571925370641 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571925370773 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571925370774 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571925370774 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571925370774 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925370776 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925370777 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925370779 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925370781 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925370782 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571925370971 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571925370971 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571925371012 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 21:56:11 2019 " "Processing ended: Thu Oct 24 21:56:11 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571925371012 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571925371012 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571925371012 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571925371012 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571925375451 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571925375453 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 21:56:15 2019 " "Processing started: Thu Oct 24 21:56:15 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571925375453 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571925375453 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571925375454 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "three_line_to_eight_decimal_decoder.vo /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim// simulation " "Generated file three_line_to_eight_decimal_decoder.vo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1571925376031 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "348 " "Peak virtual memory: 348 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571925376107 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 21:56:16 2019 " "Processing ended: Thu Oct 24 21:56:16 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571925376107 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571925376107 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571925376107 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571925376107 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 12 s " "Quartus II Full Compilation was successful. 0 errors, 12 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571925376263 ""}
diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.(0).cnf.cdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.(0).cnf.cdb
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GIT binary patch
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GIT binary patch
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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.(1).cnf.cdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.(1).cnf.cdb
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GIT binary patch
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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.(1).cnf.hdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.(1).cnf.hdb
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index c9d0a0a145a64ec06129b075f21f34c2dbec470a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.asm.qmsg b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.asm.qmsg
deleted file mode 100644
index ba609e9b..00000000
--- a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.asm.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571318781102 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571318781104 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 21:26:20 2019 " "Processing started: Thu Oct 17 21:26:20 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571318781104 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571318781104 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571318781105 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1571318782617 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571318782658 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571318783131 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 21:26:23 2019 " "Processing ended: Thu Oct 17 21:26:23 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571318783131 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571318783131 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571318783131 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571318783131 ""}
diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.asm.rdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.asm.rdb
deleted file mode 100644
index a5e67dde6e76f454d3ee5fda020b75c3e1a8b1b9..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cbx.xml b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cbx.xml
deleted file mode 100644
index 53d29932..00000000
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@@ -1,5 +0,0 @@
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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cmp.hdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cmp.hdb
deleted file mode 100644
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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cmp.idb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cmp.idb
deleted file mode 100644
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z*rvXN4<bU{se9KhMR4mYxYd>COcSxxz+sZ}e>s<b3M5622_f0y_iGByG{h!^ZJEkq
z9y3{stEOwWna6b^O$s2tm&R{!kY$J>M1rf9CtaQ)JCJ*LeELKU%dW;uo7Vu)g(hg0
zY=iU_UOyv-u@R%DltLl@hn^!jP?HDgJOno1v$?S5Nftiu##aU+h?XEw#<5tPD~Egg
z(pu2m(fw^ZX}T73u&!N8Xd~!HG)LA!%iI_vv<CSoW`&dohfM_@39dZuGzEBMC@bh+
zj4stMI;mDW{xImm>mcZ#8QpV#P??f3qoRQyL_@98io+e~E))|&)))*u$(L!FF3t>s
z&f#+Z4^rn1<$`@QKeH`vgg;Ji+X=%SU7CS^?_<iE(_ZLDw4mvit=$i(sLff4OWO^P
OyA3Av<^2Ev0RR8Db2p^`

diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cmp.logdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cmp.logdb
deleted file mode 100644
index e4d4092a..00000000
--- a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cmp.logdb
+++ /dev/null
@@ -1,54 +0,0 @@
-v1
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,12;0;12;0;0;12;12;0;12;12;0;4;0;0;8;0;4;8;0;0;0;4;0;0;0;0;0;12;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,0;12;0;12;12;0;0;12;0;0;12;8;12;12;4;12;8;4;12;12;12;8;12;12;12;12;12;0;12;12,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,A,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,B,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,C,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,D,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,I6,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,I4,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,I3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,I5,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,I7,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,I9,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,I8,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,I2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cmp.rdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cmp.rdb
deleted file mode 100644
index e5db75b43d4134832e86ff9a82f72273d200e2d8..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.eda.qmsg b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.eda.qmsg
deleted file mode 100644
index 3d221aed..00000000
--- a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.eda.qmsg
+++ /dev/null
@@ -1,5 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571318793559 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571318793561 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 21:26:33 2019 " "Processing started: Thu Oct 17 21:26:33 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571318793561 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571318793561 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571318793562 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_line_to_four_line_BCD_priority_encoder.vo /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim// simulation " "Generated file ten_line_to_four_line_BCD_priority_encoder.vo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1571318794156 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "348 " "Peak virtual memory: 348 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571318794228 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 21:26:34 2019 " "Processing ended: Thu Oct 17 21:26:34 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571318794228 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571318794228 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571318794228 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571318794228 ""}
diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.fit.qmsg b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.fit.qmsg
deleted file mode 100644
index 4192798c..00000000
--- a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.fit.qmsg
+++ /dev/null
@@ -1,45 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571318767033 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ten_line_to_four_line_BCD_priority_encoder EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"ten_line_to_four_line_BCD_priority_encoder\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571318767040 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571318767159 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571318767161 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571318767161 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1571318767305 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1571318767327 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571318767708 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571318767708 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571318767708 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1571318767708 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 42 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571318767718 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 44 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571318767718 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 46 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571318767718 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 48 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571318767718 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 50 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571318767718 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1571318767718 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1571318767723 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_line_to_four_line_BCD_priority_encoder.sdc " "Synopsys Design Constraints File file not found: 'ten_line_to_four_line_BCD_priority_encoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1571318769763 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1571318769764 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1571318769765 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1571318769766 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1571318769768 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1571318769768 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1571318769769 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1571318769777 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571318769778 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571318769778 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571318769780 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571318769781 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1571318769782 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1571318769782 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1571318769783 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1571318769783 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1571318769784 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1571318769784 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571318769817 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1571318771421 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571318771528 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1571318771548 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1571318771902 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571318771902 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1571318772156 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1571318773117 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1571318773117 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571318773175 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1571318773175 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1571318773175 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1571318773175 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.20 " "Total time spent on timing analysis during the Fitter is 0.20 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1571318773188 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571318773261 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571318773780 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571318773832 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571318774385 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571318775001 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1571318776721 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571318777008 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 21:26:17 2019 " "Processing ended: Thu Oct 17 21:26:17 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571318777008 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571318777008 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571318777008 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571318777008 ""}
diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.hier_info b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.hier_info
deleted file mode 100644
index 1ce7b501..00000000
--- a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.hier_info
+++ /dev/null
@@ -1,31 +0,0 @@
-|ten_line_to_four_line_BCD_priority_encoder
-A <= inst3.DB_MAX_OUTPUT_PORT_TYPE
-I2 => 74147:inst.2N
-I3 => 74147:inst.3N
-I6 => 74147:inst.6N
-I5 => 74147:inst.5N
-I4 => 74147:inst.4N
-I9 => 74147:inst.9N
-I8 => 74147:inst.8N
-I7 => 74147:inst.7N
-B <= inst4.DB_MAX_OUTPUT_PORT_TYPE
-C <= inst5.DB_MAX_OUTPUT_PORT_TYPE
-D <= inst6.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ten_line_to_four_line_BCD_priority_encoder|74147:inst
-DN <= 68.DB_MAX_OUTPUT_PORT_TYPE
-8N => 63.IN0
-9N => 65.IN0
-CN <= 9.DB_MAX_OUTPUT_PORT_TYPE
-4N => 57.IN0
-5N => 60.IN0
-6N => 62.IN0
-7N => 114.IN0
-BN <= 8.DB_MAX_OUTPUT_PORT_TYPE
-2N => 55.IN0
-3N => 56.IN0
-AN <= 7.DB_MAX_OUTPUT_PORT_TYPE
-1N => 53.IN0
-
-
diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.hif b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.hif
deleted file mode 100644
index b5053c4c40fcd2e9cd386665eb3c5a7f31ba389e..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 414
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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.ipinfo b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.ipinfo
deleted file mode 100644
index b19e3be175f30fec0abce2c24772f0962e31a465..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 162
zcmWe(U|?9w%?KnJ7_xxS7)Xbu78Pga=P4K(>lx}9C^(g7=A<YXni(k=8t5At>l+yu
z8Y={QDTJpcDY&L&mH?G<fb}ylltF0?C=H?(LD?0INr??$_W%Dtc1l8uKte)-N7v8l
i7C{eV#*GRB)oeekejTl5J5v2?=g;H2EkLgN{~rJkr6;-o

diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.lpc.html b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.lpc.html
deleted file mode 100644
index fbc5ab50..00000000
--- a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.lpc.html
+++ /dev/null
@@ -1,18 +0,0 @@
-<TABLE>
-<TR  bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-</TABLE>
diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.lpc.rdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.lpc.rdb
deleted file mode 100644
index 45b47e5f2e16cf9ff5fed3788e2a3eca5ffb8b5c..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 399
zcmWe(U|?9w%?KnJ7_xxS7)Xbu78Pga=P4K(>lx}9C^(g7=A<YXni(k=8t5At>l+yu
z8Y={QDTJpcDY&L&mH?G*ff&Fb1EuGJ&4UpAP_YWeIsLv|hYSQ-XZLnJcz-GMT#};*
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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.lpc.txt b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.lpc.txt
deleted file mode 100644
index a4638048..00000000
--- a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.lpc.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map.kpt b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map.kpt
deleted file mode 100644
index 0cd5223c29dcfbf60b69a0f9c9a200112761d58c..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map.logdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map.logdb
deleted file mode 100644
index 626799f0..00000000
--- a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map.qmsg b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map.qmsg
deleted file mode 100644
index 17e5affa..00000000
--- a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map.qmsg
+++ /dev/null
@@ -1,12 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571318761054 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571318761057 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 21:26:00 2019 " "Processing started: Thu Oct 17 21:26:00 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571318761057 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571318761057 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571318761058 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571318761471 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ten_line_to_four_line_BCD_priority_encoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ten_line_to_four_line_BCD_priority_encoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_line_to_four_line_BCD_priority_encoder " "Found entity 1: ten_line_to_four_line_BCD_priority_encoder" {  } { { "ten_line_to_four_line_BCD_priority_encoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571318761620 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571318761620 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ten_line_to_four_line_BCD_priority_encoder " "Elaborating entity \"ten_line_to_four_line_BCD_priority_encoder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571318761725 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74147 74147:inst " "Elaborating entity \"74147\" for hierarchy \"74147:inst\"" {  } { { "ten_line_to_four_line_BCD_priority_encoder.bdf" "inst" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf" { { 56 296 416 232 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571318761736 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "74147:inst " "Elaborated megafunction instantiation \"74147:inst\"" {  } { { "ten_line_to_four_line_BCD_priority_encoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf" { { 56 296 416 232 "inst" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571318761737 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1571318762741 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1571318763235 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571318763235 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571318763371 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571318763371 ""} { "Info" "ICUT_CUT_TM_LCELLS" "7 " "Implemented 7 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1571318763371 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571318763371 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "371 " "Peak virtual memory: 371 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571318763390 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 21:26:03 2019 " "Processing ended: Thu Oct 17 21:26:03 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571318763390 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571318763390 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571318763390 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571318763390 ""}
diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map.rdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map.rdb
deleted file mode 100644
index 2e5191e1e164709a70c64920aac31ce4fbe7018d..0000000000000000000000000000000000000000
GIT binary patch
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HcmV?d00001

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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map_bb.cdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map_bb.cdb
deleted file mode 100644
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GIT binary patch
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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map_bb.hdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.map_bb.hdb
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deleted file mode 100644
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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.smart_action.txt b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.smart_action.txt
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deleted file mode 100644
index 2c5264b2..00000000
--- a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571318786702 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571318786703 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 17 21:26:26 2019 " "Processing started: Thu Oct 17 21:26:26 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571318786703 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571318786703 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder " "Command: quartus_sta ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571318786704 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571318786766 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571318786973 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571318786977 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571318787087 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571318787088 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_line_to_four_line_BCD_priority_encoder.sdc " "Synopsys Design Constraints File file not found: 'ten_line_to_four_line_BCD_priority_encoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571318787385 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571318787386 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571318787387 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571318787388 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1571318787389 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571318787390 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571318787392 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1571318787403 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1571318787405 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318787406 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318787410 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318787412 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318787413 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318787414 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318787415 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571318787425 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571318787476 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571318788362 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571318788400 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571318788401 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571318788401 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571318788401 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318788402 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318788405 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318788407 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318788409 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318788410 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318788412 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571318788421 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571318788589 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571318788590 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571318788590 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571318788591 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318788593 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318788595 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318788597 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318788598 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571318788600 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571318788822 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571318788822 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "369 " "Peak virtual memory: 369 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571318788862 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 17 21:26:28 2019 " "Processing ended: Thu Oct 17 21:26:28 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571318788862 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571318788862 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571318788862 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571318788862 ""}
diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.sta.rdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.sta.rdb
deleted file mode 100644
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diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.tmw_info b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.tmw_info
deleted file mode 100644
index e522c786..00000000
--- a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.tmw_info
+++ /dev/null
@@ -1,5 +0,0 @@
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-start_analysis_elaboration:s
-start_fitter:s:00:00:14
-start_timing_analyzer:s:00:00:06
-start_eda_netlist_writer:s:00:00:05
diff --git a/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.vpr.ammdb b/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.vpr.ammdb
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GIT binary patch
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.asm.qmsg b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.asm.qmsg
deleted file mode 100644
index 47fa36db..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.asm.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571925469623 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571925469625 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 21:57:49 2019 " "Processing started: Thu Oct 24 21:57:49 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571925469625 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571925469625 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571925469626 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1571925471320 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571925471377 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571925471938 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 21:57:51 2019 " "Processing ended: Thu Oct 24 21:57:51 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571925471938 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571925471938 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571925471938 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571925471938 ""}
diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.asm.rdb b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.asm.rdb
deleted file mode 100644
index fbe48b605b171e625ae6100f53949fb8a4bc51e1..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.asm_labs.ddb b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.asm_labs.ddb
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GIT binary patch
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cbx.xml b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cbx.xml
deleted file mode 100644
index 3b552281..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cbx.xml
+++ /dev/null
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cmp.cdb b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cmp.cdb
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cmp.idb b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cmp.idb
deleted file mode 100644
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zG$uYSJ|R9OJ}EveJ|m9)6>;8WkB@9fe15@(ksmDkjpfj;)&jfwz+bAaRD+1+cf)GK
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zjT2rKUzb;zm}QAw<2R1iBs)jUyKY#4!H0`+<>@o?!R6A4d8zSkvsErh@^d|nwu1Co
zTdBe*d3@pQzcqmtU!E9qpcH%FBeR)wkBo0bkp)$*+!VdBcFK`=>hVwHyU63ld2VoV
z9kP7w?ASdge^dMs!sJ{@AM~3wSL53@`fRHlf5|#wFK+eE-F!S~-o6?#z4wPr>BMpK
z@pIX%&kmT^U+=8_$usDwuel+=T`lpsUT4H!(S%!MUZ&CC9yDiv-{Et2#Rbb2TVFuI
ztTF8G)S7k=`SiYB_J3~s3h=Hb-#s6>yxMYMKi}!EufG=0Po&T6%)}1>00960cmZsY
z%SyvQ6o#i4wbnw>g11#c7cTk&mM}1B#u}V-N*cR#Oe<=zHrS@VgAXD?-Kl%mE=6$b
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cmp.logdb b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cmp.logdb
deleted file mode 100644
index eb89fe79..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cmp.logdb
+++ /dev/null
@@ -1,53 +0,0 @@
-v1
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,11;0;11;0;0;11;11;0;11;11;0;8;0;0;3;0;8;3;0;0;0;8;0;0;0;0;0;11;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,0;11;0;11;11;0;0;11;0;0;11;3;11;11;8;11;3;8;11;11;11;3;11;11;11;11;11;0;11;11,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Y0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y4,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y5,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y6,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,Y7,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,C,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,A,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,B,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cmp.rdb b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cmp.rdb
deleted file mode 100644
index 2984d0d1d8b076896cc6325ffd717ed7c69bb97f..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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deleted file mode 100644
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.eda.qmsg b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.eda.qmsg
deleted file mode 100644
index b38ce3b9..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.eda.qmsg
+++ /dev/null
@@ -1,5 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571925482712 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571925482714 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 21:58:02 2019 " "Processing started: Thu Oct 24 21:58:02 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571925482714 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571925482714 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571925482715 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "three_line_to_eight_decimal_decoder.vo /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim// simulation " "Generated file three_line_to_eight_decimal_decoder.vo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1571925483272 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "348 " "Peak virtual memory: 348 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571925483350 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 21:58:03 2019 " "Processing ended: Thu Oct 24 21:58:03 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571925483350 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571925483350 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571925483350 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571925483350 ""}
diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.fit.qmsg b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.fit.qmsg
deleted file mode 100644
index 3bca34c6..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.fit.qmsg
+++ /dev/null
@@ -1,45 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571925454885 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "three_line_to_eight_decimal_decoder EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"three_line_to_eight_decimal_decoder\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571925454893 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571925455013 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571925455015 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1571925455015 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1571925455162 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1571925455185 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571925455571 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571925455571 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1571925455571 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1571925455571 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 47 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571925455585 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 49 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571925455585 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 51 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571925455585 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 53 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571925455585 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/timmy/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/timmy/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 0 { 0 ""} 0 55 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1571925455585 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1571925455585 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1571925455591 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "three_line_to_eight_decimal_decoder.sdc " "Synopsys Design Constraints File file not found: 'three_line_to_eight_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1571925457712 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1571925457713 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1571925457714 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1571925457715 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1571925457717 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1571925457717 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1571925457718 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1571925457723 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571925457724 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1571925457724 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571925457726 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1571925457727 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1571925457727 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1571925457727 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1571925457727 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1571925457728 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1571925457728 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1571925457728 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571925457752 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1571925459361 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571925459480 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1571925459495 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1571925459840 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571925459840 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1571925460103 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1571925461071 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1571925461071 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571925461134 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1571925461135 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1571925461135 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1571925461135 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.18 " "Total time spent on timing analysis during the Fitter is 0.18 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1571925461147 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571925461213 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571925461737 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1571925461787 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1571925462368 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1571925463009 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.smsg " "Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1571925464737 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "536 " "Peak virtual memory: 536 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571925465005 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 21:57:45 2019 " "Processing ended: Thu Oct 24 21:57:45 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571925465005 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571925465005 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571925465005 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571925465005 ""}
diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.hier_info b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.hier_info
deleted file mode 100644
index 79c57556..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.hier_info
+++ /dev/null
@@ -1,34 +0,0 @@
-|three_line_to_eight_decimal_decoder
-Y0 <= 74139:inst.Y10N
-A => 74139:inst.A1
-A => 74139:inst.A2
-B => 74139:inst.B1
-B => 74139:inst.B2
-C => 74139:inst.G1N
-C => inst2.IN0
-Y1 <= 74139:inst.Y11N
-Y2 <= 74139:inst.Y12N
-Y3 <= 74139:inst.Y13N
-Y4 <= 74139:inst.Y20N
-Y5 <= 74139:inst.Y21N
-Y6 <= 74139:inst.Y22N
-Y7 <= 74139:inst.Y23N
-
-
-|three_line_to_eight_decimal_decoder|74139:inst
-Y10N <= 33.DB_MAX_OUTPUT_PORT_TYPE
-G1N => 7.IN0
-B1 => 11.IN0
-A1 => 8.IN0
-Y11N <= 34.DB_MAX_OUTPUT_PORT_TYPE
-Y12N <= 35.DB_MAX_OUTPUT_PORT_TYPE
-Y13N <= 36.DB_MAX_OUTPUT_PORT_TYPE
-Y20N <= 37.DB_MAX_OUTPUT_PORT_TYPE
-G2N => 12.IN0
-B2 => 16.IN0
-A2 => 13.IN0
-Y21N <= 38.DB_MAX_OUTPUT_PORT_TYPE
-Y22N <= 39.DB_MAX_OUTPUT_PORT_TYPE
-Y23N <= 40.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.hif b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.hif
deleted file mode 100644
index bcd7e18d3a56c093573a35914a222552d27e9b2a..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.ipinfo b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.ipinfo
deleted file mode 100644
index b19e3be175f30fec0abce2c24772f0962e31a465..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.lpc.html b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.lpc.html
deleted file mode 100644
index fbc5ab50..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.lpc.html
+++ /dev/null
@@ -1,18 +0,0 @@
-<TABLE>
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-<TH>Input</TH>
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-<TH>Input only Bidir</TH>
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.lpc.rdb b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.lpc.rdb
deleted file mode 100644
index 45b47e5f2e16cf9ff5fed3788e2a3eca5ffb8b5c..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.lpc.txt b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.lpc.txt
deleted file mode 100644
index a4638048..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.lpc.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.ammdb b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.ammdb
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GIT binary patch
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.bpm b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.bpm
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deleted file mode 100644
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GIT binary patch
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.kpt b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.kpt
deleted file mode 100644
index ece30ec41136bd74a579143297cf8da0740e4fce..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.logdb b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.logdb
deleted file mode 100644
index 626799f0..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.qmsg b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.qmsg
deleted file mode 100644
index 30311e3a..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.qmsg
+++ /dev/null
@@ -1,12 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571925449129 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571925449132 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 21:57:28 2019 " "Processing started: Thu Oct 24 21:57:28 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571925449132 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571925449132 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571925449133 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571925449484 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "three_line_to_eight_decimal_decoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file three_line_to_eight_decimal_decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 three_line_to_eight_decimal_decoder " "Found entity 1: three_line_to_eight_decimal_decoder" {  } { { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571925449633 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571925449633 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "three_line_to_eight_decimal_decoder " "Elaborating entity \"three_line_to_eight_decimal_decoder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571925449736 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74139 74139:inst " "Elaborating entity \"74139\" for hierarchy \"74139:inst\"" {  } { { "three_line_to_eight_decimal_decoder.bdf" "inst" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 112 480 600 272 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571925449746 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "74139:inst " "Elaborated megafunction instantiation \"74139:inst\"" {  } { { "three_line_to_eight_decimal_decoder.bdf" "" { Schematic "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf" { { 112 480 600 272 "inst" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571925449747 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1571925450723 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1571925451122 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571925451122 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571925451221 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571925451221 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1571925451221 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571925451221 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "371 " "Peak virtual memory: 371 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571925451237 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 21:57:31 2019 " "Processing ended: Thu Oct 24 21:57:31 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571925451237 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571925451237 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571925451237 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571925451237 ""}
diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.rdb b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.map.rdb
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.sld_design_entry.sci b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.sld_design_entry.sci
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.sld_design_entry_dsc.sci b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.sld_design_entry_dsc.sci
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diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.smart_action.txt b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.smart_action.txt
deleted file mode 100644
index c8e8a135..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.sta.qmsg b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.sta.qmsg
deleted file mode 100644
index ee920d0c..00000000
--- a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571925475933 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571925475935 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 24 21:57:55 2019 " "Processing started: Thu Oct 24 21:57:55 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571925475935 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571925475935 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder " "Command: quartus_sta three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571925475936 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571925475996 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571925476237 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571925476243 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571925476390 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1571925476390 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "three_line_to_eight_decimal_decoder.sdc " "Synopsys Design Constraints File file not found: 'three_line_to_eight_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571925476756 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571925476757 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571925476759 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571925476759 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1571925476760 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571925476760 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571925476762 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1571925476773 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1571925476774 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925476776 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925476782 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925476783 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925476785 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925476786 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925476787 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571925476802 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571925476867 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571925477814 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571925477846 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571925477846 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571925477846 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571925477847 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925477847 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925477850 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925477851 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925477852 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925477854 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925477855 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1571925477861 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571925478019 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1571925478019 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1571925478019 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1571925478020 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925478022 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925478023 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925478024 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925478025 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571925478026 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571925478218 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571925478218 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571925478256 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 24 21:57:58 2019 " "Processing ended: Thu Oct 24 21:57:58 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571925478256 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571925478256 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571925478256 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571925478256 ""}
diff --git a/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.sta.rdb b/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.sta.rdb
deleted file mode 100644
index 502c3687d94b6593e4768153c76b7644536fb915..0000000000000000000000000000000000000000
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deleted file mode 100644
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index a1c04827..00000000
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diff --git a/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf b/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf
deleted file mode 100644
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diff --git a/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.qpf b/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.qpf
deleted file mode 100644
index ce43ae29..00000000
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diff --git a/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.qsf b/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.qsf
deleted file mode 100644
index 4cba3c10..00000000
--- a/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.qsf
+++ /dev/null
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-# (including device programming or simulation files), and any 
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-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
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deleted file mode 100644
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diff --git a/CH6/CH6-1/incremental_db/README b/CH6/CH6-1/incremental_db/README
deleted file mode 100644
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--- a/CH6/CH6-1/incremental_db/README
+++ /dev/null
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-This folder contains data for incremental compilation.
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-The compiled_partitions sub-folder contains previous compilation results for each partition.
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-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
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-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.cmp.ammdb b/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.cmp.ammdb
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diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.cmp.logdb b/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.cmp.logdb
deleted file mode 100644
index 626799f0..00000000
--- a/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.cmp.rcfdb b/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.cmp.rcfdb
deleted file mode 100644
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diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.map.hbdb.sig b/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.map.hbdb.sig
deleted file mode 100644
index ef58eaac..00000000
--- a/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
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\ No newline at end of file
diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.map.hdb b/CH6/CH6-1/incremental_db/compiled_partitions/BCD_to_decimal_decoder.root_partition.map.hdb
deleted file mode 100644
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diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.cmp.dfp b/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d625638bb473b681fa4acb00be38889ece3..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.cmp.hdb b/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.cmp.hdb
deleted file mode 100644
index 5bedaad0b17f4bec65772985743a8bb9d341ff82..0000000000000000000000000000000000000000
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diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.cmp.logdb b/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.cmp.logdb
deleted file mode 100644
index 626799f0..00000000
--- a/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
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diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.cmp.rcfdb b/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.cmp.rcfdb
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diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.map.hbdb.sig b/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.map.hbdb.sig
deleted file mode 100644
index ef58eaac..00000000
--- a/CH6/CH6-1/incremental_db/compiled_partitions/four_line_to_sixteen_line_decimal_decoder.root_partition.map.hbdb.sig
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deleted file mode 100644
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deleted file mode 100644
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diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/ten_line_to_four_line_BCD_priority_encoder.root_partition.map.hbdb.sig b/CH6/CH6-1/incremental_db/compiled_partitions/ten_line_to_four_line_BCD_priority_encoder.root_partition.map.hbdb.sig
deleted file mode 100644
index ef58eaac..00000000
--- a/CH6/CH6-1/incremental_db/compiled_partitions/ten_line_to_four_line_BCD_priority_encoder.root_partition.map.hbdb.sig
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diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/three_line_to_eight_decimal_decoder.root_partition.map.hbdb.sig b/CH6/CH6-1/incremental_db/compiled_partitions/three_line_to_eight_decimal_decoder.root_partition.map.hbdb.sig
deleted file mode 100644
index ef58eaac..00000000
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diff --git a/CH6/CH6-1/incremental_db/compiled_partitions/three_line_to_eight_decimal_decoder.root_partition.map.kpt b/CH6/CH6-1/incremental_db/compiled_partitions/three_line_to_eight_decimal_decoder.root_partition.map.kpt
deleted file mode 100644
index c39ca54d09341d094b34d752533729e7f355ea94..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.asm.rpt b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.asm.rpt
deleted file mode 100644
index 33c49daa..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.asm.rpt
+++ /dev/null
@@ -1,116 +0,0 @@
-Assembler report for BCD_to_decimal_decoder
-Thu Oct 17 23:24:57 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: BCD_to_decimal_decoder.sof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Oct 17 23:24:57 2019 ;
-; Revision Name         ; BCD_to_decimal_decoder                ;
-; Top-level Entity Name ; BCD_to_decimal_decoder                ;
-; Family                ; Cyclone III                           ;
-; Device                ; EP3C16F484C6                          ;
-+-----------------------+---------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Assembler Settings                                                                                     ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Option                                                                      ; Setting  ; Default Value ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Use smart compilation                                                       ; Off      ; Off           ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
-; Enable compact report table                                                 ; Off      ; Off           ;
-; Generate compressed bitstreams                                              ; On       ; On            ;
-; Compression mode                                                            ; Off      ; Off           ;
-; Clock source for configuration device                                       ; Internal ; Internal      ;
-; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
-; Divide clock frequency by                                                   ; 1        ; 1             ;
-; Auto user code                                                              ; On       ; On            ;
-; Use configuration device                                                    ; Off      ; Off           ;
-; Configuration device                                                        ; Auto     ; Auto          ;
-; Configuration device auto user code                                         ; Off      ; Off           ;
-; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
-; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
-; Hexadecimal Output File start address                                       ; 0        ; 0             ;
-; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
-; Release clears before tri-states                                            ; Off      ; Off           ;
-; Auto-restart configuration after error                                      ; On       ; On            ;
-; Enable OCT_DONE                                                             ; Off      ; Off           ;
-; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
-+-----------------------------------------------------------------------------+----------+---------------+
-
-
-+----------------------------+
-; Assembler Generated Files  ;
-+----------------------------+
-; File Name                  ;
-+----------------------------+
-; BCD_to_decimal_decoder.sof ;
-+----------------------------+
-
-
-+------------------------------------------------------+
-; Assembler Device Options: BCD_to_decimal_decoder.sof ;
-+----------------+-------------------------------------+
-; Option         ; Setting                             ;
-+----------------+-------------------------------------+
-; Device         ; EP3C16F484C6                        ;
-; JTAG usercode  ; 0x000C94FB                          ;
-; Checksum       ; 0x000C94FB                          ;
-+----------------+-------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit Assembler
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 17 23:24:55 2019
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 382 megabytes
-    Info: Processing ended: Thu Oct 17 23:24:57 2019
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.done b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.done
deleted file mode 100644
index 8a47d817..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.done
+++ /dev/null
@@ -1 +0,0 @@
-Thu Oct 17 23:25:09 2019
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.eda.rpt b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.eda.rpt
deleted file mode 100644
index 0f41223f..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.eda.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-EDA Netlist Writer report for BCD_to_decimal_decoder
-Thu Oct 17 23:25:08 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. EDA Netlist Writer Summary
-  3. Simulation Settings
-  4. Simulation Generated Files
-  5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary                                        ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Oct 17 23:25:08 2019 ;
-; Revision Name             ; BCD_to_decimal_decoder                ;
-; Top-level Entity Name     ; BCD_to_decimal_decoder                ;
-; Family                    ; Cyclone III                           ;
-; Simulation Files Creation ; Successful                            ;
-+---------------------------+---------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings                                                                                                           ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-; Option                                                                                            ; Setting                   ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
-; Generate netlist for functional simulation only                                                   ; On                        ;
-; Truncate long hierarchy paths                                                                     ; Off                       ;
-; Map illegal HDL characters                                                                        ; Off                       ;
-; Flatten buses into individual nodes                                                               ; Off                       ;
-; Maintain hierarchy                                                                                ; Off                       ;
-; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
-; Enable glitch filtering                                                                           ; Off                       ;
-; Do not write top level VHDL entity                                                                ; Off                       ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
-; Architecture name in VHDL output netlist                                                          ; structure                 ;
-; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
-; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-
-
-+---------------------------------------------------------------------------------+
-; Simulation Generated Files                                                      ;
-+---------------------------------------------------------------------------------+
-; Generated Files                                                                 ;
-+---------------------------------------------------------------------------------+
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//BCD_to_decimal_decoder.vo ;
-+---------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit EDA Netlist Writer
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 17 23:25:07 2019
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder
-Info (204019): Generated file BCD_to_decimal_decoder.vo in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//" for EDA simulation tool
-Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 348 megabytes
-    Info: Processing ended: Thu Oct 17 23:25:08 2019
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.rpt b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.rpt
deleted file mode 100644
index 67368fa6..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.rpt
+++ /dev/null
@@ -1,1303 +0,0 @@
-Fitter report for BCD_to_decimal_decoder
-Thu Oct 17 23:24:50 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. I/O Assignment Warnings
-  6. Incremental Compilation Preservation Summary
-  7. Incremental Compilation Partition Settings
-  8. Incremental Compilation Placement Preservation
-  9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. Fitter Resource Utilization by Entity
- 18. Delay Chain Summary
- 19. Pad To Core Delay Chain Fanout
- 20. Non-Global High Fan-Out Signals
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Fitter Summary                                                                  ;
-+------------------------------------+--------------------------------------------+
-; Fitter Status                      ; Successful - Thu Oct 17 23:24:50 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; BCD_to_decimal_decoder                     ;
-; Top-level Entity Name              ; BCD_to_decimal_decoder                     ;
-; Family                             ; Cyclone III                                ;
-; Device                             ; EP3C16F484C6                               ;
-; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 10 / 15,408 ( < 1 % )                      ;
-;     Total combinational functions  ; 10 / 15,408 ( < 1 % )                      ;
-;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 14 / 347 ( 4 % )                           ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
-; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
-; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
-+------------------------------------+--------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                                            ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option                                                                     ; Setting                               ; Default Value                         ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device                                                                     ; EP3C16F484C6                          ;                                       ;
-; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
-; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
-; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
-; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
-; Use smart compilation                                                      ; Off                                   ; Off                                   ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
-; Enable compact report table                                                ; Off                                   ; Off                                   ;
-; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
-; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
-; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
-; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
-; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
-; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
-; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
-; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
-; SSN Optimization                                                           ; Off                                   ; Off                                   ;
-; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
-; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
-; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
-; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
-; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
-; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
-; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
-; PCI I/O                                                                    ; Off                                   ; Off                                   ;
-; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
-; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
-; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
-; Auto Delay Chains                                                          ; On                                    ; On                                    ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
-; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
-; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
-; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
-; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
-; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
-; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
-; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
-; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
-; Auto Global Clock                                                          ; On                                    ; On                                    ;
-; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
-; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
-; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
-; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
-; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
-; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+------------------------------------------+
-; I/O Assignment Warnings                  ;
-+----------+-------------------------------+
-; Pin Name ; Reason                        ;
-+----------+-------------------------------+
-; Y0       ; Incomplete set of assignments ;
-; Y1       ; Incomplete set of assignments ;
-; Y2       ; Incomplete set of assignments ;
-; Y3       ; Incomplete set of assignments ;
-; Y4       ; Incomplete set of assignments ;
-; Y5       ; Incomplete set of assignments ;
-; Y6       ; Incomplete set of assignments ;
-; Y7       ; Incomplete set of assignments ;
-; Y8       ; Incomplete set of assignments ;
-; Y9       ; Incomplete set of assignments ;
-; A        ; Incomplete set of assignments ;
-; D        ; Incomplete set of assignments ;
-; B        ; Incomplete set of assignments ;
-; C        ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary                                                    ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ;                   ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 49 ) ; 0.00 % ( 0 / 49 )          ; 0.00 % ( 0 / 49 )        ;
-;     -- Achieved     ; 0.00 % ( 0 / 49 ) ; 0.00 % ( 0 / 49 )          ; 0.00 % ( 0 / 49 )        ;
-;                     ;                   ;                            ;                          ;
-; Routing (by net)    ;                   ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings                                                                                                                                             ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation                                                                                     ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 39 )     ; N/A                     ; Source File       ; N/A                 ;       ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/BCD_to_decimal_decoder.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                       ;
-+---------------------------------------------+-----------------------+
-; Resource                                    ; Usage                 ;
-+---------------------------------------------+-----------------------+
-; Total logic elements                        ; 10 / 15,408 ( < 1 % ) ;
-;     -- Combinational with no register       ; 10                    ;
-;     -- Register only                        ; 0                     ;
-;     -- Combinational with a register        ; 0                     ;
-;                                             ;                       ;
-; Logic element usage by number of LUT inputs ;                       ;
-;     -- 4 input functions                    ; 10                    ;
-;     -- 3 input functions                    ; 0                     ;
-;     -- <=2 input functions                  ; 0                     ;
-;     -- Register only                        ; 0                     ;
-;                                             ;                       ;
-; Logic elements by mode                      ;                       ;
-;     -- normal mode                          ; 10                    ;
-;     -- arithmetic mode                      ; 0                     ;
-;                                             ;                       ;
-; Total registers*                            ; 0 / 17,068 ( 0 % )    ;
-;     -- Dedicated logic registers            ; 0 / 15,408 ( 0 % )    ;
-;     -- I/O registers                        ; 0 / 1,660 ( 0 % )     ;
-;                                             ;                       ;
-; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )     ;
-; Virtual pins                                ; 0                     ;
-; I/O pins                                    ; 14 / 347 ( 4 % )      ;
-;     -- Clock pins                           ; 0 / 8 ( 0 % )         ;
-;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )         ;
-;                                             ;                       ;
-; Global signals                              ; 0                     ;
-; M9Ks                                        ; 0 / 56 ( 0 % )        ;
-; Total block memory bits                     ; 0 / 516,096 ( 0 % )   ;
-; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )   ;
-; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ;
-; PLLs                                        ; 0 / 4 ( 0 % )         ;
-; Global clocks                               ; 0 / 20 ( 0 % )        ;
-; JTAGs                                       ; 0 / 1 ( 0 % )         ;
-; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
-; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
-; Impedance control blocks                    ; 0 / 4 ( 0 % )         ;
-; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
-; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%          ;
-; Maximum fan-out                             ; 10                    ;
-; Highest non-global fan-out                  ; 10                    ;
-; Total fan-out                               ; 69                    ;
-; Average fan-out                             ; 1.44                  ;
-+---------------------------------------------+-----------------------+
-*  Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics                                                                         ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region                ; Low                  ; Low                            ;
-;                                             ;                      ;                                ;
-; Total logic elements                        ; 10 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
-;     -- Combinational with no register       ; 10                   ; 0                              ;
-;     -- Register only                        ; 0                    ; 0                              ;
-;     -- Combinational with a register        ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Logic element usage by number of LUT inputs ;                      ;                                ;
-;     -- 4 input functions                    ; 10                   ; 0                              ;
-;     -- 3 input functions                    ; 0                    ; 0                              ;
-;     -- <=2 input functions                  ; 0                    ; 0                              ;
-;     -- Register only                        ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Logic elements by mode                      ;                      ;                                ;
-;     -- normal mode                          ; 10                   ; 0                              ;
-;     -- arithmetic mode                      ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Total registers                             ; 0                    ; 0                              ;
-;     -- Dedicated logic registers            ; 0 / 15408 ( 0 % )    ; 0 / 15408 ( 0 % )              ;
-;     -- I/O registers                        ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )    ; 0 / 963 ( 0 % )                ;
-;                                             ;                      ;                                ;
-; Virtual pins                                ; 0                    ; 0                              ;
-; I/O pins                                    ; 14                   ; 0                              ;
-; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ; 0 / 112 ( 0 % )                ;
-; Total memory bits                           ; 0                    ; 0                              ;
-; Total RAM block bits                        ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Connections                                 ;                      ;                                ;
-;     -- Input Connections                    ; 0                    ; 0                              ;
-;     -- Registered Input Connections         ; 0                    ; 0                              ;
-;     -- Output Connections                   ; 0                    ; 0                              ;
-;     -- Registered Output Connections        ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Internal Connections                        ;                      ;                                ;
-;     -- Total Connections                    ; 64                   ; 5                              ;
-;     -- Registered Connections               ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; External Connections                        ;                      ;                                ;
-;     -- Top                                  ; 0                    ; 0                              ;
-;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Partition Interface                         ;                      ;                                ;
-;     -- Input Ports                          ; 4                    ; 0                              ;
-;     -- Output Ports                         ; 10                   ; 0                              ;
-;     -- Bidir Ports                          ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Registered Ports                            ;                      ;                                ;
-;     -- Registered Input Ports               ; 0                    ; 0                              ;
-;     -- Registered Output Ports              ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Port Connectivity                           ;                      ;                                ;
-;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
-;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
-;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
-;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
-;     -- Input Ports with no Source           ; 0                    ; 0                              ;
-;     -- Output Ports with no Source          ; 0                    ; 0                              ;
-;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
-;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                                                                ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; A    ; Y1    ; 2        ; 0            ; 6            ; 7            ; 10                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
-; B    ; T8    ; 3        ; 1            ; 0            ; 21           ; 10                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
-; C    ; T4    ; 2        ; 0            ; 4            ; 21           ; 10                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
-; D    ; N5    ; 2        ; 0            ; 10           ; 14           ; 10                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Y0   ; N8    ; 2        ; 0            ; 7            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y1   ; U1    ; 2        ; 0            ; 9            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y2   ; M3    ; 2        ; 0            ; 12           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y3   ; V6    ; 3        ; 1            ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y4   ; R10   ; 3        ; 1            ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y5   ; P5    ; 2        ; 0            ; 8            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y6   ; P3    ; 2        ; 0            ; 9            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y7   ; V3    ; 2        ; 0            ; 4            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y8   ; T9    ; 3        ; 1            ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y9   ; T3    ; 2        ; 0            ; 6            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins                                                                                         ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
-; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
-; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
-; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
-; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
-; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
-; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
-; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
-; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage                                             ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1        ; 4 / 33 ( 12 % )  ; 2.5V          ; --           ;
-; 2        ; 10 / 48 ( 21 % ) ; 2.5V          ; --           ;
-; 3        ; 4 / 46 ( 9 % )   ; 2.5V          ; --           ;
-; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
-; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
-; 6        ; 1 / 43 ( 2 % )   ; 2.5V          ; --           ;
-; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
-; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                                                                        ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; B1       ; 2          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; B2       ; 1          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C1       ; 7          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C2       ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; D2       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E1       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; E3       ; 5          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E4       ; 4          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G4       ; 17         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G5       ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; G21      ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H1       ; 26         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H6       ; 11         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H7       ; 10         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J1       ; 29         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J2       ; 28         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J3       ; 27         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J6       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J7       ; 22         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
-; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M3       ; 47         ; 2        ; Y2                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; N5       ; 56         ; 2        ; D                                                         ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N8       ; 67         ; 2        ; Y0                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P3       ; 58         ; 2        ; Y6                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P5       ; 63         ; 2        ; Y5                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R10      ; 90         ; 3        ; Y4                                                        ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
-; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T3       ; 72         ; 2        ; Y9                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; T4       ; 81         ; 2        ; C                                                         ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T8       ; 89         ; 3        ; B                                                         ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
-; T9       ; 91         ; 3        ; Y8                                                        ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
-; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; U1       ; 60         ; 2        ; Y1                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V3       ; 78         ; 2        ; Y7                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V6       ; 92         ; 3        ; Y3                                                        ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
-; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y1       ; 71         ; 2        ; A                                                         ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                               ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name     ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+--------------+
-; |BCD_to_decimal_decoder    ; 10 (10)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 14   ; 0            ; 10 (10)      ; 0 (0)             ; 0 (0)            ; |BCD_to_decimal_decoder ; work         ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+--------------------------------------------------------------------------------------+
-; Delay Chain Summary                                                                  ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-; Y0   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y1   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y2   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y3   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y4   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y5   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y6   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y7   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y8   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y9   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; A    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; D    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; B    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; C    ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+---------------------------------------------------+
-; Pad To Core Delay Chain Fanout                    ;
-+---------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------+-------------------+---------+
-; A                   ;                   ;         ;
-;      - inst         ; 0                 ; 6       ;
-;      - inst1        ; 0                 ; 6       ;
-;      - inst2        ; 0                 ; 6       ;
-;      - inst3        ; 0                 ; 6       ;
-;      - inst4        ; 0                 ; 6       ;
-;      - inst5        ; 0                 ; 6       ;
-;      - inst6        ; 0                 ; 6       ;
-;      - inst7        ; 0                 ; 6       ;
-;      - inst8        ; 0                 ; 6       ;
-;      - inst9        ; 0                 ; 6       ;
-; D                   ;                   ;         ;
-;      - inst         ; 0                 ; 6       ;
-;      - inst1        ; 0                 ; 6       ;
-;      - inst2        ; 0                 ; 6       ;
-;      - inst3        ; 0                 ; 6       ;
-;      - inst4        ; 0                 ; 6       ;
-;      - inst5        ; 0                 ; 6       ;
-;      - inst6        ; 0                 ; 6       ;
-;      - inst7        ; 0                 ; 6       ;
-;      - inst8        ; 0                 ; 6       ;
-;      - inst9        ; 0                 ; 6       ;
-; B                   ;                   ;         ;
-;      - inst         ; 0                 ; 6       ;
-;      - inst1        ; 0                 ; 6       ;
-;      - inst2        ; 0                 ; 6       ;
-;      - inst3        ; 0                 ; 6       ;
-;      - inst4        ; 0                 ; 6       ;
-;      - inst5        ; 0                 ; 6       ;
-;      - inst6        ; 0                 ; 6       ;
-;      - inst7        ; 0                 ; 6       ;
-;      - inst8        ; 0                 ; 6       ;
-;      - inst9        ; 0                 ; 6       ;
-; C                   ;                   ;         ;
-;      - inst         ; 1                 ; 6       ;
-;      - inst1        ; 1                 ; 6       ;
-;      - inst2        ; 1                 ; 6       ;
-;      - inst3        ; 1                 ; 6       ;
-;      - inst4        ; 1                 ; 6       ;
-;      - inst5        ; 1                 ; 6       ;
-;      - inst6        ; 1                 ; 6       ;
-;      - inst7        ; 1                 ; 6       ;
-;      - inst8        ; 1                 ; 6       ;
-;      - inst9        ; 1                 ; 6       ;
-+---------------------+-------------------+---------+
-
-
-+---------------------------------+
-; Non-Global High Fan-Out Signals ;
-+---------+-----------------------+
-; Name    ; Fan-Out               ;
-+---------+-----------------------+
-; C~input ; 10                    ;
-; B~input ; 10                    ;
-; D~input ; 10                    ;
-; A~input ; 10                    ;
-; inst9   ; 1                     ;
-; inst8   ; 1                     ;
-; inst7   ; 1                     ;
-; inst6   ; 1                     ;
-; inst5   ; 1                     ;
-; inst4   ; 1                     ;
-; inst3   ; 1                     ;
-; inst2   ; 1                     ;
-; inst1   ; 1                     ;
-; inst    ; 1                     ;
-+---------+-----------------------+
-
-
-+-----------------------------------------------+
-; Routing Usage Summary                         ;
-+-----------------------+-----------------------+
-; Routing Resource Type ; Usage                 ;
-+-----------------------+-----------------------+
-; Block interconnects   ; 14 / 47,787 ( < 1 % ) ;
-; C16 interconnects     ; 0 / 1,804 ( 0 % )     ;
-; C4 interconnects      ; 16 / 31,272 ( < 1 % ) ;
-; Direct links          ; 1 / 47,787 ( < 1 % )  ;
-; Global clocks         ; 0 / 20 ( 0 % )        ;
-; Local interconnects   ; 0 / 15,408 ( 0 % )    ;
-; R24 interconnects     ; 0 / 1,775 ( 0 % )     ;
-; R4 interconnects      ; 0 / 41,310 ( 0 % )    ;
-+-----------------------+-----------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements                                                        ;
-+---------------------------------------------+-----------------------------+
-; Number of Logic Elements  (Average = 10.00) ; Number of LABs  (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 1                                           ; 0                           ;
-; 2                                           ; 0                           ;
-; 3                                           ; 0                           ;
-; 4                                           ; 0                           ;
-; 5                                           ; 0                           ;
-; 6                                           ; 0                           ;
-; 7                                           ; 0                           ;
-; 8                                           ; 0                           ;
-; 9                                           ; 0                           ;
-; 10                                          ; 1                           ;
-; 11                                          ; 0                           ;
-; 12                                          ; 0                           ;
-; 13                                          ; 0                           ;
-; 14                                          ; 0                           ;
-; 15                                          ; 0                           ;
-; 16                                          ; 0                           ;
-+---------------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced                                                        ;
-+----------------------------------------------+-----------------------------+
-; Number of Signals Sourced  (Average = 10.00) ; Number of LABs  (Total = 1) ;
-+----------------------------------------------+-----------------------------+
-; 0                                            ; 0                           ;
-; 1                                            ; 0                           ;
-; 2                                            ; 0                           ;
-; 3                                            ; 0                           ;
-; 4                                            ; 0                           ;
-; 5                                            ; 0                           ;
-; 6                                            ; 0                           ;
-; 7                                            ; 0                           ;
-; 8                                            ; 0                           ;
-; 9                                            ; 0                           ;
-; 10                                           ; 1                           ;
-+----------------------------------------------+-----------------------------+
-
-
-+--------------------------------------------------------------------------------+
-; LAB Signals Sourced Out                                                        ;
-+--------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out  (Average = 10.00) ; Number of LABs  (Total = 1) ;
-+--------------------------------------------------+-----------------------------+
-; 0                                                ; 0                           ;
-; 1                                                ; 0                           ;
-; 2                                                ; 0                           ;
-; 3                                                ; 0                           ;
-; 4                                                ; 0                           ;
-; 5                                                ; 0                           ;
-; 6                                                ; 0                           ;
-; 7                                                ; 0                           ;
-; 8                                                ; 0                           ;
-; 9                                                ; 0                           ;
-; 10                                               ; 1                           ;
-+--------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs                                                       ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs  (Average = 4.00) ; Number of LABs  (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0                                           ; 0                           ;
-; 1                                           ; 0                           ;
-; 2                                           ; 0                           ;
-; 3                                           ; 0                           ;
-; 4                                           ; 1                           ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary                        ;
-+----------------------------------+-------+
-; I/O Rules Statistic              ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules                  ; 30    ;
-; Number of I/O Rules Passed       ; 9     ;
-; Number of I/O Rules Failed       ; 0     ;
-; Number of I/O Rules Unchecked    ; 0     ;
-; Number of I/O Rules Inapplicable ; 21    ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
-; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
-; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
-; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
-; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
-; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 14        ; 0            ; 0            ; 14        ; 14        ; 0            ; 10           ; 0            ; 0            ; 4            ; 0            ; 10           ; 4            ; 0            ; 0            ; 0            ; 10           ; 0            ; 0            ; 0            ; 0            ; 0            ; 14        ; 0            ; 0            ;
-; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; Total Inapplicable ; 14           ; 14           ; 14           ; 14           ; 14           ; 0         ; 14           ; 14           ; 0         ; 0         ; 14           ; 4            ; 14           ; 14           ; 10           ; 14           ; 4            ; 10           ; 14           ; 14           ; 14           ; 4            ; 14           ; 14           ; 14           ; 14           ; 14           ; 0         ; 14           ; 14           ;
-; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; Y0                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y1                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y2                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y3                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y4                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y5                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y6                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y7                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y8                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y9                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; A                  ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; D                  ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; B                  ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; C                  ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options                                                                       ;
-+------------------------------------------------------------------+--------------------------+
-; Option                                                           ; Setting                  ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
-; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
-; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
-; Enable INIT_DONE output                                          ; Off                      ;
-; Configuration scheme                                             ; Active Serial            ;
-; Error detection CRC                                              ; Off                      ;
-; Enable open drain on CRC_ERROR pin                               ; Off                      ;
-; Enable input tri-state on active configuration pins in user mode ; Off                      ;
-; Configuration Voltage Level                                      ; Auto                     ;
-; Force Configuration Voltage Level                                ; Off                      ;
-; nCEO                                                             ; As output driving ground ;
-; Data[0]                                                          ; As input tri-stated      ;
-; Data[1]/ASDO                                                     ; As input tri-stated      ;
-; Data[7..2]                                                       ; Unreserved               ;
-; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
-; Other Active Parallel pins                                       ; Unreserved               ;
-; DCLK                                                             ; As output driving ground ;
-; Base pin-out file on sameframe device                            ; Off                      ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions  ;
-+---------------------------+--------+
-; Setting                   ; Value  ;
-+---------------------------+--------+
-; Nominal Core Voltage      ; 1.20 V ;
-; Low Junction Temperature  ; 0 °C   ;
-; High Junction Temperature ; 85 °C  ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (119006): Selected device EP3C16F484C6 for design "BCD_to_decimal_decoder"
-Info (21077): Core supply voltage is 1.2V
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
-    Info (176445): Device EP3C40F484C6 is compatible
-    Info (176445): Device EP3C55F484C6 is compatible
-    Info (176445): Device EP3C80F484C6 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
-    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
-    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
-    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
-    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
-    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (169085): No exact pin location assignment(s) for 14 pins of 14 total pins
-    Info (169086): Pin Y0 not assigned to an exact location on the device
-    Info (169086): Pin Y1 not assigned to an exact location on the device
-    Info (169086): Pin Y2 not assigned to an exact location on the device
-    Info (169086): Pin Y3 not assigned to an exact location on the device
-    Info (169086): Pin Y4 not assigned to an exact location on the device
-    Info (169086): Pin Y5 not assigned to an exact location on the device
-    Info (169086): Pin Y6 not assigned to an exact location on the device
-    Info (169086): Pin Y7 not assigned to an exact location on the device
-    Info (169086): Pin Y8 not assigned to an exact location on the device
-    Info (169086): Pin Y9 not assigned to an exact location on the device
-    Info (169086): Pin A not assigned to an exact location on the device
-    Info (169086): Pin D not assigned to an exact location on the device
-    Info (169086): Pin B not assigned to an exact location on the device
-    Info (169086): Pin C not assigned to an exact location on the device
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'BCD_to_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
-    Extra Info (176219): No registers were packed into other blocks
-Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
-    Info (176211): Number of I/O pins in group: 14 (unused VREF, 2.5V VCCIO, 4 input, 10 output, 0 bidirectional)
-        Info (176212): I/O standards used: 2.5 V.
-Info (176215): I/O bank details before I/O pin placement
-    Info (176214): Statistics of I/O banks
-        Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  29 pins available
-        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
-        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
-        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available
-        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
-        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available
-        Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available
-        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
-    Info (170200): Optimizations that may affect the design's timing were skipped
-Info (11888): Total time spent on timing analysis during the Fitter is 0.18 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
-Info (144001): Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.smsg
-Info: Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings
-    Info: Peak virtual memory: 533 megabytes
-    Info: Processing ended: Thu Oct 17 23:24:50 2019
-    Info: Elapsed time: 00:00:12
-    Info: Total CPU time (on all processors): 00:00:12
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.smsg.
-
-
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.smsg b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.smsg
deleted file mode 100644
index 7121cbb1..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.summary b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.summary
deleted file mode 100644
index f73947af..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Thu Oct 17 23:24:50 2019
-Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
-Revision Name : BCD_to_decimal_decoder
-Top-level Entity Name : BCD_to_decimal_decoder
-Family : Cyclone III
-Device : EP3C16F484C6
-Timing Models : Final
-Total logic elements : 10 / 15,408 ( < 1 % )
-    Total combinational functions : 10 / 15,408 ( < 1 % )
-    Dedicated logic registers : 0 / 15,408 ( 0 % )
-Total registers : 0
-Total pins : 14 / 347 ( 4 % )
-Total virtual pins : 0
-Total memory bits : 0 / 516,096 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.flow.rpt b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.flow.rpt
deleted file mode 100644
index fbc9b6d1..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.flow.rpt
+++ /dev/null
@@ -1,130 +0,0 @@
-Flow report for BCD_to_decimal_decoder
-Thu Oct 17 23:25:08 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Flow Summary                                                                    ;
-+------------------------------------+--------------------------------------------+
-; Flow Status                        ; Successful - Thu Oct 17 23:25:08 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; BCD_to_decimal_decoder                     ;
-; Top-level Entity Name              ; BCD_to_decimal_decoder                     ;
-; Family                             ; Cyclone III                                ;
-; Device                             ; EP3C16F484C6                               ;
-; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 10 / 15,408 ( < 1 % )                      ;
-;     Total combinational functions  ; 10 / 15,408 ( < 1 % )                      ;
-;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 14 / 347 ( 4 % )                           ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
-; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
-; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
-+------------------------------------+--------------------------------------------+
-
-
-+--------------------------------------------+
-; Flow Settings                              ;
-+-------------------+------------------------+
-; Option            ; Setting                ;
-+-------------------+------------------------+
-; Start date & time ; 10/17/2019 23:24:34    ;
-; Main task         ; Compilation            ;
-; Revision Name     ; BCD_to_decimal_decoder ;
-+-------------------+------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                                           ;
-+-------------------------------------+-------------------------------------------------------+---------------+-------------+----------------+
-; Assignment Name                     ; Value                                                 ; Default Value ; Entity Name ; Section Id     ;
-+-------------------------------------+-------------------------------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID               ; 0.157132587415700                                     ; --            ; --          ; --             ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST     ; On                                                    ; --            ; --          ; eda_simulation ;
-; EDA_NETLIST_WRITER_OUTPUT_DIR       ; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/ ; --            ; --          ; eda_simulation ;
-; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                                           ; --            ; --          ; eda_simulation ;
-; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (Verilog)                             ; <None>        ; --          ; --             ;
-; MAX_CORE_JUNCTION_TEMP              ; 85                                                    ; --            ; --          ; --             ;
-; MIN_CORE_JUNCTION_TEMP              ; 0                                                     ; --            ; --          ; --             ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                                                  ; --            ; --          ; --             ;
-; PARTITION_COLOR                     ; 16764057                                              ; --            ; --          ; Top            ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                                 ; --            ; --          ; Top            ;
-; PARTITION_NETLIST_TYPE              ; SOURCE                                                ; --            ; --          ; Top            ;
-; PROJECT_OUTPUT_DIRECTORY            ; output_files                                          ; --            ; --          ; --             ;
-+-------------------------------------+-------------------------------------------------------+---------------+-------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:03     ; 1.0                     ; 372 MB              ; 00:00:02                           ;
-; Fitter                    ; 00:00:12     ; 1.0                     ; 533 MB              ; 00:00:12                           ;
-; Assembler                 ; 00:00:02     ; 1.0                     ; 382 MB              ; 00:00:02                           ;
-; TimeQuest Timing Analyzer ; 00:00:03     ; 1.0                     ; 373 MB              ; 00:00:03                           ;
-; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 338 MB              ; 00:00:01                           ;
-; Total                     ; 00:00:21     ; --                      ; --                  ; 00:00:20                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                              ;
-+---------------------------+-------------------+----------------+------------+----------------+
-; Module Name               ; Machine Hostname  ; OS Name        ; OS Version ; Processor type ;
-+---------------------------+-------------------+----------------+------------+----------------+
-; Analysis & Synthesis      ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; Fitter                    ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; Assembler                 ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; TimeQuest Timing Analyzer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; EDA Netlist Writer        ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-+---------------------------+-------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder
-quartus_fit --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder
-quartus_asm --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder
-quartus_sta BCD_to_decimal_decoder -c BCD_to_decimal_decoder
-quartus_eda --read_settings_files=off --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder
-
-
-
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.jdi b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.jdi
deleted file mode 100644
index 9c02bf15..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="bf945583a5b98c928b26"/>
-  </project>
-  <file_info>
-    <file device="EP3C16F484C6" path="BCD_to_decimal_decoder.sof" usercode="0xFFFFFFFF"/>
-  </file_info>
-</sld_project_info>
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.map.rpt b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.map.rpt
deleted file mode 100644
index df41d1b1..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.map.rpt
+++ /dev/null
@@ -1,257 +0,0 @@
-Analysis & Synthesis report for BCD_to_decimal_decoder
-Thu Oct 17 23:24:36 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. General Register Statistics
-  9. Elapsed Time Per Partition
- 10. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                    ;
-+------------------------------------+--------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Thu Oct 17 23:24:36 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; BCD_to_decimal_decoder                     ;
-; Top-level Entity Name              ; BCD_to_decimal_decoder                     ;
-; Family                             ; Cyclone III                                ;
-; Total logic elements               ; 10                                         ;
-;     Total combinational functions  ; 10                                         ;
-;     Dedicated logic registers      ; 0                                          ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 14                                         ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0                                          ;
-; Embedded Multiplier 9-bit elements ; 0                                          ;
-; Total PLLs                         ; 0                                          ;
-+------------------------------------+--------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                                ;
-+----------------------------------------------------------------------------+------------------------+------------------------+
-; Option                                                                     ; Setting                ; Default Value          ;
-+----------------------------------------------------------------------------+------------------------+------------------------+
-; Device                                                                     ; EP3C16F484C6           ;                        ;
-; Top-level entity name                                                      ; BCD_to_decimal_decoder ; BCD_to_decimal_decoder ;
-; Family name                                                                ; Cyclone III            ; Cyclone IV GX          ;
-; Use smart compilation                                                      ; Off                    ; Off                    ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                     ; On                     ;
-; Enable compact report table                                                ; Off                    ; Off                    ;
-; Restructure Multiplexers                                                   ; Auto                   ; Auto                   ;
-; Create Debugging Nodes for IP Cores                                        ; Off                    ; Off                    ;
-; Preserve fewer node names                                                  ; On                     ; On                     ;
-; Disable OpenCore Plus hardware evaluation                                  ; Off                    ; Off                    ;
-; Verilog Version                                                            ; Verilog_2001           ; Verilog_2001           ;
-; VHDL Version                                                               ; VHDL_1993              ; VHDL_1993              ;
-; State Machine Processing                                                   ; Auto                   ; Auto                   ;
-; Safe State Machine                                                         ; Off                    ; Off                    ;
-; Extract Verilog State Machines                                             ; On                     ; On                     ;
-; Extract VHDL State Machines                                                ; On                     ; On                     ;
-; Ignore Verilog initial constructs                                          ; Off                    ; Off                    ;
-; Iteration limit for constant Verilog loops                                 ; 5000                   ; 5000                   ;
-; Iteration limit for non-constant Verilog loops                             ; 250                    ; 250                    ;
-; Add Pass-Through Logic to Inferred RAMs                                    ; On                     ; On                     ;
-; Infer RAMs from Raw Logic                                                  ; On                     ; On                     ;
-; Parallel Synthesis                                                         ; On                     ; On                     ;
-; DSP Block Balancing                                                        ; Auto                   ; Auto                   ;
-; NOT Gate Push-Back                                                         ; On                     ; On                     ;
-; Power-Up Don't Care                                                        ; On                     ; On                     ;
-; Remove Redundant Logic Cells                                               ; Off                    ; Off                    ;
-; Remove Duplicate Registers                                                 ; On                     ; On                     ;
-; Ignore CARRY Buffers                                                       ; Off                    ; Off                    ;
-; Ignore CASCADE Buffers                                                     ; Off                    ; Off                    ;
-; Ignore GLOBAL Buffers                                                      ; Off                    ; Off                    ;
-; Ignore ROW GLOBAL Buffers                                                  ; Off                    ; Off                    ;
-; Ignore LCELL Buffers                                                       ; Off                    ; Off                    ;
-; Ignore SOFT Buffers                                                        ; On                     ; On                     ;
-; Limit AHDL Integers to 32 Bits                                             ; Off                    ; Off                    ;
-; Optimization Technique                                                     ; Balanced               ; Balanced               ;
-; Carry Chain Length                                                         ; 70                     ; 70                     ;
-; Auto Carry Chains                                                          ; On                     ; On                     ;
-; Auto Open-Drain Pins                                                       ; On                     ; On                     ;
-; Perform WYSIWYG Primitive Resynthesis                                      ; Off                    ; Off                    ;
-; Auto ROM Replacement                                                       ; On                     ; On                     ;
-; Auto RAM Replacement                                                       ; On                     ; On                     ;
-; Auto DSP Block Replacement                                                 ; On                     ; On                     ;
-; Auto Shift Register Replacement                                            ; Auto                   ; Auto                   ;
-; Allow Shift Register Merging across Hierarchies                            ; Auto                   ; Auto                   ;
-; Auto Clock Enable Replacement                                              ; On                     ; On                     ;
-; Strict RAM Replacement                                                     ; Off                    ; Off                    ;
-; Allow Synchronous Control Signals                                          ; On                     ; On                     ;
-; Force Use of Synchronous Clear Signals                                     ; Off                    ; Off                    ;
-; Auto RAM Block Balancing                                                   ; On                     ; On                     ;
-; Auto RAM to Logic Cell Conversion                                          ; Off                    ; Off                    ;
-; Auto Resource Sharing                                                      ; Off                    ; Off                    ;
-; Allow Any RAM Size For Recognition                                         ; Off                    ; Off                    ;
-; Allow Any ROM Size For Recognition                                         ; Off                    ; Off                    ;
-; Allow Any Shift Register Size For Recognition                              ; Off                    ; Off                    ;
-; Use LogicLock Constraints during Resource Balancing                        ; On                     ; On                     ;
-; Ignore translate_off and synthesis_off directives                          ; Off                    ; Off                    ;
-; Timing-Driven Synthesis                                                    ; On                     ; On                     ;
-; Report Parameter Settings                                                  ; On                     ; On                     ;
-; Report Source Assignments                                                  ; On                     ; On                     ;
-; Report Connectivity Checks                                                 ; On                     ; On                     ;
-; Ignore Maximum Fan-Out Assignments                                         ; Off                    ; Off                    ;
-; Synchronization Register Chain Length                                      ; 2                      ; 2                      ;
-; PowerPlay Power Optimization                                               ; Normal compilation     ; Normal compilation     ;
-; HDL message level                                                          ; Level2                 ; Level2                 ;
-; Suppress Register Optimization Related Messages                            ; Off                    ; Off                    ;
-; Number of Removed Registers Reported in Synthesis Report                   ; 5000                   ; 5000                   ;
-; Number of Swept Nodes Reported in Synthesis Report                         ; 5000                   ; 5000                   ;
-; Number of Inverted Registers Reported in Synthesis Report                  ; 100                    ; 100                    ;
-; Clock MUX Protection                                                       ; On                     ; On                     ;
-; Auto Gated Clock Conversion                                                ; Off                    ; Off                    ;
-; Block Design Naming                                                        ; Auto                   ; Auto                   ;
-; SDC constraint protection                                                  ; Off                    ; Off                    ;
-; Synthesis Effort                                                           ; Auto                   ; Auto                   ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                     ; On                     ;
-; Pre-Mapping Resynthesis Optimization                                       ; Off                    ; Off                    ;
-; Analysis & Synthesis Message Level                                         ; Medium                 ; Medium                 ;
-; Disable Register Merging Across Hierarchies                                ; Auto                   ; Auto                   ;
-; Resource Aware Inference For Block RAM                                     ; On                     ; On                     ;
-; Synthesis Seed                                                             ; 1                      ; 1                      ;
-+----------------------------------------------------------------------------+------------------------+------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                              ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                    ; Library ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+---------+
-; BCD_to_decimal_decoder.bdf       ; yes             ; User Block Diagram/Schematic File  ; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf ;         ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+---------+
-
-
-+-------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary           ;
-+---------------------------------------------+---------+
-; Resource                                    ; Usage   ;
-+---------------------------------------------+---------+
-; Estimated Total logic elements              ; 10      ;
-;                                             ;         ;
-; Total combinational functions               ; 10      ;
-; Logic element usage by number of LUT inputs ;         ;
-;     -- 4 input functions                    ; 10      ;
-;     -- 3 input functions                    ; 0       ;
-;     -- <=2 input functions                  ; 0       ;
-;                                             ;         ;
-; Logic elements by mode                      ;         ;
-;     -- normal mode                          ; 10      ;
-;     -- arithmetic mode                      ; 0       ;
-;                                             ;         ;
-; Total registers                             ; 0       ;
-;     -- Dedicated logic registers            ; 0       ;
-;     -- I/O registers                        ; 0       ;
-;                                             ;         ;
-; I/O pins                                    ; 14      ;
-; Embedded Multiplier 9-bit elements          ; 0       ;
-; Maximum fan-out node                        ; A~input ;
-; Maximum fan-out                             ; 10      ;
-; Total fan-out                               ; 64      ;
-; Average fan-out                             ; 1.68    ;
-+---------------------------------------------+---------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                             ;
-+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+--------------+
-; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name     ; Library Name ;
-+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+--------------+
-; |BCD_to_decimal_decoder    ; 10 (10)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 14   ; 0            ; |BCD_to_decimal_decoder ; work         ;
-+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 0     ;
-; Number of registers using Synchronous Clear  ; 0     ;
-; Number of registers using Synchronous Load   ; 0     ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 0     ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition    ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top            ; 00:00:01     ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit Analysis & Synthesis
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 17 23:24:33 2019
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off BCD_to_decimal_decoder -c BCD_to_decimal_decoder
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (12021): Found 1 design units, including 1 entities, in source file BCD_to_decimal_decoder.bdf
-    Info (12023): Found entity 1: BCD_to_decimal_decoder
-Info (12127): Elaborating entity "BCD_to_decimal_decoder" for the top level hierarchy
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
-    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 24 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 4 input pins
-    Info (21059): Implemented 10 output pins
-    Info (21061): Implemented 10 logic cells
-Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 383 megabytes
-    Info: Processing ended: Thu Oct 17 23:24:36 2019
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.map.summary b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.map.summary
deleted file mode 100644
index 8eae5858..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Thu Oct 17 23:24:36 2019
-Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
-Revision Name : BCD_to_decimal_decoder
-Top-level Entity Name : BCD_to_decimal_decoder
-Family : Cyclone III
-Total logic elements : 10
-    Total combinational functions : 10
-    Dedicated logic registers : 0
-Total registers : 0
-Total pins : 14
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.pin b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.pin
deleted file mode 100644
index b67e2161..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.pin
+++ /dev/null
@@ -1,554 +0,0 @@
- -- Copyright (C) 1991-2013 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Altera Program License 
- -- Subscription Agreement, Altera MegaCore Function License 
- -- Agreement, or other applicable license agreement, including, 
- -- without limitation, that your use is for the sole purpose of 
- -- programming logic devices manufactured by Altera and sold by 
- -- Altera or its authorized distributors.  Please refer to the 
- -- applicable agreement for further details.
- -- 
- -- This is a Quartus II output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus II input file. This file cannot be used
- -- to make Quartus II pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus II help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --					Bank 1:		2.5V
- --					Bank 2:		2.5V
- --					Bank 3:		2.5V
- --					Bank 4:		2.5V
- --					Bank 5:		2.5V
- --					Bank 6:		2.5V
- --					Bank 7:		2.5V
- --					Bank 8:		2.5V
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --					It can also be used to report unused dedicated pins. The connection
- --					on the board for unused dedicated pins depends on whether this will
- --					be used in a future design. One example is device migration. When
- --					using device migration, refer to the device pin-tables. If it is a
- --					GND pin in the pin table or if it will not be used in a future design
- --					for another purpose the it MUST be connected to GND. If it is an unused
- --					dedicated pin, then it can be connected to a valid signal on the board
- --					(low, high, or toggling) if that signal is required for a different
- --					revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --					This pin should be connected to GND. It may also be connected  to a
- --					valid signal  on the board  (low, high, or toggling)  if that signal
- --					is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --           	    or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-CHIP  "BCD_to_decimal_decoder"  ASSIGNED TO AN: EP3C16F484C6
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : A1        : gnd    :                   :         :           :                
-VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
-GND+                         : A11       :        :                   :         : 8         :                
-GND+                         : A12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
-VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
-GND                          : A22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
-VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
-GND+                         : AA11      :        :                   :         : 3         :                
-GND+                         : AA12      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
-GND                          : AB1       : gnd    :                   :         :           :                
-VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
-GND                          : AB6       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
-GND+                         : AB11      :        :                   :         : 3         :                
-GND+                         : AB12      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
-VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
-GND                          : AB22      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
-GND+                         : B11       :        :                   :         : 8         :                
-GND+                         : B12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
-GND                          : C5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
-GND                          : C9        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
-GND                          : C11       : gnd    :                   :         :           :                
-GND                          : C12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
-GND                          : C14       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
-GND                          : C16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
-GND                          : C18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 1         :                
-GND                          : D3        : gnd    :                   :         :           :                
-VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
-VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
-GND                          : D7        : gnd    :                   :         :           :                
-GND                          : D8        : gnd    :                   :         :           :                
-VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
-VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
-VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
-VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
-VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
-VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 1         :                
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
-VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
-VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
-GNDA2                        : E18       : gnd    :                   :         :           :                
-VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
-GND                          : E20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2        :        :                   :         : 1         :                
-GND                          : F3        : gnd    :                   :         :           :                
-VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
-GNDA3                        : F5        : gnd    :                   :         :           :                
-VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
-VCCA2                        : F18       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
-GND+                         : G1        :        :                   :         : 1         :                
-GND+                         : G2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
-VCCA3                        : G6        : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
-VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
-GND                          : G20       : gnd    :                   :         :           :                
-GND+                         : G21       :        :                   :         : 6         :                
-GND+                         : G22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
-GND                          : H3        : gnd    :                   :         :           :                
-VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 1         :                
-GND                          : H8        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
-GND                          : J5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 1         :                
-VCCINT                       : J8        : power  :                   : 1.2V    :           :                
-GND                          : J9        : gnd    :                   :         :           :                
-VCCINT                       : J10       : power  :                   : 1.2V    :           :                
-VCCINT                       : J11       : power  :                   : 1.2V    :           :                
-VCCINT                       : J12       : power  :                   : 1.2V    :           :                
-VCCINT                       : J13       : power  :                   : 1.2V    :           :                
-VCCINT                       : J14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
-GND                          : J19       : gnd    :                   :         :           :                
-VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
-~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
-GND                          : K3        : gnd    :                   :         :           :                
-VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
-nCONFIG                      : K5        :        :                   :         : 1         :                
-nSTATUS                      : K6        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
-VCCINT                       : K9        : power  :                   : 1.2V    :           :                
-GND                          : K10       : gnd    :                   :         :           :                
-GND                          : K11       : gnd    :                   :         :           :                
-GND                          : K12       : gnd    :                   :         :           :                
-GND                          : K13       : gnd    :                   :         :           :                
-VCCINT                       : K14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
-MSEL3                        : K20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
-TMS                          : L1        : input  :                   :         : 1         :                
-TCK                          : L2        : input  :                   :         : 1         :                
-nCE                          : L3        :        :                   :         : 1         :                
-TDO                          : L4        : output :                   :         : 1         :                
-TDI                          : L5        : input  :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
-VCCINT                       : L9        : power  :                   : 1.2V    :           :                
-GND                          : L10       : gnd    :                   :         :           :                
-GND                          : L11       : gnd    :                   :         :           :                
-GND                          : L12       : gnd    :                   :         :           :                
-GND                          : L13       : gnd    :                   :         :           :                
-VCCINT                       : L14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
-MSEL2                        : L17       :        :                   :         : 6         :                
-MSEL1                        : L18       :        :                   :         : 6         :                
-VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
-GND                          : L20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
-Y2                           : M3        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
-VCCINT                       : M9        : power  :                   : 1.2V    :           :                
-GND                          : M10       : gnd    :                   :         :           :                
-GND                          : M11       : gnd    :                   :         :           :                
-GND                          : M12       : gnd    :                   :         :           :                
-GND                          : M13       : gnd    :                   :         :           :                
-VCCINT                       : M14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
-MSEL0                        : M17       :        :                   :         : 6         :                
-CONF_DONE                    : M18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
-GND                          : N3        : gnd    :                   :         :           :                
-VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
-D                            : N5        : input  : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
-Y0                           : N8        : output : 2.5 V             :         : 2         : N              
-VCCINT                       : N9        : power  :                   : 1.2V    :           :                
-GND                          : N10       : gnd    :                   :         :           :                
-GND                          : N11       : gnd    :                   :         :           :                
-GND                          : N12       : gnd    :                   :         :           :                
-GND                          : N13       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
-Y6                           : P3        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
-Y5                           : P5        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
-VCCINT                       : P9        : power  :                   : 1.2V    :           :                
-VCCINT                       : P10       : power  :                   : 1.2V    :           :                
-VCCINT                       : P11       : power  :                   : 1.2V    :           :                
-VCCINT                       : P12       : power  :                   : 1.2V    :           :                
-VCCINT                       : P13       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
-VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
-GND                          : P19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
-GND                          : R3        : gnd    :                   :         :           :                
-VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
-Y4                           : R10       : output : 2.5 V             :         : 3         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
-GND+                         : T1        :        :                   :         : 2         :                
-GND+                         : T2        :        :                   :         : 2         :                
-Y9                           : T3        : output : 2.5 V             :         : 2         : N              
-C                            : T4        : input  : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
-VCCA1                        : T6        : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
-B                            : T8        : input  : 2.5 V             :         : 3         : N              
-Y8                           : T9        : output : 2.5 V             :         : 3         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
-VCCINT                       : T13       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
-VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
-GND                          : T20       : gnd    :                   :         :           :                
-GND+                         : T21       :        :                   :         : 5         :                
-GND+                         : T22       :        :                   :         : 5         :                
-Y1                           : U1        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
-GND                          : U3        : gnd    :                   :         :           :                
-VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
-GNDA1                        : U5        : gnd    :                   :         :           :                
-VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
-VCCINT                       : U16       : power  :                   : 1.2V    :           :                
-VCCINT                       : U17       : power  :                   : 1.2V    :           :                
-VCCA4                        : U18       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
-Y7                           : V3        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
-Y3                           : V6        : output : 2.5 V             :         : 3         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
-VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
-GNDA4                        : V18       : gnd    :                   :         :           :                
-VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
-GND                          : V20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
-GND                          : W3        : gnd    :                   :         :           :                
-VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
-VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
-VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
-VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
-VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
-VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
-VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
-A                            : Y1        : input  : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
-GND                          : Y5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
-GND                          : Y9        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
-GND                          : Y11       : gnd    :                   :         :           :                
-GND                          : Y12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
-VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
-GND                          : Y15       : gnd    :                   :         :           :                
-GND                          : Y16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
-GND                          : Y18       : gnd    :                   :         :           :                
-VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
-GND                          : Y20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.sof b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.sof
deleted file mode 100644
index 9ebb340208d512f210aef56a929bb6c4005ee2b7..0000000000000000000000000000000000000000
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diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.sta.rpt b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.sta.rpt
deleted file mode 100644
index 0f7e2775..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.sta.rpt
+++ /dev/null
@@ -1,790 +0,0 @@
-TimeQuest Timing Analyzer report for BCD_to_decimal_decoder
-Thu Oct 17 23:25:03 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. Clocks
-  5. Slow 1200mV 85C Model Fmax Summary
-  6. Timing Closure Recommendations
-  7. Slow 1200mV 85C Model Setup Summary
-  8. Slow 1200mV 85C Model Hold Summary
-  9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Propagation Delay
- 13. Minimum Propagation Delay
- 14. Slow 1200mV 85C Model Metastability Report
- 15. Slow 1200mV 0C Model Fmax Summary
- 16. Slow 1200mV 0C Model Setup Summary
- 17. Slow 1200mV 0C Model Hold Summary
- 18. Slow 1200mV 0C Model Recovery Summary
- 19. Slow 1200mV 0C Model Removal Summary
- 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 21. Propagation Delay
- 22. Minimum Propagation Delay
- 23. Slow 1200mV 0C Model Metastability Report
- 24. Fast 1200mV 0C Model Setup Summary
- 25. Fast 1200mV 0C Model Hold Summary
- 26. Fast 1200mV 0C Model Recovery Summary
- 27. Fast 1200mV 0C Model Removal Summary
- 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 29. Propagation Delay
- 30. Minimum Propagation Delay
- 31. Fast 1200mV 0C Model Metastability Report
- 32. Multicorner Timing Analysis Summary
- 33. Propagation Delay
- 34. Minimum Propagation Delay
- 35. Board Trace Model Assignments
- 36. Input Transition Times
- 37. Slow Corner Signal Integrity Metrics
- 38. Fast Corner Signal Integrity Metrics
- 39. Clock Transfers
- 40. Report TCCS
- 41. Report RSKM
- 42. Unconstrained Paths
- 43. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                       ;
-+--------------------+----------------------------------------------------+
-; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name      ; BCD_to_decimal_decoder                             ;
-; Device Family      ; Cyclone III                                        ;
-; Device Name        ; EP3C16F484C6                                       ;
-; Timing Models      ; Final                                              ;
-; Delay Model        ; Combined                                           ;
-; Rise/Fall Delays   ; Enabled                                            ;
-+--------------------+----------------------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ;       ; 6.660 ; 7.071 ;       ;
-; A          ; Y1          ; 6.976 ;       ;       ; 7.419 ;
-; A          ; Y2          ;       ; 6.987 ; 7.368 ;       ;
-; A          ; Y3          ; 6.441 ;       ;       ; 6.840 ;
-; A          ; Y4          ;       ; 6.443 ; 6.898 ;       ;
-; A          ; Y5          ; 6.619 ;       ;       ; 7.038 ;
-; A          ; Y6          ;       ; 6.960 ; 7.363 ;       ;
-; A          ; Y7          ; 6.309 ;       ;       ; 6.706 ;
-; A          ; Y8          ;       ; 6.412 ; 6.865 ;       ;
-; A          ; Y9          ; 7.888 ;       ;       ; 8.430 ;
-; B          ; Y0          ;       ; 6.481 ; 6.905 ;       ;
-; B          ; Y1          ;       ; 6.797 ; 7.220 ;       ;
-; B          ; Y2          ; 6.774 ;       ;       ; 7.223 ;
-; B          ; Y3          ; 6.261 ;       ;       ; 6.641 ;
-; B          ; Y4          ;       ; 6.270 ; 6.733 ;       ;
-; B          ; Y5          ;       ; 6.421 ; 6.866 ;       ;
-; B          ; Y6          ; 6.771 ;       ;       ; 7.197 ;
-; B          ; Y7          ; 6.129 ;       ;       ; 6.506 ;
-; B          ; Y8          ;       ; 6.236 ; 6.700 ;       ;
-; B          ; Y9          ;       ; 7.810 ; 8.128 ;       ;
-; C          ; Y0          ;       ; 6.518 ; 6.939 ;       ;
-; C          ; Y1          ;       ; 6.801 ; 7.244 ;       ;
-; C          ; Y2          ;       ; 6.779 ; 7.189 ;       ;
-; C          ; Y3          ;       ; 6.200 ; 6.677 ;       ;
-; C          ; Y4          ; 6.323 ;       ;       ; 6.744 ;
-; C          ; Y5          ; 6.444 ;       ;       ; 6.865 ;
-; C          ; Y6          ; 6.735 ;       ;       ; 7.180 ;
-; C          ; Y7          ; 6.090 ;       ;       ; 6.490 ;
-; C          ; Y8          ;       ; 6.287 ; 6.761 ;       ;
-; C          ; Y9          ;       ; 7.849 ; 8.169 ;       ;
-; D          ; Y0          ;       ; 7.073 ; 7.495 ;       ;
-; D          ; Y1          ;       ; 7.371 ; 7.792 ;       ;
-; D          ; Y2          ;       ; 7.340 ; 7.737 ;       ;
-; D          ; Y3          ;       ; 6.741 ; 7.211 ;       ;
-; D          ; Y4          ;       ; 6.868 ; 7.347 ;       ;
-; D          ; Y5          ;       ; 7.005 ; 7.451 ;       ;
-; D          ; Y6          ;       ; 7.327 ; 7.774 ;       ;
-; D          ; Y7          ;       ; 6.639 ; 7.121 ;       ;
-; D          ; Y8          ; 6.830 ;       ;       ; 7.252 ;
-; D          ; Y9          ; 8.260 ;       ;       ; 8.802 ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ;       ; 6.509 ; 6.908 ;       ;
-; A          ; Y1          ; 6.812 ;       ;       ; 7.242 ;
-; A          ; Y2          ;       ; 6.822 ; 7.193 ;       ;
-; A          ; Y3          ; 6.291 ;       ;       ; 6.677 ;
-; A          ; Y4          ;       ; 6.292 ; 6.736 ;       ;
-; A          ; Y5          ; 6.465 ;       ;       ; 6.871 ;
-; A          ; Y6          ;       ; 6.796 ; 7.188 ;       ;
-; A          ; Y7          ; 6.169 ;       ;       ; 6.552 ;
-; A          ; Y8          ;       ; 6.261 ; 6.703 ;       ;
-; A          ; Y9          ; 7.735 ;       ;       ; 8.264 ;
-; B          ; Y0          ;       ; 6.330 ; 6.744 ;       ;
-; B          ; Y1          ;       ; 6.633 ; 7.047 ;       ;
-; B          ; Y2          ; 6.611 ;       ;       ; 7.049 ;
-; B          ; Y3          ; 6.112 ;       ;       ; 6.481 ;
-; B          ; Y4          ;       ; 6.120 ; 6.574 ;       ;
-; B          ; Y5          ;       ; 6.268 ; 6.703 ;       ;
-; B          ; Y6          ; 6.609 ;       ;       ; 7.024 ;
-; B          ; Y7          ; 5.989 ;       ;       ; 6.355 ;
-; B          ; Y8          ;       ; 6.085 ; 6.541 ;       ;
-; B          ; Y9          ;       ; 7.657 ; 7.967 ;       ;
-; C          ; Y0          ;       ; 6.371 ; 6.780 ;       ;
-; C          ; Y1          ;       ; 6.641 ; 7.072 ;       ;
-; C          ; Y2          ;       ; 6.619 ; 7.020 ;       ;
-; C          ; Y3          ;       ; 6.057 ; 6.523 ;       ;
-; C          ; Y4          ; 6.177 ;       ;       ; 6.585 ;
-; C          ; Y5          ; 6.295 ;       ;       ; 6.704 ;
-; C          ; Y6          ; 6.579 ;       ;       ; 7.010 ;
-; C          ; Y7          ; 5.956 ;       ;       ; 6.343 ;
-; C          ; Y8          ;       ; 6.139 ; 6.601 ;       ;
-; C          ; Y9          ;       ; 7.701 ; 8.008 ;       ;
-; D          ; Y0          ;       ; 6.903 ; 7.312 ;       ;
-; D          ; Y1          ;       ; 7.188 ; 7.598 ;       ;
-; D          ; Y2          ;       ; 7.158 ; 7.546 ;       ;
-; D          ; Y3          ;       ; 6.574 ; 7.034 ;       ;
-; D          ; Y4          ;       ; 6.698 ; 7.165 ;       ;
-; D          ; Y5          ;       ; 6.832 ; 7.268 ;       ;
-; D          ; Y6          ;       ; 7.146 ; 7.581 ;       ;
-; D          ; Y7          ;       ; 6.481 ; 6.951 ;       ;
-; D          ; Y8          ; 6.663 ;       ;       ; 7.070 ;
-; D          ; Y9          ; 8.090 ;       ;       ; 8.619 ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-----------------------------------------------
-; Slow 1200mV 85C Model Metastability Report ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ;       ; 6.160 ; 6.546 ;       ;
-; A          ; Y1          ; 6.479 ;       ;       ; 6.847 ;
-; A          ; Y2          ;       ; 6.451 ; 6.817 ;       ;
-; A          ; Y3          ; 5.971 ;       ;       ; 6.293 ;
-; A          ; Y4          ;       ; 5.955 ; 6.378 ;       ;
-; A          ; Y5          ; 6.140 ;       ;       ; 6.478 ;
-; A          ; Y6          ;       ; 6.421 ; 6.808 ;       ;
-; A          ; Y7          ; 5.860 ;       ;       ; 6.186 ;
-; A          ; Y8          ;       ; 5.917 ; 6.343 ;       ;
-; A          ; Y9          ; 7.410 ;       ;       ; 7.890 ;
-; B          ; Y0          ;       ; 5.996 ; 6.385 ;       ;
-; B          ; Y1          ;       ; 6.293 ; 6.675 ;       ;
-; B          ; Y2          ; 6.289 ;       ;       ; 6.641 ;
-; B          ; Y3          ; 5.807 ;       ;       ; 6.101 ;
-; B          ; Y4          ;       ; 5.793 ; 6.219 ;       ;
-; B          ; Y5          ;       ; 5.930 ; 6.341 ;       ;
-; B          ; Y6          ; 6.285 ;       ;       ; 6.611 ;
-; B          ; Y7          ; 5.693 ;       ;       ; 5.996 ;
-; B          ; Y8          ;       ; 5.757 ; 6.183 ;       ;
-; B          ; Y9          ;       ; 7.341 ; 7.603 ;       ;
-; C          ; Y0          ;       ; 6.027 ; 6.421 ;       ;
-; C          ; Y1          ;       ; 6.301 ; 6.698 ;       ;
-; C          ; Y2          ;       ; 6.259 ; 6.644 ;       ;
-; C          ; Y3          ;       ; 5.726 ; 6.170 ;       ;
-; C          ; Y4          ; 5.866 ;       ;       ; 6.205 ;
-; C          ; Y5          ; 5.981 ;       ;       ; 6.318 ;
-; C          ; Y6          ; 6.250 ;       ;       ; 6.603 ;
-; C          ; Y7          ; 5.657 ;       ;       ; 5.979 ;
-; C          ; Y8          ;       ; 5.800 ; 6.246 ;       ;
-; C          ; Y9          ;       ; 7.374 ; 7.649 ;       ;
-; D          ; Y0          ;       ; 6.517 ; 6.913 ;       ;
-; D          ; Y1          ;       ; 6.804 ; 7.190 ;       ;
-; D          ; Y2          ;       ; 6.754 ; 7.135 ;       ;
-; D          ; Y3          ;       ; 6.202 ; 6.642 ;       ;
-; D          ; Y4          ;       ; 6.318 ; 6.767 ;       ;
-; D          ; Y5          ;       ; 6.445 ; 6.867 ;       ;
-; D          ; Y6          ;       ; 6.734 ; 7.165 ;       ;
-; D          ; Y7          ;       ; 6.123 ; 6.571 ;       ;
-; D          ; Y8          ; 6.310 ;       ;       ; 6.651 ;
-; D          ; Y9          ; 7.731 ;       ;       ; 8.216 ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ;       ; 6.031 ; 6.407 ;       ;
-; A          ; Y1          ; 6.338 ;       ;       ; 6.695 ;
-; A          ; Y2          ;       ; 6.309 ; 6.666 ;       ;
-; A          ; Y3          ; 5.844 ;       ;       ; 6.155 ;
-; A          ; Y4          ;       ; 5.825 ; 6.239 ;       ;
-; A          ; Y5          ; 6.009 ;       ;       ; 6.336 ;
-; A          ; Y6          ;       ; 6.281 ; 6.660 ;       ;
-; A          ; Y7          ; 5.740 ;       ;       ; 6.057 ;
-; A          ; Y8          ;       ; 5.790 ; 6.205 ;       ;
-; A          ; Y9          ; 7.279 ;       ;       ; 7.749 ;
-; B          ; Y0          ;       ; 5.868 ; 6.247 ;       ;
-; B          ; Y1          ;       ; 6.152 ; 6.526 ;       ;
-; B          ; Y2          ; 6.148 ;       ;       ; 6.493 ;
-; B          ; Y3          ; 5.680 ;       ;       ; 5.967 ;
-; B          ; Y4          ;       ; 5.664 ; 6.082 ;       ;
-; B          ; Y5          ;       ; 5.799 ; 6.201 ;       ;
-; B          ; Y6          ; 6.146 ;       ;       ; 6.466 ;
-; B          ; Y7          ; 5.574 ;       ;       ; 5.871 ;
-; B          ; Y8          ;       ; 5.630 ; 6.046 ;       ;
-; B          ; Y9          ;       ; 7.211 ; 7.465 ;       ;
-; C          ; Y0          ;       ; 5.903 ; 6.284 ;       ;
-; C          ; Y1          ;       ; 6.163 ; 6.552 ;       ;
-; C          ; Y2          ;       ; 6.123 ; 6.498 ;       ;
-; C          ; Y3          ;       ; 5.604 ; 6.038 ;       ;
-; C          ; Y4          ; 5.742 ;       ;       ; 6.068 ;
-; C          ; Y5          ; 5.853 ;       ;       ; 6.181 ;
-; C          ; Y6          ; 6.116 ;       ;       ; 6.459 ;
-; C          ; Y7          ; 5.543 ;       ;       ; 5.856 ;
-; C          ; Y8          ;       ; 5.676 ; 6.110 ;       ;
-; C          ; Y9          ;       ; 7.247 ; 7.511 ;       ;
-; D          ; Y0          ;       ; 6.373 ; 6.756 ;       ;
-; D          ; Y1          ;       ; 6.646 ; 7.024 ;       ;
-; D          ; Y2          ;       ; 6.598 ; 6.969 ;       ;
-; D          ; Y3          ;       ; 6.061 ; 6.491 ;       ;
-; D          ; Y4          ;       ; 6.172 ; 6.611 ;       ;
-; D          ; Y5          ;       ; 6.298 ; 6.709 ;       ;
-; D          ; Y6          ;       ; 6.580 ; 6.999 ;       ;
-; D          ; Y7          ;       ; 5.991 ; 6.426 ;       ;
-; D          ; Y8          ; 6.166 ;       ;       ; 6.497 ;
-; D          ; Y9          ; 7.584 ;       ;       ; 8.060 ;
-+------------+-------------+-------+-------+-------+-------+
-
-
----------------------------------------------
-; Slow 1200mV 0C Model Metastability Report ;
----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ;       ; 4.030 ; 4.577 ;       ;
-; A          ; Y1          ; 4.208 ;       ;       ; 4.826 ;
-; A          ; Y2          ;       ; 4.227 ; 4.745 ;       ;
-; A          ; Y3          ; 3.806 ;       ;       ; 4.411 ;
-; A          ; Y4          ;       ; 3.865 ; 4.402 ;       ;
-; A          ; Y5          ; 3.923 ;       ;       ; 4.561 ;
-; A          ; Y6          ;       ; 4.220 ; 4.731 ;       ;
-; A          ; Y7          ; 3.739 ;       ;       ; 4.352 ;
-; A          ; Y8          ;       ; 3.843 ; 4.382 ;       ;
-; A          ; Y9          ; 4.830 ;       ;       ; 5.583 ;
-; B          ; Y0          ;       ; 3.907 ; 4.465 ;       ;
-; B          ; Y1          ;       ; 4.123 ; 4.660 ;       ;
-; B          ; Y2          ; 4.060 ;       ;       ; 4.679 ;
-; B          ; Y3          ; 3.682 ;       ;       ; 4.283 ;
-; B          ; Y4          ;       ; 3.745 ; 4.296 ;       ;
-; B          ; Y5          ;       ; 3.860 ; 4.381 ;       ;
-; B          ; Y6          ; 4.044 ;       ;       ; 4.669 ;
-; B          ; Y7          ; 3.611 ;       ;       ; 4.225 ;
-; B          ; Y8          ;       ; 3.722 ; 4.273 ;       ;
-; B          ; Y9          ;       ; 4.878 ; 5.283 ;       ;
-; C          ; Y0          ;       ; 3.914 ; 4.461 ;       ;
-; C          ; Y1          ;       ; 4.119 ; 4.647 ;       ;
-; C          ; Y2          ;       ; 4.081 ; 4.603 ;       ;
-; C          ; Y3          ;       ; 3.688 ; 4.231 ;       ;
-; C          ; Y4          ; 3.721 ;       ;       ; 4.319 ;
-; C          ; Y5          ; 3.801 ;       ;       ; 4.417 ;
-; C          ; Y6          ; 4.015 ;       ;       ; 4.629 ;
-; C          ; Y7          ; 3.585 ;       ;       ; 4.180 ;
-; C          ; Y8          ;       ; 3.745 ; 4.285 ;       ;
-; C          ; Y9          ;       ; 4.892 ; 5.285 ;       ;
-; D          ; Y0          ;       ; 4.240 ; 4.819 ;       ;
-; D          ; Y1          ;       ; 4.446 ; 5.009 ;       ;
-; D          ; Y2          ;       ; 4.406 ; 4.964 ;       ;
-; D          ; Y3          ;       ; 3.999 ; 4.574 ;       ;
-; D          ; Y4          ;       ; 4.087 ; 4.668 ;       ;
-; D          ; Y5          ;       ; 4.187 ; 4.732 ;       ;
-; D          ; Y6          ;       ; 4.409 ; 4.975 ;       ;
-; D          ; Y7          ;       ; 3.969 ; 4.541 ;       ;
-; D          ; Y8          ; 4.018 ;       ;       ; 4.645 ;
-; D          ; Y9          ; 5.026 ;       ;       ; 5.793 ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ;       ; 3.939 ; 4.482 ;       ;
-; A          ; Y1          ; 4.111 ;       ;       ; 4.721 ;
-; A          ; Y2          ;       ; 4.127 ; 4.642 ;       ;
-; A          ; Y3          ; 3.718 ;       ;       ; 4.315 ;
-; A          ; Y4          ;       ; 3.774 ; 4.308 ;       ;
-; A          ; Y5          ; 3.832 ;       ;       ; 4.463 ;
-; A          ; Y6          ;       ; 4.121 ; 4.629 ;       ;
-; A          ; Y7          ; 3.656 ;       ;       ; 4.263 ;
-; A          ; Y8          ;       ; 3.753 ; 4.287 ;       ;
-; A          ; Y9          ; 4.740 ;       ;       ; 5.486 ;
-; B          ; Y0          ;       ; 3.821 ; 4.372 ;       ;
-; B          ; Y1          ;       ; 4.028 ; 4.559 ;       ;
-; B          ; Y2          ; 3.967 ;       ;       ; 4.576 ;
-; B          ; Y3          ; 3.598 ;       ;       ; 4.190 ;
-; B          ; Y4          ;       ; 3.658 ; 4.204 ;       ;
-; B          ; Y5          ;       ; 3.773 ; 4.286 ;       ;
-; B          ; Y6          ; 3.951 ;       ;       ; 4.567 ;
-; B          ; Y7          ; 3.532 ;       ;       ; 4.138 ;
-; B          ; Y8          ;       ; 3.636 ; 4.180 ;       ;
-; B          ; Y9          ;       ; 4.791 ; 5.188 ;       ;
-; C          ; Y0          ;       ; 3.827 ; 4.369 ;       ;
-; C          ; Y1          ;       ; 4.023 ; 4.548 ;       ;
-; C          ; Y2          ;       ; 3.985 ; 4.503 ;       ;
-; C          ; Y3          ;       ; 3.602 ; 4.141 ;       ;
-; C          ; Y4          ; 3.637 ;       ;       ; 4.225 ;
-; C          ; Y5          ; 3.713 ;       ;       ; 4.323 ;
-; C          ; Y6          ; 3.924 ;       ;       ; 4.529 ;
-; C          ; Y7          ; 3.507 ;       ;       ; 4.096 ;
-; C          ; Y8          ;       ; 3.656 ; 4.192 ;       ;
-; C          ; Y9          ;       ; 4.802 ; 5.191 ;       ;
-; D          ; Y0          ;       ; 4.139 ; 4.713 ;       ;
-; D          ; Y1          ;       ; 4.338 ; 4.895 ;       ;
-; D          ; Y2          ;       ; 4.298 ; 4.850 ;       ;
-; D          ; Y3          ;       ; 3.900 ; 4.469 ;       ;
-; D          ; Y4          ;       ; 3.984 ; 4.561 ;       ;
-; D          ; Y5          ;       ; 4.084 ; 4.623 ;       ;
-; D          ; Y6          ;       ; 4.300 ; 4.862 ;       ;
-; D          ; Y7          ;       ; 3.876 ; 4.441 ;       ;
-; D          ; Y8          ; 3.919 ;       ;       ; 4.538 ;
-; D          ; Y9          ; 4.926 ;       ;       ; 5.685 ;
-+------------+-------------+-------+-------+-------+-------+
-
-
----------------------------------------------
-; Fast 1200mV 0C Model Metastability Report ;
----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary                                        ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
-; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ;       ; 6.660 ; 7.071 ;       ;
-; A          ; Y1          ; 6.976 ;       ;       ; 7.419 ;
-; A          ; Y2          ;       ; 6.987 ; 7.368 ;       ;
-; A          ; Y3          ; 6.441 ;       ;       ; 6.840 ;
-; A          ; Y4          ;       ; 6.443 ; 6.898 ;       ;
-; A          ; Y5          ; 6.619 ;       ;       ; 7.038 ;
-; A          ; Y6          ;       ; 6.960 ; 7.363 ;       ;
-; A          ; Y7          ; 6.309 ;       ;       ; 6.706 ;
-; A          ; Y8          ;       ; 6.412 ; 6.865 ;       ;
-; A          ; Y9          ; 7.888 ;       ;       ; 8.430 ;
-; B          ; Y0          ;       ; 6.481 ; 6.905 ;       ;
-; B          ; Y1          ;       ; 6.797 ; 7.220 ;       ;
-; B          ; Y2          ; 6.774 ;       ;       ; 7.223 ;
-; B          ; Y3          ; 6.261 ;       ;       ; 6.641 ;
-; B          ; Y4          ;       ; 6.270 ; 6.733 ;       ;
-; B          ; Y5          ;       ; 6.421 ; 6.866 ;       ;
-; B          ; Y6          ; 6.771 ;       ;       ; 7.197 ;
-; B          ; Y7          ; 6.129 ;       ;       ; 6.506 ;
-; B          ; Y8          ;       ; 6.236 ; 6.700 ;       ;
-; B          ; Y9          ;       ; 7.810 ; 8.128 ;       ;
-; C          ; Y0          ;       ; 6.518 ; 6.939 ;       ;
-; C          ; Y1          ;       ; 6.801 ; 7.244 ;       ;
-; C          ; Y2          ;       ; 6.779 ; 7.189 ;       ;
-; C          ; Y3          ;       ; 6.200 ; 6.677 ;       ;
-; C          ; Y4          ; 6.323 ;       ;       ; 6.744 ;
-; C          ; Y5          ; 6.444 ;       ;       ; 6.865 ;
-; C          ; Y6          ; 6.735 ;       ;       ; 7.180 ;
-; C          ; Y7          ; 6.090 ;       ;       ; 6.490 ;
-; C          ; Y8          ;       ; 6.287 ; 6.761 ;       ;
-; C          ; Y9          ;       ; 7.849 ; 8.169 ;       ;
-; D          ; Y0          ;       ; 7.073 ; 7.495 ;       ;
-; D          ; Y1          ;       ; 7.371 ; 7.792 ;       ;
-; D          ; Y2          ;       ; 7.340 ; 7.737 ;       ;
-; D          ; Y3          ;       ; 6.741 ; 7.211 ;       ;
-; D          ; Y4          ;       ; 6.868 ; 7.347 ;       ;
-; D          ; Y5          ;       ; 7.005 ; 7.451 ;       ;
-; D          ; Y6          ;       ; 7.327 ; 7.774 ;       ;
-; D          ; Y7          ;       ; 6.639 ; 7.121 ;       ;
-; D          ; Y8          ; 6.830 ;       ;       ; 7.252 ;
-; D          ; Y9          ; 8.260 ;       ;       ; 8.802 ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ;       ; 3.939 ; 4.482 ;       ;
-; A          ; Y1          ; 4.111 ;       ;       ; 4.721 ;
-; A          ; Y2          ;       ; 4.127 ; 4.642 ;       ;
-; A          ; Y3          ; 3.718 ;       ;       ; 4.315 ;
-; A          ; Y4          ;       ; 3.774 ; 4.308 ;       ;
-; A          ; Y5          ; 3.832 ;       ;       ; 4.463 ;
-; A          ; Y6          ;       ; 4.121 ; 4.629 ;       ;
-; A          ; Y7          ; 3.656 ;       ;       ; 4.263 ;
-; A          ; Y8          ;       ; 3.753 ; 4.287 ;       ;
-; A          ; Y9          ; 4.740 ;       ;       ; 5.486 ;
-; B          ; Y0          ;       ; 3.821 ; 4.372 ;       ;
-; B          ; Y1          ;       ; 4.028 ; 4.559 ;       ;
-; B          ; Y2          ; 3.967 ;       ;       ; 4.576 ;
-; B          ; Y3          ; 3.598 ;       ;       ; 4.190 ;
-; B          ; Y4          ;       ; 3.658 ; 4.204 ;       ;
-; B          ; Y5          ;       ; 3.773 ; 4.286 ;       ;
-; B          ; Y6          ; 3.951 ;       ;       ; 4.567 ;
-; B          ; Y7          ; 3.532 ;       ;       ; 4.138 ;
-; B          ; Y8          ;       ; 3.636 ; 4.180 ;       ;
-; B          ; Y9          ;       ; 4.791 ; 5.188 ;       ;
-; C          ; Y0          ;       ; 3.827 ; 4.369 ;       ;
-; C          ; Y1          ;       ; 4.023 ; 4.548 ;       ;
-; C          ; Y2          ;       ; 3.985 ; 4.503 ;       ;
-; C          ; Y3          ;       ; 3.602 ; 4.141 ;       ;
-; C          ; Y4          ; 3.637 ;       ;       ; 4.225 ;
-; C          ; Y5          ; 3.713 ;       ;       ; 4.323 ;
-; C          ; Y6          ; 3.924 ;       ;       ; 4.529 ;
-; C          ; Y7          ; 3.507 ;       ;       ; 4.096 ;
-; C          ; Y8          ;       ; 3.656 ; 4.192 ;       ;
-; C          ; Y9          ;       ; 4.802 ; 5.191 ;       ;
-; D          ; Y0          ;       ; 4.139 ; 4.713 ;       ;
-; D          ; Y1          ;       ; 4.338 ; 4.895 ;       ;
-; D          ; Y2          ;       ; 4.298 ; 4.850 ;       ;
-; D          ; Y3          ;       ; 3.900 ; 4.469 ;       ;
-; D          ; Y4          ;       ; 3.984 ; 4.561 ;       ;
-; D          ; Y5          ;       ; 4.084 ; 4.623 ;       ;
-; D          ; Y6          ;       ; 4.300 ; 4.862 ;       ;
-; D          ; Y7          ;       ; 3.876 ; 4.441 ;       ;
-; D          ; Y8          ; 3.919 ;       ;       ; 4.538 ;
-; D          ; Y9          ; 4.926 ;       ;       ; 5.685 ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Y0            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y1            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y2            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y3            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y4            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y5            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y6            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y7            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y8            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y9            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times                                                     ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; A                       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; D                       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; B                       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; C                       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Y0            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y1            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y2            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y3            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
-; Y4            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
-; Y5            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.36 V              ; -0.00946 V          ; 0.111 V                              ; 0.027 V                              ; 6.46e-10 s                  ; 6.2e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.36 V             ; -0.00946 V         ; 0.111 V                             ; 0.027 V                             ; 6.46e-10 s                 ; 6.2e-10 s                  ; Yes                       ; Yes                       ;
-; Y6            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y7            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.36 V              ; -0.00946 V          ; 0.111 V                              ; 0.027 V                              ; 6.46e-10 s                  ; 6.2e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.36 V             ; -0.00946 V         ; 0.111 V                             ; 0.027 V                             ; 6.46e-10 s                 ; 6.2e-10 s                  ; Yes                       ; Yes                       ;
-; Y8            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
-; Y9            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.33 V              ; -0.00317 V          ; 0.162 V                              ; 0.063 V                              ; 3.54e-09 s                  ; 3.41e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.33 V             ; -0.00317 V         ; 0.162 V                             ; 0.063 V                             ; 3.54e-09 s                 ; 3.41e-09 s                 ; Yes                       ; Yes                       ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Y0            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y1            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y2            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y3            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
-; Y4            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
-; Y5            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
-; Y6            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y7            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
-; Y8            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
-; Y9            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths                            ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 4     ; 4    ;
-; Unconstrained Input Port Paths  ; 40    ; 40   ;
-; Unconstrained Output Ports      ; 10    ; 10   ;
-; Unconstrained Output Port Paths ; 40    ; 40   ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 17 23:25:00 2019
-Info: Command: quartus_sta BCD_to_decimal_decoder -c BCD_to_decimal_decoder
-Info: qsta_default_script.tcl version: #1
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (21077): Core supply voltage is 1.2V
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'BCD_to_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 373 megabytes
-    Info: Processing ended: Thu Oct 17 23:25:03 2019
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.sta.summary b/CH6/CH6-1/output_files/BCD_to_decimal_decoder.sta.summary
deleted file mode 100644
index 33f74363..00000000
--- a/CH6/CH6-1/output_files/BCD_to_decimal_decoder.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/CH6/CH6-1/output_files/Chain1.cdf b/CH6/CH6-1/output_files/Chain1.cdf
deleted file mode 100644
index 75a34fa7..00000000
--- a/CH6/CH6-1/output_files/Chain1.cdf
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition */
-JedecChain;
-	FileRevision(JESD32A);
-	DefaultMfr(6E);
-
-	P ActionCode(Cfg)
-		Device PartName(EP3C16F484) Path("/home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/") File("Ten_line_to_four_line_BCD_encoder.sof") MfrSpec(OpMask(1));
-
-ChainEnd;
-
-AlteraBegin;
-	ChainType(JTAG);
-AlteraEnd;
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.asm.rpt b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.asm.rpt
deleted file mode 100644
index 1be30bb2..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.asm.rpt
+++ /dev/null
@@ -1,116 +0,0 @@
-Assembler report for Ten_line_to_four_line_BCD_encoder
-Tue Oct  1 00:13:00 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: Ten_line_to_four_line_BCD_encoder.sof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Tue Oct  1 00:13:00 2019 ;
-; Revision Name         ; Ten_line_to_four_line_BCD_encoder     ;
-; Top-level Entity Name ; Ten_line_to_four_line_BCD_encoder     ;
-; Family                ; Cyclone III                           ;
-; Device                ; EP3C16F484C6                          ;
-+-----------------------+---------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Assembler Settings                                                                                     ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Option                                                                      ; Setting  ; Default Value ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Use smart compilation                                                       ; Off      ; Off           ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
-; Enable compact report table                                                 ; Off      ; Off           ;
-; Generate compressed bitstreams                                              ; On       ; On            ;
-; Compression mode                                                            ; Off      ; Off           ;
-; Clock source for configuration device                                       ; Internal ; Internal      ;
-; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
-; Divide clock frequency by                                                   ; 1        ; 1             ;
-; Auto user code                                                              ; On       ; On            ;
-; Use configuration device                                                    ; Off      ; Off           ;
-; Configuration device                                                        ; Auto     ; Auto          ;
-; Configuration device auto user code                                         ; Off      ; Off           ;
-; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
-; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
-; Hexadecimal Output File start address                                       ; 0        ; 0             ;
-; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
-; Release clears before tri-states                                            ; Off      ; Off           ;
-; Auto-restart configuration after error                                      ; On       ; On            ;
-; Enable OCT_DONE                                                             ; Off      ; Off           ;
-; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
-+-----------------------------------------------------------------------------+----------+---------------+
-
-
-+---------------------------------------+
-; Assembler Generated Files             ;
-+---------------------------------------+
-; File Name                             ;
-+---------------------------------------+
-; Ten_line_to_four_line_BCD_encoder.sof ;
-+---------------------------------------+
-
-
-+-----------------------------------------------------------------+
-; Assembler Device Options: Ten_line_to_four_line_BCD_encoder.sof ;
-+----------------+------------------------------------------------+
-; Option         ; Setting                                        ;
-+----------------+------------------------------------------------+
-; Device         ; EP3C16F484C6                                   ;
-; JTAG usercode  ; 0x000C8F4C                                     ;
-; Checksum       ; 0x000C8F4C                                     ;
-+----------------+------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit Assembler
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Tue Oct  1 00:12:57 2019
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 382 megabytes
-    Info: Processing ended: Tue Oct  1 00:13:00 2019
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.done b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.done
deleted file mode 100644
index ee0befce..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.done
+++ /dev/null
@@ -1 +0,0 @@
-Tue Oct  1 00:13:13 2019
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.eda.rpt b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.eda.rpt
deleted file mode 100644
index 4ec873de..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.eda.rpt
+++ /dev/null
@@ -1,107 +0,0 @@
-EDA Netlist Writer report for Ten_line_to_four_line_BCD_encoder
-Tue Oct  1 00:13:13 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. EDA Netlist Writer Summary
-  3. Simulation Settings
-  4. Simulation Generated Files
-  5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary                                        ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Tue Oct  1 00:13:13 2019 ;
-; Revision Name             ; Ten_line_to_four_line_BCD_encoder     ;
-; Top-level Entity Name     ; Ten_line_to_four_line_BCD_encoder     ;
-; Family                    ; Cyclone III                           ;
-; Simulation Files Creation ; Successful                            ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings                                                                                                        ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option                                                                                            ; Setting                ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name                                                                                         ; ModelSim-Altera (VHDL) ;
-; Generate netlist for functional simulation only                                                   ; Off                    ;
-; Time scale                                                                                        ; 1 ps                   ;
-; Truncate long hierarchy paths                                                                     ; Off                    ;
-; Map illegal HDL characters                                                                        ; Off                    ;
-; Flatten buses into individual nodes                                                               ; Off                    ;
-; Maintain hierarchy                                                                                ; Off                    ;
-; Bring out device-wide set/reset signals as ports                                                  ; Off                    ;
-; Enable glitch filtering                                                                           ; Off                    ;
-; Do not write top level VHDL entity                                                                ; Off                    ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                    ;
-; Architecture name in VHDL output netlist                                                          ; structure              ;
-; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                    ;
-; Generate third-party EDA tool command script for gate-level simulation                            ; Off                    ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files                                                                                            ;
-+-----------------------------------------------------------------------------------------------------------------------+
-; Generated Files                                                                                                       ;
-+-----------------------------------------------------------------------------------------------------------------------+
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_slow.vho      ;
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_slow.vho       ;
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_fast.vho     ;
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder.vho                        ;
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_vhd_slow.sdo  ;
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_vhd_slow.sdo   ;
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_vhd_fast.sdo ;
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_vhd.sdo                    ;
-+-----------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit EDA Netlist Writer
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Tue Oct  1 00:13:11 2019
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder
-Info (204019): Generated file Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_slow.vho in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_slow.vho in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_fast.vho in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file Ten_line_to_four_line_BCD_encoder.vho in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_vhd_slow.sdo in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_vhd_slow.sdo in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_vhd_fast.sdo in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file Ten_line_to_four_line_BCD_encoder_vhd.sdo in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/modelsim/" for EDA simulation tool
-Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 348 megabytes
-    Info: Processing ended: Tue Oct  1 00:13:13 2019
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.rpt b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.rpt
deleted file mode 100644
index 9b67336e..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.rpt
+++ /dev/null
@@ -1,1242 +0,0 @@
-Fitter report for Ten_line_to_four_line_BCD_encoder
-Tue Oct  1 00:12:53 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. I/O Assignment Warnings
-  6. Incremental Compilation Preservation Summary
-  7. Incremental Compilation Partition Settings
-  8. Incremental Compilation Placement Preservation
-  9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. Fitter Resource Utilization by Entity
- 18. Delay Chain Summary
- 19. Pad To Core Delay Chain Fanout
- 20. Non-Global High Fan-Out Signals
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Fitter Summary                                                                  ;
-+------------------------------------+--------------------------------------------+
-; Fitter Status                      ; Successful - Tue Oct  1 00:12:53 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; Ten_line_to_four_line_BCD_encoder          ;
-; Top-level Entity Name              ; Ten_line_to_four_line_BCD_encoder          ;
-; Family                             ; Cyclone III                                ;
-; Device                             ; EP3C16F484C6                               ;
-; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 5 / 15,408 ( < 1 % )                       ;
-;     Total combinational functions  ; 5 / 15,408 ( < 1 % )                       ;
-;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 14 / 347 ( 4 % )                           ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
-; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
-; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
-+------------------------------------+--------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                                            ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option                                                                     ; Setting                               ; Default Value                         ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device                                                                     ; EP3C16F484C6                          ;                                       ;
-; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
-; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
-; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
-; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
-; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
-; Use smart compilation                                                      ; Off                                   ; Off                                   ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
-; Enable compact report table                                                ; Off                                   ; Off                                   ;
-; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
-; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
-; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
-; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
-; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
-; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
-; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
-; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
-; SSN Optimization                                                           ; Off                                   ; Off                                   ;
-; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
-; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
-; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
-; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
-; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
-; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
-; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
-; PCI I/O                                                                    ; Off                                   ; Off                                   ;
-; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
-; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
-; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
-; Auto Delay Chains                                                          ; On                                    ; On                                    ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
-; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
-; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
-; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
-; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
-; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
-; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
-; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
-; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
-; Auto Global Clock                                                          ; On                                    ; On                                    ;
-; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
-; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
-; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
-; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
-; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
-; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings                         ;
-+----------+--------------------------------------+
-; Pin Name ; Reason                               ;
-+----------+--------------------------------------+
-; A        ; Missing drive strength and slew rate ;
-; B        ; Missing drive strength and slew rate ;
-; C        ; Missing drive strength and slew rate ;
-; D        ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary                                                    ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ;                   ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 44 ) ; 0.00 % ( 0 / 44 )          ; 0.00 % ( 0 / 44 )        ;
-;     -- Achieved     ; 0.00 % ( 0 / 44 ) ; 0.00 % ( 0 / 44 )          ; 0.00 % ( 0 / 44 )        ;
-;                     ;                   ;                            ;                          ;
-; Routing (by net)    ;                   ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings                                                                                                                                             ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation                                                                                     ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 34 )     ; N/A                     ; Source File       ; N/A                 ;       ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.pin.
-
-
-+--------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                      ;
-+---------------------------------------------+----------------------+
-; Resource                                    ; Usage                ;
-+---------------------------------------------+----------------------+
-; Total logic elements                        ; 5 / 15,408 ( < 1 % ) ;
-;     -- Combinational with no register       ; 5                    ;
-;     -- Register only                        ; 0                    ;
-;     -- Combinational with a register        ; 0                    ;
-;                                             ;                      ;
-; Logic element usage by number of LUT inputs ;                      ;
-;     -- 4 input functions                    ; 3                    ;
-;     -- 3 input functions                    ; 0                    ;
-;     -- <=2 input functions                  ; 2                    ;
-;     -- Register only                        ; 0                    ;
-;                                             ;                      ;
-; Logic elements by mode                      ;                      ;
-;     -- normal mode                          ; 5                    ;
-;     -- arithmetic mode                      ; 0                    ;
-;                                             ;                      ;
-; Total registers*                            ; 0 / 17,068 ( 0 % )   ;
-;     -- Dedicated logic registers            ; 0 / 15,408 ( 0 % )   ;
-;     -- I/O registers                        ; 0 / 1,660 ( 0 % )    ;
-;                                             ;                      ;
-; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )    ;
-; Virtual pins                                ; 0                    ;
-; I/O pins                                    ; 14 / 347 ( 4 % )     ;
-;     -- Clock pins                           ; 0 / 8 ( 0 % )        ;
-;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )        ;
-;                                             ;                      ;
-; Global signals                              ; 0                    ;
-; M9Ks                                        ; 0 / 56 ( 0 % )       ;
-; Total block memory bits                     ; 0 / 516,096 ( 0 % )  ;
-; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )  ;
-; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ;
-; PLLs                                        ; 0 / 4 ( 0 % )        ;
-; Global clocks                               ; 0 / 20 ( 0 % )       ;
-; JTAGs                                       ; 0 / 1 ( 0 % )        ;
-; CRC blocks                                  ; 0 / 1 ( 0 % )        ;
-; ASMI blocks                                 ; 0 / 1 ( 0 % )        ;
-; Impedance control blocks                    ; 0 / 4 ( 0 % )        ;
-; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%         ;
-; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%         ;
-; Maximum fan-out                             ; 3                    ;
-; Highest non-global fan-out                  ; 3                    ;
-; Total fan-out                               ; 39                   ;
-; Average fan-out                             ; 0.91                 ;
-+---------------------------------------------+----------------------+
-*  Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics                                                                        ;
-+---------------------------------------------+---------------------+--------------------------------+
-; Statistic                                   ; Top                 ; hard_block:auto_generated_inst ;
-+---------------------------------------------+---------------------+--------------------------------+
-; Difficulty Clustering Region                ; Low                 ; Low                            ;
-;                                             ;                     ;                                ;
-; Total logic elements                        ; 5 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
-;     -- Combinational with no register       ; 5                   ; 0                              ;
-;     -- Register only                        ; 0                   ; 0                              ;
-;     -- Combinational with a register        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Logic element usage by number of LUT inputs ;                     ;                                ;
-;     -- 4 input functions                    ; 3                   ; 0                              ;
-;     -- 3 input functions                    ; 0                   ; 0                              ;
-;     -- <=2 input functions                  ; 2                   ; 0                              ;
-;     -- Register only                        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Logic elements by mode                      ;                     ;                                ;
-;     -- normal mode                          ; 5                   ; 0                              ;
-;     -- arithmetic mode                      ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Total registers                             ; 0                   ; 0                              ;
-;     -- Dedicated logic registers            ; 0 / 15408 ( 0 % )   ; 0 / 15408 ( 0 % )              ;
-;     -- I/O registers                        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )   ; 0 / 963 ( 0 % )                ;
-;                                             ;                     ;                                ;
-; Virtual pins                                ; 0                   ; 0                              ;
-; I/O pins                                    ; 14                  ; 0                              ;
-; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )     ; 0 / 112 ( 0 % )                ;
-; Total memory bits                           ; 0                   ; 0                              ;
-; Total RAM block bits                        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Connections                                 ;                     ;                                ;
-;     -- Input Connections                    ; 0                   ; 0                              ;
-;     -- Registered Input Connections         ; 0                   ; 0                              ;
-;     -- Output Connections                   ; 0                   ; 0                              ;
-;     -- Registered Output Connections        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Internal Connections                        ;                     ;                                ;
-;     -- Total Connections                    ; 34                  ; 5                              ;
-;     -- Registered Connections               ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; External Connections                        ;                     ;                                ;
-;     -- Top                                  ; 0                   ; 0                              ;
-;     -- hard_block:auto_generated_inst       ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Partition Interface                         ;                     ;                                ;
-;     -- Input Ports                          ; 10                  ; 0                              ;
-;     -- Output Ports                         ; 4                   ; 0                              ;
-;     -- Bidir Ports                          ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Registered Ports                            ;                     ;                                ;
-;     -- Registered Input Ports               ; 0                   ; 0                              ;
-;     -- Registered Output Ports              ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Port Connectivity                           ;                     ;                                ;
-;     -- Input Ports driven by GND            ; 0                   ; 0                              ;
-;     -- Output Ports driven by GND           ; 0                   ; 0                              ;
-;     -- Input Ports driven by VCC            ; 0                   ; 0                              ;
-;     -- Output Ports driven by VCC           ; 0                   ; 0                              ;
-;     -- Input Ports with no Source           ; 0                   ; 0                              ;
-;     -- Output Ports with no Source          ; 0                   ; 0                              ;
-;     -- Input Ports with no Fanout           ; 0                   ; 0                              ;
-;     -- Output Ports with no Fanout          ; 0                   ; 0                              ;
-+---------------------------------------------+---------------------+--------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                                                                ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; I0   ; D2    ; 1        ; 0            ; 25           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I1   ; E4    ; 1        ; 0            ; 26           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I2   ; E3    ; 1        ; 0            ; 26           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I3   ; H7    ; 1        ; 0            ; 25           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I4   ; J7    ; 1        ; 0            ; 22           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I5   ; G5    ; 1        ; 0            ; 27           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I6   ; G4    ; 1        ; 0            ; 23           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I7   ; H6    ; 1        ; 0            ; 25           ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I8   ; H5    ; 1        ; 0            ; 27           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I9   ; J6    ; 1        ; 0            ; 24           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; A    ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; B    ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; C    ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; D    ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins                                                                                         ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; E4       ; DIFFIO_L2p, nRESET          ; Use as regular IO        ; I1                      ; Dual Purpose Pin          ;
-; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
-; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
-; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
-; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
-; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
-; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
-; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
-; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
-; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage                                             ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1        ; 18 / 33 ( 55 % ) ; 2.5V          ; --           ;
-; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
-; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
-; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
-; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
-; 6        ; 1 / 43 ( 2 % )   ; 2.5V          ; --           ;
-; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
-; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                                                                        ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; B1       ; 2          ; 1        ; D                                                         ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; B2       ; 1          ; 1        ; C                                                         ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C1       ; 7          ; 1        ; A                                                         ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; C2       ; 6          ; 1        ; B                                                         ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; D2       ; 8          ; 1        ; I0                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E1       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; E3       ; 5          ; 1        ; I2                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; E4       ; 4          ; 1        ; I1                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G4       ; 17         ; 1        ; I6                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G5       ; 3          ; 1        ; I5                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; G21      ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H1       ; 26         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; H5       ; 0          ; 1        ; I8                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H6       ; 11         ; 1        ; I7                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H7       ; 10         ; 1        ; I3                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J1       ; 29         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J2       ; 28         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J3       ; 27         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J6       ; 12         ; 1        ; I9                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J7       ; 22         ; 1        ; I4                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
-; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                  ;
-+------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------+--------------+
-; Compilation Hierarchy Node         ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                ; Library Name ;
-+------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------+--------------+
-; |Ten_line_to_four_line_BCD_encoder ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 14   ; 0            ; 5 (5)        ; 0 (0)             ; 0 (0)            ; |Ten_line_to_four_line_BCD_encoder ; work         ;
-+------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+--------------------------------------------------------------------------------------+
-; Delay Chain Summary                                                                  ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-; A    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; B    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; C    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; D    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; I0   ; Input    ; --            ; --            ; --                    ; --  ; --   ;
-; I9   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-; I5   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; I7   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; I1   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; I3   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-; I2   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; I6   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-; I4   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-; I8   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+---------------------------------------------------+
-; Pad To Core Delay Chain Fanout                    ;
-+---------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------+-------------------+---------+
-; I0                  ;                   ;         ;
-; I9                  ;                   ;         ;
-;      - or1          ; 1                 ; 6       ;
-;      - or4          ; 1                 ; 6       ;
-; I5                  ;                   ;         ;
-;      - or1~0        ; 0                 ; 6       ;
-;      - or3~0        ; 0                 ; 6       ;
-; I7                  ;                   ;         ;
-;      - or1~0        ; 0                 ; 6       ;
-;      - or2~0        ; 0                 ; 6       ;
-;      - or3~0        ; 0                 ; 6       ;
-; I1                  ;                   ;         ;
-;      - or1~0        ; 0                 ; 6       ;
-; I3                  ;                   ;         ;
-;      - or1~0        ; 1                 ; 6       ;
-;      - or2~0        ; 1                 ; 6       ;
-; I2                  ;                   ;         ;
-;      - or2~0        ; 0                 ; 6       ;
-; I6                  ;                   ;         ;
-;      - or2~0        ; 1                 ; 6       ;
-;      - or3~0        ; 1                 ; 6       ;
-; I4                  ;                   ;         ;
-;      - or3~0        ; 1                 ; 6       ;
-; I8                  ;                   ;         ;
-;      - or4          ; 0                 ; 6       ;
-+---------------------+-------------------+---------+
-
-
-+---------------------------------+
-; Non-Global High Fan-Out Signals ;
-+----------+----------------------+
-; Name     ; Fan-Out              ;
-+----------+----------------------+
-; I7~input ; 3                    ;
-; I6~input ; 2                    ;
-; I3~input ; 2                    ;
-; I5~input ; 2                    ;
-; I9~input ; 2                    ;
-; I8~input ; 1                    ;
-; I4~input ; 1                    ;
-; I2~input ; 1                    ;
-; I1~input ; 1                    ;
-; or4      ; 1                    ;
-; or3~0    ; 1                    ;
-; or2~0    ; 1                    ;
-; or1      ; 1                    ;
-; or1~0    ; 1                    ;
-+----------+----------------------+
-
-
-+-----------------------------------------------+
-; Routing Usage Summary                         ;
-+-----------------------+-----------------------+
-; Routing Resource Type ; Usage                 ;
-+-----------------------+-----------------------+
-; Block interconnects   ; 13 / 47,787 ( < 1 % ) ;
-; C16 interconnects     ; 0 / 1,804 ( 0 % )     ;
-; C4 interconnects      ; 10 / 31,272 ( < 1 % ) ;
-; Direct links          ; 2 / 47,787 ( < 1 % )  ;
-; Global clocks         ; 0 / 20 ( 0 % )        ;
-; Local interconnects   ; 1 / 15,408 ( < 1 % )  ;
-; R24 interconnects     ; 0 / 1,775 ( 0 % )     ;
-; R4 interconnects      ; 0 / 41,310 ( 0 % )    ;
-+-----------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements                                                       ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements  (Average = 5.00) ; Number of LABs  (Total = 1) ;
-+--------------------------------------------+-----------------------------+
-; 1                                          ; 0                           ;
-; 2                                          ; 0                           ;
-; 3                                          ; 0                           ;
-; 4                                          ; 0                           ;
-; 5                                          ; 1                           ;
-; 6                                          ; 0                           ;
-; 7                                          ; 0                           ;
-; 8                                          ; 0                           ;
-; 9                                          ; 0                           ;
-; 10                                         ; 0                           ;
-; 11                                         ; 0                           ;
-; 12                                         ; 0                           ;
-; 13                                         ; 0                           ;
-; 14                                         ; 0                           ;
-; 15                                         ; 0                           ;
-; 16                                         ; 0                           ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced                                                       ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced  (Average = 5.00) ; Number of LABs  (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0                                           ; 0                           ;
-; 1                                           ; 0                           ;
-; 2                                           ; 0                           ;
-; 3                                           ; 0                           ;
-; 4                                           ; 0                           ;
-; 5                                           ; 1                           ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out                                                       ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out  (Average = 4.00) ; Number of LABs  (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0                                               ; 0                           ;
-; 1                                               ; 0                           ;
-; 2                                               ; 0                           ;
-; 3                                               ; 0                           ;
-; 4                                               ; 1                           ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs                                                       ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs  (Average = 9.00) ; Number of LABs  (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0                                           ; 0                           ;
-; 1                                           ; 0                           ;
-; 2                                           ; 0                           ;
-; 3                                           ; 0                           ;
-; 4                                           ; 0                           ;
-; 5                                           ; 0                           ;
-; 6                                           ; 0                           ;
-; 7                                           ; 0                           ;
-; 8                                           ; 0                           ;
-; 9                                           ; 1                           ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary                        ;
-+----------------------------------+-------+
-; I/O Rules Statistic              ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules                  ; 30    ;
-; Number of I/O Rules Passed       ; 12    ;
-; Number of I/O Rules Failed       ; 0     ;
-; Number of I/O Rules Unchecked    ; 0     ;
-; Number of I/O Rules Inapplicable ; 18    ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
-; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
-; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
-; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Total Pass         ; 14        ; 0            ; 14        ; 0            ; 0            ; 14        ; 14        ; 0            ; 14        ; 14        ; 0            ; 4            ; 0            ; 0            ; 10           ; 0            ; 4            ; 10           ; 0            ; 0            ; 0            ; 4            ; 0            ; 0            ; 0            ; 0            ; 0            ; 14        ; 0            ; 0            ;
-; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; Total Inapplicable ; 0         ; 14           ; 0         ; 14           ; 14           ; 0         ; 0         ; 14           ; 0         ; 0         ; 14           ; 10           ; 14           ; 14           ; 4            ; 14           ; 10           ; 4            ; 14           ; 14           ; 14           ; 10           ; 14           ; 14           ; 14           ; 14           ; 14           ; 0         ; 14           ; 14           ;
-; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; A                  ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; B                  ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; C                  ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; D                  ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I0                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I9                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I5                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I7                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I1                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I3                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I2                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I6                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I4                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I8                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options                                                                       ;
-+------------------------------------------------------------------+--------------------------+
-; Option                                                           ; Setting                  ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
-; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
-; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
-; Enable INIT_DONE output                                          ; Off                      ;
-; Configuration scheme                                             ; Active Serial            ;
-; Error detection CRC                                              ; Off                      ;
-; Enable open drain on CRC_ERROR pin                               ; Off                      ;
-; Enable input tri-state on active configuration pins in user mode ; Off                      ;
-; Configuration Voltage Level                                      ; Auto                     ;
-; Force Configuration Voltage Level                                ; Off                      ;
-; nCEO                                                             ; As output driving ground ;
-; Data[0]                                                          ; As input tri-stated      ;
-; Data[1]/ASDO                                                     ; As input tri-stated      ;
-; Data[7..2]                                                       ; Unreserved               ;
-; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
-; Other Active Parallel pins                                       ; Unreserved               ;
-; DCLK                                                             ; As output driving ground ;
-; Base pin-out file on sameframe device                            ; Off                      ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions  ;
-+---------------------------+--------+
-; Setting                   ; Value  ;
-+---------------------------+--------+
-; Nominal Core Voltage      ; 1.20 V ;
-; Low Junction Temperature  ; 0 °C   ;
-; High Junction Temperature ; 85 °C  ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (119006): Selected device EP3C16F484C6 for design "Ten_line_to_four_line_BCD_encoder"
-Info (21077): Core supply voltage is 1.2V
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
-    Info (176445): Device EP3C40F484C6 is compatible
-    Info (176445): Device EP3C55F484C6 is compatible
-    Info (176445): Device EP3C80F484C6 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
-    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
-    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
-    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
-    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
-    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'Ten_line_to_four_line_BCD_encoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
-    Extra Info (176219): No registers were packed into other blocks
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
-    Info (170200): Optimizations that may affect the design's timing were skipped
-Info (11888): Total time spent on timing analysis during the Fitter is 0.20 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
-Info (144001): Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.smsg
-Info: Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 535 megabytes
-    Info: Processing ended: Tue Oct  1 00:12:53 2019
-    Info: Elapsed time: 00:00:12
-    Info: Total CPU time (on all processors): 00:00:12
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.smsg.
-
-
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.smsg b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.smsg
deleted file mode 100644
index 7121cbb1..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.summary b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.summary
deleted file mode 100644
index 0f593a3d..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Tue Oct  1 00:12:53 2019
-Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
-Revision Name : Ten_line_to_four_line_BCD_encoder
-Top-level Entity Name : Ten_line_to_four_line_BCD_encoder
-Family : Cyclone III
-Device : EP3C16F484C6
-Timing Models : Final
-Total logic elements : 5 / 15,408 ( < 1 % )
-    Total combinational functions : 5 / 15,408 ( < 1 % )
-    Dedicated logic registers : 0 / 15,408 ( 0 % )
-Total registers : 0
-Total pins : 14 / 347 ( 4 % )
-Total virtual pins : 0
-Total memory bits : 0 / 516,096 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.flow.rpt b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.flow.rpt
deleted file mode 100644
index d3156c42..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.flow.rpt
+++ /dev/null
@@ -1,128 +0,0 @@
-Flow report for Ten_line_to_four_line_BCD_encoder
-Tue Oct  1 00:13:13 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Flow Summary                                                                    ;
-+------------------------------------+--------------------------------------------+
-; Flow Status                        ; Successful - Tue Oct  1 00:13:13 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; Ten_line_to_four_line_BCD_encoder          ;
-; Top-level Entity Name              ; Ten_line_to_four_line_BCD_encoder          ;
-; Family                             ; Cyclone III                                ;
-; Device                             ; EP3C16F484C6                               ;
-; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 5 / 15,408 ( < 1 % )                       ;
-;     Total combinational functions  ; 5 / 15,408 ( < 1 % )                       ;
-;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 14 / 347 ( 4 % )                           ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
-; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
-; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
-+------------------------------------+--------------------------------------------+
-
-
-+-------------------------------------------------------+
-; Flow Settings                                         ;
-+-------------------+-----------------------------------+
-; Option            ; Setting                           ;
-+-------------------+-----------------------------------+
-; Start date & time ; 10/01/2019 00:12:36               ;
-; Main task         ; Compilation                       ;
-; Revision Name     ; Ten_line_to_four_line_BCD_encoder ;
-+-------------------+-----------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                            ;
-+-------------------------------------+------------------------+---------------+-------------+----------------+
-; Assignment Name                     ; Value                  ; Default Value ; Entity Name ; Section Id     ;
-+-------------------------------------+------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID               ; 0.156985995612465      ; --            ; --          ; --             ;
-; EDA_OUTPUT_DATA_FORMAT              ; Vhdl                   ; --            ; --          ; eda_simulation ;
-; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (VHDL) ; <None>        ; --          ; --             ;
-; MAX_CORE_JUNCTION_TEMP              ; 85                     ; --            ; --          ; --             ;
-; MIN_CORE_JUNCTION_TEMP              ; 0                      ; --            ; --          ; --             ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                   ; --            ; --          ; --             ;
-; PARTITION_COLOR                     ; 16764057               ; --            ; --          ; Top            ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING  ; --            ; --          ; Top            ;
-; PARTITION_NETLIST_TYPE              ; SOURCE                 ; --            ; --          ; Top            ;
-; PROJECT_OUTPUT_DIRECTORY            ; output_files           ; --            ; --          ; --             ;
-+-------------------------------------+------------------------+---------------+-------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 360 MB              ; 00:00:02                           ;
-; Fitter                    ; 00:00:12     ; 1.0                     ; 535 MB              ; 00:00:12                           ;
-; Assembler                 ; 00:00:03     ; 1.0                     ; 382 MB              ; 00:00:03                           ;
-; TimeQuest Timing Analyzer ; 00:00:03     ; 1.0                     ; 383 MB              ; 00:00:03                           ;
-; EDA Netlist Writer        ; 00:00:02     ; 1.0                     ; 338 MB              ; 00:00:01                           ;
-; Total                     ; 00:00:22     ; --                      ; --                  ; 00:00:21                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                              ;
-+---------------------------+-------------------+----------------+------------+----------------+
-; Module Name               ; Machine Hostname  ; OS Name        ; OS Version ; Processor type ;
-+---------------------------+-------------------+----------------+------------+----------------+
-; Analysis & Synthesis      ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; Fitter                    ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; Assembler                 ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; TimeQuest Timing Analyzer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; EDA Netlist Writer        ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-+---------------------------+-------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder
-quartus_fit --read_settings_files=off --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder
-quartus_asm --read_settings_files=off --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder
-quartus_sta Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder
-quartus_eda --read_settings_files=off --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder
-
-
-
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.jdi b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.jdi
deleted file mode 100644
index 61bb85cb..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="c9b0c1b9cea7abee9011"/>
-  </project>
-  <file_info>
-    <file device="EP3C16F484C6" path="Ten_line_to_four_line_BCD_encoder.sof" usercode="0xFFFFFFFF"/>
-  </file_info>
-</sld_project_info>
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.map.rpt b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.map.rpt
deleted file mode 100644
index b1e5f025..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.map.rpt
+++ /dev/null
@@ -1,260 +0,0 @@
-Analysis & Synthesis report for Ten_line_to_four_line_BCD_encoder
-Tue Oct  1 00:12:38 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. General Register Statistics
-  9. Elapsed Time Per Partition
- 10. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                    ;
-+------------------------------------+--------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Tue Oct  1 00:12:38 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; Ten_line_to_four_line_BCD_encoder          ;
-; Top-level Entity Name              ; Ten_line_to_four_line_BCD_encoder          ;
-; Family                             ; Cyclone III                                ;
-; Total logic elements               ; 5                                          ;
-;     Total combinational functions  ; 5                                          ;
-;     Dedicated logic registers      ; 0                                          ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 14                                         ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0                                          ;
-; Embedded Multiplier 9-bit elements ; 0                                          ;
-; Total PLLs                         ; 0                                          ;
-+------------------------------------+--------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                                                      ;
-+----------------------------------------------------------------------------+-----------------------------------+-----------------------------------+
-; Option                                                                     ; Setting                           ; Default Value                     ;
-+----------------------------------------------------------------------------+-----------------------------------+-----------------------------------+
-; Device                                                                     ; EP3C16F484C6                      ;                                   ;
-; Top-level entity name                                                      ; Ten_line_to_four_line_BCD_encoder ; Ten_line_to_four_line_BCD_encoder ;
-; Family name                                                                ; Cyclone III                       ; Cyclone IV GX                     ;
-; Use smart compilation                                                      ; Off                               ; Off                               ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                ; On                                ;
-; Enable compact report table                                                ; Off                               ; Off                               ;
-; Restructure Multiplexers                                                   ; Auto                              ; Auto                              ;
-; Create Debugging Nodes for IP Cores                                        ; Off                               ; Off                               ;
-; Preserve fewer node names                                                  ; On                                ; On                                ;
-; Disable OpenCore Plus hardware evaluation                                  ; Off                               ; Off                               ;
-; Verilog Version                                                            ; Verilog_2001                      ; Verilog_2001                      ;
-; VHDL Version                                                               ; VHDL_1993                         ; VHDL_1993                         ;
-; State Machine Processing                                                   ; Auto                              ; Auto                              ;
-; Safe State Machine                                                         ; Off                               ; Off                               ;
-; Extract Verilog State Machines                                             ; On                                ; On                                ;
-; Extract VHDL State Machines                                                ; On                                ; On                                ;
-; Ignore Verilog initial constructs                                          ; Off                               ; Off                               ;
-; Iteration limit for constant Verilog loops                                 ; 5000                              ; 5000                              ;
-; Iteration limit for non-constant Verilog loops                             ; 250                               ; 250                               ;
-; Add Pass-Through Logic to Inferred RAMs                                    ; On                                ; On                                ;
-; Infer RAMs from Raw Logic                                                  ; On                                ; On                                ;
-; Parallel Synthesis                                                         ; On                                ; On                                ;
-; DSP Block Balancing                                                        ; Auto                              ; Auto                              ;
-; NOT Gate Push-Back                                                         ; On                                ; On                                ;
-; Power-Up Don't Care                                                        ; On                                ; On                                ;
-; Remove Redundant Logic Cells                                               ; Off                               ; Off                               ;
-; Remove Duplicate Registers                                                 ; On                                ; On                                ;
-; Ignore CARRY Buffers                                                       ; Off                               ; Off                               ;
-; Ignore CASCADE Buffers                                                     ; Off                               ; Off                               ;
-; Ignore GLOBAL Buffers                                                      ; Off                               ; Off                               ;
-; Ignore ROW GLOBAL Buffers                                                  ; Off                               ; Off                               ;
-; Ignore LCELL Buffers                                                       ; Off                               ; Off                               ;
-; Ignore SOFT Buffers                                                        ; On                                ; On                                ;
-; Limit AHDL Integers to 32 Bits                                             ; Off                               ; Off                               ;
-; Optimization Technique                                                     ; Balanced                          ; Balanced                          ;
-; Carry Chain Length                                                         ; 70                                ; 70                                ;
-; Auto Carry Chains                                                          ; On                                ; On                                ;
-; Auto Open-Drain Pins                                                       ; On                                ; On                                ;
-; Perform WYSIWYG Primitive Resynthesis                                      ; Off                               ; Off                               ;
-; Auto ROM Replacement                                                       ; On                                ; On                                ;
-; Auto RAM Replacement                                                       ; On                                ; On                                ;
-; Auto DSP Block Replacement                                                 ; On                                ; On                                ;
-; Auto Shift Register Replacement                                            ; Auto                              ; Auto                              ;
-; Allow Shift Register Merging across Hierarchies                            ; Auto                              ; Auto                              ;
-; Auto Clock Enable Replacement                                              ; On                                ; On                                ;
-; Strict RAM Replacement                                                     ; Off                               ; Off                               ;
-; Allow Synchronous Control Signals                                          ; On                                ; On                                ;
-; Force Use of Synchronous Clear Signals                                     ; Off                               ; Off                               ;
-; Auto RAM Block Balancing                                                   ; On                                ; On                                ;
-; Auto RAM to Logic Cell Conversion                                          ; Off                               ; Off                               ;
-; Auto Resource Sharing                                                      ; Off                               ; Off                               ;
-; Allow Any RAM Size For Recognition                                         ; Off                               ; Off                               ;
-; Allow Any ROM Size For Recognition                                         ; Off                               ; Off                               ;
-; Allow Any Shift Register Size For Recognition                              ; Off                               ; Off                               ;
-; Use LogicLock Constraints during Resource Balancing                        ; On                                ; On                                ;
-; Ignore translate_off and synthesis_off directives                          ; Off                               ; Off                               ;
-; Timing-Driven Synthesis                                                    ; On                                ; On                                ;
-; Report Parameter Settings                                                  ; On                                ; On                                ;
-; Report Source Assignments                                                  ; On                                ; On                                ;
-; Report Connectivity Checks                                                 ; On                                ; On                                ;
-; Ignore Maximum Fan-Out Assignments                                         ; Off                               ; Off                               ;
-; Synchronization Register Chain Length                                      ; 2                                 ; 2                                 ;
-; PowerPlay Power Optimization                                               ; Normal compilation                ; Normal compilation                ;
-; HDL message level                                                          ; Level2                            ; Level2                            ;
-; Suppress Register Optimization Related Messages                            ; Off                               ; Off                               ;
-; Number of Removed Registers Reported in Synthesis Report                   ; 5000                              ; 5000                              ;
-; Number of Swept Nodes Reported in Synthesis Report                         ; 5000                              ; 5000                              ;
-; Number of Inverted Registers Reported in Synthesis Report                  ; 100                               ; 100                               ;
-; Clock MUX Protection                                                       ; On                                ; On                                ;
-; Auto Gated Clock Conversion                                                ; Off                               ; Off                               ;
-; Block Design Naming                                                        ; Auto                              ; Auto                              ;
-; SDC constraint protection                                                  ; Off                               ; Off                               ;
-; Synthesis Effort                                                           ; Auto                              ; Auto                              ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                                ; On                                ;
-; Pre-Mapping Resynthesis Optimization                                       ; Off                               ; Off                               ;
-; Analysis & Synthesis Message Level                                         ; Medium                            ; Medium                            ;
-; Disable Register Merging Across Hierarchies                                ; Auto                              ; Auto                              ;
-; Resource Aware Inference For Block RAM                                     ; On                                ; On                                ;
-; Synthesis Seed                                                             ; 1                                 ; 1                                 ;
-+----------------------------------------------------------------------------+-----------------------------------+-----------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                                              ;
-+---------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path      ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                               ; Library ;
-+---------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------+---------+
-; Ten_line_to_four_line_BCD_encoder.bdf ; yes             ; User Block Diagram/Schematic File  ; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.bdf ;         ;
-+---------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------+---------+
-
-
-+--------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary            ;
-+---------------------------------------------+----------+
-; Resource                                    ; Usage    ;
-+---------------------------------------------+----------+
-; Estimated Total logic elements              ; 5        ;
-;                                             ;          ;
-; Total combinational functions               ; 5        ;
-; Logic element usage by number of LUT inputs ;          ;
-;     -- 4 input functions                    ; 3        ;
-;     -- 3 input functions                    ; 0        ;
-;     -- <=2 input functions                  ; 2        ;
-;                                             ;          ;
-; Logic elements by mode                      ;          ;
-;     -- normal mode                          ; 5        ;
-;     -- arithmetic mode                      ; 0        ;
-;                                             ;          ;
-; Total registers                             ; 0        ;
-;     -- Dedicated logic registers            ; 0        ;
-;     -- I/O registers                        ; 0        ;
-;                                             ;          ;
-; I/O pins                                    ; 14       ;
-; Embedded Multiplier 9-bit elements          ; 0        ;
-; Maximum fan-out node                        ; I7~input ;
-; Maximum fan-out                             ; 3        ;
-; Total fan-out                               ; 34       ;
-; Average fan-out                             ; 1.03     ;
-+---------------------------------------------+----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                ;
-+------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+
-; Compilation Hierarchy Node         ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                ; Library Name ;
-+------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+
-; |Ten_line_to_four_line_BCD_encoder ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 14   ; 0            ; |Ten_line_to_four_line_BCD_encoder ; work         ;
-+------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 0     ;
-; Number of registers using Synchronous Clear  ; 0     ;
-; Number of registers using Synchronous Load   ; 0     ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 0     ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition    ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top            ; 00:00:01     ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit Analysis & Synthesis
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Tue Oct  1 00:12:36 2019
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (12021): Found 1 design units, including 1 entities, in source file Ten_line_to_four_line_BCD_encoder.bdf
-    Info (12023): Found entity 1: Ten_line_to_four_line_BCD_encoder
-Info (12127): Elaborating entity "Ten_line_to_four_line_BCD_encoder" for the top level hierarchy
-Warning (275009): Pin "I0" not connected
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
-    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 1 input pin(s) that do not drive logic
-    Warning (15610): No output dependent on input pin "I0"
-Info (21057): Implemented 19 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 10 input pins
-    Info (21059): Implemented 4 output pins
-    Info (21061): Implemented 5 logic cells
-Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings
-    Info: Peak virtual memory: 371 megabytes
-    Info: Processing ended: Tue Oct  1 00:12:38 2019
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.map.summary b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.map.summary
deleted file mode 100644
index 4c870d23..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Tue Oct  1 00:12:38 2019
-Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
-Revision Name : Ten_line_to_four_line_BCD_encoder
-Top-level Entity Name : Ten_line_to_four_line_BCD_encoder
-Family : Cyclone III
-Total logic elements : 5
-    Total combinational functions : 5
-    Dedicated logic registers : 0
-Total registers : 0
-Total pins : 14
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.pin b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.pin
deleted file mode 100644
index 5dc29714..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.pin
+++ /dev/null
@@ -1,554 +0,0 @@
- -- Copyright (C) 1991-2013 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Altera Program License 
- -- Subscription Agreement, Altera MegaCore Function License 
- -- Agreement, or other applicable license agreement, including, 
- -- without limitation, that your use is for the sole purpose of 
- -- programming logic devices manufactured by Altera and sold by 
- -- Altera or its authorized distributors.  Please refer to the 
- -- applicable agreement for further details.
- -- 
- -- This is a Quartus II output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus II input file. This file cannot be used
- -- to make Quartus II pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus II help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --					Bank 1:		2.5V
- --					Bank 2:		2.5V
- --					Bank 3:		2.5V
- --					Bank 4:		2.5V
- --					Bank 5:		2.5V
- --					Bank 6:		2.5V
- --					Bank 7:		2.5V
- --					Bank 8:		2.5V
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --					It can also be used to report unused dedicated pins. The connection
- --					on the board for unused dedicated pins depends on whether this will
- --					be used in a future design. One example is device migration. When
- --					using device migration, refer to the device pin-tables. If it is a
- --					GND pin in the pin table or if it will not be used in a future design
- --					for another purpose the it MUST be connected to GND. If it is an unused
- --					dedicated pin, then it can be connected to a valid signal on the board
- --					(low, high, or toggling) if that signal is required for a different
- --					revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --					This pin should be connected to GND. It may also be connected  to a
- --					valid signal  on the board  (low, high, or toggling)  if that signal
- --					is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --           	    or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-CHIP  "Ten_line_to_four_line_BCD_encoder"  ASSIGNED TO AN: EP3C16F484C6
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : A1        : gnd    :                   :         :           :                
-VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
-GND+                         : A11       :        :                   :         : 8         :                
-GND+                         : A12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
-VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
-GND                          : A22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
-VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
-GND+                         : AA11      :        :                   :         : 3         :                
-GND+                         : AA12      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
-GND                          : AB1       : gnd    :                   :         :           :                
-VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
-GND                          : AB6       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
-GND+                         : AB11      :        :                   :         : 3         :                
-GND+                         : AB12      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
-VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
-GND                          : AB22      : gnd    :                   :         :           :                
-D                            : B1        : output : 2.5 V             :         : 1         : Y              
-C                            : B2        : output : 2.5 V             :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
-GND+                         : B11       :        :                   :         : 8         :                
-GND+                         : B12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
-A                            : C1        : output : 2.5 V             :         : 1         : Y              
-B                            : C2        : output : 2.5 V             :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
-GND                          : C5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
-GND                          : C9        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
-GND                          : C11       : gnd    :                   :         :           :                
-GND                          : C12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
-GND                          : C14       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
-GND                          : C16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
-GND                          : C18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
-I0                           : D2        : input  : 2.5 V             :         : 1         : Y              
-GND                          : D3        : gnd    :                   :         :           :                
-VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
-VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
-GND                          : D7        : gnd    :                   :         :           :                
-GND                          : D8        : gnd    :                   :         :           :                
-VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
-VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
-VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
-VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
-VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
-VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 1         :                
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
-I2                           : E3        : input  : 2.5 V             :         : 1         : Y              
-I1                           : E4        : input  : 2.5 V             :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
-VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
-VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
-GNDA2                        : E18       : gnd    :                   :         :           :                
-VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
-GND                          : E20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2        :        :                   :         : 1         :                
-GND                          : F3        : gnd    :                   :         :           :                
-VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
-GNDA3                        : F5        : gnd    :                   :         :           :                
-VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
-VCCA2                        : F18       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
-GND+                         : G1        :        :                   :         : 1         :                
-GND+                         : G2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3        :        :                   :         : 1         :                
-I6                           : G4        : input  : 2.5 V             :         : 1         : Y              
-I5                           : G5        : input  : 2.5 V             :         : 1         : Y              
-VCCA3                        : G6        : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
-VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
-GND                          : G20       : gnd    :                   :         :           :                
-GND+                         : G21       :        :                   :         : 6         :                
-GND+                         : G22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
-GND                          : H3        : gnd    :                   :         :           :                
-VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
-I8                           : H5        : input  : 2.5 V             :         : 1         : Y              
-I7                           : H6        : input  : 2.5 V             :         : 1         : Y              
-I3                           : H7        : input  : 2.5 V             :         : 1         : Y              
-GND                          : H8        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
-GND                          : J5        : gnd    :                   :         :           :                
-I9                           : J6        : input  : 2.5 V             :         : 1         : Y              
-I4                           : J7        : input  : 2.5 V             :         : 1         : Y              
-VCCINT                       : J8        : power  :                   : 1.2V    :           :                
-GND                          : J9        : gnd    :                   :         :           :                
-VCCINT                       : J10       : power  :                   : 1.2V    :           :                
-VCCINT                       : J11       : power  :                   : 1.2V    :           :                
-VCCINT                       : J12       : power  :                   : 1.2V    :           :                
-VCCINT                       : J13       : power  :                   : 1.2V    :           :                
-VCCINT                       : J14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
-GND                          : J19       : gnd    :                   :         :           :                
-VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
-~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
-GND                          : K3        : gnd    :                   :         :           :                
-VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
-nCONFIG                      : K5        :        :                   :         : 1         :                
-nSTATUS                      : K6        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
-VCCINT                       : K9        : power  :                   : 1.2V    :           :                
-GND                          : K10       : gnd    :                   :         :           :                
-GND                          : K11       : gnd    :                   :         :           :                
-GND                          : K12       : gnd    :                   :         :           :                
-GND                          : K13       : gnd    :                   :         :           :                
-VCCINT                       : K14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
-MSEL3                        : K20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
-TMS                          : L1        : input  :                   :         : 1         :                
-TCK                          : L2        : input  :                   :         : 1         :                
-nCE                          : L3        :        :                   :         : 1         :                
-TDO                          : L4        : output :                   :         : 1         :                
-TDI                          : L5        : input  :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
-VCCINT                       : L9        : power  :                   : 1.2V    :           :                
-GND                          : L10       : gnd    :                   :         :           :                
-GND                          : L11       : gnd    :                   :         :           :                
-GND                          : L12       : gnd    :                   :         :           :                
-GND                          : L13       : gnd    :                   :         :           :                
-VCCINT                       : L14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
-MSEL2                        : L17       :        :                   :         : 6         :                
-MSEL1                        : L18       :        :                   :         : 6         :                
-VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
-GND                          : L20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
-VCCINT                       : M9        : power  :                   : 1.2V    :           :                
-GND                          : M10       : gnd    :                   :         :           :                
-GND                          : M11       : gnd    :                   :         :           :                
-GND                          : M12       : gnd    :                   :         :           :                
-GND                          : M13       : gnd    :                   :         :           :                
-VCCINT                       : M14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
-MSEL0                        : M17       :        :                   :         : 6         :                
-CONF_DONE                    : M18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
-GND                          : N3        : gnd    :                   :         :           :                
-VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
-VCCINT                       : N9        : power  :                   : 1.2V    :           :                
-GND                          : N10       : gnd    :                   :         :           :                
-GND                          : N11       : gnd    :                   :         :           :                
-GND                          : N12       : gnd    :                   :         :           :                
-GND                          : N13       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
-VCCINT                       : P9        : power  :                   : 1.2V    :           :                
-VCCINT                       : P10       : power  :                   : 1.2V    :           :                
-VCCINT                       : P11       : power  :                   : 1.2V    :           :                
-VCCINT                       : P12       : power  :                   : 1.2V    :           :                
-VCCINT                       : P13       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
-VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
-GND                          : P19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
-GND                          : R3        : gnd    :                   :         :           :                
-VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
-GND+                         : T1        :        :                   :         : 2         :                
-GND+                         : T2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
-VCCA1                        : T6        : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
-VCCINT                       : T13       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
-VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
-GND                          : T20       : gnd    :                   :         :           :                
-GND+                         : T21       :        :                   :         : 5         :                
-GND+                         : T22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
-GND                          : U3        : gnd    :                   :         :           :                
-VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
-GNDA1                        : U5        : gnd    :                   :         :           :                
-VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
-VCCINT                       : U16       : power  :                   : 1.2V    :           :                
-VCCINT                       : U17       : power  :                   : 1.2V    :           :                
-VCCA4                        : U18       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
-VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
-GNDA4                        : V18       : gnd    :                   :         :           :                
-VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
-GND                          : V20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
-GND                          : W3        : gnd    :                   :         :           :                
-VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
-VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
-VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
-VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
-VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
-VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
-VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
-GND                          : Y5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
-GND                          : Y9        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
-GND                          : Y11       : gnd    :                   :         :           :                
-GND                          : Y12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
-VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
-GND                          : Y15       : gnd    :                   :         :           :                
-GND                          : Y16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
-GND                          : Y18       : gnd    :                   :         :           :                
-VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
-GND                          : Y20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.sof b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.sof
deleted file mode 100644
index d96ac0c7dd24f55cd553e86bc35136a8b7707a8e..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.sta.rpt b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.sta.rpt
deleted file mode 100644
index a6a1bfff..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.sta.rpt
+++ /dev/null
@@ -1,578 +0,0 @@
-TimeQuest Timing Analyzer report for Ten_line_to_four_line_BCD_encoder
-Tue Oct  1 00:13:07 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. Clocks
-  5. Slow 1200mV 85C Model Fmax Summary
-  6. Timing Closure Recommendations
-  7. Slow 1200mV 85C Model Setup Summary
-  8. Slow 1200mV 85C Model Hold Summary
-  9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Propagation Delay
- 13. Minimum Propagation Delay
- 14. Slow 1200mV 85C Model Metastability Report
- 15. Slow 1200mV 0C Model Fmax Summary
- 16. Slow 1200mV 0C Model Setup Summary
- 17. Slow 1200mV 0C Model Hold Summary
- 18. Slow 1200mV 0C Model Recovery Summary
- 19. Slow 1200mV 0C Model Removal Summary
- 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 21. Propagation Delay
- 22. Minimum Propagation Delay
- 23. Slow 1200mV 0C Model Metastability Report
- 24. Fast 1200mV 0C Model Setup Summary
- 25. Fast 1200mV 0C Model Hold Summary
- 26. Fast 1200mV 0C Model Recovery Summary
- 27. Fast 1200mV 0C Model Removal Summary
- 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 29. Propagation Delay
- 30. Minimum Propagation Delay
- 31. Fast 1200mV 0C Model Metastability Report
- 32. Multicorner Timing Analysis Summary
- 33. Propagation Delay
- 34. Minimum Propagation Delay
- 35. Board Trace Model Assignments
- 36. Input Transition Times
- 37. Slow Corner Signal Integrity Metrics
- 38. Fast Corner Signal Integrity Metrics
- 39. Clock Transfers
- 40. Report TCCS
- 41. Report RSKM
- 42. Unconstrained Paths
- 43. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                       ;
-+--------------------+----------------------------------------------------+
-; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name      ; Ten_line_to_four_line_BCD_encoder                  ;
-; Device Family      ; Cyclone III                                        ;
-; Device Name        ; EP3C16F484C6                                       ;
-; Timing Models      ; Final                                              ;
-; Delay Model        ; Combined                                           ;
-; Rise/Fall Delays   ; Enabled                                            ;
-+--------------------+----------------------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------+
-; Propagation Delay                                  ;
-+------------+-------------+-------+----+----+-------+
-; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
-+------------+-------------+-------+----+----+-------+
-; I1         ; A           ; 6.961 ;    ;    ; 7.373 ;
-; I2         ; B           ; 6.458 ;    ;    ; 6.834 ;
-; I3         ; A           ; 7.016 ;    ;    ; 7.439 ;
-; I3         ; B           ; 6.724 ;    ;    ; 7.141 ;
-; I4         ; C           ; 6.571 ;    ;    ; 6.993 ;
-; I5         ; A           ; 6.510 ;    ;    ; 6.903 ;
-; I5         ; C           ; 5.937 ;    ;    ; 6.320 ;
-; I6         ; B           ; 6.790 ;    ;    ; 7.227 ;
-; I6         ; C           ; 6.508 ;    ;    ; 6.942 ;
-; I7         ; A           ; 6.916 ;    ;    ; 7.329 ;
-; I7         ; B           ; 6.633 ;    ;    ; 7.042 ;
-; I7         ; C           ; 6.489 ;    ;    ; 6.893 ;
-; I8         ; D           ; 5.907 ;    ;    ; 6.288 ;
-; I9         ; A           ; 6.571 ;    ;    ; 6.998 ;
-; I9         ; D           ; 6.301 ;    ;    ; 6.725 ;
-+------------+-------------+-------+----+----+-------+
-
-
-+----------------------------------------------------+
-; Minimum Propagation Delay                          ;
-+------------+-------------+-------+----+----+-------+
-; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
-+------------+-------------+-------+----+----+-------+
-; I1         ; A           ; 6.797 ;    ;    ; 7.196 ;
-; I2         ; B           ; 6.314 ;    ;    ; 6.679 ;
-; I3         ; A           ; 6.850 ;    ;    ; 7.260 ;
-; I3         ; B           ; 6.570 ;    ;    ; 6.974 ;
-; I4         ; C           ; 6.422 ;    ;    ; 6.831 ;
-; I5         ; A           ; 6.363 ;    ;    ; 6.744 ;
-; I5         ; C           ; 5.814 ;    ;    ; 6.186 ;
-; I6         ; B           ; 6.633 ;    ;    ; 7.057 ;
-; I6         ; C           ; 6.363 ;    ;    ; 6.784 ;
-; I7         ; A           ; 6.753 ;    ;    ; 7.154 ;
-; I7         ; B           ; 6.482 ;    ;    ; 6.879 ;
-; I7         ; C           ; 6.344 ;    ;    ; 6.736 ;
-; I8         ; D           ; 5.785 ;    ;    ; 6.154 ;
-; I9         ; A           ; 6.421 ;    ;    ; 6.836 ;
-; I9         ; D           ; 6.163 ;    ;    ; 6.575 ;
-+------------+-------------+-------+----+----+-------+
-
-
-----------------------------------------------
-; Slow 1200mV 85C Model Metastability Report ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------+
-; Propagation Delay                                  ;
-+------------+-------------+-------+----+----+-------+
-; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
-+------------+-------------+-------+----+----+-------+
-; I1         ; A           ; 6.469 ;    ;    ; 6.785 ;
-; I2         ; B           ; 6.010 ;    ;    ; 6.311 ;
-; I3         ; A           ; 6.513 ;    ;    ; 6.857 ;
-; I3         ; B           ; 6.247 ;    ;    ; 6.588 ;
-; I4         ; C           ; 6.114 ;    ;    ; 6.458 ;
-; I5         ; A           ; 6.054 ;    ;    ; 6.368 ;
-; I5         ; C           ; 5.530 ;    ;    ; 5.847 ;
-; I6         ; B           ; 6.307 ;    ;    ; 6.651 ;
-; I6         ; C           ; 6.047 ;    ;    ; 6.399 ;
-; I7         ; A           ; 6.420 ;    ;    ; 6.762 ;
-; I7         ; B           ; 6.163 ;    ;    ; 6.505 ;
-; I7         ; C           ; 6.027 ;    ;    ; 6.367 ;
-; I8         ; D           ; 5.503 ;    ;    ; 5.817 ;
-; I9         ; A           ; 6.111 ;    ;    ; 6.449 ;
-; I9         ; D           ; 5.866 ;    ;    ; 6.205 ;
-+------------+-------------+-------+----+----+-------+
-
-
-+----------------------------------------------------+
-; Minimum Propagation Delay                          ;
-+------------+-------------+-------+----+----+-------+
-; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
-+------------+-------------+-------+----+----+-------+
-; I1         ; A           ; 6.327 ;    ;    ; 6.634 ;
-; I2         ; B           ; 5.887 ;    ;    ; 6.181 ;
-; I3         ; A           ; 6.368 ;    ;    ; 6.702 ;
-; I3         ; B           ; 6.114 ;    ;    ; 6.445 ;
-; I4         ; C           ; 5.987 ;    ;    ; 6.320 ;
-; I5         ; A           ; 5.928 ;    ;    ; 6.235 ;
-; I5         ; C           ; 5.425 ;    ;    ; 5.735 ;
-; I6         ; B           ; 6.172 ;    ;    ; 6.506 ;
-; I6         ; C           ; 5.923 ;    ;    ; 6.263 ;
-; I7         ; A           ; 6.279 ;    ;    ; 6.611 ;
-; I7         ; B           ; 6.034 ;    ;    ; 6.366 ;
-; I7         ; C           ; 5.903 ;    ;    ; 6.233 ;
-; I8         ; D           ; 5.400 ;    ;    ; 5.706 ;
-; I9         ; A           ; 5.983 ;    ;    ; 6.312 ;
-; I9         ; D           ; 5.749 ;    ;    ; 6.077 ;
-+------------+-------------+-------+----+----+-------+
-
-
----------------------------------------------
-; Slow 1200mV 0C Model Metastability Report ;
----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------+
-; Propagation Delay                                  ;
-+------------+-------------+-------+----+----+-------+
-; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
-+------------+-------------+-------+----+----+-------+
-; I1         ; A           ; 4.132 ;    ;    ; 4.731 ;
-; I2         ; B           ; 3.863 ;    ;    ; 4.445 ;
-; I3         ; A           ; 4.176 ;    ;    ; 4.782 ;
-; I3         ; B           ; 4.028 ;    ;    ; 4.622 ;
-; I4         ; C           ; 3.952 ;    ;    ; 4.534 ;
-; I5         ; A           ; 3.877 ;    ;    ; 4.454 ;
-; I5         ; C           ; 3.569 ;    ;    ; 4.113 ;
-; I6         ; B           ; 4.073 ;    ;    ; 4.667 ;
-; I6         ; C           ; 3.912 ;    ;    ; 4.487 ;
-; I7         ; A           ; 4.110 ;    ;    ; 4.711 ;
-; I7         ; B           ; 3.971 ;    ;    ; 4.562 ;
-; I7         ; C           ; 3.888 ;    ;    ; 4.458 ;
-; I8         ; D           ; 3.554 ;    ;    ; 4.093 ;
-; I9         ; A           ; 3.937 ;    ;    ; 4.524 ;
-; I9         ; D           ; 3.790 ;    ;    ; 4.355 ;
-+------------+-------------+-------+----+----+-------+
-
-
-+----------------------------------------------------+
-; Minimum Propagation Delay                          ;
-+------------+-------------+-------+----+----+-------+
-; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
-+------------+-------------+-------+----+----+-------+
-; I1         ; A           ; 4.037 ;    ;    ; 4.630 ;
-; I2         ; B           ; 3.779 ;    ;    ; 4.356 ;
-; I3         ; A           ; 4.079 ;    ;    ; 4.679 ;
-; I3         ; B           ; 3.938 ;    ;    ; 4.525 ;
-; I4         ; C           ; 3.864 ;    ;    ; 4.439 ;
-; I5         ; A           ; 3.790 ;    ;    ; 4.364 ;
-; I5         ; C           ; 3.496 ;    ;    ; 4.035 ;
-; I6         ; B           ; 3.981 ;    ;    ; 4.568 ;
-; I6         ; C           ; 3.827 ;    ;    ; 4.394 ;
-; I7         ; A           ; 4.015 ;    ;    ; 4.610 ;
-; I7         ; B           ; 3.883 ;    ;    ; 4.467 ;
-; I7         ; C           ; 3.803 ;    ;    ; 4.366 ;
-; I8         ; D           ; 3.483 ;    ;    ; 4.017 ;
-; I9         ; A           ; 3.850 ;    ;    ; 4.430 ;
-; I9         ; D           ; 3.709 ;    ;    ; 4.268 ;
-+------------+-------------+-------+----+----+-------+
-
-
----------------------------------------------
-; Fast 1200mV 0C Model Metastability Report ;
----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary                                        ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
-; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+----------------------------------------------------+
-; Propagation Delay                                  ;
-+------------+-------------+-------+----+----+-------+
-; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
-+------------+-------------+-------+----+----+-------+
-; I1         ; A           ; 6.961 ;    ;    ; 7.373 ;
-; I2         ; B           ; 6.458 ;    ;    ; 6.834 ;
-; I3         ; A           ; 7.016 ;    ;    ; 7.439 ;
-; I3         ; B           ; 6.724 ;    ;    ; 7.141 ;
-; I4         ; C           ; 6.571 ;    ;    ; 6.993 ;
-; I5         ; A           ; 6.510 ;    ;    ; 6.903 ;
-; I5         ; C           ; 5.937 ;    ;    ; 6.320 ;
-; I6         ; B           ; 6.790 ;    ;    ; 7.227 ;
-; I6         ; C           ; 6.508 ;    ;    ; 6.942 ;
-; I7         ; A           ; 6.916 ;    ;    ; 7.329 ;
-; I7         ; B           ; 6.633 ;    ;    ; 7.042 ;
-; I7         ; C           ; 6.489 ;    ;    ; 6.893 ;
-; I8         ; D           ; 5.907 ;    ;    ; 6.288 ;
-; I9         ; A           ; 6.571 ;    ;    ; 6.998 ;
-; I9         ; D           ; 6.301 ;    ;    ; 6.725 ;
-+------------+-------------+-------+----+----+-------+
-
-
-+----------------------------------------------------+
-; Minimum Propagation Delay                          ;
-+------------+-------------+-------+----+----+-------+
-; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
-+------------+-------------+-------+----+----+-------+
-; I1         ; A           ; 4.037 ;    ;    ; 4.630 ;
-; I2         ; B           ; 3.779 ;    ;    ; 4.356 ;
-; I3         ; A           ; 4.079 ;    ;    ; 4.679 ;
-; I3         ; B           ; 3.938 ;    ;    ; 4.525 ;
-; I4         ; C           ; 3.864 ;    ;    ; 4.439 ;
-; I5         ; A           ; 3.790 ;    ;    ; 4.364 ;
-; I5         ; C           ; 3.496 ;    ;    ; 4.035 ;
-; I6         ; B           ; 3.981 ;    ;    ; 4.568 ;
-; I6         ; C           ; 3.827 ;    ;    ; 4.394 ;
-; I7         ; A           ; 4.015 ;    ;    ; 4.610 ;
-; I7         ; B           ; 3.883 ;    ;    ; 4.467 ;
-; I7         ; C           ; 3.803 ;    ;    ; 4.366 ;
-; I8         ; D           ; 3.483 ;    ;    ; 4.017 ;
-; I9         ; A           ; 3.850 ;    ;    ; 4.430 ;
-; I9         ; D           ; 3.709 ;    ;    ; 4.268 ;
-+------------+-------------+-------+----+----+-------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; A             ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; B             ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; C             ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; D             ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times                                                     ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; I0                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I9                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I5                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I7                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I1                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I3                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I2                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I6                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I4                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I8                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; A             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; B             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; C             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; D             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; A             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; B             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; C             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; D             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths                            ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 9     ; 9    ;
-; Unconstrained Input Port Paths  ; 15    ; 15   ;
-; Unconstrained Output Ports      ; 4     ; 4    ;
-; Unconstrained Output Port Paths ; 15    ; 15   ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Tue Oct  1 00:13:04 2019
-Info: Command: quartus_sta Ten_line_to_four_line_BCD_encoder -c Ten_line_to_four_line_BCD_encoder
-Info: qsta_default_script.tcl version: #1
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (21077): Core supply voltage is 1.2V
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'Ten_line_to_four_line_BCD_encoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 383 megabytes
-    Info: Processing ended: Tue Oct  1 00:13:07 2019
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.sta.summary b/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.sta.summary
deleted file mode 100644
index 33f74363..00000000
--- a/CH6/CH6-1/output_files/Ten_line_to_four_line_BCD_encoder.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.asm.rpt b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.asm.rpt
deleted file mode 100644
index 7dff6a96..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.asm.rpt
+++ /dev/null
@@ -1,116 +0,0 @@
-Assembler report for four_line_to_sixteen_line_decimal_decoder
-Thu Oct 24 22:11:33 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: four_line_to_sixteen_line_decimal_decoder.sof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------+
-; Assembler Summary                                                 ;
-+-----------------------+-------------------------------------------+
-; Assembler Status      ; Successful - Thu Oct 24 22:11:33 2019     ;
-; Revision Name         ; four_line_to_sixteen_line_decimal_decoder ;
-; Top-level Entity Name ; four_line_to_sixteen_line_decimal_decoder ;
-; Family                ; Cyclone III                               ;
-; Device                ; EP3C16F484C6                              ;
-+-----------------------+-------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Assembler Settings                                                                                     ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Option                                                                      ; Setting  ; Default Value ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Use smart compilation                                                       ; Off      ; Off           ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
-; Enable compact report table                                                 ; Off      ; Off           ;
-; Generate compressed bitstreams                                              ; On       ; On            ;
-; Compression mode                                                            ; Off      ; Off           ;
-; Clock source for configuration device                                       ; Internal ; Internal      ;
-; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
-; Divide clock frequency by                                                   ; 1        ; 1             ;
-; Auto user code                                                              ; On       ; On            ;
-; Use configuration device                                                    ; Off      ; Off           ;
-; Configuration device                                                        ; Auto     ; Auto          ;
-; Configuration device auto user code                                         ; Off      ; Off           ;
-; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
-; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
-; Hexadecimal Output File start address                                       ; 0        ; 0             ;
-; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
-; Release clears before tri-states                                            ; Off      ; Off           ;
-; Auto-restart configuration after error                                      ; On       ; On            ;
-; Enable OCT_DONE                                                             ; Off      ; Off           ;
-; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
-+-----------------------------------------------------------------------------+----------+---------------+
-
-
-+-----------------------------------------------+
-; Assembler Generated Files                     ;
-+-----------------------------------------------+
-; File Name                                     ;
-+-----------------------------------------------+
-; four_line_to_sixteen_line_decimal_decoder.sof ;
-+-----------------------------------------------+
-
-
-+-------------------------------------------------------------------------+
-; Assembler Device Options: four_line_to_sixteen_line_decimal_decoder.sof ;
-+----------------+--------------------------------------------------------+
-; Option         ; Setting                                                ;
-+----------------+--------------------------------------------------------+
-; Device         ; EP3C16F484C6                                           ;
-; JTAG usercode  ; 0x000C9ECE                                             ;
-; Checksum       ; 0x000C9ECE                                             ;
-+----------------+--------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit Assembler
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 24 22:11:31 2019
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 382 megabytes
-    Info: Processing ended: Thu Oct 24 22:11:33 2019
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.done b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.done
deleted file mode 100644
index 1f5a20b8..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.done
+++ /dev/null
@@ -1 +0,0 @@
-Thu Oct 24 22:11:46 2019
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.eda.rpt b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.eda.rpt
deleted file mode 100644
index a2a31add..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.eda.rpt
+++ /dev/null
@@ -1,105 +0,0 @@
-EDA Netlist Writer report for four_line_to_sixteen_line_decimal_decoder
-Thu Oct 24 22:24:53 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. EDA Netlist Writer Summary
-  3. Simulation Settings
-  4. Simulation Generated Files
-  5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------+
-; EDA Netlist Writer Summary                                            ;
-+---------------------------+-------------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Oct 24 22:24:53 2019     ;
-; Revision Name             ; four_line_to_sixteen_line_decimal_decoder ;
-; Top-level Entity Name     ; four_line_to_sixteen_line_decimal_decoder ;
-; Family                    ; Cyclone III                               ;
-; Simulation Files Creation ; Successful                                ;
-+---------------------------+-------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings                                                                                                           ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-; Option                                                                                            ; Setting                   ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
-; Generate netlist for functional simulation only                                                   ; On                        ;
-; Truncate long hierarchy paths                                                                     ; Off                       ;
-; Map illegal HDL characters                                                                        ; Off                       ;
-; Flatten buses into individual nodes                                                               ; Off                       ;
-; Maintain hierarchy                                                                                ; Off                       ;
-; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
-; Enable glitch filtering                                                                           ; Off                       ;
-; Do not write top level VHDL entity                                                                ; Off                       ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
-; Architecture name in VHDL output netlist                                                          ; structure                 ;
-; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
-; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-
-
-+----------------------------------------------------------------------------------------------------+
-; Simulation Generated Files                                                                         ;
-+----------------------------------------------------------------------------------------------------+
-; Generated Files                                                                                    ;
-+----------------------------------------------------------------------------------------------------+
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//four_line_to_sixteen_line_decimal_decoder.vo ;
-+----------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit EDA Netlist Writer
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
-    Info: Your use of Altera Corporation's design tools, logic functions 
-    Info: and other software and tools, and its AMPP partner logic 
-    Info: functions, and any output files from any of the foregoing 
-    Info: (including device programming or simulation files), and any 
-    Info: associated documentation or information are expressly subject 
-    Info: to the terms and conditions of the Altera Program License 
-    Info: Subscription Agreement, Altera MegaCore Function License 
-    Info: Agreement, or other applicable license agreement, including, 
-    Info: without limitation, that your use is for the sole purpose of 
-    Info: programming logic devices manufactured by Altera and sold by 
-    Info: Altera or its authorized distributors.  Please refer to the 
-    Info: applicable agreement for further details.
-    Info: Processing started: Thu Oct 24 22:24:52 2019
-Info: Command: quartus_eda --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/ four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder
-Info (204019): Generated file four_line_to_sixteen_line_decimal_decoder.vo in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//" for EDA simulation tool
-Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 348 megabytes
-    Info: Processing ended: Thu Oct 24 22:24:53 2019
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.rpt b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.rpt
deleted file mode 100644
index 9fd983ed..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.rpt
+++ /dev/null
@@ -1,1376 +0,0 @@
-Fitter report for four_line_to_sixteen_line_decimal_decoder
-Thu Oct 24 22:11:27 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. I/O Assignment Warnings
-  6. Incremental Compilation Preservation Summary
-  7. Incremental Compilation Partition Settings
-  8. Incremental Compilation Placement Preservation
-  9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. Fitter Resource Utilization by Entity
- 18. Delay Chain Summary
- 19. Pad To Core Delay Chain Fanout
- 20. Non-Global High Fan-Out Signals
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Fitter Summary                                                                  ;
-+------------------------------------+--------------------------------------------+
-; Fitter Status                      ; Successful - Thu Oct 24 22:11:27 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; four_line_to_sixteen_line_decimal_decoder  ;
-; Top-level Entity Name              ; four_line_to_sixteen_line_decimal_decoder  ;
-; Family                             ; Cyclone III                                ;
-; Device                             ; EP3C16F484C6                               ;
-; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 16 / 15,408 ( < 1 % )                      ;
-;     Total combinational functions  ; 16 / 15,408 ( < 1 % )                      ;
-;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 20 / 347 ( 6 % )                           ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
-; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
-; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
-+------------------------------------+--------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                                            ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option                                                                     ; Setting                               ; Default Value                         ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device                                                                     ; EP3C16F484C6                          ;                                       ;
-; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
-; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
-; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
-; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
-; Use smart compilation                                                      ; Off                                   ; Off                                   ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
-; Enable compact report table                                                ; Off                                   ; Off                                   ;
-; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
-; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
-; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
-; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
-; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
-; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
-; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
-; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
-; SSN Optimization                                                           ; Off                                   ; Off                                   ;
-; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
-; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
-; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
-; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
-; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
-; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
-; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
-; PCI I/O                                                                    ; Off                                   ; Off                                   ;
-; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
-; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
-; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
-; Auto Delay Chains                                                          ; On                                    ; On                                    ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
-; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
-; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
-; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
-; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
-; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
-; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
-; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
-; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
-; Auto Global Clock                                                          ; On                                    ; On                                    ;
-; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
-; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
-; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
-; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
-; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
-; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+------------------------------------------+
-; I/O Assignment Warnings                  ;
-+----------+-------------------------------+
-; Pin Name ; Reason                        ;
-+----------+-------------------------------+
-; Y0       ; Incomplete set of assignments ;
-; Y1       ; Incomplete set of assignments ;
-; Y2       ; Incomplete set of assignments ;
-; Y3       ; Incomplete set of assignments ;
-; Y4       ; Incomplete set of assignments ;
-; Y5       ; Incomplete set of assignments ;
-; Y6       ; Incomplete set of assignments ;
-; Y7       ; Incomplete set of assignments ;
-; Y8       ; Incomplete set of assignments ;
-; Y9       ; Incomplete set of assignments ;
-; Y10      ; Incomplete set of assignments ;
-; Y11      ; Incomplete set of assignments ;
-; Y12      ; Incomplete set of assignments ;
-; Y13      ; Incomplete set of assignments ;
-; Y14      ; Incomplete set of assignments ;
-; Y15      ; Incomplete set of assignments ;
-; D        ; Incomplete set of assignments ;
-; C        ; Incomplete set of assignments ;
-; B        ; Incomplete set of assignments ;
-; A        ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary                                                    ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ;                   ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 67 ) ; 0.00 % ( 0 / 67 )          ; 0.00 % ( 0 / 67 )        ;
-;     -- Achieved     ; 0.00 % ( 0 / 67 ) ; 0.00 % ( 0 / 67 )          ; 0.00 % ( 0 / 67 )        ;
-;                     ;                   ;                            ;                          ;
-; Routing (by net)    ;                   ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings                                                                                                                                             ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation                                                                                     ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 57 )     ; N/A                     ; Source File       ; N/A                 ;       ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                       ;
-+---------------------------------------------+-----------------------+
-; Resource                                    ; Usage                 ;
-+---------------------------------------------+-----------------------+
-; Total logic elements                        ; 16 / 15,408 ( < 1 % ) ;
-;     -- Combinational with no register       ; 16                    ;
-;     -- Register only                        ; 0                     ;
-;     -- Combinational with a register        ; 0                     ;
-;                                             ;                       ;
-; Logic element usage by number of LUT inputs ;                       ;
-;     -- 4 input functions                    ; 16                    ;
-;     -- 3 input functions                    ; 0                     ;
-;     -- <=2 input functions                  ; 0                     ;
-;     -- Register only                        ; 0                     ;
-;                                             ;                       ;
-; Logic elements by mode                      ;                       ;
-;     -- normal mode                          ; 16                    ;
-;     -- arithmetic mode                      ; 0                     ;
-;                                             ;                       ;
-; Total registers*                            ; 0 / 17,068 ( 0 % )    ;
-;     -- Dedicated logic registers            ; 0 / 15,408 ( 0 % )    ;
-;     -- I/O registers                        ; 0 / 1,660 ( 0 % )     ;
-;                                             ;                       ;
-; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )     ;
-; Virtual pins                                ; 0                     ;
-; I/O pins                                    ; 20 / 347 ( 6 % )      ;
-;     -- Clock pins                           ; 0 / 8 ( 0 % )         ;
-;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )         ;
-;                                             ;                       ;
-; Global signals                              ; 0                     ;
-; M9Ks                                        ; 0 / 56 ( 0 % )        ;
-; Total block memory bits                     ; 0 / 516,096 ( 0 % )   ;
-; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )   ;
-; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ;
-; PLLs                                        ; 0 / 4 ( 0 % )         ;
-; Global clocks                               ; 0 / 20 ( 0 % )        ;
-; JTAGs                                       ; 0 / 1 ( 0 % )         ;
-; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
-; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
-; Impedance control blocks                    ; 0 / 4 ( 0 % )         ;
-; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
-; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%          ;
-; Maximum fan-out                             ; 16                    ;
-; Highest non-global fan-out                  ; 16                    ;
-; Total fan-out                               ; 105                   ;
-; Average fan-out                             ; 1.59                  ;
-+---------------------------------------------+-----------------------+
-*  Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics                                                                         ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region                ; Low                  ; Low                            ;
-;                                             ;                      ;                                ;
-; Total logic elements                        ; 16 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
-;     -- Combinational with no register       ; 16                   ; 0                              ;
-;     -- Register only                        ; 0                    ; 0                              ;
-;     -- Combinational with a register        ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Logic element usage by number of LUT inputs ;                      ;                                ;
-;     -- 4 input functions                    ; 16                   ; 0                              ;
-;     -- 3 input functions                    ; 0                    ; 0                              ;
-;     -- <=2 input functions                  ; 0                    ; 0                              ;
-;     -- Register only                        ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Logic elements by mode                      ;                      ;                                ;
-;     -- normal mode                          ; 16                   ; 0                              ;
-;     -- arithmetic mode                      ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Total registers                             ; 0                    ; 0                              ;
-;     -- Dedicated logic registers            ; 0 / 15408 ( 0 % )    ; 0 / 15408 ( 0 % )              ;
-;     -- I/O registers                        ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )    ; 0 / 963 ( 0 % )                ;
-;                                             ;                      ;                                ;
-; Virtual pins                                ; 0                    ; 0                              ;
-; I/O pins                                    ; 20                   ; 0                              ;
-; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ; 0 / 112 ( 0 % )                ;
-; Total memory bits                           ; 0                    ; 0                              ;
-; Total RAM block bits                        ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Connections                                 ;                      ;                                ;
-;     -- Input Connections                    ; 0                    ; 0                              ;
-;     -- Registered Input Connections         ; 0                    ; 0                              ;
-;     -- Output Connections                   ; 0                    ; 0                              ;
-;     -- Registered Output Connections        ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Internal Connections                        ;                      ;                                ;
-;     -- Total Connections                    ; 100                  ; 5                              ;
-;     -- Registered Connections               ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; External Connections                        ;                      ;                                ;
-;     -- Top                                  ; 0                    ; 0                              ;
-;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Partition Interface                         ;                      ;                                ;
-;     -- Input Ports                          ; 4                    ; 0                              ;
-;     -- Output Ports                         ; 16                   ; 0                              ;
-;     -- Bidir Ports                          ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Registered Ports                            ;                      ;                                ;
-;     -- Registered Input Ports               ; 0                    ; 0                              ;
-;     -- Registered Output Ports              ; 0                    ; 0                              ;
-;                                             ;                      ;                                ;
-; Port Connectivity                           ;                      ;                                ;
-;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
-;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
-;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
-;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
-;     -- Input Ports with no Source           ; 0                    ; 0                              ;
-;     -- Output Ports with no Source          ; 0                    ; 0                              ;
-;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
-;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                                                                ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; A    ; AB3   ; 3        ; 7            ; 0            ; 28           ; 16                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
-; B    ; N7    ; 2        ; 0            ; 6            ; 21           ; 16                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
-; C    ; Y1    ; 2        ; 0            ; 6            ; 7            ; 16                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
-; D    ; T5    ; 2        ; 0            ; 3            ; 0            ; 16                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Y0   ; L7    ; 2        ; 0            ; 11           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y1   ; J4    ; 1        ; 0            ; 21           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y10  ; P5    ; 2        ; 0            ; 8            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y11  ; Y2    ; 2        ; 0            ; 6            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y12  ; M7    ; 2        ; 0            ; 8            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y13  ; W2    ; 2        ; 0            ; 7            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y14  ; M3    ; 2        ; 0            ; 12           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y15  ; P6    ; 2        ; 0            ; 4            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y2   ; P7    ; 2        ; 0            ; 5            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y3   ; W1    ; 2        ; 0            ; 7            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y4   ; T7    ; 2        ; 0            ; 2            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y5   ; V1    ; 2        ; 0            ; 8            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y6   ; R6    ; 2        ; 0            ; 3            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y7   ; R9    ; 3        ; 1            ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y8   ; M5    ; 2        ; 0            ; 11           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-; Y9   ; M4    ; 2        ; 0            ; 12           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins                                                                                         ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
-; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
-; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
-; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
-; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
-; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
-; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
-; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
-; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage                                             ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1        ; 5 / 33 ( 15 % )  ; 2.5V          ; --           ;
-; 2        ; 17 / 48 ( 35 % ) ; 2.5V          ; --           ;
-; 3        ; 2 / 46 ( 4 % )   ; 2.5V          ; --           ;
-; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
-; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
-; 6        ; 1 / 43 ( 2 % )   ; 2.5V          ; --           ;
-; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
-; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                                                                        ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AB3      ; 103        ; 3        ; A                                                         ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
-; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; B1       ; 2          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; B2       ; 1          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C1       ; 7          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C2       ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; D2       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E1       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; E3       ; 5          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E4       ; 4          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G4       ; 17         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G5       ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; G21      ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H1       ; 26         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H6       ; 11         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H7       ; 10         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J1       ; 29         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J2       ; 28         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J3       ; 27         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; J4       ; 24         ; 1        ; Y1                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J6       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J7       ; 22         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
-; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L7       ; 50         ; 2        ; Y0                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M3       ; 47         ; 2        ; Y14                                                       ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; M4       ; 46         ; 2        ; Y9                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; M5       ; 51         ; 2        ; Y8                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M7       ; 65         ; 2        ; Y12                                                       ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N7       ; 73         ; 2        ; B                                                         ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P5       ; 63         ; 2        ; Y10                                                       ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; P6       ; 79         ; 2        ; Y15                                                       ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; P7       ; 74         ; 2        ; Y2                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R6       ; 83         ; 2        ; Y6                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R9       ; 88         ; 3        ; Y7                                                        ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
-; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T5       ; 82         ; 2        ; D                                                         ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T7       ; 85         ; 2        ; Y4                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V1       ; 62         ; 2        ; Y5                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W1       ; 69         ; 2        ; Y3                                                        ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; W2       ; 68         ; 2        ; Y13                                                       ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y1       ; 71         ; 2        ; C                                                         ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; Y2       ; 70         ; 2        ; Y11                                                       ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                             ;
-+--------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------+--------------+
-; Compilation Hierarchy Node                 ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                   ; Library Name ;
-+--------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------+--------------+
-; |four_line_to_sixteen_line_decimal_decoder ; 16 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 20   ; 0            ; 16 (0)       ; 0 (0)             ; 0 (0)            ; |four_line_to_sixteen_line_decimal_decoder            ; work         ;
-;    |74138:inst|                            ; 16 (16)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 0 (0)            ; |four_line_to_sixteen_line_decimal_decoder|74138:inst ; work         ;
-+--------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+--------------------------------------------------------------------------------------+
-; Delay Chain Summary                                                                  ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-; Y0   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y1   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y2   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y3   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y4   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y5   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y6   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y7   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y8   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y9   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y10  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y11  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y12  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y13  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y14  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y15  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; D    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; C    ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-; B    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; A    ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+-------------------------------------------------------+
-; Pad To Core Delay Chain Fanout                        ;
-+-------------------------+-------------------+---------+
-; Source Pin / Fanout     ; Pad To Core Index ; Setting ;
-+-------------------------+-------------------+---------+
-; D                       ;                   ;         ;
-;      - 74138:inst|15~0  ; 0                 ; 6       ;
-;      - 74138:inst|15~1  ; 0                 ; 6       ;
-;      - 74138:inst|15~2  ; 0                 ; 6       ;
-;      - 74138:inst|15~3  ; 0                 ; 6       ;
-;      - 74138:inst|15~4  ; 0                 ; 6       ;
-;      - 74138:inst|15~5  ; 0                 ; 6       ;
-;      - 74138:inst|15~6  ; 0                 ; 6       ;
-;      - 74138:inst|15~7  ; 0                 ; 6       ;
-;      - 74138:inst|15~8  ; 0                 ; 6       ;
-;      - 74138:inst|15~9  ; 0                 ; 6       ;
-;      - 74138:inst|15~10 ; 0                 ; 6       ;
-;      - 74138:inst|15~11 ; 0                 ; 6       ;
-;      - 74138:inst|15~12 ; 0                 ; 6       ;
-;      - 74138:inst|15~13 ; 0                 ; 6       ;
-;      - 74138:inst|15~14 ; 0                 ; 6       ;
-;      - 74138:inst|15~15 ; 0                 ; 6       ;
-; C                       ;                   ;         ;
-;      - 74138:inst|15~0  ; 1                 ; 6       ;
-;      - 74138:inst|15~1  ; 1                 ; 6       ;
-;      - 74138:inst|15~2  ; 1                 ; 6       ;
-;      - 74138:inst|15~3  ; 1                 ; 6       ;
-;      - 74138:inst|15~4  ; 1                 ; 6       ;
-;      - 74138:inst|15~5  ; 1                 ; 6       ;
-;      - 74138:inst|15~6  ; 1                 ; 6       ;
-;      - 74138:inst|15~7  ; 1                 ; 6       ;
-;      - 74138:inst|15~8  ; 1                 ; 6       ;
-;      - 74138:inst|15~9  ; 1                 ; 6       ;
-;      - 74138:inst|15~10 ; 1                 ; 6       ;
-;      - 74138:inst|15~11 ; 1                 ; 6       ;
-;      - 74138:inst|15~12 ; 1                 ; 6       ;
-;      - 74138:inst|15~13 ; 1                 ; 6       ;
-;      - 74138:inst|15~14 ; 1                 ; 6       ;
-;      - 74138:inst|15~15 ; 1                 ; 6       ;
-; B                       ;                   ;         ;
-;      - 74138:inst|15~0  ; 0                 ; 6       ;
-;      - 74138:inst|15~1  ; 0                 ; 6       ;
-;      - 74138:inst|15~2  ; 0                 ; 6       ;
-;      - 74138:inst|15~3  ; 0                 ; 6       ;
-;      - 74138:inst|15~4  ; 0                 ; 6       ;
-;      - 74138:inst|15~5  ; 0                 ; 6       ;
-;      - 74138:inst|15~6  ; 0                 ; 6       ;
-;      - 74138:inst|15~7  ; 0                 ; 6       ;
-;      - 74138:inst|15~8  ; 0                 ; 6       ;
-;      - 74138:inst|15~9  ; 0                 ; 6       ;
-;      - 74138:inst|15~10 ; 0                 ; 6       ;
-;      - 74138:inst|15~11 ; 0                 ; 6       ;
-;      - 74138:inst|15~12 ; 0                 ; 6       ;
-;      - 74138:inst|15~13 ; 0                 ; 6       ;
-;      - 74138:inst|15~14 ; 0                 ; 6       ;
-;      - 74138:inst|15~15 ; 0                 ; 6       ;
-; A                       ;                   ;         ;
-;      - 74138:inst|15~0  ; 1                 ; 6       ;
-;      - 74138:inst|15~1  ; 1                 ; 6       ;
-;      - 74138:inst|15~2  ; 1                 ; 6       ;
-;      - 74138:inst|15~3  ; 1                 ; 6       ;
-;      - 74138:inst|15~4  ; 1                 ; 6       ;
-;      - 74138:inst|15~5  ; 1                 ; 6       ;
-;      - 74138:inst|15~6  ; 1                 ; 6       ;
-;      - 74138:inst|15~7  ; 1                 ; 6       ;
-;      - 74138:inst|15~8  ; 1                 ; 6       ;
-;      - 74138:inst|15~9  ; 1                 ; 6       ;
-;      - 74138:inst|15~10 ; 1                 ; 6       ;
-;      - 74138:inst|15~11 ; 1                 ; 6       ;
-;      - 74138:inst|15~12 ; 1                 ; 6       ;
-;      - 74138:inst|15~13 ; 1                 ; 6       ;
-;      - 74138:inst|15~14 ; 1                 ; 6       ;
-;      - 74138:inst|15~15 ; 1                 ; 6       ;
-+-------------------------+-------------------+---------+
-
-
-+---------------------------------+
-; Non-Global High Fan-Out Signals ;
-+------------------+--------------+
-; Name             ; Fan-Out      ;
-+------------------+--------------+
-; A~input          ; 16           ;
-; B~input          ; 16           ;
-; C~input          ; 16           ;
-; D~input          ; 16           ;
-; 74138:inst|15~15 ; 1            ;
-; 74138:inst|15~14 ; 1            ;
-; 74138:inst|15~13 ; 1            ;
-; 74138:inst|15~12 ; 1            ;
-; 74138:inst|15~11 ; 1            ;
-; 74138:inst|15~10 ; 1            ;
-; 74138:inst|15~9  ; 1            ;
-; 74138:inst|15~8  ; 1            ;
-; 74138:inst|15~7  ; 1            ;
-; 74138:inst|15~6  ; 1            ;
-; 74138:inst|15~5  ; 1            ;
-; 74138:inst|15~4  ; 1            ;
-; 74138:inst|15~3  ; 1            ;
-; 74138:inst|15~2  ; 1            ;
-; 74138:inst|15~1  ; 1            ;
-; 74138:inst|15~0  ; 1            ;
-+------------------+--------------+
-
-
-+-----------------------------------------------+
-; Routing Usage Summary                         ;
-+-----------------------+-----------------------+
-; Routing Resource Type ; Usage                 ;
-+-----------------------+-----------------------+
-; Block interconnects   ; 20 / 47,787 ( < 1 % ) ;
-; C16 interconnects     ; 1 / 1,804 ( < 1 % )   ;
-; C4 interconnects      ; 26 / 31,272 ( < 1 % ) ;
-; Direct links          ; 0 / 47,787 ( 0 % )    ;
-; Global clocks         ; 0 / 20 ( 0 % )        ;
-; Local interconnects   ; 0 / 15,408 ( 0 % )    ;
-; R24 interconnects     ; 0 / 1,775 ( 0 % )     ;
-; R4 interconnects      ; 5 / 41,310 ( < 1 % )  ;
-+-----------------------+-----------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements                                                        ;
-+---------------------------------------------+-----------------------------+
-; Number of Logic Elements  (Average = 16.00) ; Number of LABs  (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 1                                           ; 0                           ;
-; 2                                           ; 0                           ;
-; 3                                           ; 0                           ;
-; 4                                           ; 0                           ;
-; 5                                           ; 0                           ;
-; 6                                           ; 0                           ;
-; 7                                           ; 0                           ;
-; 8                                           ; 0                           ;
-; 9                                           ; 0                           ;
-; 10                                          ; 0                           ;
-; 11                                          ; 0                           ;
-; 12                                          ; 0                           ;
-; 13                                          ; 0                           ;
-; 14                                          ; 0                           ;
-; 15                                          ; 0                           ;
-; 16                                          ; 1                           ;
-+---------------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced                                                        ;
-+----------------------------------------------+-----------------------------+
-; Number of Signals Sourced  (Average = 16.00) ; Number of LABs  (Total = 1) ;
-+----------------------------------------------+-----------------------------+
-; 0                                            ; 0                           ;
-; 1                                            ; 0                           ;
-; 2                                            ; 0                           ;
-; 3                                            ; 0                           ;
-; 4                                            ; 0                           ;
-; 5                                            ; 0                           ;
-; 6                                            ; 0                           ;
-; 7                                            ; 0                           ;
-; 8                                            ; 0                           ;
-; 9                                            ; 0                           ;
-; 10                                           ; 0                           ;
-; 11                                           ; 0                           ;
-; 12                                           ; 0                           ;
-; 13                                           ; 0                           ;
-; 14                                           ; 0                           ;
-; 15                                           ; 0                           ;
-; 16                                           ; 1                           ;
-+----------------------------------------------+-----------------------------+
-
-
-+--------------------------------------------------------------------------------+
-; LAB Signals Sourced Out                                                        ;
-+--------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out  (Average = 16.00) ; Number of LABs  (Total = 1) ;
-+--------------------------------------------------+-----------------------------+
-; 0                                                ; 0                           ;
-; 1                                                ; 0                           ;
-; 2                                                ; 0                           ;
-; 3                                                ; 0                           ;
-; 4                                                ; 0                           ;
-; 5                                                ; 0                           ;
-; 6                                                ; 0                           ;
-; 7                                                ; 0                           ;
-; 8                                                ; 0                           ;
-; 9                                                ; 0                           ;
-; 10                                               ; 0                           ;
-; 11                                               ; 0                           ;
-; 12                                               ; 0                           ;
-; 13                                               ; 0                           ;
-; 14                                               ; 0                           ;
-; 15                                               ; 0                           ;
-; 16                                               ; 1                           ;
-+--------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs                                                       ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs  (Average = 4.00) ; Number of LABs  (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0                                           ; 0                           ;
-; 1                                           ; 0                           ;
-; 2                                           ; 0                           ;
-; 3                                           ; 0                           ;
-; 4                                           ; 1                           ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary                        ;
-+----------------------------------+-------+
-; I/O Rules Statistic              ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules                  ; 30    ;
-; Number of I/O Rules Passed       ; 9     ;
-; Number of I/O Rules Failed       ; 0     ;
-; Number of I/O Rules Unchecked    ; 0     ;
-; Number of I/O Rules Inapplicable ; 21    ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
-; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
-; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
-; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
-; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
-; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 20        ; 0            ; 0            ; 20        ; 20        ; 0            ; 16           ; 0            ; 0            ; 4            ; 0            ; 16           ; 4            ; 0            ; 0            ; 0            ; 16           ; 0            ; 0            ; 0            ; 0            ; 0            ; 20        ; 0            ; 0            ;
-; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; Total Inapplicable ; 20           ; 20           ; 20           ; 20           ; 20           ; 0         ; 20           ; 20           ; 0         ; 0         ; 20           ; 4            ; 20           ; 20           ; 16           ; 20           ; 4            ; 16           ; 20           ; 20           ; 20           ; 4            ; 20           ; 20           ; 20           ; 20           ; 20           ; 0         ; 20           ; 20           ;
-; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; Y0                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y1                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y2                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y3                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y4                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y5                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y6                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y7                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y8                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y9                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y10                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y11                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y12                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y13                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y14                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y15                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; D                  ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; C                  ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; B                  ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; A                  ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options                                                                       ;
-+------------------------------------------------------------------+--------------------------+
-; Option                                                           ; Setting                  ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
-; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
-; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
-; Enable INIT_DONE output                                          ; Off                      ;
-; Configuration scheme                                             ; Active Serial            ;
-; Error detection CRC                                              ; Off                      ;
-; Enable open drain on CRC_ERROR pin                               ; Off                      ;
-; Enable input tri-state on active configuration pins in user mode ; Off                      ;
-; Configuration Voltage Level                                      ; Auto                     ;
-; Force Configuration Voltage Level                                ; Off                      ;
-; nCEO                                                             ; As output driving ground ;
-; Data[0]                                                          ; As input tri-stated      ;
-; Data[1]/ASDO                                                     ; As input tri-stated      ;
-; Data[7..2]                                                       ; Unreserved               ;
-; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
-; Other Active Parallel pins                                       ; Unreserved               ;
-; DCLK                                                             ; As output driving ground ;
-; Base pin-out file on sameframe device                            ; Off                      ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions  ;
-+---------------------------+--------+
-; Setting                   ; Value  ;
-+---------------------------+--------+
-; Nominal Core Voltage      ; 1.20 V ;
-; Low Junction Temperature  ; 0 °C   ;
-; High Junction Temperature ; 85 °C  ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (119006): Selected device EP3C16F484C6 for design "four_line_to_sixteen_line_decimal_decoder"
-Info (21077): Core supply voltage is 1.2V
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
-    Info (176445): Device EP3C40F484C6 is compatible
-    Info (176445): Device EP3C55F484C6 is compatible
-    Info (176445): Device EP3C80F484C6 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
-    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
-    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
-    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
-    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
-    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (169085): No exact pin location assignment(s) for 20 pins of 20 total pins
-    Info (169086): Pin Y0 not assigned to an exact location on the device
-    Info (169086): Pin Y1 not assigned to an exact location on the device
-    Info (169086): Pin Y2 not assigned to an exact location on the device
-    Info (169086): Pin Y3 not assigned to an exact location on the device
-    Info (169086): Pin Y4 not assigned to an exact location on the device
-    Info (169086): Pin Y5 not assigned to an exact location on the device
-    Info (169086): Pin Y6 not assigned to an exact location on the device
-    Info (169086): Pin Y7 not assigned to an exact location on the device
-    Info (169086): Pin Y8 not assigned to an exact location on the device
-    Info (169086): Pin Y9 not assigned to an exact location on the device
-    Info (169086): Pin Y10 not assigned to an exact location on the device
-    Info (169086): Pin Y11 not assigned to an exact location on the device
-    Info (169086): Pin Y12 not assigned to an exact location on the device
-    Info (169086): Pin Y13 not assigned to an exact location on the device
-    Info (169086): Pin Y14 not assigned to an exact location on the device
-    Info (169086): Pin Y15 not assigned to an exact location on the device
-    Info (169086): Pin D not assigned to an exact location on the device
-    Info (169086): Pin C not assigned to an exact location on the device
-    Info (169086): Pin B not assigned to an exact location on the device
-    Info (169086): Pin A not assigned to an exact location on the device
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'four_line_to_sixteen_line_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
-    Extra Info (176219): No registers were packed into other blocks
-Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
-    Info (176211): Number of I/O pins in group: 20 (unused VREF, 2.5V VCCIO, 4 input, 16 output, 0 bidirectional)
-        Info (176212): I/O standards used: 2.5 V.
-Info (176215): I/O bank details before I/O pin placement
-    Info (176214): Statistics of I/O banks
-        Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  29 pins available
-        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
-        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
-        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available
-        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
-        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available
-        Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available
-        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:03
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X9_Y9
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
-    Info (170200): Optimizations that may affect the design's timing were skipped
-Info (11888): Total time spent on timing analysis during the Fitter is 0.22 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
-Info (144001): Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.smsg
-Info: Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings
-    Info: Peak virtual memory: 533 megabytes
-    Info: Processing ended: Thu Oct 24 22:11:27 2019
-    Info: Elapsed time: 00:00:12
-    Info: Total CPU time (on all processors): 00:00:12
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.smsg.
-
-
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.smsg b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.smsg
deleted file mode 100644
index 7121cbb1..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.summary b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.summary
deleted file mode 100644
index a9b222c0..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Thu Oct 24 22:11:27 2019
-Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
-Revision Name : four_line_to_sixteen_line_decimal_decoder
-Top-level Entity Name : four_line_to_sixteen_line_decimal_decoder
-Family : Cyclone III
-Device : EP3C16F484C6
-Timing Models : Final
-Total logic elements : 16 / 15,408 ( < 1 % )
-    Total combinational functions : 16 / 15,408 ( < 1 % )
-    Dedicated logic registers : 0 / 15,408 ( 0 % )
-Total registers : 0
-Total pins : 20 / 347 ( 6 % )
-Total virtual pins : 0
-Total memory bits : 0 / 516,096 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.flow.rpt b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.flow.rpt
deleted file mode 100644
index ee025e46..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.flow.rpt
+++ /dev/null
@@ -1,140 +0,0 @@
-Flow report for four_line_to_sixteen_line_decimal_decoder
-Thu Oct 24 22:24:53 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Flow Summary                                                                    ;
-+------------------------------------+--------------------------------------------+
-; Flow Status                        ; Successful - Thu Oct 24 22:24:53 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; four_line_to_sixteen_line_decimal_decoder  ;
-; Top-level Entity Name              ; four_line_to_sixteen_line_decimal_decoder  ;
-; Family                             ; Cyclone III                                ;
-; Device                             ; EP3C16F484C6                               ;
-; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 16 / 15,408 ( < 1 % )                      ;
-;     Total combinational functions  ; 16 / 15,408 ( < 1 % )                      ;
-;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 20 / 347 ( 6 % )                           ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
-; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
-; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
-+------------------------------------+--------------------------------------------+
-
-
-+---------------------------------------------------------------+
-; Flow Settings                                                 ;
-+-------------------+-------------------------------------------+
-; Option            ; Setting                                   ;
-+-------------------+-------------------------------------------+
-; Start date & time ; 10/24/2019 22:11:11                       ;
-; Main task         ; Compilation                               ;
-; Revision Name     ; four_line_to_sixteen_line_decimal_decoder ;
-+-------------------+-------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                            ;
-+-------------------------------------+------------------------+---------------+-------------+----------------+
-; Assignment Name                     ; Value                  ; Default Value ; Entity Name ; Section Id     ;
-+-------------------------------------+------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID               ; 0.157192627132650      ; --            ; --          ; --             ;
-; EDA_OUTPUT_DATA_FORMAT              ; Vhdl                   ; --            ; --          ; eda_simulation ;
-; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (VHDL) ; <None>        ; --          ; --             ;
-; MAX_CORE_JUNCTION_TEMP              ; 85                     ; --            ; --          ; --             ;
-; MIN_CORE_JUNCTION_TEMP              ; 0                      ; --            ; --          ; --             ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                   ; --            ; --          ; --             ;
-; PARTITION_COLOR                     ; 16764057               ; --            ; --          ; Top            ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING  ; --            ; --          ; Top            ;
-; PARTITION_NETLIST_TYPE              ; SOURCE                 ; --            ; --          ; Top            ;
-; PROJECT_OUTPUT_DIRECTORY            ; output_files           ; --            ; --          ; --             ;
-+-------------------------------------+------------------------+---------------+-------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 360 MB              ; 00:00:02                           ;
-; Fitter                    ; 00:00:12     ; 1.0                     ; 533 MB              ; 00:00:12                           ;
-; Assembler                 ; 00:00:02     ; 1.0                     ; 382 MB              ; 00:00:02                           ;
-; TimeQuest Timing Analyzer ; 00:00:03     ; 1.0                     ; 383 MB              ; 00:00:03                           ;
-; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 334 MB              ; 00:00:01                           ;
-; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 348 MB              ; 00:00:01                           ;
-; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 348 MB              ; 00:00:01                           ;
-; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 348 MB              ; 00:00:01                           ;
-; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 348 MB              ; 00:00:01                           ;
-; Total                     ; 00:00:24     ; --                      ; --                  ; 00:00:24                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                              ;
-+---------------------------+-------------------+----------------+------------+----------------+
-; Module Name               ; Machine Hostname  ; OS Name        ; OS Version ; Processor type ;
-+---------------------------+-------------------+----------------+------------+----------------+
-; Analysis & Synthesis      ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; Fitter                    ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; Assembler                 ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; TimeQuest Timing Analyzer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; EDA Netlist Writer        ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; EDA Netlist Writer        ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; EDA Netlist Writer        ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; EDA Netlist Writer        ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; EDA Netlist Writer        ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-+---------------------------+-------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder
-quartus_fit --read_settings_files=off --write_settings_files=off four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder
-quartus_asm --read_settings_files=off --write_settings_files=off four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder
-quartus_sta four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder
-quartus_eda --read_settings_files=off --write_settings_files=off four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder
-quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder --vector_source=/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.vwf --testbench_file=/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.vwf.vt
-quartus_eda --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/ four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder
-quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder --vector_source=/home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.vwf --testbench_file=/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.vwf.vt
-quartus_eda --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/ four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder
-
-
-
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.jdi b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.jdi
deleted file mode 100644
index c17103cf..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="2c956a2ccee9423c6fe1"/>
-  </project>
-  <file_info>
-    <file device="EP3C16F484C6" path="four_line_to_sixteen_line_decimal_decoder.sof" usercode="0xFFFFFFFF"/>
-  </file_info>
-</sld_project_info>
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.map.rpt b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.map.rpt
deleted file mode 100644
index c04e07f9..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.map.rpt
+++ /dev/null
@@ -1,261 +0,0 @@
-Analysis & Synthesis report for four_line_to_sixteen_line_decimal_decoder
-Thu Oct 24 22:11:13 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. General Register Statistics
-  9. Elapsed Time Per Partition
- 10. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                    ;
-+------------------------------------+--------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Thu Oct 24 22:11:13 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; four_line_to_sixteen_line_decimal_decoder  ;
-; Top-level Entity Name              ; four_line_to_sixteen_line_decimal_decoder  ;
-; Family                             ; Cyclone III                                ;
-; Total logic elements               ; 16                                         ;
-;     Total combinational functions  ; 16                                         ;
-;     Dedicated logic registers      ; 0                                          ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 20                                         ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0                                          ;
-; Embedded Multiplier 9-bit elements ; 0                                          ;
-; Total PLLs                         ; 0                                          ;
-+------------------------------------+--------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                                                                      ;
-+----------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+
-; Option                                                                     ; Setting                                   ; Default Value                             ;
-+----------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+
-; Device                                                                     ; EP3C16F484C6                              ;                                           ;
-; Top-level entity name                                                      ; four_line_to_sixteen_line_decimal_decoder ; four_line_to_sixteen_line_decimal_decoder ;
-; Family name                                                                ; Cyclone III                               ; Cyclone IV GX                             ;
-; Use smart compilation                                                      ; Off                                       ; Off                                       ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                        ; On                                        ;
-; Enable compact report table                                                ; Off                                       ; Off                                       ;
-; Restructure Multiplexers                                                   ; Auto                                      ; Auto                                      ;
-; Create Debugging Nodes for IP Cores                                        ; Off                                       ; Off                                       ;
-; Preserve fewer node names                                                  ; On                                        ; On                                        ;
-; Disable OpenCore Plus hardware evaluation                                  ; Off                                       ; Off                                       ;
-; Verilog Version                                                            ; Verilog_2001                              ; Verilog_2001                              ;
-; VHDL Version                                                               ; VHDL_1993                                 ; VHDL_1993                                 ;
-; State Machine Processing                                                   ; Auto                                      ; Auto                                      ;
-; Safe State Machine                                                         ; Off                                       ; Off                                       ;
-; Extract Verilog State Machines                                             ; On                                        ; On                                        ;
-; Extract VHDL State Machines                                                ; On                                        ; On                                        ;
-; Ignore Verilog initial constructs                                          ; Off                                       ; Off                                       ;
-; Iteration limit for constant Verilog loops                                 ; 5000                                      ; 5000                                      ;
-; Iteration limit for non-constant Verilog loops                             ; 250                                       ; 250                                       ;
-; Add Pass-Through Logic to Inferred RAMs                                    ; On                                        ; On                                        ;
-; Infer RAMs from Raw Logic                                                  ; On                                        ; On                                        ;
-; Parallel Synthesis                                                         ; On                                        ; On                                        ;
-; DSP Block Balancing                                                        ; Auto                                      ; Auto                                      ;
-; NOT Gate Push-Back                                                         ; On                                        ; On                                        ;
-; Power-Up Don't Care                                                        ; On                                        ; On                                        ;
-; Remove Redundant Logic Cells                                               ; Off                                       ; Off                                       ;
-; Remove Duplicate Registers                                                 ; On                                        ; On                                        ;
-; Ignore CARRY Buffers                                                       ; Off                                       ; Off                                       ;
-; Ignore CASCADE Buffers                                                     ; Off                                       ; Off                                       ;
-; Ignore GLOBAL Buffers                                                      ; Off                                       ; Off                                       ;
-; Ignore ROW GLOBAL Buffers                                                  ; Off                                       ; Off                                       ;
-; Ignore LCELL Buffers                                                       ; Off                                       ; Off                                       ;
-; Ignore SOFT Buffers                                                        ; On                                        ; On                                        ;
-; Limit AHDL Integers to 32 Bits                                             ; Off                                       ; Off                                       ;
-; Optimization Technique                                                     ; Balanced                                  ; Balanced                                  ;
-; Carry Chain Length                                                         ; 70                                        ; 70                                        ;
-; Auto Carry Chains                                                          ; On                                        ; On                                        ;
-; Auto Open-Drain Pins                                                       ; On                                        ; On                                        ;
-; Perform WYSIWYG Primitive Resynthesis                                      ; Off                                       ; Off                                       ;
-; Auto ROM Replacement                                                       ; On                                        ; On                                        ;
-; Auto RAM Replacement                                                       ; On                                        ; On                                        ;
-; Auto DSP Block Replacement                                                 ; On                                        ; On                                        ;
-; Auto Shift Register Replacement                                            ; Auto                                      ; Auto                                      ;
-; Allow Shift Register Merging across Hierarchies                            ; Auto                                      ; Auto                                      ;
-; Auto Clock Enable Replacement                                              ; On                                        ; On                                        ;
-; Strict RAM Replacement                                                     ; Off                                       ; Off                                       ;
-; Allow Synchronous Control Signals                                          ; On                                        ; On                                        ;
-; Force Use of Synchronous Clear Signals                                     ; Off                                       ; Off                                       ;
-; Auto RAM Block Balancing                                                   ; On                                        ; On                                        ;
-; Auto RAM to Logic Cell Conversion                                          ; Off                                       ; Off                                       ;
-; Auto Resource Sharing                                                      ; Off                                       ; Off                                       ;
-; Allow Any RAM Size For Recognition                                         ; Off                                       ; Off                                       ;
-; Allow Any ROM Size For Recognition                                         ; Off                                       ; Off                                       ;
-; Allow Any Shift Register Size For Recognition                              ; Off                                       ; Off                                       ;
-; Use LogicLock Constraints during Resource Balancing                        ; On                                        ; On                                        ;
-; Ignore translate_off and synthesis_off directives                          ; Off                                       ; Off                                       ;
-; Timing-Driven Synthesis                                                    ; On                                        ; On                                        ;
-; Report Parameter Settings                                                  ; On                                        ; On                                        ;
-; Report Source Assignments                                                  ; On                                        ; On                                        ;
-; Report Connectivity Checks                                                 ; On                                        ; On                                        ;
-; Ignore Maximum Fan-Out Assignments                                         ; Off                                       ; Off                                       ;
-; Synchronization Register Chain Length                                      ; 2                                         ; 2                                         ;
-; PowerPlay Power Optimization                                               ; Normal compilation                        ; Normal compilation                        ;
-; HDL message level                                                          ; Level2                                    ; Level2                                    ;
-; Suppress Register Optimization Related Messages                            ; Off                                       ; Off                                       ;
-; Number of Removed Registers Reported in Synthesis Report                   ; 5000                                      ; 5000                                      ;
-; Number of Swept Nodes Reported in Synthesis Report                         ; 5000                                      ; 5000                                      ;
-; Number of Inverted Registers Reported in Synthesis Report                  ; 100                                       ; 100                                       ;
-; Clock MUX Protection                                                       ; On                                        ; On                                        ;
-; Auto Gated Clock Conversion                                                ; Off                                       ; Off                                       ;
-; Block Design Naming                                                        ; Auto                                      ; Auto                                      ;
-; SDC constraint protection                                                  ; Off                                       ; Off                                       ;
-; Synthesis Effort                                                           ; Auto                                      ; Auto                                      ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                                        ; On                                        ;
-; Pre-Mapping Resynthesis Optimization                                       ; Off                                       ; Off                                       ;
-; Analysis & Synthesis Message Level                                         ; Medium                                    ; Medium                                    ;
-; Disable Register Merging Across Hierarchies                                ; Auto                                      ; Auto                                      ;
-; Resource Aware Inference For Block RAM                                     ; On                                        ; On                                        ;
-; Synthesis Seed                                                             ; 1                                         ; 1                                         ;
-+----------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                                                              ;
-+-----------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path              ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                       ; Library ;
-+-----------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------------+---------+
-; four_line_to_sixteen_line_decimal_decoder.bdf ; yes             ; User Block Diagram/Schematic File  ; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf ;         ;
-; 74138.bdf                                     ; yes             ; Megafunction                       ; /home/timmy/altera/13.1/quartus/libraries/others/maxplus2/74138.bdf                ;         ;
-+-----------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------------+---------+
-
-
-+-------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary           ;
-+---------------------------------------------+---------+
-; Resource                                    ; Usage   ;
-+---------------------------------------------+---------+
-; Estimated Total logic elements              ; 16      ;
-;                                             ;         ;
-; Total combinational functions               ; 16      ;
-; Logic element usage by number of LUT inputs ;         ;
-;     -- 4 input functions                    ; 16      ;
-;     -- 3 input functions                    ; 0       ;
-;     -- <=2 input functions                  ; 0       ;
-;                                             ;         ;
-; Logic elements by mode                      ;         ;
-;     -- normal mode                          ; 16      ;
-;     -- arithmetic mode                      ; 0       ;
-;                                             ;         ;
-; Total registers                             ; 0       ;
-;     -- Dedicated logic registers            ; 0       ;
-;     -- I/O registers                        ; 0       ;
-;                                             ;         ;
-; I/O pins                                    ; 20      ;
-; Embedded Multiplier 9-bit elements          ; 0       ;
-; Maximum fan-out node                        ; D~input ;
-; Maximum fan-out                             ; 16      ;
-; Total fan-out                               ; 100     ;
-; Average fan-out                             ; 1.79    ;
-+---------------------------------------------+---------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                           ;
-+--------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------+--------------+
-; Compilation Hierarchy Node                 ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                   ; Library Name ;
-+--------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------+--------------+
-; |four_line_to_sixteen_line_decimal_decoder ; 16 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 20   ; 0            ; |four_line_to_sixteen_line_decimal_decoder            ; work         ;
-;    |74138:inst|                            ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |four_line_to_sixteen_line_decimal_decoder|74138:inst ; work         ;
-+--------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 0     ;
-; Number of registers using Synchronous Clear  ; 0     ;
-; Number of registers using Synchronous Load   ; 0     ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 0     ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition    ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top            ; 00:00:00     ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit Analysis & Synthesis
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 24 22:11:11 2019
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (12021): Found 1 design units, including 1 entities, in source file four_line_to_sixteen_line_decimal_decoder.bdf
-    Info (12023): Found entity 1: four_line_to_sixteen_line_decimal_decoder
-Info (12127): Elaborating entity "four_line_to_sixteen_line_decimal_decoder" for the top level hierarchy
-Info (12128): Elaborating entity "74138" for hierarchy "74138:inst"
-Info (12130): Elaborated megafunction instantiation "74138:inst"
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
-    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 36 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 4 input pins
-    Info (21059): Implemented 16 output pins
-    Info (21061): Implemented 16 logic cells
-Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 371 megabytes
-    Info: Processing ended: Thu Oct 24 22:11:13 2019
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.map.summary b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.map.summary
deleted file mode 100644
index 27ad28c4..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Thu Oct 24 22:11:13 2019
-Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
-Revision Name : four_line_to_sixteen_line_decimal_decoder
-Top-level Entity Name : four_line_to_sixteen_line_decimal_decoder
-Family : Cyclone III
-Total logic elements : 16
-    Total combinational functions : 16
-    Dedicated logic registers : 0
-Total registers : 0
-Total pins : 20
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.pin b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.pin
deleted file mode 100644
index 05e6752b..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.pin
+++ /dev/null
@@ -1,554 +0,0 @@
- -- Copyright (C) 1991-2013 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Altera Program License 
- -- Subscription Agreement, Altera MegaCore Function License 
- -- Agreement, or other applicable license agreement, including, 
- -- without limitation, that your use is for the sole purpose of 
- -- programming logic devices manufactured by Altera and sold by 
- -- Altera or its authorized distributors.  Please refer to the 
- -- applicable agreement for further details.
- -- 
- -- This is a Quartus II output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus II input file. This file cannot be used
- -- to make Quartus II pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus II help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --					Bank 1:		2.5V
- --					Bank 2:		2.5V
- --					Bank 3:		2.5V
- --					Bank 4:		2.5V
- --					Bank 5:		2.5V
- --					Bank 6:		2.5V
- --					Bank 7:		2.5V
- --					Bank 8:		2.5V
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --					It can also be used to report unused dedicated pins. The connection
- --					on the board for unused dedicated pins depends on whether this will
- --					be used in a future design. One example is device migration. When
- --					using device migration, refer to the device pin-tables. If it is a
- --					GND pin in the pin table or if it will not be used in a future design
- --					for another purpose the it MUST be connected to GND. If it is an unused
- --					dedicated pin, then it can be connected to a valid signal on the board
- --					(low, high, or toggling) if that signal is required for a different
- --					revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --					This pin should be connected to GND. It may also be connected  to a
- --					valid signal  on the board  (low, high, or toggling)  if that signal
- --					is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --           	    or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-CHIP  "four_line_to_sixteen_line_decimal_decoder"  ASSIGNED TO AN: EP3C16F484C6
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : A1        : gnd    :                   :         :           :                
-VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
-GND+                         : A11       :        :                   :         : 8         :                
-GND+                         : A12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
-VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
-GND                          : A22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
-VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
-GND+                         : AA11      :        :                   :         : 3         :                
-GND+                         : AA12      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
-GND                          : AB1       : gnd    :                   :         :           :                
-VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
-A                            : AB3       : input  : 2.5 V             :         : 3         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
-GND                          : AB6       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
-GND+                         : AB11      :        :                   :         : 3         :                
-GND+                         : AB12      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
-VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
-GND                          : AB22      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
-GND+                         : B11       :        :                   :         : 8         :                
-GND+                         : B12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
-GND                          : C5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
-GND                          : C9        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
-GND                          : C11       : gnd    :                   :         :           :                
-GND                          : C12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
-GND                          : C14       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
-GND                          : C16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
-GND                          : C18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 1         :                
-GND                          : D3        : gnd    :                   :         :           :                
-VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
-VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
-GND                          : D7        : gnd    :                   :         :           :                
-GND                          : D8        : gnd    :                   :         :           :                
-VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
-VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
-VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
-VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
-VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
-VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 1         :                
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
-VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
-VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
-GNDA2                        : E18       : gnd    :                   :         :           :                
-VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
-GND                          : E20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2        :        :                   :         : 1         :                
-GND                          : F3        : gnd    :                   :         :           :                
-VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
-GNDA3                        : F5        : gnd    :                   :         :           :                
-VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
-VCCA2                        : F18       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
-GND+                         : G1        :        :                   :         : 1         :                
-GND+                         : G2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
-VCCA3                        : G6        : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
-VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
-GND                          : G20       : gnd    :                   :         :           :                
-GND+                         : G21       :        :                   :         : 6         :                
-GND+                         : G22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
-GND                          : H3        : gnd    :                   :         :           :                
-VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 1         :                
-GND                          : H8        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3        :        :                   :         : 1         :                
-Y1                           : J4        : output : 2.5 V             :         : 1         : N              
-GND                          : J5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 1         :                
-VCCINT                       : J8        : power  :                   : 1.2V    :           :                
-GND                          : J9        : gnd    :                   :         :           :                
-VCCINT                       : J10       : power  :                   : 1.2V    :           :                
-VCCINT                       : J11       : power  :                   : 1.2V    :           :                
-VCCINT                       : J12       : power  :                   : 1.2V    :           :                
-VCCINT                       : J13       : power  :                   : 1.2V    :           :                
-VCCINT                       : J14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
-GND                          : J19       : gnd    :                   :         :           :                
-VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
-~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
-GND                          : K3        : gnd    :                   :         :           :                
-VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
-nCONFIG                      : K5        :        :                   :         : 1         :                
-nSTATUS                      : K6        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
-VCCINT                       : K9        : power  :                   : 1.2V    :           :                
-GND                          : K10       : gnd    :                   :         :           :                
-GND                          : K11       : gnd    :                   :         :           :                
-GND                          : K12       : gnd    :                   :         :           :                
-GND                          : K13       : gnd    :                   :         :           :                
-VCCINT                       : K14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
-MSEL3                        : K20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
-TMS                          : L1        : input  :                   :         : 1         :                
-TCK                          : L2        : input  :                   :         : 1         :                
-nCE                          : L3        :        :                   :         : 1         :                
-TDO                          : L4        : output :                   :         : 1         :                
-TDI                          : L5        : input  :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
-Y0                           : L7        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
-VCCINT                       : L9        : power  :                   : 1.2V    :           :                
-GND                          : L10       : gnd    :                   :         :           :                
-GND                          : L11       : gnd    :                   :         :           :                
-GND                          : L12       : gnd    :                   :         :           :                
-GND                          : L13       : gnd    :                   :         :           :                
-VCCINT                       : L14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
-MSEL2                        : L17       :        :                   :         : 6         :                
-MSEL1                        : L18       :        :                   :         : 6         :                
-VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
-GND                          : L20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
-Y14                          : M3        : output : 2.5 V             :         : 2         : N              
-Y9                           : M4        : output : 2.5 V             :         : 2         : N              
-Y8                           : M5        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
-Y12                          : M7        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
-VCCINT                       : M9        : power  :                   : 1.2V    :           :                
-GND                          : M10       : gnd    :                   :         :           :                
-GND                          : M11       : gnd    :                   :         :           :                
-GND                          : M12       : gnd    :                   :         :           :                
-GND                          : M13       : gnd    :                   :         :           :                
-VCCINT                       : M14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
-MSEL0                        : M17       :        :                   :         : 6         :                
-CONF_DONE                    : M18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
-GND                          : N3        : gnd    :                   :         :           :                
-VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
-B                            : N7        : input  : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
-VCCINT                       : N9        : power  :                   : 1.2V    :           :                
-GND                          : N10       : gnd    :                   :         :           :                
-GND                          : N11       : gnd    :                   :         :           :                
-GND                          : N12       : gnd    :                   :         :           :                
-GND                          : N13       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
-Y10                          : P5        : output : 2.5 V             :         : 2         : N              
-Y15                          : P6        : output : 2.5 V             :         : 2         : N              
-Y2                           : P7        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
-VCCINT                       : P9        : power  :                   : 1.2V    :           :                
-VCCINT                       : P10       : power  :                   : 1.2V    :           :                
-VCCINT                       : P11       : power  :                   : 1.2V    :           :                
-VCCINT                       : P12       : power  :                   : 1.2V    :           :                
-VCCINT                       : P13       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
-VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
-GND                          : P19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
-GND                          : R3        : gnd    :                   :         :           :                
-VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
-Y6                           : R6        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
-Y7                           : R9        : output : 2.5 V             :         : 3         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
-GND+                         : T1        :        :                   :         : 2         :                
-GND+                         : T2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
-D                            : T5        : input  : 2.5 V             :         : 2         : N              
-VCCA1                        : T6        : power  :                   : 2.5V    :           :                
-Y4                           : T7        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
-VCCINT                       : T13       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
-VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
-GND                          : T20       : gnd    :                   :         :           :                
-GND+                         : T21       :        :                   :         : 5         :                
-GND+                         : T22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
-GND                          : U3        : gnd    :                   :         :           :                
-VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
-GNDA1                        : U5        : gnd    :                   :         :           :                
-VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
-VCCINT                       : U16       : power  :                   : 1.2V    :           :                
-VCCINT                       : U17       : power  :                   : 1.2V    :           :                
-VCCA4                        : U18       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
-Y5                           : V1        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
-VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
-GNDA4                        : V18       : gnd    :                   :         :           :                
-VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
-GND                          : V20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
-Y3                           : W1        : output : 2.5 V             :         : 2         : N              
-Y13                          : W2        : output : 2.5 V             :         : 2         : N              
-GND                          : W3        : gnd    :                   :         :           :                
-VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
-VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
-VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
-VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
-VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
-VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
-VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
-C                            : Y1        : input  : 2.5 V             :         : 2         : N              
-Y11                          : Y2        : output : 2.5 V             :         : 2         : N              
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
-GND                          : Y5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
-GND                          : Y9        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
-GND                          : Y11       : gnd    :                   :         :           :                
-GND                          : Y12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
-VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
-GND                          : Y15       : gnd    :                   :         :           :                
-GND                          : Y16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
-GND                          : Y18       : gnd    :                   :         :           :                
-VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
-GND                          : Y20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.sof b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.sof
deleted file mode 100644
index c4bf94251f6d0e13c35645a6f12b812fcaf6b065..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.sta.rpt b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.sta.rpt
deleted file mode 100644
index d3b1a9f6..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.sta.rpt
+++ /dev/null
@@ -1,1000 +0,0 @@
-TimeQuest Timing Analyzer report for four_line_to_sixteen_line_decimal_decoder
-Thu Oct 24 22:11:40 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. Clocks
-  5. Slow 1200mV 85C Model Fmax Summary
-  6. Timing Closure Recommendations
-  7. Slow 1200mV 85C Model Setup Summary
-  8. Slow 1200mV 85C Model Hold Summary
-  9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Propagation Delay
- 13. Minimum Propagation Delay
- 14. Slow 1200mV 85C Model Metastability Report
- 15. Slow 1200mV 0C Model Fmax Summary
- 16. Slow 1200mV 0C Model Setup Summary
- 17. Slow 1200mV 0C Model Hold Summary
- 18. Slow 1200mV 0C Model Recovery Summary
- 19. Slow 1200mV 0C Model Removal Summary
- 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 21. Propagation Delay
- 22. Minimum Propagation Delay
- 23. Slow 1200mV 0C Model Metastability Report
- 24. Fast 1200mV 0C Model Setup Summary
- 25. Fast 1200mV 0C Model Hold Summary
- 26. Fast 1200mV 0C Model Recovery Summary
- 27. Fast 1200mV 0C Model Removal Summary
- 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 29. Propagation Delay
- 30. Minimum Propagation Delay
- 31. Fast 1200mV 0C Model Metastability Report
- 32. Multicorner Timing Analysis Summary
- 33. Propagation Delay
- 34. Minimum Propagation Delay
- 35. Board Trace Model Assignments
- 36. Input Transition Times
- 37. Slow Corner Signal Integrity Metrics
- 38. Fast Corner Signal Integrity Metrics
- 39. Clock Transfers
- 40. Report TCCS
- 41. Report RSKM
- 42. Unconstrained Paths
- 43. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                       ;
-+--------------------+----------------------------------------------------+
-; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name      ; four_line_to_sixteen_line_decimal_decoder          ;
-; Device Family      ; Cyclone III                                        ;
-; Device Name        ; EP3C16F484C6                                       ;
-; Timing Models      ; Final                                              ;
-; Delay Model        ; Combined                                           ;
-; Rise/Fall Delays   ; Enabled                                            ;
-+--------------------+----------------------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 6.798 ;       ;       ; 7.319 ;
-; A          ; Y1          ;       ; 7.231 ; 7.683 ;       ;
-; A          ; Y2          ; 6.929 ;       ;       ; 7.397 ;
-; A          ; Y3          ;       ; 6.969 ; 7.424 ;       ;
-; A          ; Y4          ; 7.216 ;       ;       ; 7.700 ;
-; A          ; Y5          ;       ; 6.982 ; 7.432 ;       ;
-; A          ; Y6          ; 7.262 ;       ;       ; 7.725 ;
-; A          ; Y7          ;       ; 7.145 ; 7.534 ;       ;
-; A          ; Y8          ; 8.214 ;       ;       ; 8.596 ;
-; A          ; Y9          ;       ; 6.924 ; 7.408 ;       ;
-; A          ; Y10         ; 6.922 ;       ;       ; 7.456 ;
-; A          ; Y11         ;       ; 6.966 ; 7.445 ;       ;
-; A          ; Y12         ; 6.896 ;       ;       ; 7.399 ;
-; A          ; Y13         ;       ; 7.140 ; 7.580 ;       ;
-; A          ; Y14         ; 6.901 ;       ;       ; 7.386 ;
-; A          ; Y15         ;       ; 7.097 ; 7.520 ;       ;
-; B          ; Y0          ; 6.758 ;       ;       ; 7.253 ;
-; B          ; Y1          ; 7.146 ;       ;       ; 7.613 ;
-; B          ; Y2          ;       ; 6.888 ; 7.372 ;       ;
-; B          ; Y3          ;       ; 6.855 ; 7.315 ;       ;
-; B          ; Y4          ; 7.204 ;       ;       ; 7.672 ;
-; B          ; Y5          ; 6.883 ;       ;       ; 7.368 ;
-; B          ; Y6          ;       ; 7.175 ; 7.691 ;       ;
-; B          ; Y7          ;       ; 7.044 ; 7.471 ;       ;
-; B          ; Y8          ; 8.180 ;       ;       ; 8.539 ;
-; B          ; Y9          ; 6.853 ;       ;       ; 7.311 ;
-; B          ; Y10         ;       ; 6.913 ; 7.311 ;       ;
-; B          ; Y11         ;       ; 6.879 ; 7.336 ;       ;
-; B          ; Y12         ; 6.887 ;       ;       ; 7.368 ;
-; B          ; Y13         ; 7.049 ;       ;       ; 7.534 ;
-; B          ; Y14         ;       ; 6.838 ; 7.336 ;       ;
-; B          ; Y15         ;       ; 6.967 ; 7.423 ;       ;
-; C          ; Y0          ; 6.760 ;       ;       ; 7.280 ;
-; C          ; Y1          ; 7.146 ;       ;       ; 7.640 ;
-; C          ; Y2          ; 6.927 ;       ;       ; 7.405 ;
-; C          ; Y3          ; 6.869 ;       ;       ; 7.387 ;
-; C          ; Y4          ;       ; 7.175 ; 7.671 ;       ;
-; C          ; Y5          ;       ; 6.867 ; 7.343 ;       ;
-; C          ; Y6          ;       ; 7.175 ; 7.716 ;       ;
-; C          ; Y7          ;       ; 7.043 ; 7.494 ;       ;
-; C          ; Y8          ; 8.174 ;       ;       ; 8.566 ;
-; C          ; Y9          ; 6.847 ;       ;       ; 7.338 ;
-; C          ; Y10         ; 6.895 ;       ;       ; 7.422 ;
-; C          ; Y11         ; 6.915 ;       ;       ; 7.395 ;
-; C          ; Y12         ;       ; 6.871 ; 7.335 ;       ;
-; C          ; Y13         ;       ; 7.042 ; 7.488 ;       ;
-; C          ; Y14         ;       ; 6.837 ; 7.367 ;       ;
-; C          ; Y15         ;       ; 6.967 ; 7.452 ;       ;
-; D          ; Y0          ; 6.811 ;       ;       ; 7.327 ;
-; D          ; Y1          ; 7.218 ;       ;       ; 7.700 ;
-; D          ; Y2          ; 6.930 ;       ;       ; 7.398 ;
-; D          ; Y3          ; 6.970 ;       ;       ; 7.456 ;
-; D          ; Y4          ; 7.225 ;       ;       ; 7.703 ;
-; D          ; Y5          ; 6.982 ;       ;       ; 7.464 ;
-; D          ; Y6          ; 7.271 ;       ;       ; 7.736 ;
-; D          ; Y7          ; 7.073 ;       ;       ; 7.620 ;
-; D          ; Y8          ;       ; 8.121 ; 8.709 ;       ;
-; D          ; Y9          ;       ; 6.941 ; 7.446 ;       ;
-; D          ; Y10         ;       ; 6.993 ; 7.434 ;       ;
-; D          ; Y11         ;       ; 6.985 ; 7.485 ;       ;
-; D          ; Y12         ;       ; 6.931 ; 7.405 ;       ;
-; D          ; Y13         ;       ; 7.152 ; 7.624 ;       ;
-; D          ; Y14         ;       ; 6.921 ; 7.415 ;       ;
-; D          ; Y15         ;       ; 7.109 ; 7.571 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 6.631 ;       ;       ; 7.141 ;
-; A          ; Y1          ;       ; 7.048 ; 7.488 ;       ;
-; A          ; Y2          ; 6.760 ;       ;       ; 7.219 ;
-; A          ; Y3          ;       ; 6.802 ; 7.244 ;       ;
-; A          ; Y4          ; 7.035 ;       ;       ; 7.509 ;
-; A          ; Y5          ;       ; 6.814 ; 7.252 ;       ;
-; A          ; Y6          ; 7.080 ;       ;       ; 7.533 ;
-; A          ; Y7          ;       ; 6.962 ; 7.341 ;       ;
-; A          ; Y8          ; 8.047 ;       ;       ; 8.417 ;
-; A          ; Y9          ;       ; 6.757 ; 7.227 ;       ;
-; A          ; Y10         ; 6.749 ;       ;       ; 7.272 ;
-; A          ; Y11         ;       ; 6.799 ; 7.265 ;       ;
-; A          ; Y12         ; 6.729 ;       ;       ; 7.221 ;
-; A          ; Y13         ;       ; 6.965 ; 7.395 ;       ;
-; A          ; Y14         ; 6.734 ;       ;       ; 7.208 ;
-; A          ; Y15         ;       ; 6.923 ; 7.336 ;       ;
-; B          ; Y0          ; 6.596 ;       ;       ; 7.078 ;
-; B          ; Y1          ; 6.967 ;       ;       ; 7.423 ;
-; B          ; Y2          ;       ; 6.725 ; 7.193 ;       ;
-; B          ; Y3          ;       ; 6.694 ; 7.141 ;       ;
-; B          ; Y4          ; 7.028 ;       ;       ; 7.483 ;
-; B          ; Y5          ; 6.721 ;       ;       ; 7.193 ;
-; B          ; Y6          ;       ; 7.001 ; 7.501 ;       ;
-; B          ; Y7          ;       ; 6.869 ; 7.282 ;       ;
-; B          ; Y8          ; 8.018 ;       ;       ; 8.363 ;
-; B          ; Y9          ; 6.690 ;       ;       ; 7.138 ;
-; B          ; Y10         ;       ; 6.746 ; 7.131 ;       ;
-; B          ; Y11         ;       ; 6.718 ; 7.162 ;       ;
-; B          ; Y12         ; 6.723 ;       ;       ; 7.192 ;
-; B          ; Y13         ; 6.882 ;       ;       ; 7.352 ;
-; B          ; Y14         ;       ; 6.678 ; 7.159 ;       ;
-; B          ; Y15         ;       ; 6.803 ; 7.243 ;       ;
-; C          ; Y0          ; 6.600 ;       ;       ; 7.105 ;
-; C          ; Y1          ; 6.969 ;       ;       ; 7.451 ;
-; C          ; Y2          ; 6.763 ;       ;       ; 7.228 ;
-; C          ; Y3          ; 6.709 ;       ;       ; 7.212 ;
-; C          ; Y4          ;       ; 7.003 ; 7.482 ;       ;
-; C          ; Y5          ;       ; 6.708 ; 7.170 ;       ;
-; C          ; Y6          ;       ; 7.002 ; 7.527 ;       ;
-; C          ; Y7          ;       ; 6.870 ; 7.305 ;       ;
-; C          ; Y8          ; 8.012 ;       ;       ; 8.390 ;
-; C          ; Y9          ; 6.687 ;       ;       ; 7.165 ;
-; C          ; Y10         ; 6.729 ;       ;       ; 7.241 ;
-; C          ; Y11         ; 6.754 ;       ;       ; 7.220 ;
-; C          ; Y12         ;       ; 6.711 ; 7.160 ;       ;
-; C          ; Y13         ;       ; 6.875 ; 7.310 ;       ;
-; C          ; Y14         ;       ; 6.678 ; 7.191 ;       ;
-; C          ; Y15         ;       ; 6.804 ; 7.272 ;       ;
-; D          ; Y0          ; 6.647 ;       ;       ; 7.149 ;
-; D          ; Y1          ; 7.037 ;       ;       ; 7.505 ;
-; D          ; Y2          ; 6.764 ;       ;       ; 7.219 ;
-; D          ; Y3          ; 6.804 ;       ;       ; 7.276 ;
-; D          ; Y4          ; 7.047 ;       ;       ; 7.512 ;
-; D          ; Y5          ; 6.817 ;       ;       ; 7.283 ;
-; D          ; Y6          ; 7.092 ;       ;       ; 7.544 ;
-; D          ; Y7          ; 6.895 ;       ;       ; 7.427 ;
-; D          ; Y8          ;       ; 7.956 ; 8.530 ;       ;
-; D          ; Y9          ;       ; 6.775 ; 7.264 ;       ;
-; D          ; Y10         ;       ; 6.822 ; 7.249 ;       ;
-; D          ; Y11         ;       ; 6.819 ; 7.304 ;       ;
-; D          ; Y12         ;       ; 6.766 ; 7.225 ;       ;
-; D          ; Y13         ;       ; 6.979 ; 7.438 ;       ;
-; D          ; Y14         ;       ; 6.756 ; 7.235 ;       ;
-; D          ; Y15         ;       ; 6.937 ; 7.385 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-----------------------------------------------
-; Slow 1200mV 85C Model Metastability Report ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 6.324 ;       ;       ; 6.757 ;
-; A          ; Y1          ;       ; 6.738 ; 7.057 ;       ;
-; A          ; Y2          ; 6.433 ;       ;       ; 6.832 ;
-; A          ; Y3          ;       ; 6.502 ; 6.850 ;       ;
-; A          ; Y4          ; 6.704 ;       ;       ; 7.111 ;
-; A          ; Y5          ;       ; 6.510 ; 6.846 ;       ;
-; A          ; Y6          ; 6.745 ;       ;       ; 7.132 ;
-; A          ; Y7          ;       ; 6.656 ; 6.947 ;       ;
-; A          ; Y8          ; 7.738 ;       ;       ; 8.031 ;
-; A          ; Y9          ;       ; 6.457 ; 6.816 ;       ;
-; A          ; Y10         ; 6.421 ;       ;       ; 6.894 ;
-; A          ; Y11         ;       ; 6.499 ; 6.845 ;       ;
-; A          ; Y12         ; 6.410 ;       ;       ; 6.834 ;
-; A          ; Y13         ;       ; 6.670 ; 6.974 ;       ;
-; A          ; Y14         ; 6.407 ;       ;       ; 6.819 ;
-; A          ; Y15         ;       ; 6.627 ; 6.940 ;       ;
-; B          ; Y0          ; 6.243 ;       ;       ; 6.676 ;
-; B          ; Y1          ; 6.579 ;       ;       ; 7.013 ;
-; B          ; Y2          ;       ; 6.379 ; 6.766 ;       ;
-; B          ; Y3          ;       ; 6.354 ; 6.735 ;       ;
-; B          ; Y4          ; 6.649 ;       ;       ; 7.065 ;
-; B          ; Y5          ; 6.353 ;       ;       ; 6.785 ;
-; B          ; Y6          ;       ; 6.640 ; 7.062 ;       ;
-; B          ; Y7          ;       ; 6.519 ; 6.873 ;       ;
-; B          ; Y8          ; 7.666 ;       ;       ; 7.963 ;
-; B          ; Y9          ; 6.326 ;       ;       ; 6.738 ;
-; B          ; Y10         ;       ; 6.410 ; 6.707 ;       ;
-; B          ; Y11         ;       ; 6.376 ; 6.741 ;       ;
-; B          ; Y12         ; 6.358 ;       ;       ; 6.790 ;
-; B          ; Y13         ; 6.500 ;       ;       ; 6.956 ;
-; B          ; Y14         ;       ; 6.332 ; 6.731 ;       ;
-; B          ; Y15         ;       ; 6.467 ; 6.832 ;       ;
-; C          ; Y0          ; 6.262 ;       ;       ; 6.718 ;
-; C          ; Y1          ; 6.598 ;       ;       ; 7.058 ;
-; C          ; Y2          ; 6.402 ;       ;       ; 6.842 ;
-; C          ; Y3          ; 6.369 ;       ;       ; 6.825 ;
-; C          ; Y4          ;       ; 6.661 ; 7.067 ;       ;
-; C          ; Y5          ;       ; 6.380 ; 6.764 ;       ;
-; C          ; Y6          ;       ; 6.654 ; 7.104 ;       ;
-; C          ; Y7          ;       ; 6.537 ; 6.915 ;       ;
-; C          ; Y8          ; 7.679 ;       ;       ; 8.008 ;
-; C          ; Y9          ; 6.341 ;       ;       ; 6.782 ;
-; C          ; Y10         ; 6.371 ;       ;       ; 6.865 ;
-; C          ; Y11         ; 6.398 ;       ;       ; 6.836 ;
-; C          ; Y12         ;       ; 6.383 ; 6.759 ;       ;
-; C          ; Y13         ;       ; 6.555 ; 6.892 ;       ;
-; C          ; Y14         ;       ; 6.347 ; 6.781 ;       ;
-; C          ; Y15         ;       ; 6.482 ; 6.878 ;       ;
-; D          ; Y0          ; 6.287 ;       ;       ; 6.737 ;
-; D          ; Y1          ; 6.640 ;       ;       ; 7.081 ;
-; D          ; Y2          ; 6.386 ;       ;       ; 6.806 ;
-; D          ; Y3          ; 6.442 ;       ;       ; 6.862 ;
-; D          ; Y4          ; 6.666 ;       ;       ; 7.087 ;
-; D          ; Y5          ; 6.442 ;       ;       ; 6.868 ;
-; D          ; Y6          ; 6.706 ;       ;       ; 7.116 ;
-; D          ; Y7          ; 6.534 ;       ;       ; 7.007 ;
-; D          ; Y8          ;       ; 7.605 ; 8.105 ;       ;
-; D          ; Y9          ;       ; 6.423 ; 6.826 ;       ;
-; D          ; Y10         ;       ; 6.478 ; 6.807 ;       ;
-; D          ; Y11         ;       ; 6.468 ; 6.864 ;       ;
-; D          ; Y12         ;       ; 6.414 ; 6.792 ;       ;
-; D          ; Y13         ;       ; 6.634 ; 6.988 ;       ;
-; D          ; Y14         ;       ; 6.406 ; 6.793 ;       ;
-; D          ; Y15         ;       ; 6.591 ; 6.959 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 6.179 ;       ;       ; 6.602 ;
-; A          ; Y1          ;       ; 6.579 ; 6.890 ;       ;
-; A          ; Y2          ; 6.288 ;       ;       ; 6.678 ;
-; A          ; Y3          ;       ; 6.357 ; 6.698 ;       ;
-; A          ; Y4          ; 6.548 ;       ;       ; 6.945 ;
-; A          ; Y5          ;       ; 6.365 ; 6.693 ;       ;
-; A          ; Y6          ; 6.587 ;       ;       ; 6.966 ;
-; A          ; Y7          ;       ; 6.497 ; 6.781 ;       ;
-; A          ; Y8          ; 7.593 ;       ;       ; 7.878 ;
-; A          ; Y9          ;       ; 6.311 ; 6.662 ;       ;
-; A          ; Y10         ; 6.272 ;       ;       ; 6.735 ;
-; A          ; Y11         ;       ; 6.354 ; 6.693 ;       ;
-; A          ; Y12         ; 6.266 ;       ;       ; 6.680 ;
-; A          ; Y13         ;       ; 6.518 ; 6.818 ;       ;
-; A          ; Y14         ; 6.263 ;       ;       ; 6.665 ;
-; A          ; Y15         ;       ; 6.476 ; 6.783 ;       ;
-; B          ; Y0          ; 6.105 ;       ;       ; 6.525 ;
-; B          ; Y1          ; 6.426 ;       ;       ; 6.851 ;
-; B          ; Y2          ;       ; 6.240 ; 6.614 ;       ;
-; B          ; Y3          ;       ; 6.217 ; 6.587 ;       ;
-; B          ; Y4          ; 6.497 ;       ;       ; 6.903 ;
-; B          ; Y5          ; 6.216 ;       ;       ; 6.637 ;
-; B          ; Y6          ;       ; 6.489 ; 6.899 ;       ;
-; B          ; Y7          ;       ; 6.369 ; 6.710 ;       ;
-; B          ; Y8          ; 7.526 ;       ;       ; 7.815 ;
-; B          ; Y9          ; 6.188 ;       ;       ; 6.589 ;
-; B          ; Y10         ;       ; 6.266 ; 6.555 ;       ;
-; B          ; Y11         ;       ; 6.239 ; 6.593 ;       ;
-; B          ; Y12         ; 6.219 ;       ;       ; 6.638 ;
-; B          ; Y13         ; 6.359 ;       ;       ; 6.801 ;
-; B          ; Y14         ;       ; 6.195 ; 6.583 ;       ;
-; B          ; Y15         ;       ; 6.325 ; 6.680 ;       ;
-; C          ; Y0          ; 6.124 ;       ;       ; 6.567 ;
-; C          ; Y1          ; 6.446 ;       ;       ; 6.896 ;
-; C          ; Y2          ; 6.264 ;       ;       ; 6.691 ;
-; C          ; Y3          ; 6.233 ;       ;       ; 6.676 ;
-; C          ; Y4          ;       ; 6.511 ; 6.905 ;       ;
-; C          ; Y5          ;       ; 6.244 ; 6.617 ;       ;
-; C          ; Y6          ;       ; 6.506 ; 6.941 ;       ;
-; C          ; Y7          ;       ; 6.387 ; 6.751 ;       ;
-; C          ; Y8          ; 7.540 ;       ;       ; 7.859 ;
-; C          ; Y9          ; 6.203 ;       ;       ; 6.633 ;
-; C          ; Y10         ; 6.229 ;       ;       ; 6.709 ;
-; C          ; Y11         ; 6.261 ;       ;       ; 6.687 ;
-; C          ; Y12         ;       ; 6.244 ; 6.610 ;       ;
-; C          ; Y13         ;       ; 6.412 ; 6.741 ;       ;
-; C          ; Y14         ;       ; 6.211 ; 6.631 ;       ;
-; C          ; Y15         ;       ; 6.341 ; 6.724 ;       ;
-; D          ; Y0          ; 6.145 ;       ;       ; 6.584 ;
-; D          ; Y1          ; 6.484 ;       ;       ; 6.916 ;
-; D          ; Y2          ; 6.245 ;       ;       ; 6.654 ;
-; D          ; Y3          ; 6.300 ;       ;       ; 6.710 ;
-; D          ; Y4          ; 6.513 ;       ;       ; 6.924 ;
-; D          ; Y5          ; 6.300 ;       ;       ; 6.716 ;
-; D          ; Y6          ; 6.552 ;       ;       ; 6.952 ;
-; D          ; Y7          ; 6.379 ;       ;       ; 6.842 ;
-; D          ; Y8          ;       ; 7.465 ; 7.952 ;       ;
-; D          ; Y9          ;       ; 6.280 ; 6.672 ;       ;
-; D          ; Y10         ;       ; 6.331 ; 6.650 ;       ;
-; D          ; Y11         ;       ; 6.326 ; 6.711 ;       ;
-; D          ; Y12         ;       ; 6.273 ; 6.640 ;       ;
-; D          ; Y13         ;       ; 6.485 ; 6.830 ;       ;
-; D          ; Y14         ;       ; 6.264 ; 6.641 ;       ;
-; D          ; Y15         ;       ; 6.443 ; 6.800 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
----------------------------------------------
-; Slow 1200mV 0C Model Metastability Report ;
----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 4.100 ;       ;       ; 4.670 ;
-; A          ; Y1          ;       ; 4.275 ; 4.984 ;       ;
-; A          ; Y2          ; 4.170 ;       ;       ; 4.782 ;
-; A          ; Y3          ;       ; 4.192 ; 4.837 ;       ;
-; A          ; Y4          ; 4.358 ;       ;       ; 4.945 ;
-; A          ; Y5          ;       ; 4.186 ; 4.834 ;       ;
-; A          ; Y6          ; 4.383 ;       ;       ; 4.963 ;
-; A          ; Y7          ;       ; 4.199 ; 4.885 ;       ;
-; A          ; Y8          ; 5.120 ;       ;       ; 5.582 ;
-; A          ; Y9          ;       ; 4.158 ; 4.800 ;       ;
-; A          ; Y10         ; 4.165 ;       ;       ; 4.728 ;
-; A          ; Y11         ;       ; 4.197 ; 4.834 ;       ;
-; A          ; Y12         ; 4.163 ;       ;       ; 4.766 ;
-; A          ; Y13         ;       ; 4.266 ; 4.922 ;       ;
-; A          ; Y14         ; 4.155 ;       ;       ; 4.763 ;
-; A          ; Y15         ;       ; 4.224 ; 4.875 ;       ;
-; B          ; Y0          ; 4.055 ;       ;       ; 4.592 ;
-; B          ; Y1          ; 4.308 ;       ;       ; 4.818 ;
-; B          ; Y2          ;       ; 4.124 ; 4.742 ;       ;
-; B          ; Y3          ;       ; 4.117 ; 4.733 ;       ;
-; B          ; Y4          ; 4.333 ;       ;       ; 4.899 ;
-; B          ; Y5          ; 4.143 ;       ;       ; 4.726 ;
-; B          ; Y6          ;       ; 4.275 ; 4.940 ;       ;
-; B          ; Y7          ;       ; 4.134 ; 4.818 ;       ;
-; B          ; Y8          ; 5.085 ;       ;       ; 5.521 ;
-; B          ; Y9          ; 4.119 ;       ;       ; 4.698 ;
-; B          ; Y10         ;       ; 4.049 ; 4.703 ;       ;
-; B          ; Y11         ;       ; 4.137 ; 4.747 ;       ;
-; B          ; Y12         ; 4.142 ;       ;       ; 4.725 ;
-; B          ; Y13         ; 4.245 ;       ;       ; 4.817 ;
-; B          ; Y14         ;       ; 4.089 ; 4.721 ;       ;
-; B          ; Y15         ;       ; 4.135 ; 4.778 ;       ;
-; C          ; Y0          ; 4.084 ;       ;       ; 4.623 ;
-; C          ; Y1          ; 4.337 ;       ;       ; 4.851 ;
-; C          ; Y2          ; 4.187 ;       ;       ; 4.772 ;
-; C          ; Y3          ; 4.181 ;       ;       ; 4.764 ;
-; C          ; Y4          ;       ; 4.307 ; 4.946 ;       ;
-; C          ; Y5          ;       ; 4.133 ; 4.752 ;       ;
-; C          ; Y6          ;       ; 4.304 ; 4.966 ;       ;
-; C          ; Y7          ;       ; 4.162 ; 4.844 ;       ;
-; C          ; Y8          ; 5.113 ;       ;       ; 5.552 ;
-; C          ; Y9          ; 4.147 ;       ;       ; 4.732 ;
-; C          ; Y10         ; 4.160 ;       ;       ; 4.692 ;
-; C          ; Y11         ; 4.201 ;       ;       ; 4.781 ;
-; C          ; Y12         ;       ; 4.131 ; 4.747 ;       ;
-; C          ; Y13         ;       ; 4.223 ; 4.847 ;       ;
-; C          ; Y14         ;       ; 4.120 ; 4.752 ;       ;
-; C          ; Y15         ;       ; 4.165 ; 4.807 ;       ;
-; D          ; Y0          ; 4.113 ;       ;       ; 4.660 ;
-; D          ; Y1          ; 4.365 ;       ;       ; 4.877 ;
-; D          ; Y2          ; 4.174 ;       ;       ; 4.759 ;
-; D          ; Y3          ; 4.229 ;       ;       ; 4.809 ;
-; D          ; Y4          ; 4.370 ;       ;       ; 4.934 ;
-; D          ; Y5          ; 4.229 ;       ;       ; 4.806 ;
-; D          ; Y6          ; 4.398 ;       ;       ; 4.955 ;
-; D          ; Y7          ; 4.269 ;       ;       ; 4.806 ;
-; D          ; Y8          ;       ; 4.955 ; 5.735 ;       ;
-; D          ; Y9          ;       ; 4.169 ; 4.805 ;       ;
-; D          ; Y10         ;       ; 4.119 ; 4.800 ;       ;
-; D          ; Y11         ;       ; 4.215 ; 4.848 ;       ;
-; D          ; Y12         ;       ; 4.150 ; 4.787 ;       ;
-; D          ; Y13         ;       ; 4.285 ; 4.936 ;       ;
-; D          ; Y14         ;       ; 4.150 ; 4.784 ;       ;
-; D          ; Y15         ;       ; 4.243 ; 4.890 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 4.004 ;       ;       ; 4.566 ;
-; A          ; Y1          ;       ; 4.170 ; 4.869 ;       ;
-; A          ; Y2          ; 4.074 ;       ;       ; 4.676 ;
-; A          ; Y3          ;       ; 4.098 ; 4.731 ;       ;
-; A          ; Y4          ; 4.255 ;       ;       ; 4.834 ;
-; A          ; Y5          ;       ; 4.092 ; 4.729 ;       ;
-; A          ; Y6          ; 4.279 ;       ;       ; 4.850 ;
-; A          ; Y7          ;       ; 4.095 ; 4.770 ;       ;
-; A          ; Y8          ; 5.025 ;       ;       ; 5.478 ;
-; A          ; Y9          ;       ; 4.062 ; 4.694 ;       ;
-; A          ; Y10         ; 4.067 ;       ;       ; 4.621 ;
-; A          ; Y11         ;       ; 4.102 ; 4.729 ;       ;
-; A          ; Y12         ; 4.069 ;       ;       ; 4.662 ;
-; A          ; Y13         ;       ; 4.169 ; 4.813 ;       ;
-; A          ; Y14         ; 4.060 ;       ;       ; 4.659 ;
-; A          ; Y15         ;       ; 4.127 ; 4.767 ;       ;
-; B          ; Y0          ; 3.958 ;       ;       ; 4.491 ;
-; B          ; Y1          ; 4.202 ;       ;       ; 4.706 ;
-; B          ; Y2          ;       ; 4.028 ; 4.638 ;       ;
-; B          ; Y3          ;       ; 4.023 ; 4.630 ;       ;
-; B          ; Y4          ; 4.227 ;       ;       ; 4.789 ;
-; B          ; Y5          ; 4.046 ;       ;       ; 4.625 ;
-; B          ; Y6          ;       ; 4.173 ; 4.826 ;       ;
-; B          ; Y7          ;       ; 4.031 ; 4.704 ;       ;
-; B          ; Y8          ; 4.988 ;       ;       ; 5.419 ;
-; B          ; Y9          ; 4.024 ;       ;       ; 4.595 ;
-; B          ; Y10         ;       ; 3.952 ; 4.598 ;       ;
-; B          ; Y11         ;       ; 4.044 ; 4.644 ;       ;
-; B          ; Y12         ; 4.044 ;       ;       ; 4.621 ;
-; B          ; Y13         ; 4.145 ;       ;       ; 4.712 ;
-; B          ; Y14         ;       ; 3.995 ; 4.618 ;       ;
-; B          ; Y15         ;       ; 4.039 ; 4.672 ;       ;
-; C          ; Y0          ; 3.988 ;       ;       ; 4.522 ;
-; C          ; Y1          ; 4.232 ;       ;       ; 4.739 ;
-; C          ; Y2          ; 4.088 ;       ;       ; 4.667 ;
-; C          ; Y3          ; 4.085 ;       ;       ; 4.663 ;
-; C          ; Y4          ;       ; 4.206 ; 4.836 ;       ;
-; C          ; Y5          ;       ; 4.040 ; 4.650 ;       ;
-; C          ; Y6          ;       ; 4.202 ; 4.854 ;       ;
-; C          ; Y7          ;       ; 4.059 ; 4.730 ;       ;
-; C          ; Y8          ; 5.017 ;       ;       ; 5.450 ;
-; C          ; Y9          ; 4.052 ;       ;       ; 4.629 ;
-; C          ; Y10         ; 4.060 ;       ;       ; 4.586 ;
-; C          ; Y11         ; 4.105 ;       ;       ; 4.680 ;
-; C          ; Y12         ;       ; 4.036 ; 4.644 ;       ;
-; C          ; Y13         ;       ; 4.127 ; 4.742 ;       ;
-; C          ; Y14         ;       ; 4.026 ; 4.649 ;       ;
-; C          ; Y15         ;       ; 4.069 ; 4.701 ;       ;
-; D          ; Y0          ; 4.013 ;       ;       ; 4.554 ;
-; D          ; Y1          ; 4.255 ;       ;       ; 4.762 ;
-; D          ; Y2          ; 4.075 ;       ;       ; 4.653 ;
-; D          ; Y3          ; 4.129 ;       ;       ; 4.704 ;
-; D          ; Y4          ; 4.263 ;       ;       ; 4.821 ;
-; D          ; Y5          ; 4.129 ;       ;       ; 4.700 ;
-; D          ; Y6          ; 4.290 ;       ;       ; 4.842 ;
-; D          ; Y7          ; 4.160 ;       ;       ; 4.692 ;
-; D          ; Y8          ;       ; 4.858 ; 5.628 ;       ;
-; D          ; Y9          ;       ; 4.070 ; 4.698 ;       ;
-; D          ; Y10         ;       ; 4.018 ; 4.690 ;       ;
-; D          ; Y11         ;       ; 4.117 ; 4.741 ;       ;
-; D          ; Y12         ;       ; 4.052 ; 4.681 ;       ;
-; D          ; Y13         ;       ; 4.184 ; 4.826 ;       ;
-; D          ; Y14         ;       ; 4.052 ; 4.678 ;       ;
-; D          ; Y15         ;       ; 4.142 ; 4.779 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
----------------------------------------------
-; Fast 1200mV 0C Model Metastability Report ;
----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary                                        ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
-; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 6.798 ;       ;       ; 7.319 ;
-; A          ; Y1          ;       ; 7.231 ; 7.683 ;       ;
-; A          ; Y2          ; 6.929 ;       ;       ; 7.397 ;
-; A          ; Y3          ;       ; 6.969 ; 7.424 ;       ;
-; A          ; Y4          ; 7.216 ;       ;       ; 7.700 ;
-; A          ; Y5          ;       ; 6.982 ; 7.432 ;       ;
-; A          ; Y6          ; 7.262 ;       ;       ; 7.725 ;
-; A          ; Y7          ;       ; 7.145 ; 7.534 ;       ;
-; A          ; Y8          ; 8.214 ;       ;       ; 8.596 ;
-; A          ; Y9          ;       ; 6.924 ; 7.408 ;       ;
-; A          ; Y10         ; 6.922 ;       ;       ; 7.456 ;
-; A          ; Y11         ;       ; 6.966 ; 7.445 ;       ;
-; A          ; Y12         ; 6.896 ;       ;       ; 7.399 ;
-; A          ; Y13         ;       ; 7.140 ; 7.580 ;       ;
-; A          ; Y14         ; 6.901 ;       ;       ; 7.386 ;
-; A          ; Y15         ;       ; 7.097 ; 7.520 ;       ;
-; B          ; Y0          ; 6.758 ;       ;       ; 7.253 ;
-; B          ; Y1          ; 7.146 ;       ;       ; 7.613 ;
-; B          ; Y2          ;       ; 6.888 ; 7.372 ;       ;
-; B          ; Y3          ;       ; 6.855 ; 7.315 ;       ;
-; B          ; Y4          ; 7.204 ;       ;       ; 7.672 ;
-; B          ; Y5          ; 6.883 ;       ;       ; 7.368 ;
-; B          ; Y6          ;       ; 7.175 ; 7.691 ;       ;
-; B          ; Y7          ;       ; 7.044 ; 7.471 ;       ;
-; B          ; Y8          ; 8.180 ;       ;       ; 8.539 ;
-; B          ; Y9          ; 6.853 ;       ;       ; 7.311 ;
-; B          ; Y10         ;       ; 6.913 ; 7.311 ;       ;
-; B          ; Y11         ;       ; 6.879 ; 7.336 ;       ;
-; B          ; Y12         ; 6.887 ;       ;       ; 7.368 ;
-; B          ; Y13         ; 7.049 ;       ;       ; 7.534 ;
-; B          ; Y14         ;       ; 6.838 ; 7.336 ;       ;
-; B          ; Y15         ;       ; 6.967 ; 7.423 ;       ;
-; C          ; Y0          ; 6.760 ;       ;       ; 7.280 ;
-; C          ; Y1          ; 7.146 ;       ;       ; 7.640 ;
-; C          ; Y2          ; 6.927 ;       ;       ; 7.405 ;
-; C          ; Y3          ; 6.869 ;       ;       ; 7.387 ;
-; C          ; Y4          ;       ; 7.175 ; 7.671 ;       ;
-; C          ; Y5          ;       ; 6.867 ; 7.343 ;       ;
-; C          ; Y6          ;       ; 7.175 ; 7.716 ;       ;
-; C          ; Y7          ;       ; 7.043 ; 7.494 ;       ;
-; C          ; Y8          ; 8.174 ;       ;       ; 8.566 ;
-; C          ; Y9          ; 6.847 ;       ;       ; 7.338 ;
-; C          ; Y10         ; 6.895 ;       ;       ; 7.422 ;
-; C          ; Y11         ; 6.915 ;       ;       ; 7.395 ;
-; C          ; Y12         ;       ; 6.871 ; 7.335 ;       ;
-; C          ; Y13         ;       ; 7.042 ; 7.488 ;       ;
-; C          ; Y14         ;       ; 6.837 ; 7.367 ;       ;
-; C          ; Y15         ;       ; 6.967 ; 7.452 ;       ;
-; D          ; Y0          ; 6.811 ;       ;       ; 7.327 ;
-; D          ; Y1          ; 7.218 ;       ;       ; 7.700 ;
-; D          ; Y2          ; 6.930 ;       ;       ; 7.398 ;
-; D          ; Y3          ; 6.970 ;       ;       ; 7.456 ;
-; D          ; Y4          ; 7.225 ;       ;       ; 7.703 ;
-; D          ; Y5          ; 6.982 ;       ;       ; 7.464 ;
-; D          ; Y6          ; 7.271 ;       ;       ; 7.736 ;
-; D          ; Y7          ; 7.073 ;       ;       ; 7.620 ;
-; D          ; Y8          ;       ; 8.121 ; 8.709 ;       ;
-; D          ; Y9          ;       ; 6.941 ; 7.446 ;       ;
-; D          ; Y10         ;       ; 6.993 ; 7.434 ;       ;
-; D          ; Y11         ;       ; 6.985 ; 7.485 ;       ;
-; D          ; Y12         ;       ; 6.931 ; 7.405 ;       ;
-; D          ; Y13         ;       ; 7.152 ; 7.624 ;       ;
-; D          ; Y14         ;       ; 6.921 ; 7.415 ;       ;
-; D          ; Y15         ;       ; 7.109 ; 7.571 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 4.004 ;       ;       ; 4.566 ;
-; A          ; Y1          ;       ; 4.170 ; 4.869 ;       ;
-; A          ; Y2          ; 4.074 ;       ;       ; 4.676 ;
-; A          ; Y3          ;       ; 4.098 ; 4.731 ;       ;
-; A          ; Y4          ; 4.255 ;       ;       ; 4.834 ;
-; A          ; Y5          ;       ; 4.092 ; 4.729 ;       ;
-; A          ; Y6          ; 4.279 ;       ;       ; 4.850 ;
-; A          ; Y7          ;       ; 4.095 ; 4.770 ;       ;
-; A          ; Y8          ; 5.025 ;       ;       ; 5.478 ;
-; A          ; Y9          ;       ; 4.062 ; 4.694 ;       ;
-; A          ; Y10         ; 4.067 ;       ;       ; 4.621 ;
-; A          ; Y11         ;       ; 4.102 ; 4.729 ;       ;
-; A          ; Y12         ; 4.069 ;       ;       ; 4.662 ;
-; A          ; Y13         ;       ; 4.169 ; 4.813 ;       ;
-; A          ; Y14         ; 4.060 ;       ;       ; 4.659 ;
-; A          ; Y15         ;       ; 4.127 ; 4.767 ;       ;
-; B          ; Y0          ; 3.958 ;       ;       ; 4.491 ;
-; B          ; Y1          ; 4.202 ;       ;       ; 4.706 ;
-; B          ; Y2          ;       ; 4.028 ; 4.638 ;       ;
-; B          ; Y3          ;       ; 4.023 ; 4.630 ;       ;
-; B          ; Y4          ; 4.227 ;       ;       ; 4.789 ;
-; B          ; Y5          ; 4.046 ;       ;       ; 4.625 ;
-; B          ; Y6          ;       ; 4.173 ; 4.826 ;       ;
-; B          ; Y7          ;       ; 4.031 ; 4.704 ;       ;
-; B          ; Y8          ; 4.988 ;       ;       ; 5.419 ;
-; B          ; Y9          ; 4.024 ;       ;       ; 4.595 ;
-; B          ; Y10         ;       ; 3.952 ; 4.598 ;       ;
-; B          ; Y11         ;       ; 4.044 ; 4.644 ;       ;
-; B          ; Y12         ; 4.044 ;       ;       ; 4.621 ;
-; B          ; Y13         ; 4.145 ;       ;       ; 4.712 ;
-; B          ; Y14         ;       ; 3.995 ; 4.618 ;       ;
-; B          ; Y15         ;       ; 4.039 ; 4.672 ;       ;
-; C          ; Y0          ; 3.988 ;       ;       ; 4.522 ;
-; C          ; Y1          ; 4.232 ;       ;       ; 4.739 ;
-; C          ; Y2          ; 4.088 ;       ;       ; 4.667 ;
-; C          ; Y3          ; 4.085 ;       ;       ; 4.663 ;
-; C          ; Y4          ;       ; 4.206 ; 4.836 ;       ;
-; C          ; Y5          ;       ; 4.040 ; 4.650 ;       ;
-; C          ; Y6          ;       ; 4.202 ; 4.854 ;       ;
-; C          ; Y7          ;       ; 4.059 ; 4.730 ;       ;
-; C          ; Y8          ; 5.017 ;       ;       ; 5.450 ;
-; C          ; Y9          ; 4.052 ;       ;       ; 4.629 ;
-; C          ; Y10         ; 4.060 ;       ;       ; 4.586 ;
-; C          ; Y11         ; 4.105 ;       ;       ; 4.680 ;
-; C          ; Y12         ;       ; 4.036 ; 4.644 ;       ;
-; C          ; Y13         ;       ; 4.127 ; 4.742 ;       ;
-; C          ; Y14         ;       ; 4.026 ; 4.649 ;       ;
-; C          ; Y15         ;       ; 4.069 ; 4.701 ;       ;
-; D          ; Y0          ; 4.013 ;       ;       ; 4.554 ;
-; D          ; Y1          ; 4.255 ;       ;       ; 4.762 ;
-; D          ; Y2          ; 4.075 ;       ;       ; 4.653 ;
-; D          ; Y3          ; 4.129 ;       ;       ; 4.704 ;
-; D          ; Y4          ; 4.263 ;       ;       ; 4.821 ;
-; D          ; Y5          ; 4.129 ;       ;       ; 4.700 ;
-; D          ; Y6          ; 4.290 ;       ;       ; 4.842 ;
-; D          ; Y7          ; 4.160 ;       ;       ; 4.692 ;
-; D          ; Y8          ;       ; 4.858 ; 5.628 ;       ;
-; D          ; Y9          ;       ; 4.070 ; 4.698 ;       ;
-; D          ; Y10         ;       ; 4.018 ; 4.690 ;       ;
-; D          ; Y11         ;       ; 4.117 ; 4.741 ;       ;
-; D          ; Y12         ;       ; 4.052 ; 4.681 ;       ;
-; D          ; Y13         ;       ; 4.184 ; 4.826 ;       ;
-; D          ; Y14         ;       ; 4.052 ; 4.678 ;       ;
-; D          ; Y15         ;       ; 4.142 ; 4.779 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Y0            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y1            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y2            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y3            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y4            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y5            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y6            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y7            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y8            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y9            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y10           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y11           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y12           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y13           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y14           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y15           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times                                                     ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; D                       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; C                       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; B                       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; A                       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Y0            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.36 V              ; -0.00946 V          ; 0.111 V                              ; 0.027 V                              ; 6.46e-10 s                  ; 6.2e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.36 V             ; -0.00946 V         ; 0.111 V                             ; 0.027 V                             ; 6.46e-10 s                 ; 6.2e-10 s                  ; Yes                       ; Yes                       ;
-; Y1            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.36 V              ; -0.00946 V          ; 0.111 V                              ; 0.027 V                              ; 6.46e-10 s                  ; 6.2e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.36 V             ; -0.00946 V         ; 0.111 V                             ; 0.027 V                             ; 6.46e-10 s                 ; 6.2e-10 s                  ; Yes                       ; Yes                       ;
-; Y2            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y3            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y4            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y5            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y6            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y7            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
-; Y8            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.33 V              ; -0.00317 V          ; 0.162 V                              ; 0.063 V                              ; 3.54e-09 s                  ; 3.41e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.33 V             ; -0.00317 V         ; 0.162 V                             ; 0.063 V                             ; 3.54e-09 s                 ; 3.41e-09 s                 ; Yes                       ; Yes                       ;
-; Y9            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y10           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.36 V              ; -0.00946 V          ; 0.111 V                              ; 0.027 V                              ; 6.46e-10 s                  ; 6.2e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.36 V             ; -0.00946 V         ; 0.111 V                             ; 0.027 V                             ; 6.46e-10 s                 ; 6.2e-10 s                  ; Yes                       ; Yes                       ;
-; Y11           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y12           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y13           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y14           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y15           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Y0            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
-; Y1            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
-; Y2            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y3            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y4            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y5            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y6            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y7            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
-; Y8            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
-; Y9            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y10           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
-; Y11           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y12           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y13           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y14           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y15           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths                            ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 4     ; 4    ;
-; Unconstrained Input Port Paths  ; 64    ; 64   ;
-; Unconstrained Output Ports      ; 16    ; 16   ;
-; Unconstrained Output Port Paths ; 64    ; 64   ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 24 22:11:37 2019
-Info: Command: quartus_sta four_line_to_sixteen_line_decimal_decoder -c four_line_to_sixteen_line_decimal_decoder
-Info: qsta_default_script.tcl version: #1
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (21077): Core supply voltage is 1.2V
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'four_line_to_sixteen_line_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 383 megabytes
-    Info: Processing ended: Thu Oct 24 22:11:40 2019
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.sta.summary b/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.sta.summary
deleted file mode 100644
index 33f74363..00000000
--- a/CH6/CH6-1/output_files/four_line_to_sixteen_line_decimal_decoder.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.asm.rpt b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.asm.rpt
deleted file mode 100644
index 67f8b4d1..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.asm.rpt
+++ /dev/null
@@ -1,116 +0,0 @@
-Assembler report for ten_line_to_four_line_BCD_priority_encoder
-Thu Oct 17 21:26:23 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: ten_line_to_four_line_BCD_priority_encoder.sof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+--------------------------------------------------------------------+
-; Assembler Summary                                                  ;
-+-----------------------+--------------------------------------------+
-; Assembler Status      ; Successful - Thu Oct 17 21:26:23 2019      ;
-; Revision Name         ; ten_line_to_four_line_BCD_priority_encoder ;
-; Top-level Entity Name ; ten_line_to_four_line_BCD_priority_encoder ;
-; Family                ; Cyclone III                                ;
-; Device                ; EP3C16F484C6                               ;
-+-----------------------+--------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Assembler Settings                                                                                     ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Option                                                                      ; Setting  ; Default Value ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Use smart compilation                                                       ; Off      ; Off           ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
-; Enable compact report table                                                 ; Off      ; Off           ;
-; Generate compressed bitstreams                                              ; On       ; On            ;
-; Compression mode                                                            ; Off      ; Off           ;
-; Clock source for configuration device                                       ; Internal ; Internal      ;
-; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
-; Divide clock frequency by                                                   ; 1        ; 1             ;
-; Auto user code                                                              ; On       ; On            ;
-; Use configuration device                                                    ; Off      ; Off           ;
-; Configuration device                                                        ; Auto     ; Auto          ;
-; Configuration device auto user code                                         ; Off      ; Off           ;
-; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
-; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
-; Hexadecimal Output File start address                                       ; 0        ; 0             ;
-; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
-; Release clears before tri-states                                            ; Off      ; Off           ;
-; Auto-restart configuration after error                                      ; On       ; On            ;
-; Enable OCT_DONE                                                             ; Off      ; Off           ;
-; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
-+-----------------------------------------------------------------------------+----------+---------------+
-
-
-+------------------------------------------------+
-; Assembler Generated Files                      ;
-+------------------------------------------------+
-; File Name                                      ;
-+------------------------------------------------+
-; ten_line_to_four_line_BCD_priority_encoder.sof ;
-+------------------------------------------------+
-
-
-+--------------------------------------------------------------------------+
-; Assembler Device Options: ten_line_to_four_line_BCD_priority_encoder.sof ;
-+----------------+---------------------------------------------------------+
-; Option         ; Setting                                                 ;
-+----------------+---------------------------------------------------------+
-; Device         ; EP3C16F484C6                                            ;
-; JTAG usercode  ; 0x000C8FED                                              ;
-; Checksum       ; 0x000C8FED                                              ;
-+----------------+---------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit Assembler
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 17 21:26:20 2019
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 382 megabytes
-    Info: Processing ended: Thu Oct 17 21:26:23 2019
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.done b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.done
deleted file mode 100644
index 98741b94..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.done
+++ /dev/null
@@ -1 +0,0 @@
-Thu Oct 17 21:26:34 2019
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.eda.rpt b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.eda.rpt
deleted file mode 100644
index 9baf5569..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.eda.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-EDA Netlist Writer report for ten_line_to_four_line_BCD_priority_encoder
-Thu Oct 17 21:26:34 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. EDA Netlist Writer Summary
-  3. Simulation Settings
-  4. Simulation Generated Files
-  5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+------------------------------------------------------------------------+
-; EDA Netlist Writer Summary                                             ;
-+---------------------------+--------------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Oct 17 21:26:34 2019      ;
-; Revision Name             ; ten_line_to_four_line_BCD_priority_encoder ;
-; Top-level Entity Name     ; ten_line_to_four_line_BCD_priority_encoder ;
-; Family                    ; Cyclone III                                ;
-; Simulation Files Creation ; Successful                                 ;
-+---------------------------+--------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings                                                                                                           ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-; Option                                                                                            ; Setting                   ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
-; Generate netlist for functional simulation only                                                   ; On                        ;
-; Truncate long hierarchy paths                                                                     ; Off                       ;
-; Map illegal HDL characters                                                                        ; Off                       ;
-; Flatten buses into individual nodes                                                               ; Off                       ;
-; Maintain hierarchy                                                                                ; Off                       ;
-; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
-; Enable glitch filtering                                                                           ; Off                       ;
-; Do not write top level VHDL entity                                                                ; Off                       ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
-; Architecture name in VHDL output netlist                                                          ; structure                 ;
-; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
-; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Simulation Generated Files                                                                          ;
-+-----------------------------------------------------------------------------------------------------+
-; Generated Files                                                                                     ;
-+-----------------------------------------------------------------------------------------------------+
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//ten_line_to_four_line_BCD_priority_encoder.vo ;
-+-----------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit EDA Netlist Writer
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 17 21:26:33 2019
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder
-Info (204019): Generated file ten_line_to_four_line_BCD_priority_encoder.vo in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//" for EDA simulation tool
-Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 348 megabytes
-    Info: Processing ended: Thu Oct 17 21:26:34 2019
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.rpt b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.rpt
deleted file mode 100644
index 4f273ed8..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.rpt
+++ /dev/null
@@ -1,1241 +0,0 @@
-Fitter report for ten_line_to_four_line_BCD_priority_encoder
-Thu Oct 17 21:26:16 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. I/O Assignment Warnings
-  6. Incremental Compilation Preservation Summary
-  7. Incremental Compilation Partition Settings
-  8. Incremental Compilation Placement Preservation
-  9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. Fitter Resource Utilization by Entity
- 18. Delay Chain Summary
- 19. Pad To Core Delay Chain Fanout
- 20. Non-Global High Fan-Out Signals
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Fitter Summary                                                                  ;
-+------------------------------------+--------------------------------------------+
-; Fitter Status                      ; Successful - Thu Oct 17 21:26:16 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; ten_line_to_four_line_BCD_priority_encoder ;
-; Top-level Entity Name              ; ten_line_to_four_line_BCD_priority_encoder ;
-; Family                             ; Cyclone III                                ;
-; Device                             ; EP3C16F484C6                               ;
-; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 7 / 15,408 ( < 1 % )                       ;
-;     Total combinational functions  ; 7 / 15,408 ( < 1 % )                       ;
-;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 12 / 347 ( 3 % )                           ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
-; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
-; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
-+------------------------------------+--------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                                            ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option                                                                     ; Setting                               ; Default Value                         ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device                                                                     ; EP3C16F484C6                          ;                                       ;
-; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
-; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
-; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
-; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
-; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
-; Use smart compilation                                                      ; Off                                   ; Off                                   ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
-; Enable compact report table                                                ; Off                                   ; Off                                   ;
-; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
-; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
-; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
-; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
-; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
-; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
-; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
-; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
-; SSN Optimization                                                           ; Off                                   ; Off                                   ;
-; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
-; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
-; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
-; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
-; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
-; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
-; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
-; PCI I/O                                                                    ; Off                                   ; Off                                   ;
-; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
-; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
-; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
-; Auto Delay Chains                                                          ; On                                    ; On                                    ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
-; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
-; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
-; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
-; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
-; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
-; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
-; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
-; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
-; Auto Global Clock                                                          ; On                                    ; On                                    ;
-; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
-; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
-; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
-; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
-; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
-; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings                         ;
-+----------+--------------------------------------+
-; Pin Name ; Reason                               ;
-+----------+--------------------------------------+
-; A        ; Missing drive strength and slew rate ;
-; B        ; Missing drive strength and slew rate ;
-; C        ; Missing drive strength and slew rate ;
-; D        ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary                                                    ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ;                   ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 42 ) ; 0.00 % ( 0 / 42 )          ; 0.00 % ( 0 / 42 )        ;
-;     -- Achieved     ; 0.00 % ( 0 / 42 ) ; 0.00 % ( 0 / 42 )          ; 0.00 % ( 0 / 42 )        ;
-;                     ;                   ;                            ;                          ;
-; Routing (by net)    ;                   ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings                                                                                                                                             ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation                                                                                     ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 32 )     ; N/A                     ; Source File       ; N/A                 ;       ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.pin.
-
-
-+--------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                      ;
-+---------------------------------------------+----------------------+
-; Resource                                    ; Usage                ;
-+---------------------------------------------+----------------------+
-; Total logic elements                        ; 7 / 15,408 ( < 1 % ) ;
-;     -- Combinational with no register       ; 7                    ;
-;     -- Register only                        ; 0                    ;
-;     -- Combinational with a register        ; 0                    ;
-;                                             ;                      ;
-; Logic element usage by number of LUT inputs ;                      ;
-;     -- 4 input functions                    ; 5                    ;
-;     -- 3 input functions                    ; 0                    ;
-;     -- <=2 input functions                  ; 2                    ;
-;     -- Register only                        ; 0                    ;
-;                                             ;                      ;
-; Logic elements by mode                      ;                      ;
-;     -- normal mode                          ; 7                    ;
-;     -- arithmetic mode                      ; 0                    ;
-;                                             ;                      ;
-; Total registers*                            ; 0 / 17,068 ( 0 % )   ;
-;     -- Dedicated logic registers            ; 0 / 15,408 ( 0 % )   ;
-;     -- I/O registers                        ; 0 / 1,660 ( 0 % )    ;
-;                                             ;                      ;
-; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )    ;
-; Virtual pins                                ; 0                    ;
-; I/O pins                                    ; 12 / 347 ( 3 % )     ;
-;     -- Clock pins                           ; 0 / 8 ( 0 % )        ;
-;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )        ;
-;                                             ;                      ;
-; Global signals                              ; 0                    ;
-; M9Ks                                        ; 0 / 56 ( 0 % )       ;
-; Total block memory bits                     ; 0 / 516,096 ( 0 % )  ;
-; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )  ;
-; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ;
-; PLLs                                        ; 0 / 4 ( 0 % )        ;
-; Global clocks                               ; 0 / 20 ( 0 % )       ;
-; JTAGs                                       ; 0 / 1 ( 0 % )        ;
-; CRC blocks                                  ; 0 / 1 ( 0 % )        ;
-; ASMI blocks                                 ; 0 / 1 ( 0 % )        ;
-; Impedance control blocks                    ; 0 / 4 ( 0 % )        ;
-; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%         ;
-; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%         ;
-; Maximum fan-out                             ; 3                    ;
-; Highest non-global fan-out                  ; 3                    ;
-; Total fan-out                               ; 45                   ;
-; Average fan-out                             ; 1.10                 ;
-+---------------------------------------------+----------------------+
-*  Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics                                                                        ;
-+---------------------------------------------+---------------------+--------------------------------+
-; Statistic                                   ; Top                 ; hard_block:auto_generated_inst ;
-+---------------------------------------------+---------------------+--------------------------------+
-; Difficulty Clustering Region                ; Low                 ; Low                            ;
-;                                             ;                     ;                                ;
-; Total logic elements                        ; 7 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
-;     -- Combinational with no register       ; 7                   ; 0                              ;
-;     -- Register only                        ; 0                   ; 0                              ;
-;     -- Combinational with a register        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Logic element usage by number of LUT inputs ;                     ;                                ;
-;     -- 4 input functions                    ; 5                   ; 0                              ;
-;     -- 3 input functions                    ; 0                   ; 0                              ;
-;     -- <=2 input functions                  ; 2                   ; 0                              ;
-;     -- Register only                        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Logic elements by mode                      ;                     ;                                ;
-;     -- normal mode                          ; 7                   ; 0                              ;
-;     -- arithmetic mode                      ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Total registers                             ; 0                   ; 0                              ;
-;     -- Dedicated logic registers            ; 0 / 15408 ( 0 % )   ; 0 / 15408 ( 0 % )              ;
-;     -- I/O registers                        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )   ; 0 / 963 ( 0 % )                ;
-;                                             ;                     ;                                ;
-; Virtual pins                                ; 0                   ; 0                              ;
-; I/O pins                                    ; 12                  ; 0                              ;
-; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )     ; 0 / 112 ( 0 % )                ;
-; Total memory bits                           ; 0                   ; 0                              ;
-; Total RAM block bits                        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Connections                                 ;                     ;                                ;
-;     -- Input Connections                    ; 0                   ; 0                              ;
-;     -- Registered Input Connections         ; 0                   ; 0                              ;
-;     -- Output Connections                   ; 0                   ; 0                              ;
-;     -- Registered Output Connections        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Internal Connections                        ;                     ;                                ;
-;     -- Total Connections                    ; 40                  ; 5                              ;
-;     -- Registered Connections               ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; External Connections                        ;                     ;                                ;
-;     -- Top                                  ; 0                   ; 0                              ;
-;     -- hard_block:auto_generated_inst       ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Partition Interface                         ;                     ;                                ;
-;     -- Input Ports                          ; 8                   ; 0                              ;
-;     -- Output Ports                         ; 4                   ; 0                              ;
-;     -- Bidir Ports                          ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Registered Ports                            ;                     ;                                ;
-;     -- Registered Input Ports               ; 0                   ; 0                              ;
-;     -- Registered Output Ports              ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Port Connectivity                           ;                     ;                                ;
-;     -- Input Ports driven by GND            ; 0                   ; 0                              ;
-;     -- Output Ports driven by GND           ; 0                   ; 0                              ;
-;     -- Input Ports driven by VCC            ; 0                   ; 0                              ;
-;     -- Output Ports driven by VCC           ; 0                   ; 0                              ;
-;     -- Input Ports with no Source           ; 0                   ; 0                              ;
-;     -- Output Ports with no Source          ; 0                   ; 0                              ;
-;     -- Input Ports with no Fanout           ; 0                   ; 0                              ;
-;     -- Output Ports with no Fanout          ; 0                   ; 0                              ;
-+---------------------------------------------+---------------------+--------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                                                                ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; I2   ; D2    ; 1        ; 0            ; 25           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I3   ; E4    ; 1        ; 0            ; 26           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I4   ; E3    ; 1        ; 0            ; 26           ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I5   ; H7    ; 1        ; 0            ; 25           ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I6   ; J7    ; 1        ; 0            ; 22           ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I7   ; G5    ; 1        ; 0            ; 27           ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I8   ; G4    ; 1        ; 0            ; 23           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; I9   ; H6    ; 1        ; 0            ; 25           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; A    ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; B    ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; C    ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; D    ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins                                                                                         ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; E4       ; DIFFIO_L2p, nRESET          ; Use as regular IO        ; I3                      ; Dual Purpose Pin          ;
-; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
-; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
-; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
-; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
-; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
-; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
-; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
-; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
-; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage                                             ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1        ; 16 / 33 ( 48 % ) ; 2.5V          ; --           ;
-; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
-; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
-; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
-; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
-; 6        ; 1 / 43 ( 2 % )   ; 2.5V          ; --           ;
-; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
-; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                                                                        ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; B1       ; 2          ; 1        ; D                                                         ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; B2       ; 1          ; 1        ; C                                                         ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C1       ; 7          ; 1        ; A                                                         ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; C2       ; 6          ; 1        ; B                                                         ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; D2       ; 8          ; 1        ; I2                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E1       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; E3       ; 5          ; 1        ; I4                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; E4       ; 4          ; 1        ; I3                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G4       ; 17         ; 1        ; I8                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G5       ; 3          ; 1        ; I7                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; G21      ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H1       ; 26         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H6       ; 11         ; 1        ; I9                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H7       ; 10         ; 1        ; I5                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J1       ; 29         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J2       ; 28         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J3       ; 27         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J6       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J7       ; 22         ; 1        ; I6                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
-; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                               ;
-+---------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------+--------------+
-; Compilation Hierarchy Node                  ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                    ; Library Name ;
-+---------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------+--------------+
-; |ten_line_to_four_line_BCD_priority_encoder ; 7 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 12   ; 0            ; 7 (0)        ; 0 (0)             ; 0 (0)            ; |ten_line_to_four_line_BCD_priority_encoder            ; work         ;
-;    |74147:inst|                             ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |ten_line_to_four_line_BCD_priority_encoder|74147:inst ; work         ;
-+---------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+--------------------------------------------------------------------------------------+
-; Delay Chain Summary                                                                  ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-; A    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; B    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; C    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; D    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; I6   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-; I4   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; I3   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; I5   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-; I7   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-; I9   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-; I8   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-; I2   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+-----------------------------------------------------+
-; Pad To Core Delay Chain Fanout                      ;
-+-----------------------+-------------------+---------+
-; Source Pin / Fanout   ; Pad To Core Index ; Setting ;
-+-----------------------+-------------------+---------+
-; I6                    ;                   ;         ;
-;      - 74147:inst|7~2 ; 1                 ; 6       ;
-;      - 74147:inst|9~0 ; 1                 ; 6       ;
-;      - 74147:inst|8~5 ; 1                 ; 6       ;
-; I4                    ;                   ;         ;
-;      - 74147:inst|7~2 ; 0                 ; 6       ;
-;      - 74147:inst|8~4 ; 0                 ; 6       ;
-;      - 74147:inst|9~1 ; 0                 ; 6       ;
-; I3                    ;                   ;         ;
-;      - 74147:inst|7~2 ; 0                 ; 6       ;
-;      - 74147:inst|8~4 ; 0                 ; 6       ;
-; I5                    ;                   ;         ;
-;      - 74147:inst|7~2 ; 1                 ; 6       ;
-;      - 74147:inst|8~4 ; 1                 ; 6       ;
-;      - 74147:inst|9~1 ; 1                 ; 6       ;
-; I7                    ;                   ;         ;
-;      - 74147:inst|9~0 ; 1                 ; 6       ;
-;      - 74147:inst|7~3 ; 1                 ; 6       ;
-;      - 74147:inst|8~5 ; 1                 ; 6       ;
-; I9                    ;                   ;         ;
-;      - 74147:inst|67  ; 1                 ; 6       ;
-;      - 74147:inst|7~3 ; 1                 ; 6       ;
-; I8                    ;                   ;         ;
-;      - 74147:inst|67  ; 1                 ; 6       ;
-;      - 74147:inst|7~3 ; 1                 ; 6       ;
-; I2                    ;                   ;         ;
-;      - 74147:inst|8~4 ; 0                 ; 6       ;
-+-----------------------+-------------------+---------+
-
-
-+---------------------------------+
-; Non-Global High Fan-Out Signals ;
-+----------------+----------------+
-; Name           ; Fan-Out        ;
-+----------------+----------------+
-; I7~input       ; 3              ;
-; I5~input       ; 3              ;
-; I4~input       ; 3              ;
-; I6~input       ; 3              ;
-; 74147:inst|67  ; 3              ;
-; I8~input       ; 2              ;
-; I9~input       ; 2              ;
-; I3~input       ; 2              ;
-; I2~input       ; 1              ;
-; 74147:inst|8~5 ; 1              ;
-; 74147:inst|7~3 ; 1              ;
-; 74147:inst|9~1 ; 1              ;
-; 74147:inst|9~0 ; 1              ;
-; 74147:inst|8~4 ; 1              ;
-; 74147:inst|7~2 ; 1              ;
-+----------------+----------------+
-
-
-+-----------------------------------------------+
-; Routing Usage Summary                         ;
-+-----------------------+-----------------------+
-; Routing Resource Type ; Usage                 ;
-+-----------------------+-----------------------+
-; Block interconnects   ; 12 / 47,787 ( < 1 % ) ;
-; C16 interconnects     ; 0 / 1,804 ( 0 % )     ;
-; C4 interconnects      ; 7 / 31,272 ( < 1 % )  ;
-; Direct links          ; 2 / 47,787 ( < 1 % )  ;
-; Global clocks         ; 0 / 20 ( 0 % )        ;
-; Local interconnects   ; 4 / 15,408 ( < 1 % )  ;
-; R24 interconnects     ; 0 / 1,775 ( 0 % )     ;
-; R4 interconnects      ; 1 / 41,310 ( < 1 % )  ;
-+-----------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements                                                       ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements  (Average = 7.00) ; Number of LABs  (Total = 1) ;
-+--------------------------------------------+-----------------------------+
-; 1                                          ; 0                           ;
-; 2                                          ; 0                           ;
-; 3                                          ; 0                           ;
-; 4                                          ; 0                           ;
-; 5                                          ; 0                           ;
-; 6                                          ; 0                           ;
-; 7                                          ; 1                           ;
-; 8                                          ; 0                           ;
-; 9                                          ; 0                           ;
-; 10                                         ; 0                           ;
-; 11                                         ; 0                           ;
-; 12                                         ; 0                           ;
-; 13                                         ; 0                           ;
-; 14                                         ; 0                           ;
-; 15                                         ; 0                           ;
-; 16                                         ; 0                           ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced                                                       ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced  (Average = 7.00) ; Number of LABs  (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0                                           ; 0                           ;
-; 1                                           ; 0                           ;
-; 2                                           ; 0                           ;
-; 3                                           ; 0                           ;
-; 4                                           ; 0                           ;
-; 5                                           ; 0                           ;
-; 6                                           ; 0                           ;
-; 7                                           ; 1                           ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out                                                       ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out  (Average = 4.00) ; Number of LABs  (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0                                               ; 0                           ;
-; 1                                               ; 0                           ;
-; 2                                               ; 0                           ;
-; 3                                               ; 0                           ;
-; 4                                               ; 1                           ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs                                                       ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs  (Average = 8.00) ; Number of LABs  (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0                                           ; 0                           ;
-; 1                                           ; 0                           ;
-; 2                                           ; 0                           ;
-; 3                                           ; 0                           ;
-; 4                                           ; 0                           ;
-; 5                                           ; 0                           ;
-; 6                                           ; 0                           ;
-; 7                                           ; 0                           ;
-; 8                                           ; 1                           ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary                        ;
-+----------------------------------+-------+
-; I/O Rules Statistic              ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules                  ; 30    ;
-; Number of I/O Rules Passed       ; 12    ;
-; Number of I/O Rules Failed       ; 0     ;
-; Number of I/O Rules Unchecked    ; 0     ;
-; Number of I/O Rules Inapplicable ; 18    ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
-; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
-; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
-; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Total Pass         ; 12        ; 0            ; 12        ; 0            ; 0            ; 12        ; 12        ; 0            ; 12        ; 12        ; 0            ; 4            ; 0            ; 0            ; 8            ; 0            ; 4            ; 8            ; 0            ; 0            ; 0            ; 4            ; 0            ; 0            ; 0            ; 0            ; 0            ; 12        ; 0            ; 0            ;
-; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; Total Inapplicable ; 0         ; 12           ; 0         ; 12           ; 12           ; 0         ; 0         ; 12           ; 0         ; 0         ; 12           ; 8            ; 12           ; 12           ; 4            ; 12           ; 8            ; 4            ; 12           ; 12           ; 12           ; 8            ; 12           ; 12           ; 12           ; 12           ; 12           ; 0         ; 12           ; 12           ;
-; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; A                  ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; B                  ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; C                  ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; D                  ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I6                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I4                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I3                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I5                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I7                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I9                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I8                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; I2                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options                                                                       ;
-+------------------------------------------------------------------+--------------------------+
-; Option                                                           ; Setting                  ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
-; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
-; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
-; Enable INIT_DONE output                                          ; Off                      ;
-; Configuration scheme                                             ; Active Serial            ;
-; Error detection CRC                                              ; Off                      ;
-; Enable open drain on CRC_ERROR pin                               ; Off                      ;
-; Enable input tri-state on active configuration pins in user mode ; Off                      ;
-; Configuration Voltage Level                                      ; Auto                     ;
-; Force Configuration Voltage Level                                ; Off                      ;
-; nCEO                                                             ; As output driving ground ;
-; Data[0]                                                          ; As input tri-stated      ;
-; Data[1]/ASDO                                                     ; As input tri-stated      ;
-; Data[7..2]                                                       ; Unreserved               ;
-; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
-; Other Active Parallel pins                                       ; Unreserved               ;
-; DCLK                                                             ; As output driving ground ;
-; Base pin-out file on sameframe device                            ; Off                      ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions  ;
-+---------------------------+--------+
-; Setting                   ; Value  ;
-+---------------------------+--------+
-; Nominal Core Voltage      ; 1.20 V ;
-; Low Junction Temperature  ; 0 °C   ;
-; High Junction Temperature ; 85 °C  ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (119006): Selected device EP3C16F484C6 for design "ten_line_to_four_line_BCD_priority_encoder"
-Info (21077): Core supply voltage is 1.2V
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
-    Info (176445): Device EP3C40F484C6 is compatible
-    Info (176445): Device EP3C55F484C6 is compatible
-    Info (176445): Device EP3C80F484C6 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
-    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
-    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
-    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
-    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
-    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ten_line_to_four_line_BCD_priority_encoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
-    Extra Info (176219): No registers were packed into other blocks
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
-    Info (170200): Optimizations that may affect the design's timing were skipped
-Info (11888): Total time spent on timing analysis during the Fitter is 0.20 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
-Info (144001): Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.smsg
-Info: Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 535 megabytes
-    Info: Processing ended: Thu Oct 17 21:26:17 2019
-    Info: Elapsed time: 00:00:12
-    Info: Total CPU time (on all processors): 00:00:11
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.smsg.
-
-
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.smsg b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.smsg
deleted file mode 100644
index 7121cbb1..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.summary b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.summary
deleted file mode 100644
index d761189b..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Thu Oct 17 21:26:16 2019
-Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
-Revision Name : ten_line_to_four_line_BCD_priority_encoder
-Top-level Entity Name : ten_line_to_four_line_BCD_priority_encoder
-Family : Cyclone III
-Device : EP3C16F484C6
-Timing Models : Final
-Total logic elements : 7 / 15,408 ( < 1 % )
-    Total combinational functions : 7 / 15,408 ( < 1 % )
-    Dedicated logic registers : 0 / 15,408 ( 0 % )
-Total registers : 0
-Total pins : 12 / 347 ( 3 % )
-Total virtual pins : 0
-Total memory bits : 0 / 516,096 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.flow.rpt b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.flow.rpt
deleted file mode 100644
index 8417a1ec..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.flow.rpt
+++ /dev/null
@@ -1,130 +0,0 @@
-Flow report for ten_line_to_four_line_BCD_priority_encoder
-Thu Oct 17 21:26:34 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Flow Summary                                                                    ;
-+------------------------------------+--------------------------------------------+
-; Flow Status                        ; Successful - Thu Oct 17 21:26:34 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; ten_line_to_four_line_BCD_priority_encoder ;
-; Top-level Entity Name              ; ten_line_to_four_line_BCD_priority_encoder ;
-; Family                             ; Cyclone III                                ;
-; Device                             ; EP3C16F484C6                               ;
-; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 7 / 15,408 ( < 1 % )                       ;
-;     Total combinational functions  ; 7 / 15,408 ( < 1 % )                       ;
-;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 12 / 347 ( 3 % )                           ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
-; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
-; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
-+------------------------------------+--------------------------------------------+
-
-
-+----------------------------------------------------------------+
-; Flow Settings                                                  ;
-+-------------------+--------------------------------------------+
-; Option            ; Setting                                    ;
-+-------------------+--------------------------------------------+
-; Start date & time ; 10/17/2019 21:26:01                        ;
-; Main task         ; Compilation                                ;
-; Revision Name     ; ten_line_to_four_line_BCD_priority_encoder ;
-+-------------------+--------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                                           ;
-+-------------------------------------+-------------------------------------------------------+---------------+-------------+----------------+
-; Assignment Name                     ; Value                                                 ; Default Value ; Entity Name ; Section Id     ;
-+-------------------------------------+-------------------------------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID               ; 0.157131876110551                                     ; --            ; --          ; --             ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST     ; On                                                    ; --            ; --          ; eda_simulation ;
-; EDA_NETLIST_WRITER_OUTPUT_DIR       ; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/ ; --            ; --          ; eda_simulation ;
-; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                                           ; --            ; --          ; eda_simulation ;
-; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (Verilog)                             ; <None>        ; --          ; --             ;
-; MAX_CORE_JUNCTION_TEMP              ; 85                                                    ; --            ; --          ; --             ;
-; MIN_CORE_JUNCTION_TEMP              ; 0                                                     ; --            ; --          ; --             ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                                                  ; --            ; --          ; --             ;
-; PARTITION_COLOR                     ; 16764057                                              ; --            ; --          ; Top            ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                                 ; --            ; --          ; Top            ;
-; PARTITION_NETLIST_TYPE              ; SOURCE                                                ; --            ; --          ; Top            ;
-; PROJECT_OUTPUT_DIRECTORY            ; output_files                                          ; --            ; --          ; --             ;
-+-------------------------------------+-------------------------------------------------------+---------------+-------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:03     ; 1.0                     ; 360 MB              ; 00:00:02                           ;
-; Fitter                    ; 00:00:11     ; 1.0                     ; 535 MB              ; 00:00:11                           ;
-; Assembler                 ; 00:00:03     ; 1.0                     ; 382 MB              ; 00:00:02                           ;
-; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 369 MB              ; 00:00:03                           ;
-; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 338 MB              ; 00:00:01                           ;
-; Total                     ; 00:00:20     ; --                      ; --                  ; 00:00:19                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                              ;
-+---------------------------+-------------------+----------------+------------+----------------+
-; Module Name               ; Machine Hostname  ; OS Name        ; OS Version ; Processor type ;
-+---------------------------+-------------------+----------------+------------+----------------+
-; Analysis & Synthesis      ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; Fitter                    ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; Assembler                 ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; TimeQuest Timing Analyzer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; EDA Netlist Writer        ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-+---------------------------+-------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder
-quartus_fit --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder
-quartus_asm --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder
-quartus_sta ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder
-quartus_eda --read_settings_files=off --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder
-
-
-
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.jdi b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.jdi
deleted file mode 100644
index aecddc84..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="a461285906bb0fd4cf91"/>
-  </project>
-  <file_info>
-    <file device="EP3C16F484C6" path="ten_line_to_four_line_BCD_priority_encoder.sof" usercode="0xFFFFFFFF"/>
-  </file_info>
-</sld_project_info>
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.map.rpt b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.map.rpt
deleted file mode 100644
index 66bf96ec..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.map.rpt
+++ /dev/null
@@ -1,261 +0,0 @@
-Analysis & Synthesis report for ten_line_to_four_line_BCD_priority_encoder
-Thu Oct 17 21:26:03 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. General Register Statistics
-  9. Elapsed Time Per Partition
- 10. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                    ;
-+------------------------------------+--------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Thu Oct 17 21:26:03 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; ten_line_to_four_line_BCD_priority_encoder ;
-; Top-level Entity Name              ; ten_line_to_four_line_BCD_priority_encoder ;
-; Family                             ; Cyclone III                                ;
-; Total logic elements               ; 7                                          ;
-;     Total combinational functions  ; 7                                          ;
-;     Dedicated logic registers      ; 0                                          ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 12                                         ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0                                          ;
-; Embedded Multiplier 9-bit elements ; 0                                          ;
-; Total PLLs                         ; 0                                          ;
-+------------------------------------+--------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                                                                        ;
-+----------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
-; Option                                                                     ; Setting                                    ; Default Value                              ;
-+----------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
-; Device                                                                     ; EP3C16F484C6                               ;                                            ;
-; Top-level entity name                                                      ; ten_line_to_four_line_BCD_priority_encoder ; ten_line_to_four_line_BCD_priority_encoder ;
-; Family name                                                                ; Cyclone III                                ; Cyclone IV GX                              ;
-; Use smart compilation                                                      ; Off                                        ; Off                                        ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                         ; On                                         ;
-; Enable compact report table                                                ; Off                                        ; Off                                        ;
-; Restructure Multiplexers                                                   ; Auto                                       ; Auto                                       ;
-; Create Debugging Nodes for IP Cores                                        ; Off                                        ; Off                                        ;
-; Preserve fewer node names                                                  ; On                                         ; On                                         ;
-; Disable OpenCore Plus hardware evaluation                                  ; Off                                        ; Off                                        ;
-; Verilog Version                                                            ; Verilog_2001                               ; Verilog_2001                               ;
-; VHDL Version                                                               ; VHDL_1993                                  ; VHDL_1993                                  ;
-; State Machine Processing                                                   ; Auto                                       ; Auto                                       ;
-; Safe State Machine                                                         ; Off                                        ; Off                                        ;
-; Extract Verilog State Machines                                             ; On                                         ; On                                         ;
-; Extract VHDL State Machines                                                ; On                                         ; On                                         ;
-; Ignore Verilog initial constructs                                          ; Off                                        ; Off                                        ;
-; Iteration limit for constant Verilog loops                                 ; 5000                                       ; 5000                                       ;
-; Iteration limit for non-constant Verilog loops                             ; 250                                        ; 250                                        ;
-; Add Pass-Through Logic to Inferred RAMs                                    ; On                                         ; On                                         ;
-; Infer RAMs from Raw Logic                                                  ; On                                         ; On                                         ;
-; Parallel Synthesis                                                         ; On                                         ; On                                         ;
-; DSP Block Balancing                                                        ; Auto                                       ; Auto                                       ;
-; NOT Gate Push-Back                                                         ; On                                         ; On                                         ;
-; Power-Up Don't Care                                                        ; On                                         ; On                                         ;
-; Remove Redundant Logic Cells                                               ; Off                                        ; Off                                        ;
-; Remove Duplicate Registers                                                 ; On                                         ; On                                         ;
-; Ignore CARRY Buffers                                                       ; Off                                        ; Off                                        ;
-; Ignore CASCADE Buffers                                                     ; Off                                        ; Off                                        ;
-; Ignore GLOBAL Buffers                                                      ; Off                                        ; Off                                        ;
-; Ignore ROW GLOBAL Buffers                                                  ; Off                                        ; Off                                        ;
-; Ignore LCELL Buffers                                                       ; Off                                        ; Off                                        ;
-; Ignore SOFT Buffers                                                        ; On                                         ; On                                         ;
-; Limit AHDL Integers to 32 Bits                                             ; Off                                        ; Off                                        ;
-; Optimization Technique                                                     ; Balanced                                   ; Balanced                                   ;
-; Carry Chain Length                                                         ; 70                                         ; 70                                         ;
-; Auto Carry Chains                                                          ; On                                         ; On                                         ;
-; Auto Open-Drain Pins                                                       ; On                                         ; On                                         ;
-; Perform WYSIWYG Primitive Resynthesis                                      ; Off                                        ; Off                                        ;
-; Auto ROM Replacement                                                       ; On                                         ; On                                         ;
-; Auto RAM Replacement                                                       ; On                                         ; On                                         ;
-; Auto DSP Block Replacement                                                 ; On                                         ; On                                         ;
-; Auto Shift Register Replacement                                            ; Auto                                       ; Auto                                       ;
-; Allow Shift Register Merging across Hierarchies                            ; Auto                                       ; Auto                                       ;
-; Auto Clock Enable Replacement                                              ; On                                         ; On                                         ;
-; Strict RAM Replacement                                                     ; Off                                        ; Off                                        ;
-; Allow Synchronous Control Signals                                          ; On                                         ; On                                         ;
-; Force Use of Synchronous Clear Signals                                     ; Off                                        ; Off                                        ;
-; Auto RAM Block Balancing                                                   ; On                                         ; On                                         ;
-; Auto RAM to Logic Cell Conversion                                          ; Off                                        ; Off                                        ;
-; Auto Resource Sharing                                                      ; Off                                        ; Off                                        ;
-; Allow Any RAM Size For Recognition                                         ; Off                                        ; Off                                        ;
-; Allow Any ROM Size For Recognition                                         ; Off                                        ; Off                                        ;
-; Allow Any Shift Register Size For Recognition                              ; Off                                        ; Off                                        ;
-; Use LogicLock Constraints during Resource Balancing                        ; On                                         ; On                                         ;
-; Ignore translate_off and synthesis_off directives                          ; Off                                        ; Off                                        ;
-; Timing-Driven Synthesis                                                    ; On                                         ; On                                         ;
-; Report Parameter Settings                                                  ; On                                         ; On                                         ;
-; Report Source Assignments                                                  ; On                                         ; On                                         ;
-; Report Connectivity Checks                                                 ; On                                         ; On                                         ;
-; Ignore Maximum Fan-Out Assignments                                         ; Off                                        ; Off                                        ;
-; Synchronization Register Chain Length                                      ; 2                                          ; 2                                          ;
-; PowerPlay Power Optimization                                               ; Normal compilation                         ; Normal compilation                         ;
-; HDL message level                                                          ; Level2                                     ; Level2                                     ;
-; Suppress Register Optimization Related Messages                            ; Off                                        ; Off                                        ;
-; Number of Removed Registers Reported in Synthesis Report                   ; 5000                                       ; 5000                                       ;
-; Number of Swept Nodes Reported in Synthesis Report                         ; 5000                                       ; 5000                                       ;
-; Number of Inverted Registers Reported in Synthesis Report                  ; 100                                        ; 100                                        ;
-; Clock MUX Protection                                                       ; On                                         ; On                                         ;
-; Auto Gated Clock Conversion                                                ; Off                                        ; Off                                        ;
-; Block Design Naming                                                        ; Auto                                       ; Auto                                       ;
-; SDC constraint protection                                                  ; Off                                        ; Off                                        ;
-; Synthesis Effort                                                           ; Auto                                       ; Auto                                       ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                                         ; On                                         ;
-; Pre-Mapping Resynthesis Optimization                                       ; Off                                        ; Off                                        ;
-; Analysis & Synthesis Message Level                                         ; Medium                                     ; Medium                                     ;
-; Disable Register Merging Across Hierarchies                                ; Auto                                       ; Auto                                       ;
-; Resource Aware Inference For Block RAM                                     ; On                                         ; On                                         ;
-; Synthesis Seed                                                             ; 1                                          ; 1                                          ;
-+----------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                                                                ;
-+------------------------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path               ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                        ; Library ;
-+------------------------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------------+---------+
-; ten_line_to_four_line_BCD_priority_encoder.bdf ; yes             ; User Block Diagram/Schematic File  ; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf ;         ;
-; 74147.bdf                                      ; yes             ; Megafunction                       ; /home/timmy/altera/13.1/quartus/libraries/others/maxplus2/74147.bdf                 ;         ;
-+------------------------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------------+---------+
-
-
-+-------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary                 ;
-+---------------------------------------------+---------------+
-; Resource                                    ; Usage         ;
-+---------------------------------------------+---------------+
-; Estimated Total logic elements              ; 7             ;
-;                                             ;               ;
-; Total combinational functions               ; 7             ;
-; Logic element usage by number of LUT inputs ;               ;
-;     -- 4 input functions                    ; 5             ;
-;     -- 3 input functions                    ; 0             ;
-;     -- <=2 input functions                  ; 2             ;
-;                                             ;               ;
-; Logic elements by mode                      ;               ;
-;     -- normal mode                          ; 7             ;
-;     -- arithmetic mode                      ; 0             ;
-;                                             ;               ;
-; Total registers                             ; 0             ;
-;     -- Dedicated logic registers            ; 0             ;
-;     -- I/O registers                        ; 0             ;
-;                                             ;               ;
-; I/O pins                                    ; 12            ;
-; Embedded Multiplier 9-bit elements          ; 0             ;
-; Maximum fan-out node                        ; 74147:inst|67 ;
-; Maximum fan-out                             ; 3             ;
-; Total fan-out                               ; 40            ;
-; Average fan-out                             ; 1.29          ;
-+---------------------------------------------+---------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                             ;
-+---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------+--------------+
-; Compilation Hierarchy Node                  ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                    ; Library Name ;
-+---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------+--------------+
-; |ten_line_to_four_line_BCD_priority_encoder ; 7 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 12   ; 0            ; |ten_line_to_four_line_BCD_priority_encoder            ; work         ;
-;    |74147:inst|                             ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ten_line_to_four_line_BCD_priority_encoder|74147:inst ; work         ;
-+---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 0     ;
-; Number of registers using Synchronous Clear  ; 0     ;
-; Number of registers using Synchronous Load   ; 0     ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 0     ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition    ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top            ; 00:00:00     ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit Analysis & Synthesis
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 17 21:26:00 2019
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (12021): Found 1 design units, including 1 entities, in source file ten_line_to_four_line_BCD_priority_encoder.bdf
-    Info (12023): Found entity 1: ten_line_to_four_line_BCD_priority_encoder
-Info (12127): Elaborating entity "ten_line_to_four_line_BCD_priority_encoder" for the top level hierarchy
-Info (12128): Elaborating entity "74147" for hierarchy "74147:inst"
-Info (12130): Elaborated megafunction instantiation "74147:inst"
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
-    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 19 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 8 input pins
-    Info (21059): Implemented 4 output pins
-    Info (21061): Implemented 7 logic cells
-Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 371 megabytes
-    Info: Processing ended: Thu Oct 17 21:26:03 2019
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.map.summary b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.map.summary
deleted file mode 100644
index dc4261da..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Thu Oct 17 21:26:03 2019
-Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
-Revision Name : ten_line_to_four_line_BCD_priority_encoder
-Top-level Entity Name : ten_line_to_four_line_BCD_priority_encoder
-Family : Cyclone III
-Total logic elements : 7
-    Total combinational functions : 7
-    Dedicated logic registers : 0
-Total registers : 0
-Total pins : 12
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.pin b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.pin
deleted file mode 100644
index 09bb691f..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.pin
+++ /dev/null
@@ -1,554 +0,0 @@
- -- Copyright (C) 1991-2013 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Altera Program License 
- -- Subscription Agreement, Altera MegaCore Function License 
- -- Agreement, or other applicable license agreement, including, 
- -- without limitation, that your use is for the sole purpose of 
- -- programming logic devices manufactured by Altera and sold by 
- -- Altera or its authorized distributors.  Please refer to the 
- -- applicable agreement for further details.
- -- 
- -- This is a Quartus II output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus II input file. This file cannot be used
- -- to make Quartus II pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus II help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --					Bank 1:		2.5V
- --					Bank 2:		2.5V
- --					Bank 3:		2.5V
- --					Bank 4:		2.5V
- --					Bank 5:		2.5V
- --					Bank 6:		2.5V
- --					Bank 7:		2.5V
- --					Bank 8:		2.5V
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --					It can also be used to report unused dedicated pins. The connection
- --					on the board for unused dedicated pins depends on whether this will
- --					be used in a future design. One example is device migration. When
- --					using device migration, refer to the device pin-tables. If it is a
- --					GND pin in the pin table or if it will not be used in a future design
- --					for another purpose the it MUST be connected to GND. If it is an unused
- --					dedicated pin, then it can be connected to a valid signal on the board
- --					(low, high, or toggling) if that signal is required for a different
- --					revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --					This pin should be connected to GND. It may also be connected  to a
- --					valid signal  on the board  (low, high, or toggling)  if that signal
- --					is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --           	    or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-CHIP  "ten_line_to_four_line_BCD_priority_encoder"  ASSIGNED TO AN: EP3C16F484C6
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : A1        : gnd    :                   :         :           :                
-VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
-GND+                         : A11       :        :                   :         : 8         :                
-GND+                         : A12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
-VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
-GND                          : A22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
-VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
-GND+                         : AA11      :        :                   :         : 3         :                
-GND+                         : AA12      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
-GND                          : AB1       : gnd    :                   :         :           :                
-VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
-GND                          : AB6       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
-GND+                         : AB11      :        :                   :         : 3         :                
-GND+                         : AB12      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
-VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
-GND                          : AB22      : gnd    :                   :         :           :                
-D                            : B1        : output : 2.5 V             :         : 1         : Y              
-C                            : B2        : output : 2.5 V             :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
-GND+                         : B11       :        :                   :         : 8         :                
-GND+                         : B12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
-A                            : C1        : output : 2.5 V             :         : 1         : Y              
-B                            : C2        : output : 2.5 V             :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
-GND                          : C5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
-GND                          : C9        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
-GND                          : C11       : gnd    :                   :         :           :                
-GND                          : C12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
-GND                          : C14       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
-GND                          : C16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
-GND                          : C18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
-I2                           : D2        : input  : 2.5 V             :         : 1         : Y              
-GND                          : D3        : gnd    :                   :         :           :                
-VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
-VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
-GND                          : D7        : gnd    :                   :         :           :                
-GND                          : D8        : gnd    :                   :         :           :                
-VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
-VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
-VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
-VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
-VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
-VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 1         :                
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
-I4                           : E3        : input  : 2.5 V             :         : 1         : Y              
-I3                           : E4        : input  : 2.5 V             :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
-VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
-VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
-GNDA2                        : E18       : gnd    :                   :         :           :                
-VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
-GND                          : E20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2        :        :                   :         : 1         :                
-GND                          : F3        : gnd    :                   :         :           :                
-VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
-GNDA3                        : F5        : gnd    :                   :         :           :                
-VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
-VCCA2                        : F18       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
-GND+                         : G1        :        :                   :         : 1         :                
-GND+                         : G2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3        :        :                   :         : 1         :                
-I8                           : G4        : input  : 2.5 V             :         : 1         : Y              
-I7                           : G5        : input  : 2.5 V             :         : 1         : Y              
-VCCA3                        : G6        : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
-VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
-GND                          : G20       : gnd    :                   :         :           :                
-GND+                         : G21       :        :                   :         : 6         :                
-GND+                         : G22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
-GND                          : H3        : gnd    :                   :         :           :                
-VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5        :        :                   :         : 1         :                
-I9                           : H6        : input  : 2.5 V             :         : 1         : Y              
-I5                           : H7        : input  : 2.5 V             :         : 1         : Y              
-GND                          : H8        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
-GND                          : J5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6        :        :                   :         : 1         :                
-I6                           : J7        : input  : 2.5 V             :         : 1         : Y              
-VCCINT                       : J8        : power  :                   : 1.2V    :           :                
-GND                          : J9        : gnd    :                   :         :           :                
-VCCINT                       : J10       : power  :                   : 1.2V    :           :                
-VCCINT                       : J11       : power  :                   : 1.2V    :           :                
-VCCINT                       : J12       : power  :                   : 1.2V    :           :                
-VCCINT                       : J13       : power  :                   : 1.2V    :           :                
-VCCINT                       : J14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
-GND                          : J19       : gnd    :                   :         :           :                
-VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
-~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
-GND                          : K3        : gnd    :                   :         :           :                
-VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
-nCONFIG                      : K5        :        :                   :         : 1         :                
-nSTATUS                      : K6        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
-VCCINT                       : K9        : power  :                   : 1.2V    :           :                
-GND                          : K10       : gnd    :                   :         :           :                
-GND                          : K11       : gnd    :                   :         :           :                
-GND                          : K12       : gnd    :                   :         :           :                
-GND                          : K13       : gnd    :                   :         :           :                
-VCCINT                       : K14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
-MSEL3                        : K20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
-TMS                          : L1        : input  :                   :         : 1         :                
-TCK                          : L2        : input  :                   :         : 1         :                
-nCE                          : L3        :        :                   :         : 1         :                
-TDO                          : L4        : output :                   :         : 1         :                
-TDI                          : L5        : input  :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
-VCCINT                       : L9        : power  :                   : 1.2V    :           :                
-GND                          : L10       : gnd    :                   :         :           :                
-GND                          : L11       : gnd    :                   :         :           :                
-GND                          : L12       : gnd    :                   :         :           :                
-GND                          : L13       : gnd    :                   :         :           :                
-VCCINT                       : L14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
-MSEL2                        : L17       :        :                   :         : 6         :                
-MSEL1                        : L18       :        :                   :         : 6         :                
-VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
-GND                          : L20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
-VCCINT                       : M9        : power  :                   : 1.2V    :           :                
-GND                          : M10       : gnd    :                   :         :           :                
-GND                          : M11       : gnd    :                   :         :           :                
-GND                          : M12       : gnd    :                   :         :           :                
-GND                          : M13       : gnd    :                   :         :           :                
-VCCINT                       : M14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
-MSEL0                        : M17       :        :                   :         : 6         :                
-CONF_DONE                    : M18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
-GND                          : N3        : gnd    :                   :         :           :                
-VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
-VCCINT                       : N9        : power  :                   : 1.2V    :           :                
-GND                          : N10       : gnd    :                   :         :           :                
-GND                          : N11       : gnd    :                   :         :           :                
-GND                          : N12       : gnd    :                   :         :           :                
-GND                          : N13       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
-VCCINT                       : P9        : power  :                   : 1.2V    :           :                
-VCCINT                       : P10       : power  :                   : 1.2V    :           :                
-VCCINT                       : P11       : power  :                   : 1.2V    :           :                
-VCCINT                       : P12       : power  :                   : 1.2V    :           :                
-VCCINT                       : P13       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
-VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
-GND                          : P19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
-GND                          : R3        : gnd    :                   :         :           :                
-VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
-GND+                         : T1        :        :                   :         : 2         :                
-GND+                         : T2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
-VCCA1                        : T6        : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
-VCCINT                       : T13       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
-VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
-GND                          : T20       : gnd    :                   :         :           :                
-GND+                         : T21       :        :                   :         : 5         :                
-GND+                         : T22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
-GND                          : U3        : gnd    :                   :         :           :                
-VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
-GNDA1                        : U5        : gnd    :                   :         :           :                
-VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
-VCCINT                       : U16       : power  :                   : 1.2V    :           :                
-VCCINT                       : U17       : power  :                   : 1.2V    :           :                
-VCCA4                        : U18       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
-VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
-GNDA4                        : V18       : gnd    :                   :         :           :                
-VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
-GND                          : V20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
-GND                          : W3        : gnd    :                   :         :           :                
-VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
-VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
-VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
-VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
-VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
-VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
-VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
-GND                          : Y5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
-GND                          : Y9        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
-GND                          : Y11       : gnd    :                   :         :           :                
-GND                          : Y12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
-VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
-GND                          : Y15       : gnd    :                   :         :           :                
-GND                          : Y16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
-GND                          : Y18       : gnd    :                   :         :           :                
-VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
-GND                          : Y20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.sof b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.sof
deleted file mode 100644
index c88e43c4ca3379c88313bf7696fbc8646c0f306d..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.sta.rpt b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.sta.rpt
deleted file mode 100644
index 1e3961fe..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.sta.rpt
+++ /dev/null
@@ -1,640 +0,0 @@
-TimeQuest Timing Analyzer report for ten_line_to_four_line_BCD_priority_encoder
-Thu Oct 17 21:26:28 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. Clocks
-  5. Slow 1200mV 85C Model Fmax Summary
-  6. Timing Closure Recommendations
-  7. Slow 1200mV 85C Model Setup Summary
-  8. Slow 1200mV 85C Model Hold Summary
-  9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Propagation Delay
- 13. Minimum Propagation Delay
- 14. Slow 1200mV 85C Model Metastability Report
- 15. Slow 1200mV 0C Model Fmax Summary
- 16. Slow 1200mV 0C Model Setup Summary
- 17. Slow 1200mV 0C Model Hold Summary
- 18. Slow 1200mV 0C Model Recovery Summary
- 19. Slow 1200mV 0C Model Removal Summary
- 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 21. Propagation Delay
- 22. Minimum Propagation Delay
- 23. Slow 1200mV 0C Model Metastability Report
- 24. Fast 1200mV 0C Model Setup Summary
- 25. Fast 1200mV 0C Model Hold Summary
- 26. Fast 1200mV 0C Model Recovery Summary
- 27. Fast 1200mV 0C Model Removal Summary
- 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 29. Propagation Delay
- 30. Minimum Propagation Delay
- 31. Fast 1200mV 0C Model Metastability Report
- 32. Multicorner Timing Analysis Summary
- 33. Propagation Delay
- 34. Minimum Propagation Delay
- 35. Board Trace Model Assignments
- 36. Input Transition Times
- 37. Slow Corner Signal Integrity Metrics
- 38. Fast Corner Signal Integrity Metrics
- 39. Clock Transfers
- 40. Report TCCS
- 41. Report RSKM
- 42. Unconstrained Paths
- 43. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                       ;
-+--------------------+----------------------------------------------------+
-; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name      ; ten_line_to_four_line_BCD_priority_encoder         ;
-; Device Family      ; Cyclone III                                        ;
-; Device Name        ; EP3C16F484C6                                       ;
-; Timing Models      ; Final                                              ;
-; Delay Model        ; Combined                                           ;
-; Rise/Fall Delays   ; Enabled                                            ;
-+--------------------+----------------------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; I2         ; B           ;       ; 7.089 ; 7.440 ;       ;
-; I3         ; A           ;       ; 6.494 ; 6.910 ;       ;
-; I3         ; B           ;       ; 6.788 ; 7.144 ;       ;
-; I4         ; A           ; 6.250 ;       ;       ; 6.641 ;
-; I4         ; B           ; 6.486 ;       ;       ; 6.937 ;
-; I4         ; C           ;       ; 6.289 ; 6.735 ;       ;
-; I5         ; A           ;       ; 6.593 ; 7.000 ;       ;
-; I5         ; B           ; 6.842 ;       ;       ; 7.317 ;
-; I5         ; C           ;       ; 6.425 ; 6.857 ;       ;
-; I6         ; A           ; 6.780 ;       ;       ; 7.228 ;
-; I6         ; B           ;       ; 6.470 ; 6.907 ;       ;
-; I6         ; C           ;       ; 6.890 ; 7.386 ;       ;
-; I7         ; A           ;       ; 6.456 ; 6.875 ;       ;
-; I7         ; B           ;       ; 6.292 ; 6.709 ;       ;
-; I7         ; C           ;       ; 6.727 ; 7.201 ;       ;
-; I8         ; A           ; 6.355 ;       ;       ; 6.780 ;
-; I8         ; B           ; 6.721 ;       ;       ; 7.100 ;
-; I8         ; C           ; 7.156 ;       ;       ; 7.512 ;
-; I8         ; D           ;       ; 6.596 ; 7.037 ;       ;
-; I9         ; A           ;       ; 6.462 ; 6.877 ;       ;
-; I9         ; B           ; 6.561 ;       ;       ; 6.918 ;
-; I9         ; C           ; 6.996 ;       ;       ; 7.330 ;
-; I9         ; D           ;       ; 6.436 ; 6.855 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; I2         ; B           ;       ; 6.922 ; 7.264 ;       ;
-; I3         ; A           ;       ; 6.348 ; 6.753 ;       ;
-; I3         ; B           ;       ; 6.631 ; 6.978 ;       ;
-; I4         ; A           ; 6.115 ;       ;       ; 6.493 ;
-; I4         ; B           ; 6.341 ;       ;       ; 6.778 ;
-; I4         ; C           ;       ; 6.151 ; 6.586 ;       ;
-; I5         ; A           ;       ; 6.440 ; 6.838 ;       ;
-; I5         ; B           ; 6.682 ;       ;       ; 7.143 ;
-; I5         ; C           ;       ; 6.281 ; 6.701 ;       ;
-; I6         ; A           ; 6.562 ;       ;       ; 6.972 ;
-; I6         ; B           ;       ; 6.325 ; 6.749 ;       ;
-; I6         ; C           ;       ; 6.681 ; 7.151 ;       ;
-; I7         ; A           ;       ; 6.311 ; 6.720 ;       ;
-; I7         ; B           ;       ; 6.154 ; 6.559 ;       ;
-; I7         ; C           ;       ; 6.568 ; 7.031 ;       ;
-; I8         ; A           ; 6.213 ;       ;       ; 6.627 ;
-; I8         ; B           ; 6.568 ;       ;       ; 6.935 ;
-; I8         ; C           ; 6.908 ;       ;       ; 7.260 ;
-; I8         ; D           ;       ; 6.447 ; 6.875 ;       ;
-; I9         ; A           ;       ; 6.250 ; 6.654 ;       ;
-; I9         ; B           ; 6.414 ;       ;       ; 6.761 ;
-; I9         ; C           ; 6.754 ;       ;       ; 7.086 ;
-; I9         ; D           ;       ; 6.293 ; 6.701 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-----------------------------------------------
-; Slow 1200mV 85C Model Metastability Report ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; I2         ; B           ;       ; 6.554 ; 6.862 ;       ;
-; I3         ; A           ;       ; 6.010 ; 6.389 ;       ;
-; I3         ; B           ;       ; 6.271 ; 6.595 ;       ;
-; I4         ; A           ; 5.814 ;       ;       ; 6.130 ;
-; I4         ; B           ; 6.021 ;       ;       ; 6.394 ;
-; I4         ; C           ;       ; 5.840 ; 6.248 ;       ;
-; I5         ; A           ;       ; 6.108 ; 6.473 ;       ;
-; I5         ; B           ; 6.349 ;       ;       ; 6.733 ;
-; I5         ; C           ;       ; 5.960 ; 6.357 ;       ;
-; I6         ; A           ; 6.297 ;       ;       ; 6.642 ;
-; I6         ; B           ;       ; 6.003 ; 6.373 ;       ;
-; I6         ; C           ;       ; 6.383 ; 6.818 ;       ;
-; I7         ; A           ;       ; 5.991 ; 6.349 ;       ;
-; I7         ; B           ;       ; 5.844 ; 6.208 ;       ;
-; I7         ; C           ;       ; 6.240 ; 6.665 ;       ;
-; I8         ; A           ; 5.909 ;       ;       ; 6.255 ;
-; I8         ; B           ; 6.237 ;       ;       ; 6.546 ;
-; I8         ; C           ; 6.639 ;       ;       ; 6.915 ;
-; I8         ; D           ;       ; 6.119 ; 6.507 ;       ;
-; I9         ; A           ;       ; 5.987 ; 6.350 ;       ;
-; I9         ; B           ; 6.094 ;       ;       ; 6.383 ;
-; I9         ; C           ; 6.496 ;       ;       ; 6.752 ;
-; I9         ; D           ;       ; 5.976 ; 6.344 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; I2         ; B           ;       ; 6.410 ; 6.712 ;       ;
-; I3         ; A           ;       ; 5.888 ; 6.256 ;       ;
-; I3         ; B           ;       ; 6.137 ; 6.453 ;       ;
-; I4         ; A           ; 5.698 ;       ;       ; 6.009 ;
-; I4         ; B           ; 5.897 ;       ;       ; 6.259 ;
-; I4         ; C           ;       ; 5.723 ; 6.121 ;       ;
-; I5         ; A           ;       ; 5.979 ; 6.334 ;       ;
-; I5         ; B           ; 6.212 ;       ;       ; 6.584 ;
-; I5         ; C           ;       ; 5.838 ; 6.225 ;       ;
-; I6         ; A           ; 6.106 ;       ;       ; 6.424 ;
-; I6         ; B           ;       ; 5.878 ; 6.241 ;       ;
-; I6         ; C           ;       ; 6.200 ; 6.614 ;       ;
-; I7         ; A           ;       ; 5.869 ; 6.216 ;       ;
-; I7         ; B           ;       ; 5.726 ; 6.081 ;       ;
-; I7         ; C           ;       ; 6.104 ; 6.518 ;       ;
-; I8         ; A           ; 5.787 ;       ;       ; 6.126 ;
-; I8         ; B           ; 6.103 ;       ;       ; 6.406 ;
-; I8         ; C           ; 6.422 ;       ;       ; 6.702 ;
-; I8         ; D           ;       ; 5.990 ; 6.370 ;       ;
-; I9         ; A           ;       ; 5.808 ; 6.157 ;       ;
-; I9         ; B           ; 5.966 ;       ;       ; 6.247 ;
-; I9         ; C           ; 6.285 ;       ;       ; 6.543 ;
-; I9         ; D           ;       ; 5.853 ; 6.211 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
----------------------------------------------
-; Slow 1200mV 0C Model Metastability Report ;
----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; I2         ; B           ;       ; 4.235 ; 4.769 ;       ;
-; I3         ; A           ;       ; 3.884 ; 4.431 ;       ;
-; I3         ; B           ;       ; 4.050 ; 4.564 ;       ;
-; I4         ; A           ; 3.733 ;       ;       ; 4.291 ;
-; I4         ; B           ; 3.868 ;       ;       ; 4.459 ;
-; I4         ; C           ;       ; 3.780 ; 4.339 ;       ;
-; I5         ; A           ;       ; 3.945 ; 4.485 ;       ;
-; I5         ; B           ; 4.074 ;       ;       ; 4.685 ;
-; I5         ; C           ;       ; 3.863 ; 4.414 ;       ;
-; I6         ; A           ; 4.038 ;       ;       ; 4.637 ;
-; I6         ; B           ;       ; 3.884 ; 4.456 ;       ;
-; I6         ; C           ;       ; 4.116 ; 4.712 ;       ;
-; I7         ; A           ;       ; 3.873 ; 4.442 ;       ;
-; I7         ; B           ;       ; 3.787 ; 4.339 ;       ;
-; I7         ; C           ;       ; 4.020 ; 4.601 ;       ;
-; I8         ; A           ; 3.821 ;       ;       ; 4.388 ;
-; I8         ; B           ; 4.031 ;       ;       ; 4.564 ;
-; I8         ; C           ; 4.272 ;       ;       ; 4.792 ;
-; I8         ; D           ;       ; 3.995 ; 4.524 ;       ;
-; I9         ; A           ;       ; 3.865 ; 4.439 ;       ;
-; I9         ; B           ; 3.920 ;       ;       ; 4.459 ;
-; I9         ; C           ; 4.161 ;       ;       ; 4.687 ;
-; I9         ; D           ;       ; 3.884 ; 4.419 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; I2         ; B           ;       ; 4.138 ; 4.668 ;       ;
-; I3         ; A           ;       ; 3.799 ; 4.340 ;       ;
-; I3         ; B           ;       ; 3.959 ; 4.470 ;       ;
-; I4         ; A           ; 3.653 ;       ;       ; 4.207 ;
-; I4         ; B           ; 3.784 ;       ;       ; 4.368 ;
-; I4         ; C           ;       ; 3.699 ; 4.253 ;       ;
-; I5         ; A           ;       ; 3.857 ; 4.390 ;       ;
-; I5         ; B           ; 3.982 ;       ;       ; 4.585 ;
-; I5         ; C           ;       ; 3.779 ; 4.325 ;       ;
-; I6         ; A           ; 3.911 ;       ;       ; 4.490 ;
-; I6         ; B           ;       ; 3.799 ; 4.366 ;       ;
-; I6         ; C           ;       ; 3.997 ; 4.576 ;       ;
-; I7         ; A           ;       ; 3.787 ; 4.350 ;       ;
-; I7         ; B           ;       ; 3.706 ; 4.253 ;       ;
-; I7         ; C           ;       ; 3.931 ; 4.505 ;       ;
-; I8         ; A           ; 3.738 ;       ;       ; 4.299 ;
-; I8         ; B           ; 3.940 ;       ;       ; 4.469 ;
-; I8         ; C           ; 4.123 ;       ;       ; 4.647 ;
-; I8         ; D           ;       ; 3.905 ; 4.430 ;       ;
-; I9         ; A           ;       ; 3.740 ; 4.306 ;       ;
-; I9         ; B           ; 3.833 ;       ;       ; 4.368 ;
-; I9         ; C           ; 4.016 ;       ;       ; 4.546 ;
-; I9         ; D           ;       ; 3.798 ; 4.329 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
----------------------------------------------
-; Fast 1200mV 0C Model Metastability Report ;
----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary                                        ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
-; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; I2         ; B           ;       ; 7.089 ; 7.440 ;       ;
-; I3         ; A           ;       ; 6.494 ; 6.910 ;       ;
-; I3         ; B           ;       ; 6.788 ; 7.144 ;       ;
-; I4         ; A           ; 6.250 ;       ;       ; 6.641 ;
-; I4         ; B           ; 6.486 ;       ;       ; 6.937 ;
-; I4         ; C           ;       ; 6.289 ; 6.735 ;       ;
-; I5         ; A           ;       ; 6.593 ; 7.000 ;       ;
-; I5         ; B           ; 6.842 ;       ;       ; 7.317 ;
-; I5         ; C           ;       ; 6.425 ; 6.857 ;       ;
-; I6         ; A           ; 6.780 ;       ;       ; 7.228 ;
-; I6         ; B           ;       ; 6.470 ; 6.907 ;       ;
-; I6         ; C           ;       ; 6.890 ; 7.386 ;       ;
-; I7         ; A           ;       ; 6.456 ; 6.875 ;       ;
-; I7         ; B           ;       ; 6.292 ; 6.709 ;       ;
-; I7         ; C           ;       ; 6.727 ; 7.201 ;       ;
-; I8         ; A           ; 6.355 ;       ;       ; 6.780 ;
-; I8         ; B           ; 6.721 ;       ;       ; 7.100 ;
-; I8         ; C           ; 7.156 ;       ;       ; 7.512 ;
-; I8         ; D           ;       ; 6.596 ; 7.037 ;       ;
-; I9         ; A           ;       ; 6.462 ; 6.877 ;       ;
-; I9         ; B           ; 6.561 ;       ;       ; 6.918 ;
-; I9         ; C           ; 6.996 ;       ;       ; 7.330 ;
-; I9         ; D           ;       ; 6.436 ; 6.855 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; I2         ; B           ;       ; 4.138 ; 4.668 ;       ;
-; I3         ; A           ;       ; 3.799 ; 4.340 ;       ;
-; I3         ; B           ;       ; 3.959 ; 4.470 ;       ;
-; I4         ; A           ; 3.653 ;       ;       ; 4.207 ;
-; I4         ; B           ; 3.784 ;       ;       ; 4.368 ;
-; I4         ; C           ;       ; 3.699 ; 4.253 ;       ;
-; I5         ; A           ;       ; 3.857 ; 4.390 ;       ;
-; I5         ; B           ; 3.982 ;       ;       ; 4.585 ;
-; I5         ; C           ;       ; 3.779 ; 4.325 ;       ;
-; I6         ; A           ; 3.911 ;       ;       ; 4.490 ;
-; I6         ; B           ;       ; 3.799 ; 4.366 ;       ;
-; I6         ; C           ;       ; 3.997 ; 4.576 ;       ;
-; I7         ; A           ;       ; 3.787 ; 4.350 ;       ;
-; I7         ; B           ;       ; 3.706 ; 4.253 ;       ;
-; I7         ; C           ;       ; 3.931 ; 4.505 ;       ;
-; I8         ; A           ; 3.738 ;       ;       ; 4.299 ;
-; I8         ; B           ; 3.940 ;       ;       ; 4.469 ;
-; I8         ; C           ; 4.123 ;       ;       ; 4.647 ;
-; I8         ; D           ;       ; 3.905 ; 4.430 ;       ;
-; I9         ; A           ;       ; 3.740 ; 4.306 ;       ;
-; I9         ; B           ; 3.833 ;       ;       ; 4.368 ;
-; I9         ; C           ; 4.016 ;       ;       ; 4.546 ;
-; I9         ; D           ;       ; 3.798 ; 4.329 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; A             ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; B             ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; C             ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; D             ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times                                                     ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; I6                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I4                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I3                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I5                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I7                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I9                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I8                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; I2                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; A             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; B             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; C             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; D             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; A             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; B             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; C             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; D             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths                            ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 8     ; 8    ;
-; Unconstrained Input Port Paths  ; 23    ; 23   ;
-; Unconstrained Output Ports      ; 4     ; 4    ;
-; Unconstrained Output Port Paths ; 23    ; 23   ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 17 21:26:26 2019
-Info: Command: quartus_sta ten_line_to_four_line_BCD_priority_encoder -c ten_line_to_four_line_BCD_priority_encoder
-Info: qsta_default_script.tcl version: #1
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (21077): Core supply voltage is 1.2V
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ten_line_to_four_line_BCD_priority_encoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 369 megabytes
-    Info: Processing ended: Thu Oct 17 21:26:28 2019
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.sta.summary b/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.sta.summary
deleted file mode 100644
index 33f74363..00000000
--- a/CH6/CH6-1/output_files/ten_line_to_four_line_BCD_priority_encoder.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.asm.rpt b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.asm.rpt
deleted file mode 100644
index 6cea6a0b..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.asm.rpt
+++ /dev/null
@@ -1,116 +0,0 @@
-Assembler report for three_line_to_eight_decimal_decoder
-Thu Oct 24 21:57:51 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: three_line_to_eight_decimal_decoder.sof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Oct 24 21:57:51 2019 ;
-; Revision Name         ; three_line_to_eight_decimal_decoder   ;
-; Top-level Entity Name ; three_line_to_eight_decimal_decoder   ;
-; Family                ; Cyclone III                           ;
-; Device                ; EP3C16F484C6                          ;
-+-----------------------+---------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Assembler Settings                                                                                     ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Option                                                                      ; Setting  ; Default Value ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Use smart compilation                                                       ; Off      ; Off           ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
-; Enable compact report table                                                 ; Off      ; Off           ;
-; Generate compressed bitstreams                                              ; On       ; On            ;
-; Compression mode                                                            ; Off      ; Off           ;
-; Clock source for configuration device                                       ; Internal ; Internal      ;
-; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
-; Divide clock frequency by                                                   ; 1        ; 1             ;
-; Auto user code                                                              ; On       ; On            ;
-; Use configuration device                                                    ; Off      ; Off           ;
-; Configuration device                                                        ; Auto     ; Auto          ;
-; Configuration device auto user code                                         ; Off      ; Off           ;
-; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
-; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
-; Hexadecimal Output File start address                                       ; 0        ; 0             ;
-; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
-; Release clears before tri-states                                            ; Off      ; Off           ;
-; Auto-restart configuration after error                                      ; On       ; On            ;
-; Enable OCT_DONE                                                             ; Off      ; Off           ;
-; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
-+-----------------------------------------------------------------------------+----------+---------------+
-
-
-+-----------------------------------------+
-; Assembler Generated Files               ;
-+-----------------------------------------+
-; File Name                               ;
-+-----------------------------------------+
-; three_line_to_eight_decimal_decoder.sof ;
-+-----------------------------------------+
-
-
-+-------------------------------------------------------------------+
-; Assembler Device Options: three_line_to_eight_decimal_decoder.sof ;
-+----------------+--------------------------------------------------+
-; Option         ; Setting                                          ;
-+----------------+--------------------------------------------------+
-; Device         ; EP3C16F484C6                                     ;
-; JTAG usercode  ; 0x000C903B                                       ;
-; Checksum       ; 0x000C903B                                       ;
-+----------------+--------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit Assembler
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 24 21:57:49 2019
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 382 megabytes
-    Info: Processing ended: Thu Oct 24 21:57:51 2019
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.done b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.done
deleted file mode 100644
index 33a4669a..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.done
+++ /dev/null
@@ -1 +0,0 @@
-Thu Oct 24 21:58:03 2019
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.eda.rpt b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.eda.rpt
deleted file mode 100644
index b8c4d447..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.eda.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-EDA Netlist Writer report for three_line_to_eight_decimal_decoder
-Thu Oct 24 21:58:03 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. EDA Netlist Writer Summary
-  3. Simulation Settings
-  4. Simulation Generated Files
-  5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary                                        ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Oct 24 21:58:03 2019 ;
-; Revision Name             ; three_line_to_eight_decimal_decoder   ;
-; Top-level Entity Name     ; three_line_to_eight_decimal_decoder   ;
-; Family                    ; Cyclone III                           ;
-; Simulation Files Creation ; Successful                            ;
-+---------------------------+---------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings                                                                                                           ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-; Option                                                                                            ; Setting                   ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
-; Generate netlist for functional simulation only                                                   ; On                        ;
-; Truncate long hierarchy paths                                                                     ; Off                       ;
-; Map illegal HDL characters                                                                        ; Off                       ;
-; Flatten buses into individual nodes                                                               ; Off                       ;
-; Maintain hierarchy                                                                                ; Off                       ;
-; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
-; Enable glitch filtering                                                                           ; Off                       ;
-; Do not write top level VHDL entity                                                                ; Off                       ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
-; Architecture name in VHDL output netlist                                                          ; structure                 ;
-; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
-; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
-+---------------------------------------------------------------------------------------------------+---------------------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Simulation Generated Files                                                                   ;
-+----------------------------------------------------------------------------------------------+
-; Generated Files                                                                              ;
-+----------------------------------------------------------------------------------------------+
-; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//three_line_to_eight_decimal_decoder.vo ;
-+----------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit EDA Netlist Writer
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 24 21:58:02 2019
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder
-Info (204019): Generated file three_line_to_eight_decimal_decoder.vo in folder "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim//" for EDA simulation tool
-Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 348 megabytes
-    Info: Processing ended: Thu Oct 24 21:58:03 2019
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.rpt b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.rpt
deleted file mode 100644
index 3de312b3..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.rpt
+++ /dev/null
@@ -1,1238 +0,0 @@
-Fitter report for three_line_to_eight_decimal_decoder
-Thu Oct 24 21:57:44 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. I/O Assignment Warnings
-  6. Incremental Compilation Preservation Summary
-  7. Incremental Compilation Partition Settings
-  8. Incremental Compilation Placement Preservation
-  9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. Fitter Resource Utilization by Entity
- 18. Delay Chain Summary
- 19. Pad To Core Delay Chain Fanout
- 20. Non-Global High Fan-Out Signals
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Fitter Summary                                                                  ;
-+------------------------------------+--------------------------------------------+
-; Fitter Status                      ; Successful - Thu Oct 24 21:57:44 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; three_line_to_eight_decimal_decoder        ;
-; Top-level Entity Name              ; three_line_to_eight_decimal_decoder        ;
-; Family                             ; Cyclone III                                ;
-; Device                             ; EP3C16F484C6                               ;
-; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 8 / 15,408 ( < 1 % )                       ;
-;     Total combinational functions  ; 8 / 15,408 ( < 1 % )                       ;
-;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 11 / 347 ( 3 % )                           ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
-; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
-; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
-+------------------------------------+--------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                                            ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option                                                                     ; Setting                               ; Default Value                         ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device                                                                     ; EP3C16F484C6                          ;                                       ;
-; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
-; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
-; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
-; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
-; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
-; Use smart compilation                                                      ; Off                                   ; Off                                   ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
-; Enable compact report table                                                ; Off                                   ; Off                                   ;
-; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
-; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
-; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
-; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
-; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
-; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
-; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
-; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
-; SSN Optimization                                                           ; Off                                   ; Off                                   ;
-; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
-; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
-; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
-; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
-; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
-; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
-; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
-; PCI I/O                                                                    ; Off                                   ; Off                                   ;
-; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
-; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
-; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
-; Auto Delay Chains                                                          ; On                                    ; On                                    ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
-; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
-; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
-; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
-; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
-; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
-; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
-; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
-; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
-; Auto Global Clock                                                          ; On                                    ; On                                    ;
-; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
-; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
-; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
-; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
-; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
-; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings                         ;
-+----------+--------------------------------------+
-; Pin Name ; Reason                               ;
-+----------+--------------------------------------+
-; Y0       ; Missing drive strength and slew rate ;
-; Y1       ; Missing drive strength and slew rate ;
-; Y2       ; Missing drive strength and slew rate ;
-; Y3       ; Missing drive strength and slew rate ;
-; Y4       ; Missing drive strength and slew rate ;
-; Y5       ; Missing drive strength and slew rate ;
-; Y6       ; Missing drive strength and slew rate ;
-; Y7       ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary                                                    ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ;                   ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 41 ) ; 0.00 % ( 0 / 41 )          ; 0.00 % ( 0 / 41 )        ;
-;     -- Achieved     ; 0.00 % ( 0 / 41 ) ; 0.00 % ( 0 / 41 )          ; 0.00 % ( 0 / 41 )        ;
-;                     ;                   ;                            ;                          ;
-; Routing (by net)    ;                   ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings                                                                                                                                             ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation                                                                                     ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 31 )     ; N/A                     ; Source File       ; N/A                 ;       ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.pin.
-
-
-+--------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                      ;
-+---------------------------------------------+----------------------+
-; Resource                                    ; Usage                ;
-+---------------------------------------------+----------------------+
-; Total logic elements                        ; 8 / 15,408 ( < 1 % ) ;
-;     -- Combinational with no register       ; 8                    ;
-;     -- Register only                        ; 0                    ;
-;     -- Combinational with a register        ; 0                    ;
-;                                             ;                      ;
-; Logic element usage by number of LUT inputs ;                      ;
-;     -- 4 input functions                    ; 0                    ;
-;     -- 3 input functions                    ; 8                    ;
-;     -- <=2 input functions                  ; 0                    ;
-;     -- Register only                        ; 0                    ;
-;                                             ;                      ;
-; Logic elements by mode                      ;                      ;
-;     -- normal mode                          ; 8                    ;
-;     -- arithmetic mode                      ; 0                    ;
-;                                             ;                      ;
-; Total registers*                            ; 0 / 17,068 ( 0 % )   ;
-;     -- Dedicated logic registers            ; 0 / 15,408 ( 0 % )   ;
-;     -- I/O registers                        ; 0 / 1,660 ( 0 % )    ;
-;                                             ;                      ;
-; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )    ;
-; Virtual pins                                ; 0                    ;
-; I/O pins                                    ; 11 / 347 ( 3 % )     ;
-;     -- Clock pins                           ; 0 / 8 ( 0 % )        ;
-;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )        ;
-;                                             ;                      ;
-; Global signals                              ; 0                    ;
-; M9Ks                                        ; 0 / 56 ( 0 % )       ;
-; Total block memory bits                     ; 0 / 516,096 ( 0 % )  ;
-; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )  ;
-; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ;
-; PLLs                                        ; 0 / 4 ( 0 % )        ;
-; Global clocks                               ; 0 / 20 ( 0 % )       ;
-; JTAGs                                       ; 0 / 1 ( 0 % )        ;
-; CRC blocks                                  ; 0 / 1 ( 0 % )        ;
-; ASMI blocks                                 ; 0 / 1 ( 0 % )        ;
-; Impedance control blocks                    ; 0 / 4 ( 0 % )        ;
-; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%         ;
-; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%         ;
-; Maximum fan-out                             ; 8                    ;
-; Highest non-global fan-out                  ; 8                    ;
-; Total fan-out                               ; 48                   ;
-; Average fan-out                             ; 1.20                 ;
-+---------------------------------------------+----------------------+
-*  Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics                                                                        ;
-+---------------------------------------------+---------------------+--------------------------------+
-; Statistic                                   ; Top                 ; hard_block:auto_generated_inst ;
-+---------------------------------------------+---------------------+--------------------------------+
-; Difficulty Clustering Region                ; Low                 ; Low                            ;
-;                                             ;                     ;                                ;
-; Total logic elements                        ; 8 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
-;     -- Combinational with no register       ; 8                   ; 0                              ;
-;     -- Register only                        ; 0                   ; 0                              ;
-;     -- Combinational with a register        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Logic element usage by number of LUT inputs ;                     ;                                ;
-;     -- 4 input functions                    ; 0                   ; 0                              ;
-;     -- 3 input functions                    ; 8                   ; 0                              ;
-;     -- <=2 input functions                  ; 0                   ; 0                              ;
-;     -- Register only                        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Logic elements by mode                      ;                     ;                                ;
-;     -- normal mode                          ; 8                   ; 0                              ;
-;     -- arithmetic mode                      ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Total registers                             ; 0                   ; 0                              ;
-;     -- Dedicated logic registers            ; 0 / 15408 ( 0 % )   ; 0 / 15408 ( 0 % )              ;
-;     -- I/O registers                        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )   ; 0 / 963 ( 0 % )                ;
-;                                             ;                     ;                                ;
-; Virtual pins                                ; 0                   ; 0                              ;
-; I/O pins                                    ; 11                  ; 0                              ;
-; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )     ; 0 / 112 ( 0 % )                ;
-; Total memory bits                           ; 0                   ; 0                              ;
-; Total RAM block bits                        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Connections                                 ;                     ;                                ;
-;     -- Input Connections                    ; 0                   ; 0                              ;
-;     -- Registered Input Connections         ; 0                   ; 0                              ;
-;     -- Output Connections                   ; 0                   ; 0                              ;
-;     -- Registered Output Connections        ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Internal Connections                        ;                     ;                                ;
-;     -- Total Connections                    ; 43                  ; 5                              ;
-;     -- Registered Connections               ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; External Connections                        ;                     ;                                ;
-;     -- Top                                  ; 0                   ; 0                              ;
-;     -- hard_block:auto_generated_inst       ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Partition Interface                         ;                     ;                                ;
-;     -- Input Ports                          ; 3                   ; 0                              ;
-;     -- Output Ports                         ; 8                   ; 0                              ;
-;     -- Bidir Ports                          ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Registered Ports                            ;                     ;                                ;
-;     -- Registered Input Ports               ; 0                   ; 0                              ;
-;     -- Registered Output Ports              ; 0                   ; 0                              ;
-;                                             ;                     ;                                ;
-; Port Connectivity                           ;                     ;                                ;
-;     -- Input Ports driven by GND            ; 0                   ; 0                              ;
-;     -- Output Ports driven by GND           ; 0                   ; 0                              ;
-;     -- Input Ports driven by VCC            ; 0                   ; 0                              ;
-;     -- Output Ports driven by VCC           ; 0                   ; 0                              ;
-;     -- Input Ports with no Source           ; 0                   ; 0                              ;
-;     -- Output Ports with no Source          ; 0                   ; 0                              ;
-;     -- Input Ports with no Fanout           ; 0                   ; 0                              ;
-;     -- Output Ports with no Fanout          ; 0                   ; 0                              ;
-+---------------------------------------------+---------------------+--------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                                                                ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; A    ; E3    ; 1        ; 0            ; 26           ; 7            ; 8                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; B    ; E4    ; 1        ; 0            ; 26           ; 0            ; 8                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-; C    ; D2    ; 1        ; 0            ; 25           ; 0            ; 8                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
-+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Y0   ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; Y1   ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; Y2   ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; Y3   ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; Y4   ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; Y5   ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; Y6   ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-; Y7   ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins                                                                                         ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; E4       ; DIFFIO_L2p, nRESET          ; Use as regular IO        ; B                       ; Dual Purpose Pin          ;
-; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
-; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
-; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
-; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
-; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
-; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
-; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
-; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
-; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
-; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage                                             ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1        ; 15 / 33 ( 45 % ) ; 2.5V          ; --           ;
-; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
-; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
-; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
-; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
-; 6        ; 1 / 43 ( 2 % )   ; 2.5V          ; --           ;
-; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
-; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                                                                        ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; B1       ; 2          ; 1        ; Y0                                                        ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; B2       ; 1          ; 1        ; Y1                                                        ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C1       ; 7          ; 1        ; Y3                                                        ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; C2       ; 6          ; 1        ; Y2                                                        ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; D2       ; 8          ; 1        ; C                                                         ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E1       ; 14         ; 1        ; Y4                                                        ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; E3       ; 5          ; 1        ; A                                                         ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; E4       ; 4          ; 1        ; B                                                         ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F2       ; 15         ; 1        ; Y5                                                        ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G4       ; 17         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G5       ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; G21      ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H1       ; 26         ; 1        ; Y6                                                        ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H6       ; 11         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H7       ; 10         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J1       ; 29         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J2       ; 28         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J3       ; 27         ; 1        ; Y7                                                        ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J6       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J7       ; 22         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
-; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
-; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                 ;
-+--------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------+--------------+
-; Compilation Hierarchy Node           ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                             ; Library Name ;
-+--------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------+--------------+
-; |three_line_to_eight_decimal_decoder ; 8 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 11   ; 0            ; 8 (0)        ; 0 (0)             ; 0 (0)            ; |three_line_to_eight_decimal_decoder            ; work         ;
-;    |74139:inst|                      ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; |three_line_to_eight_decimal_decoder|74139:inst ; work         ;
-+--------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+--------------------------------------------------------------------------------------+
-; Delay Chain Summary                                                                  ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-; Y0   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y1   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y2   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y3   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y4   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y5   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y6   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; Y7   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
-; C    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
-; A    ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-; B    ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
-+------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+------------------------------------------------------+
-; Pad To Core Delay Chain Fanout                       ;
-+------------------------+-------------------+---------+
-; Source Pin / Fanout    ; Pad To Core Index ; Setting ;
-+------------------------+-------------------+---------+
-; C                      ;                   ;         ;
-;      - 74139:inst|33~0 ; 0                 ; 6       ;
-;      - 74139:inst|33~1 ; 0                 ; 6       ;
-;      - 74139:inst|33~2 ; 0                 ; 6       ;
-;      - 74139:inst|33~3 ; 0                 ; 6       ;
-;      - 74139:inst|33~4 ; 0                 ; 6       ;
-;      - 74139:inst|33~5 ; 0                 ; 6       ;
-;      - 74139:inst|33~6 ; 0                 ; 6       ;
-;      - 74139:inst|33~7 ; 0                 ; 6       ;
-; A                      ;                   ;         ;
-;      - 74139:inst|33~0 ; 1                 ; 6       ;
-;      - 74139:inst|33~1 ; 1                 ; 6       ;
-;      - 74139:inst|33~2 ; 1                 ; 6       ;
-;      - 74139:inst|33~3 ; 1                 ; 6       ;
-;      - 74139:inst|33~4 ; 1                 ; 6       ;
-;      - 74139:inst|33~5 ; 1                 ; 6       ;
-;      - 74139:inst|33~6 ; 1                 ; 6       ;
-;      - 74139:inst|33~7 ; 1                 ; 6       ;
-; B                      ;                   ;         ;
-;      - 74139:inst|33~0 ; 1                 ; 6       ;
-;      - 74139:inst|33~1 ; 1                 ; 6       ;
-;      - 74139:inst|33~2 ; 1                 ; 6       ;
-;      - 74139:inst|33~3 ; 1                 ; 6       ;
-;      - 74139:inst|33~4 ; 1                 ; 6       ;
-;      - 74139:inst|33~5 ; 1                 ; 6       ;
-;      - 74139:inst|33~6 ; 1                 ; 6       ;
-;      - 74139:inst|33~7 ; 1                 ; 6       ;
-+------------------------+-------------------+---------+
-
-
-+---------------------------------+
-; Non-Global High Fan-Out Signals ;
-+-----------------+---------------+
-; Name            ; Fan-Out       ;
-+-----------------+---------------+
-; B~input         ; 8             ;
-; A~input         ; 8             ;
-; C~input         ; 8             ;
-; 74139:inst|33~7 ; 1             ;
-; 74139:inst|33~6 ; 1             ;
-; 74139:inst|33~5 ; 1             ;
-; 74139:inst|33~4 ; 1             ;
-; 74139:inst|33~3 ; 1             ;
-; 74139:inst|33~2 ; 1             ;
-; 74139:inst|33~1 ; 1             ;
-; 74139:inst|33~0 ; 1             ;
-+-----------------+---------------+
-
-
-+-----------------------------------------------+
-; Routing Usage Summary                         ;
-+-----------------------+-----------------------+
-; Routing Resource Type ; Usage                 ;
-+-----------------------+-----------------------+
-; Block interconnects   ; 11 / 47,787 ( < 1 % ) ;
-; C16 interconnects     ; 0 / 1,804 ( 0 % )     ;
-; C4 interconnects      ; 10 / 31,272 ( < 1 % ) ;
-; Direct links          ; 0 / 47,787 ( 0 % )    ;
-; Global clocks         ; 0 / 20 ( 0 % )        ;
-; Local interconnects   ; 0 / 15,408 ( 0 % )    ;
-; R24 interconnects     ; 0 / 1,775 ( 0 % )     ;
-; R4 interconnects      ; 1 / 41,310 ( < 1 % )  ;
-+-----------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements                                                       ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements  (Average = 8.00) ; Number of LABs  (Total = 1) ;
-+--------------------------------------------+-----------------------------+
-; 1                                          ; 0                           ;
-; 2                                          ; 0                           ;
-; 3                                          ; 0                           ;
-; 4                                          ; 0                           ;
-; 5                                          ; 0                           ;
-; 6                                          ; 0                           ;
-; 7                                          ; 0                           ;
-; 8                                          ; 1                           ;
-; 9                                          ; 0                           ;
-; 10                                         ; 0                           ;
-; 11                                         ; 0                           ;
-; 12                                         ; 0                           ;
-; 13                                         ; 0                           ;
-; 14                                         ; 0                           ;
-; 15                                         ; 0                           ;
-; 16                                         ; 0                           ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced                                                       ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced  (Average = 8.00) ; Number of LABs  (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0                                           ; 0                           ;
-; 1                                           ; 0                           ;
-; 2                                           ; 0                           ;
-; 3                                           ; 0                           ;
-; 4                                           ; 0                           ;
-; 5                                           ; 0                           ;
-; 6                                           ; 0                           ;
-; 7                                           ; 0                           ;
-; 8                                           ; 1                           ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out                                                       ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out  (Average = 8.00) ; Number of LABs  (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0                                               ; 0                           ;
-; 1                                               ; 0                           ;
-; 2                                               ; 0                           ;
-; 3                                               ; 0                           ;
-; 4                                               ; 0                           ;
-; 5                                               ; 0                           ;
-; 6                                               ; 0                           ;
-; 7                                               ; 0                           ;
-; 8                                               ; 1                           ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs                                                       ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs  (Average = 3.00) ; Number of LABs  (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0                                           ; 0                           ;
-; 1                                           ; 0                           ;
-; 2                                           ; 0                           ;
-; 3                                           ; 1                           ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary                        ;
-+----------------------------------+-------+
-; I/O Rules Statistic              ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules                  ; 30    ;
-; Number of I/O Rules Passed       ; 12    ;
-; Number of I/O Rules Failed       ; 0     ;
-; Number of I/O Rules Unchecked    ; 0     ;
-; Number of I/O Rules Inapplicable ; 18    ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
-; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
-; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
-; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Total Pass         ; 11        ; 0            ; 11        ; 0            ; 0            ; 11        ; 11        ; 0            ; 11        ; 11        ; 0            ; 8            ; 0            ; 0            ; 3            ; 0            ; 8            ; 3            ; 0            ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 0            ; 11        ; 0            ; 0            ;
-; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; Total Inapplicable ; 0         ; 11           ; 0         ; 11           ; 11           ; 0         ; 0         ; 11           ; 0         ; 0         ; 11           ; 3            ; 11           ; 11           ; 8            ; 11           ; 3            ; 8            ; 11           ; 11           ; 11           ; 3            ; 11           ; 11           ; 11           ; 11           ; 11           ; 0         ; 11           ; 11           ;
-; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; Y0                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y1                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y2                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y3                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y4                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y5                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y6                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; Y7                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; C                  ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; A                  ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; B                  ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options                                                                       ;
-+------------------------------------------------------------------+--------------------------+
-; Option                                                           ; Setting                  ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
-; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
-; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
-; Enable INIT_DONE output                                          ; Off                      ;
-; Configuration scheme                                             ; Active Serial            ;
-; Error detection CRC                                              ; Off                      ;
-; Enable open drain on CRC_ERROR pin                               ; Off                      ;
-; Enable input tri-state on active configuration pins in user mode ; Off                      ;
-; Configuration Voltage Level                                      ; Auto                     ;
-; Force Configuration Voltage Level                                ; Off                      ;
-; nCEO                                                             ; As output driving ground ;
-; Data[0]                                                          ; As input tri-stated      ;
-; Data[1]/ASDO                                                     ; As input tri-stated      ;
-; Data[7..2]                                                       ; Unreserved               ;
-; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
-; Other Active Parallel pins                                       ; Unreserved               ;
-; DCLK                                                             ; As output driving ground ;
-; Base pin-out file on sameframe device                            ; Off                      ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions  ;
-+---------------------------+--------+
-; Setting                   ; Value  ;
-+---------------------------+--------+
-; Nominal Core Voltage      ; 1.20 V ;
-; Low Junction Temperature  ; 0 °C   ;
-; High Junction Temperature ; 85 °C  ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (119006): Selected device EP3C16F484C6 for design "three_line_to_eight_decimal_decoder"
-Info (21077): Core supply voltage is 1.2V
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
-    Info (176445): Device EP3C40F484C6 is compatible
-    Info (176445): Device EP3C55F484C6 is compatible
-    Info (176445): Device EP3C80F484C6 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
-    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
-    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
-    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
-    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
-    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'three_line_to_eight_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
-    Extra Info (176219): No registers were packed into other blocks
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
-    Info (170200): Optimizations that may affect the design's timing were skipped
-Info (11888): Total time spent on timing analysis during the Fitter is 0.18 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
-Info (144001): Generated suppressed messages file /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.smsg
-Info: Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 536 megabytes
-    Info: Processing ended: Thu Oct 24 21:57:45 2019
-    Info: Elapsed time: 00:00:12
-    Info: Total CPU time (on all processors): 00:00:12
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.smsg.
-
-
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.smsg b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.smsg
deleted file mode 100644
index 7121cbb1..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.summary b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.summary
deleted file mode 100644
index 9ad787a4..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Thu Oct 24 21:57:44 2019
-Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
-Revision Name : three_line_to_eight_decimal_decoder
-Top-level Entity Name : three_line_to_eight_decimal_decoder
-Family : Cyclone III
-Device : EP3C16F484C6
-Timing Models : Final
-Total logic elements : 8 / 15,408 ( < 1 % )
-    Total combinational functions : 8 / 15,408 ( < 1 % )
-    Dedicated logic registers : 0 / 15,408 ( 0 % )
-Total registers : 0
-Total pins : 11 / 347 ( 3 % )
-Total virtual pins : 0
-Total memory bits : 0 / 516,096 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.flow.rpt b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.flow.rpt
deleted file mode 100644
index 22c9b85e..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.flow.rpt
+++ /dev/null
@@ -1,130 +0,0 @@
-Flow report for three_line_to_eight_decimal_decoder
-Thu Oct 24 21:58:03 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Flow Summary                                                                    ;
-+------------------------------------+--------------------------------------------+
-; Flow Status                        ; Successful - Thu Oct 24 21:58:03 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; three_line_to_eight_decimal_decoder        ;
-; Top-level Entity Name              ; three_line_to_eight_decimal_decoder        ;
-; Family                             ; Cyclone III                                ;
-; Device                             ; EP3C16F484C6                               ;
-; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 8 / 15,408 ( < 1 % )                       ;
-;     Total combinational functions  ; 8 / 15,408 ( < 1 % )                       ;
-;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 11 / 347 ( 3 % )                           ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
-; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
-; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
-+------------------------------------+--------------------------------------------+
-
-
-+---------------------------------------------------------+
-; Flow Settings                                           ;
-+-------------------+-------------------------------------+
-; Option            ; Setting                             ;
-+-------------------+-------------------------------------+
-; Start date & time ; 10/24/2019 21:57:29                 ;
-; Main task         ; Compilation                         ;
-; Revision Name     ; three_line_to_eight_decimal_decoder ;
-+-------------------+-------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                                           ;
-+-------------------------------------+-------------------------------------------------------+---------------+-------------+----------------+
-; Assignment Name                     ; Value                                                 ; Default Value ; Entity Name ; Section Id     ;
-+-------------------------------------+-------------------------------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID               ; 0.157192544931923                                     ; --            ; --          ; --             ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST     ; On                                                    ; --            ; --          ; eda_simulation ;
-; EDA_NETLIST_WRITER_OUTPUT_DIR       ; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/ ; --            ; --          ; eda_simulation ;
-; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                                           ; --            ; --          ; eda_simulation ;
-; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (Verilog)                             ; <None>        ; --          ; --             ;
-; MAX_CORE_JUNCTION_TEMP              ; 85                                                    ; --            ; --          ; --             ;
-; MIN_CORE_JUNCTION_TEMP              ; 0                                                     ; --            ; --          ; --             ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                                                  ; --            ; --          ; --             ;
-; PARTITION_COLOR                     ; 16764057                                              ; --            ; --          ; Top            ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                                 ; --            ; --          ; Top            ;
-; PARTITION_NETLIST_TYPE              ; SOURCE                                                ; --            ; --          ; Top            ;
-; PROJECT_OUTPUT_DIRECTORY            ; output_files                                          ; --            ; --          ; --             ;
-+-------------------------------------+-------------------------------------------------------+---------------+-------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 360 MB              ; 00:00:02                           ;
-; Fitter                    ; 00:00:11     ; 1.0                     ; 536 MB              ; 00:00:11                           ;
-; Assembler                 ; 00:00:02     ; 1.0                     ; 382 MB              ; 00:00:03                           ;
-; TimeQuest Timing Analyzer ; 00:00:03     ; 1.0                     ; 383 MB              ; 00:00:03                           ;
-; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 338 MB              ; 00:00:01                           ;
-; Total                     ; 00:00:19     ; --                      ; --                  ; 00:00:20                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                              ;
-+---------------------------+-------------------+----------------+------------+----------------+
-; Module Name               ; Machine Hostname  ; OS Name        ; OS Version ; Processor type ;
-+---------------------------+-------------------+----------------+------------+----------------+
-; Analysis & Synthesis      ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; Fitter                    ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; Assembler                 ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; TimeQuest Timing Analyzer ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-; EDA Netlist Writer        ; timmy-Aspire-4750 ; Ubuntu 16.04.6 ; 16         ; x86_64         ;
-+---------------------------+-------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder
-quartus_fit --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder
-quartus_asm --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder
-quartus_sta three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder
-quartus_eda --read_settings_files=off --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder
-
-
-
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.jdi b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.jdi
deleted file mode 100644
index 713700c6..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="1489afb30176c54ccbc8"/>
-  </project>
-  <file_info>
-    <file device="EP3C16F484C6" path="three_line_to_eight_decimal_decoder.sof" usercode="0xFFFFFFFF"/>
-  </file_info>
-</sld_project_info>
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.map.rpt b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.map.rpt
deleted file mode 100644
index 1f3eb210..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.map.rpt
+++ /dev/null
@@ -1,261 +0,0 @@
-Analysis & Synthesis report for three_line_to_eight_decimal_decoder
-Thu Oct 24 21:57:31 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. General Register Statistics
-  9. Elapsed Time Per Partition
- 10. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                    ;
-+------------------------------------+--------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Thu Oct 24 21:57:31 2019      ;
-; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name                      ; three_line_to_eight_decimal_decoder        ;
-; Top-level Entity Name              ; three_line_to_eight_decimal_decoder        ;
-; Family                             ; Cyclone III                                ;
-; Total logic elements               ; 8                                          ;
-;     Total combinational functions  ; 8                                          ;
-;     Dedicated logic registers      ; 0                                          ;
-; Total registers                    ; 0                                          ;
-; Total pins                         ; 11                                         ;
-; Total virtual pins                 ; 0                                          ;
-; Total memory bits                  ; 0                                          ;
-; Embedded Multiplier 9-bit elements ; 0                                          ;
-; Total PLLs                         ; 0                                          ;
-+------------------------------------+--------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                                                          ;
-+----------------------------------------------------------------------------+-------------------------------------+-------------------------------------+
-; Option                                                                     ; Setting                             ; Default Value                       ;
-+----------------------------------------------------------------------------+-------------------------------------+-------------------------------------+
-; Device                                                                     ; EP3C16F484C6                        ;                                     ;
-; Top-level entity name                                                      ; three_line_to_eight_decimal_decoder ; three_line_to_eight_decimal_decoder ;
-; Family name                                                                ; Cyclone III                         ; Cyclone IV GX                       ;
-; Use smart compilation                                                      ; Off                                 ; Off                                 ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                  ; On                                  ;
-; Enable compact report table                                                ; Off                                 ; Off                                 ;
-; Restructure Multiplexers                                                   ; Auto                                ; Auto                                ;
-; Create Debugging Nodes for IP Cores                                        ; Off                                 ; Off                                 ;
-; Preserve fewer node names                                                  ; On                                  ; On                                  ;
-; Disable OpenCore Plus hardware evaluation                                  ; Off                                 ; Off                                 ;
-; Verilog Version                                                            ; Verilog_2001                        ; Verilog_2001                        ;
-; VHDL Version                                                               ; VHDL_1993                           ; VHDL_1993                           ;
-; State Machine Processing                                                   ; Auto                                ; Auto                                ;
-; Safe State Machine                                                         ; Off                                 ; Off                                 ;
-; Extract Verilog State Machines                                             ; On                                  ; On                                  ;
-; Extract VHDL State Machines                                                ; On                                  ; On                                  ;
-; Ignore Verilog initial constructs                                          ; Off                                 ; Off                                 ;
-; Iteration limit for constant Verilog loops                                 ; 5000                                ; 5000                                ;
-; Iteration limit for non-constant Verilog loops                             ; 250                                 ; 250                                 ;
-; Add Pass-Through Logic to Inferred RAMs                                    ; On                                  ; On                                  ;
-; Infer RAMs from Raw Logic                                                  ; On                                  ; On                                  ;
-; Parallel Synthesis                                                         ; On                                  ; On                                  ;
-; DSP Block Balancing                                                        ; Auto                                ; Auto                                ;
-; NOT Gate Push-Back                                                         ; On                                  ; On                                  ;
-; Power-Up Don't Care                                                        ; On                                  ; On                                  ;
-; Remove Redundant Logic Cells                                               ; Off                                 ; Off                                 ;
-; Remove Duplicate Registers                                                 ; On                                  ; On                                  ;
-; Ignore CARRY Buffers                                                       ; Off                                 ; Off                                 ;
-; Ignore CASCADE Buffers                                                     ; Off                                 ; Off                                 ;
-; Ignore GLOBAL Buffers                                                      ; Off                                 ; Off                                 ;
-; Ignore ROW GLOBAL Buffers                                                  ; Off                                 ; Off                                 ;
-; Ignore LCELL Buffers                                                       ; Off                                 ; Off                                 ;
-; Ignore SOFT Buffers                                                        ; On                                  ; On                                  ;
-; Limit AHDL Integers to 32 Bits                                             ; Off                                 ; Off                                 ;
-; Optimization Technique                                                     ; Balanced                            ; Balanced                            ;
-; Carry Chain Length                                                         ; 70                                  ; 70                                  ;
-; Auto Carry Chains                                                          ; On                                  ; On                                  ;
-; Auto Open-Drain Pins                                                       ; On                                  ; On                                  ;
-; Perform WYSIWYG Primitive Resynthesis                                      ; Off                                 ; Off                                 ;
-; Auto ROM Replacement                                                       ; On                                  ; On                                  ;
-; Auto RAM Replacement                                                       ; On                                  ; On                                  ;
-; Auto DSP Block Replacement                                                 ; On                                  ; On                                  ;
-; Auto Shift Register Replacement                                            ; Auto                                ; Auto                                ;
-; Allow Shift Register Merging across Hierarchies                            ; Auto                                ; Auto                                ;
-; Auto Clock Enable Replacement                                              ; On                                  ; On                                  ;
-; Strict RAM Replacement                                                     ; Off                                 ; Off                                 ;
-; Allow Synchronous Control Signals                                          ; On                                  ; On                                  ;
-; Force Use of Synchronous Clear Signals                                     ; Off                                 ; Off                                 ;
-; Auto RAM Block Balancing                                                   ; On                                  ; On                                  ;
-; Auto RAM to Logic Cell Conversion                                          ; Off                                 ; Off                                 ;
-; Auto Resource Sharing                                                      ; Off                                 ; Off                                 ;
-; Allow Any RAM Size For Recognition                                         ; Off                                 ; Off                                 ;
-; Allow Any ROM Size For Recognition                                         ; Off                                 ; Off                                 ;
-; Allow Any Shift Register Size For Recognition                              ; Off                                 ; Off                                 ;
-; Use LogicLock Constraints during Resource Balancing                        ; On                                  ; On                                  ;
-; Ignore translate_off and synthesis_off directives                          ; Off                                 ; Off                                 ;
-; Timing-Driven Synthesis                                                    ; On                                  ; On                                  ;
-; Report Parameter Settings                                                  ; On                                  ; On                                  ;
-; Report Source Assignments                                                  ; On                                  ; On                                  ;
-; Report Connectivity Checks                                                 ; On                                  ; On                                  ;
-; Ignore Maximum Fan-Out Assignments                                         ; Off                                 ; Off                                 ;
-; Synchronization Register Chain Length                                      ; 2                                   ; 2                                   ;
-; PowerPlay Power Optimization                                               ; Normal compilation                  ; Normal compilation                  ;
-; HDL message level                                                          ; Level2                              ; Level2                              ;
-; Suppress Register Optimization Related Messages                            ; Off                                 ; Off                                 ;
-; Number of Removed Registers Reported in Synthesis Report                   ; 5000                                ; 5000                                ;
-; Number of Swept Nodes Reported in Synthesis Report                         ; 5000                                ; 5000                                ;
-; Number of Inverted Registers Reported in Synthesis Report                  ; 100                                 ; 100                                 ;
-; Clock MUX Protection                                                       ; On                                  ; On                                  ;
-; Auto Gated Clock Conversion                                                ; Off                                 ; Off                                 ;
-; Block Design Naming                                                        ; Auto                                ; Auto                                ;
-; SDC constraint protection                                                  ; Off                                 ; Off                                 ;
-; Synthesis Effort                                                           ; Auto                                ; Auto                                ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                                  ; On                                  ;
-; Pre-Mapping Resynthesis Optimization                                       ; Off                                 ; Off                                 ;
-; Analysis & Synthesis Message Level                                         ; Medium                              ; Medium                              ;
-; Disable Register Merging Across Hierarchies                                ; Auto                                ; Auto                                ;
-; Resource Aware Inference For Block RAM                                     ; On                                  ; On                                  ;
-; Synthesis Seed                                                             ; 1                                   ; 1                                   ;
-+----------------------------------------------------------------------------+-------------------------------------+-------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                                                  ;
-+-----------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path        ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                 ; Library ;
-+-----------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
-; three_line_to_eight_decimal_decoder.bdf ; yes             ; User Block Diagram/Schematic File  ; /home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf ;         ;
-; 74139.bdf                               ; yes             ; Megafunction                       ; /home/timmy/altera/13.1/quartus/libraries/others/maxplus2/74139.bdf          ;         ;
-+-----------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
-
-
-+-------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary           ;
-+---------------------------------------------+---------+
-; Resource                                    ; Usage   ;
-+---------------------------------------------+---------+
-; Estimated Total logic elements              ; 8       ;
-;                                             ;         ;
-; Total combinational functions               ; 8       ;
-; Logic element usage by number of LUT inputs ;         ;
-;     -- 4 input functions                    ; 0       ;
-;     -- 3 input functions                    ; 8       ;
-;     -- <=2 input functions                  ; 0       ;
-;                                             ;         ;
-; Logic elements by mode                      ;         ;
-;     -- normal mode                          ; 8       ;
-;     -- arithmetic mode                      ; 0       ;
-;                                             ;         ;
-; Total registers                             ; 0       ;
-;     -- Dedicated logic registers            ; 0       ;
-;     -- I/O registers                        ; 0       ;
-;                                             ;         ;
-; I/O pins                                    ; 11      ;
-; Embedded Multiplier 9-bit elements          ; 0       ;
-; Maximum fan-out node                        ; C~input ;
-; Maximum fan-out                             ; 8       ;
-; Total fan-out                               ; 43      ;
-; Average fan-out                             ; 1.43    ;
-+---------------------------------------------+---------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                               ;
-+--------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------+--------------+
-; Compilation Hierarchy Node           ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                             ; Library Name ;
-+--------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------+--------------+
-; |three_line_to_eight_decimal_decoder ; 8 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 11   ; 0            ; |three_line_to_eight_decimal_decoder            ; work         ;
-;    |74139:inst|                      ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |three_line_to_eight_decimal_decoder|74139:inst ; work         ;
-+--------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 0     ;
-; Number of registers using Synchronous Clear  ; 0     ;
-; Number of registers using Synchronous Load   ; 0     ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 0     ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition    ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top            ; 00:00:00     ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit Analysis & Synthesis
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 24 21:57:28 2019
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (12021): Found 1 design units, including 1 entities, in source file three_line_to_eight_decimal_decoder.bdf
-    Info (12023): Found entity 1: three_line_to_eight_decimal_decoder
-Info (12127): Elaborating entity "three_line_to_eight_decimal_decoder" for the top level hierarchy
-Info (12128): Elaborating entity "74139" for hierarchy "74139:inst"
-Info (12130): Elaborated megafunction instantiation "74139:inst"
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
-    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 19 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 3 input pins
-    Info (21059): Implemented 8 output pins
-    Info (21061): Implemented 8 logic cells
-Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 371 megabytes
-    Info: Processing ended: Thu Oct 24 21:57:31 2019
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.map.summary b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.map.summary
deleted file mode 100644
index ff71f205..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Thu Oct 24 21:57:31 2019
-Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
-Revision Name : three_line_to_eight_decimal_decoder
-Top-level Entity Name : three_line_to_eight_decimal_decoder
-Family : Cyclone III
-Total logic elements : 8
-    Total combinational functions : 8
-    Dedicated logic registers : 0
-Total registers : 0
-Total pins : 11
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.pin b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.pin
deleted file mode 100644
index 9c4079df..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.pin
+++ /dev/null
@@ -1,554 +0,0 @@
- -- Copyright (C) 1991-2013 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Altera Program License 
- -- Subscription Agreement, Altera MegaCore Function License 
- -- Agreement, or other applicable license agreement, including, 
- -- without limitation, that your use is for the sole purpose of 
- -- programming logic devices manufactured by Altera and sold by 
- -- Altera or its authorized distributors.  Please refer to the 
- -- applicable agreement for further details.
- -- 
- -- This is a Quartus II output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus II input file. This file cannot be used
- -- to make Quartus II pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus II help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --					Bank 1:		2.5V
- --					Bank 2:		2.5V
- --					Bank 3:		2.5V
- --					Bank 4:		2.5V
- --					Bank 5:		2.5V
- --					Bank 6:		2.5V
- --					Bank 7:		2.5V
- --					Bank 8:		2.5V
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --					It can also be used to report unused dedicated pins. The connection
- --					on the board for unused dedicated pins depends on whether this will
- --					be used in a future design. One example is device migration. When
- --					using device migration, refer to the device pin-tables. If it is a
- --					GND pin in the pin table or if it will not be used in a future design
- --					for another purpose the it MUST be connected to GND. If it is an unused
- --					dedicated pin, then it can be connected to a valid signal on the board
- --					(low, high, or toggling) if that signal is required for a different
- --					revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --					This pin should be connected to GND. It may also be connected  to a
- --					valid signal  on the board  (low, high, or toggling)  if that signal
- --					is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --           	    or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-CHIP  "three_line_to_eight_decimal_decoder"  ASSIGNED TO AN: EP3C16F484C6
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : A1        : gnd    :                   :         :           :                
-VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
-GND+                         : A11       :        :                   :         : 8         :                
-GND+                         : A12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
-VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
-GND                          : A22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
-VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
-GND+                         : AA11      :        :                   :         : 3         :                
-GND+                         : AA12      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
-GND                          : AB1       : gnd    :                   :         :           :                
-VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
-GND                          : AB6       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
-GND+                         : AB11      :        :                   :         : 3         :                
-GND+                         : AB12      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
-VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
-GND                          : AB22      : gnd    :                   :         :           :                
-Y0                           : B1        : output : 2.5 V             :         : 1         : Y              
-Y1                           : B2        : output : 2.5 V             :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
-GND+                         : B11       :        :                   :         : 8         :                
-GND+                         : B12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
-Y3                           : C1        : output : 2.5 V             :         : 1         : Y              
-Y2                           : C2        : output : 2.5 V             :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
-GND                          : C5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
-GND                          : C9        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
-GND                          : C11       : gnd    :                   :         :           :                
-GND                          : C12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
-GND                          : C14       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
-GND                          : C16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
-GND                          : C18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
-C                            : D2        : input  : 2.5 V             :         : 1         : Y              
-GND                          : D3        : gnd    :                   :         :           :                
-VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
-VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
-GND                          : D7        : gnd    :                   :         :           :                
-GND                          : D8        : gnd    :                   :         :           :                
-VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
-VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
-VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
-VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
-VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
-VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
-Y4                           : E1        : output : 2.5 V             :         : 1         : Y              
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
-A                            : E3        : input  : 2.5 V             :         : 1         : Y              
-B                            : E4        : input  : 2.5 V             :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
-VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
-VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
-GNDA2                        : E18       : gnd    :                   :         :           :                
-VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
-GND                          : E20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1        :        :                   :         : 1         :                
-Y5                           : F2        : output : 2.5 V             :         : 1         : Y              
-GND                          : F3        : gnd    :                   :         :           :                
-VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
-GNDA3                        : F5        : gnd    :                   :         :           :                
-VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
-VCCA2                        : F18       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
-GND+                         : G1        :        :                   :         : 1         :                
-GND+                         : G2        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
-VCCA3                        : G6        : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
-VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
-GND                          : G20       : gnd    :                   :         :           :                
-GND+                         : G21       :        :                   :         : 6         :                
-GND+                         : G22       :        :                   :         : 6         :                
-Y6                           : H1        : output : 2.5 V             :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
-GND                          : H3        : gnd    :                   :         :           :                
-VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 1         :                
-GND                          : H8        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
-Y7                           : J3        : output : 2.5 V             :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
-GND                          : J5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 1         :                
-VCCINT                       : J8        : power  :                   : 1.2V    :           :                
-GND                          : J9        : gnd    :                   :         :           :                
-VCCINT                       : J10       : power  :                   : 1.2V    :           :                
-VCCINT                       : J11       : power  :                   : 1.2V    :           :                
-VCCINT                       : J12       : power  :                   : 1.2V    :           :                
-VCCINT                       : J13       : power  :                   : 1.2V    :           :                
-VCCINT                       : J14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
-GND                          : J19       : gnd    :                   :         :           :                
-VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
-~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
-GND                          : K3        : gnd    :                   :         :           :                
-VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
-nCONFIG                      : K5        :        :                   :         : 1         :                
-nSTATUS                      : K6        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
-VCCINT                       : K9        : power  :                   : 1.2V    :           :                
-GND                          : K10       : gnd    :                   :         :           :                
-GND                          : K11       : gnd    :                   :         :           :                
-GND                          : K12       : gnd    :                   :         :           :                
-GND                          : K13       : gnd    :                   :         :           :                
-VCCINT                       : K14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
-MSEL3                        : K20       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
-TMS                          : L1        : input  :                   :         : 1         :                
-TCK                          : L2        : input  :                   :         : 1         :                
-nCE                          : L3        :        :                   :         : 1         :                
-TDO                          : L4        : output :                   :         : 1         :                
-TDI                          : L5        : input  :                   :         : 1         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
-VCCINT                       : L9        : power  :                   : 1.2V    :           :                
-GND                          : L10       : gnd    :                   :         :           :                
-GND                          : L11       : gnd    :                   :         :           :                
-GND                          : L12       : gnd    :                   :         :           :                
-GND                          : L13       : gnd    :                   :         :           :                
-VCCINT                       : L14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
-MSEL2                        : L17       :        :                   :         : 6         :                
-MSEL1                        : L18       :        :                   :         : 6         :                
-VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
-GND                          : L20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
-VCCINT                       : M9        : power  :                   : 1.2V    :           :                
-GND                          : M10       : gnd    :                   :         :           :                
-GND                          : M11       : gnd    :                   :         :           :                
-GND                          : M12       : gnd    :                   :         :           :                
-GND                          : M13       : gnd    :                   :         :           :                
-VCCINT                       : M14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
-MSEL0                        : M17       :        :                   :         : 6         :                
-CONF_DONE                    : M18       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
-GND                          : N3        : gnd    :                   :         :           :                
-VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
-VCCINT                       : N9        : power  :                   : 1.2V    :           :                
-GND                          : N10       : gnd    :                   :         :           :                
-GND                          : N11       : gnd    :                   :         :           :                
-GND                          : N12       : gnd    :                   :         :           :                
-GND                          : N13       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
-VCCINT                       : P9        : power  :                   : 1.2V    :           :                
-VCCINT                       : P10       : power  :                   : 1.2V    :           :                
-VCCINT                       : P11       : power  :                   : 1.2V    :           :                
-VCCINT                       : P12       : power  :                   : 1.2V    :           :                
-VCCINT                       : P13       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
-VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
-GND                          : P19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
-GND                          : R3        : gnd    :                   :         :           :                
-VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
-GND+                         : T1        :        :                   :         : 2         :                
-GND+                         : T2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
-VCCA1                        : T6        : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
-VCCINT                       : T13       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
-VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
-GND                          : T20       : gnd    :                   :         :           :                
-GND+                         : T21       :        :                   :         : 5         :                
-GND+                         : T22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
-GND                          : U3        : gnd    :                   :         :           :                
-VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
-GNDA1                        : U5        : gnd    :                   :         :           :                
-VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
-VCCINT                       : U16       : power  :                   : 1.2V    :           :                
-VCCINT                       : U17       : power  :                   : 1.2V    :           :                
-VCCA4                        : U18       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
-VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
-GNDA4                        : V18       : gnd    :                   :         :           :                
-VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
-GND                          : V20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
-GND                          : W3        : gnd    :                   :         :           :                
-VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
-VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
-VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
-VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
-VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
-VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
-VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
-GND                          : Y5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
-GND                          : Y9        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
-GND                          : Y11       : gnd    :                   :         :           :                
-GND                          : Y12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
-VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
-GND                          : Y15       : gnd    :                   :         :           :                
-GND                          : Y16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
-GND                          : Y18       : gnd    :                   :         :           :                
-VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
-GND                          : Y20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.sof b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.sof
deleted file mode 100644
index 42d88e8394ce8e9c79833b44e302f50686881c01..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.sta.rpt b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.sta.rpt
deleted file mode 100644
index aedaee75..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.sta.rpt
+++ /dev/null
@@ -1,655 +0,0 @@
-TimeQuest Timing Analyzer report for three_line_to_eight_decimal_decoder
-Thu Oct 24 21:57:58 2019
-Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. Clocks
-  5. Slow 1200mV 85C Model Fmax Summary
-  6. Timing Closure Recommendations
-  7. Slow 1200mV 85C Model Setup Summary
-  8. Slow 1200mV 85C Model Hold Summary
-  9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Propagation Delay
- 13. Minimum Propagation Delay
- 14. Slow 1200mV 85C Model Metastability Report
- 15. Slow 1200mV 0C Model Fmax Summary
- 16. Slow 1200mV 0C Model Setup Summary
- 17. Slow 1200mV 0C Model Hold Summary
- 18. Slow 1200mV 0C Model Recovery Summary
- 19. Slow 1200mV 0C Model Removal Summary
- 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 21. Propagation Delay
- 22. Minimum Propagation Delay
- 23. Slow 1200mV 0C Model Metastability Report
- 24. Fast 1200mV 0C Model Setup Summary
- 25. Fast 1200mV 0C Model Hold Summary
- 26. Fast 1200mV 0C Model Recovery Summary
- 27. Fast 1200mV 0C Model Removal Summary
- 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 29. Propagation Delay
- 30. Minimum Propagation Delay
- 31. Fast 1200mV 0C Model Metastability Report
- 32. Multicorner Timing Analysis Summary
- 33. Propagation Delay
- 34. Minimum Propagation Delay
- 35. Board Trace Model Assignments
- 36. Input Transition Times
- 37. Slow Corner Signal Integrity Metrics
- 38. Fast Corner Signal Integrity Metrics
- 39. Clock Transfers
- 40. Report TCCS
- 41. Report RSKM
- 42. Unconstrained Paths
- 43. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                       ;
-+--------------------+----------------------------------------------------+
-; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
-; Revision Name      ; three_line_to_eight_decimal_decoder                ;
-; Device Family      ; Cyclone III                                        ;
-; Device Name        ; EP3C16F484C6                                       ;
-; Timing Models      ; Final                                              ;
-; Delay Model        ; Combined                                           ;
-; Rise/Fall Delays   ; Enabled                                            ;
-+--------------------+----------------------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 6.524 ;       ;       ; 6.957 ;
-; A          ; Y1          ;       ; 6.558 ; 6.954 ;       ;
-; A          ; Y2          ; 6.524 ;       ;       ; 6.962 ;
-; A          ; Y3          ;       ; 6.695 ; 7.068 ;       ;
-; A          ; Y4          ; 6.510 ;       ;       ; 6.937 ;
-; A          ; Y5          ;       ; 6.527 ; 6.914 ;       ;
-; A          ; Y6          ; 6.517 ;       ;       ; 6.930 ;
-; A          ; Y7          ;       ; 7.764 ; 8.274 ;       ;
-; B          ; Y0          ; 6.600 ;       ;       ; 7.021 ;
-; B          ; Y1          ; 6.628 ;       ;       ; 7.037 ;
-; B          ; Y2          ;       ; 6.628 ; 7.033 ;       ;
-; B          ; Y3          ;       ; 6.773 ; 7.175 ;       ;
-; B          ; Y4          ; 6.583 ;       ;       ; 7.006 ;
-; B          ; Y5          ; 6.589 ;       ;       ; 7.005 ;
-; B          ; Y6          ;       ; 6.597 ; 7.025 ;       ;
-; B          ; Y7          ;       ; 7.841 ; 8.379 ;       ;
-; C          ; Y0          ; 6.597 ;       ;       ; 7.030 ;
-; C          ; Y1          ; 6.575 ;       ;       ; 7.005 ;
-; C          ; Y2          ; 6.600 ;       ;       ; 7.029 ;
-; C          ; Y3          ; 6.704 ;       ;       ; 7.145 ;
-; C          ; Y4          ;       ; 6.577 ; 7.007 ;       ;
-; C          ; Y5          ;       ; 6.532 ; 6.959 ;       ;
-; C          ; Y6          ;       ; 6.563 ; 7.004 ;       ;
-; C          ; Y7          ;       ; 7.772 ; 8.325 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 6.376 ;       ;       ; 6.798 ;
-; A          ; Y1          ;       ; 6.411 ; 6.795 ;       ;
-; A          ; Y2          ; 6.377 ;       ;       ; 6.803 ;
-; A          ; Y3          ;       ; 6.541 ; 6.904 ;       ;
-; A          ; Y4          ; 6.362 ;       ;       ; 6.779 ;
-; A          ; Y5          ;       ; 6.380 ; 6.755 ;       ;
-; A          ; Y6          ; 6.369 ;       ;       ; 6.772 ;
-; A          ; Y7          ;       ; 7.616 ; 8.112 ;       ;
-; B          ; Y0          ; 6.449 ;       ;       ; 6.859 ;
-; B          ; Y1          ; 6.478 ;       ;       ; 6.875 ;
-; B          ; Y2          ;       ; 6.477 ; 6.870 ;       ;
-; B          ; Y3          ;       ; 6.616 ; 7.006 ;       ;
-; B          ; Y4          ; 6.433 ;       ;       ; 6.844 ;
-; B          ; Y5          ; 6.439 ;       ;       ; 6.843 ;
-; B          ; Y6          ;       ; 6.446 ; 6.863 ;       ;
-; B          ; Y7          ;       ; 7.689 ; 8.214 ;       ;
-; C          ; Y0          ; 6.439 ;       ;       ; 6.850 ;
-; C          ; Y1          ; 6.415 ;       ;       ; 6.823 ;
-; C          ; Y2          ; 6.423 ;       ;       ; 6.850 ;
-; C          ; Y3          ; 6.524 ;       ;       ; 6.960 ;
-; C          ; Y4          ;       ; 6.414 ; 6.829 ;       ;
-; C          ; Y5          ;       ; 6.371 ; 6.780 ;       ;
-; C          ; Y6          ;       ; 6.402 ; 6.817 ;       ;
-; C          ; Y7          ;       ; 7.610 ; 8.138 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-----------------------------------------------
-; Slow 1200mV 85C Model Metastability Report ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 6.057 ;       ;       ; 6.433 ;
-; A          ; Y1          ;       ; 6.096 ; 6.419 ;       ;
-; A          ; Y2          ; 6.045 ;       ;       ; 6.434 ;
-; A          ; Y3          ;       ; 6.232 ; 6.512 ;       ;
-; A          ; Y4          ; 6.031 ;       ;       ; 6.416 ;
-; A          ; Y5          ;       ; 6.067 ; 6.365 ;       ;
-; A          ; Y6          ; 6.026 ;       ;       ; 6.403 ;
-; A          ; Y7          ;       ; 7.291 ; 7.720 ;       ;
-; B          ; Y0          ; 6.120 ;       ;       ; 6.489 ;
-; B          ; Y1          ; 6.147 ;       ;       ; 6.504 ;
-; B          ; Y2          ;       ; 6.157 ; 6.480 ;       ;
-; B          ; Y3          ;       ; 6.299 ; 6.607 ;       ;
-; B          ; Y4          ; 6.093 ;       ;       ; 6.474 ;
-; B          ; Y5          ; 6.098 ;       ;       ; 6.473 ;
-; B          ; Y6          ;       ; 6.128 ; 6.461 ;       ;
-; B          ; Y7          ;       ; 7.368 ; 7.816 ;       ;
-; C          ; Y0          ; 6.101 ;       ;       ; 6.496 ;
-; C          ; Y1          ; 6.079 ;       ;       ; 6.477 ;
-; C          ; Y2          ; 6.093 ;       ;       ; 6.495 ;
-; C          ; Y3          ; 6.184 ;       ;       ; 6.611 ;
-; C          ; Y4          ;       ; 6.092 ; 6.453 ;       ;
-; C          ; Y5          ;       ; 6.050 ; 6.409 ;       ;
-; C          ; Y6          ;       ; 6.077 ; 6.444 ;       ;
-; C          ; Y7          ;       ; 7.286 ; 7.769 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 5.931 ;       ;       ; 6.297 ;
-; A          ; Y1          ;       ; 5.970 ; 6.285 ;       ;
-; A          ; Y2          ; 5.918 ;       ;       ; 6.299 ;
-; A          ; Y3          ;       ; 6.100 ; 6.373 ;       ;
-; A          ; Y4          ; 5.906 ;       ;       ; 6.282 ;
-; A          ; Y5          ;       ; 5.941 ; 6.233 ;       ;
-; A          ; Y6          ; 5.901 ;       ;       ; 6.267 ;
-; A          ; Y7          ;       ; 7.163 ; 7.586 ;       ;
-; B          ; Y0          ; 5.992 ;       ;       ; 6.352 ;
-; B          ; Y1          ; 6.018 ;       ;       ; 6.367 ;
-; B          ; Y2          ;       ; 6.029 ; 6.341 ;       ;
-; B          ; Y3          ;       ; 6.164 ; 6.463 ;       ;
-; B          ; Y4          ; 5.965 ;       ;       ; 6.337 ;
-; B          ; Y5          ; 5.970 ;       ;       ; 6.336 ;
-; B          ; Y6          ;       ; 5.999 ; 6.323 ;       ;
-; B          ; Y7          ;       ; 7.237 ; 7.676 ;       ;
-; C          ; Y0          ; 5.970 ;       ;       ; 6.339 ;
-; C          ; Y1          ; 5.948 ;       ;       ; 6.322 ;
-; C          ; Y2          ; 5.944 ;       ;       ; 6.343 ;
-; C          ; Y3          ; 6.035 ;       ;       ; 6.451 ;
-; C          ; Y4          ;       ; 5.952 ; 6.302 ;       ;
-; C          ; Y5          ;       ; 5.912 ; 6.257 ;       ;
-; C          ; Y6          ;       ; 5.936 ; 6.285 ;       ;
-; C          ; Y7          ;       ; 7.145 ; 7.610 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
----------------------------------------------
-; Slow 1200mV 0C Model Metastability Report ;
----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 3.944 ;       ;       ; 4.504 ;
-; A          ; Y1          ;       ; 3.933 ; 4.529 ;       ;
-; A          ; Y2          ; 3.942 ;       ;       ; 4.499 ;
-; A          ; Y3          ;       ; 3.986 ; 4.584 ;       ;
-; A          ; Y4          ; 3.923 ;       ;       ; 4.475 ;
-; A          ; Y5          ;       ; 3.898 ; 4.489 ;       ;
-; A          ; Y6          ; 3.915 ;       ;       ; 4.473 ;
-; A          ; Y7          ;       ; 4.736 ; 5.471 ;       ;
-; B          ; Y0          ; 3.988 ;       ;       ; 4.534 ;
-; B          ; Y1          ; 4.002 ;       ;       ; 4.543 ;
-; B          ; Y2          ;       ; 3.968 ; 4.567 ;       ;
-; B          ; Y3          ;       ; 4.034 ; 4.644 ;       ;
-; B          ; Y4          ; 3.967 ;       ;       ; 4.509 ;
-; B          ; Y5          ; 3.966 ;       ;       ; 4.508 ;
-; B          ; Y6          ;       ; 3.946 ; 4.542 ;       ;
-; B          ; Y7          ;       ; 4.786 ; 5.525 ;       ;
-; C          ; Y0          ; 3.986 ;       ;       ; 4.540 ;
-; C          ; Y1          ; 3.969 ;       ;       ; 4.529 ;
-; C          ; Y2          ; 3.984 ;       ;       ; 4.534 ;
-; C          ; Y3          ; 4.038 ;       ;       ; 4.585 ;
-; C          ; Y4          ;       ; 3.930 ; 4.537 ;       ;
-; C          ; Y5          ;       ; 3.908 ; 4.512 ;       ;
-; C          ; Y6          ;       ; 3.929 ; 4.530 ;       ;
-; C          ; Y7          ;       ; 4.744 ; 5.499 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 3.856 ;       ;       ; 4.411 ;
-; A          ; Y1          ;       ; 3.847 ; 4.435 ;       ;
-; A          ; Y2          ; 3.855 ;       ;       ; 4.407 ;
-; A          ; Y3          ;       ; 3.897 ; 4.487 ;       ;
-; A          ; Y4          ; 3.836 ;       ;       ; 4.382 ;
-; A          ; Y5          ;       ; 3.813 ; 4.396 ;       ;
-; A          ; Y6          ; 3.828 ;       ;       ; 4.380 ;
-; A          ; Y7          ;       ; 4.648 ; 5.376 ;       ;
-; B          ; Y0          ; 3.898 ;       ;       ; 4.440 ;
-; B          ; Y1          ; 3.912 ;       ;       ; 4.448 ;
-; B          ; Y2          ;       ; 3.880 ; 4.471 ;       ;
-; B          ; Y3          ;       ; 3.943 ; 4.544 ;       ;
-; B          ; Y4          ; 3.878 ;       ;       ; 4.415 ;
-; B          ; Y5          ; 3.877 ;       ;       ; 4.415 ;
-; B          ; Y6          ;       ; 3.858 ; 4.446 ;       ;
-; B          ; Y7          ;       ; 4.697 ; 5.428 ;       ;
-; C          ; Y0          ; 3.887 ;       ;       ; 4.434 ;
-; C          ; Y1          ; 3.872 ;       ;       ; 4.422 ;
-; C          ; Y2          ; 3.879 ;       ;       ; 4.430 ;
-; C          ; Y3          ; 3.931 ;       ;       ; 4.476 ;
-; C          ; Y4          ;       ; 3.838 ; 4.434 ;       ;
-; C          ; Y5          ;       ; 3.818 ; 4.407 ;       ;
-; C          ; Y6          ;       ; 3.836 ; 4.423 ;       ;
-; C          ; Y7          ;       ; 4.652 ; 5.389 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
----------------------------------------------
-; Fast 1200mV 0C Model Metastability Report ;
----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary                                        ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
-; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+----------------------------------------------------------+
-; Propagation Delay                                        ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 6.524 ;       ;       ; 6.957 ;
-; A          ; Y1          ;       ; 6.558 ; 6.954 ;       ;
-; A          ; Y2          ; 6.524 ;       ;       ; 6.962 ;
-; A          ; Y3          ;       ; 6.695 ; 7.068 ;       ;
-; A          ; Y4          ; 6.510 ;       ;       ; 6.937 ;
-; A          ; Y5          ;       ; 6.527 ; 6.914 ;       ;
-; A          ; Y6          ; 6.517 ;       ;       ; 6.930 ;
-; A          ; Y7          ;       ; 7.764 ; 8.274 ;       ;
-; B          ; Y0          ; 6.600 ;       ;       ; 7.021 ;
-; B          ; Y1          ; 6.628 ;       ;       ; 7.037 ;
-; B          ; Y2          ;       ; 6.628 ; 7.033 ;       ;
-; B          ; Y3          ;       ; 6.773 ; 7.175 ;       ;
-; B          ; Y4          ; 6.583 ;       ;       ; 7.006 ;
-; B          ; Y5          ; 6.589 ;       ;       ; 7.005 ;
-; B          ; Y6          ;       ; 6.597 ; 7.025 ;       ;
-; B          ; Y7          ;       ; 7.841 ; 8.379 ;       ;
-; C          ; Y0          ; 6.597 ;       ;       ; 7.030 ;
-; C          ; Y1          ; 6.575 ;       ;       ; 7.005 ;
-; C          ; Y2          ; 6.600 ;       ;       ; 7.029 ;
-; C          ; Y3          ; 6.704 ;       ;       ; 7.145 ;
-; C          ; Y4          ;       ; 6.577 ; 7.007 ;       ;
-; C          ; Y5          ;       ; 6.532 ; 6.959 ;       ;
-; C          ; Y6          ;       ; 6.563 ; 7.004 ;       ;
-; C          ; Y7          ;       ; 7.772 ; 8.325 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+----------------------------------------------------------+
-; Minimum Propagation Delay                                ;
-+------------+-------------+-------+-------+-------+-------+
-; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
-+------------+-------------+-------+-------+-------+-------+
-; A          ; Y0          ; 3.856 ;       ;       ; 4.411 ;
-; A          ; Y1          ;       ; 3.847 ; 4.435 ;       ;
-; A          ; Y2          ; 3.855 ;       ;       ; 4.407 ;
-; A          ; Y3          ;       ; 3.897 ; 4.487 ;       ;
-; A          ; Y4          ; 3.836 ;       ;       ; 4.382 ;
-; A          ; Y5          ;       ; 3.813 ; 4.396 ;       ;
-; A          ; Y6          ; 3.828 ;       ;       ; 4.380 ;
-; A          ; Y7          ;       ; 4.648 ; 5.376 ;       ;
-; B          ; Y0          ; 3.898 ;       ;       ; 4.440 ;
-; B          ; Y1          ; 3.912 ;       ;       ; 4.448 ;
-; B          ; Y2          ;       ; 3.880 ; 4.471 ;       ;
-; B          ; Y3          ;       ; 3.943 ; 4.544 ;       ;
-; B          ; Y4          ; 3.878 ;       ;       ; 4.415 ;
-; B          ; Y5          ; 3.877 ;       ;       ; 4.415 ;
-; B          ; Y6          ;       ; 3.858 ; 4.446 ;       ;
-; B          ; Y7          ;       ; 4.697 ; 5.428 ;       ;
-; C          ; Y0          ; 3.887 ;       ;       ; 4.434 ;
-; C          ; Y1          ; 3.872 ;       ;       ; 4.422 ;
-; C          ; Y2          ; 3.879 ;       ;       ; 4.430 ;
-; C          ; Y3          ; 3.931 ;       ;       ; 4.476 ;
-; C          ; Y4          ;       ; 3.838 ; 4.434 ;       ;
-; C          ; Y5          ;       ; 3.818 ; 4.407 ;       ;
-; C          ; Y6          ;       ; 3.836 ; 4.423 ;       ;
-; C          ; Y7          ;       ; 4.652 ; 5.389 ;       ;
-+------------+-------------+-------+-------+-------+-------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Y0            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y1            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y2            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y3            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y4            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y5            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y6            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; Y7            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times                                                     ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; C                       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; A                       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; B                       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Y0            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y1            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y2            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y3            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y4            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y5            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y6            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
-; Y7            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.33 V              ; -0.00317 V          ; 0.162 V                              ; 0.063 V                              ; 3.54e-09 s                  ; 3.41e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.33 V             ; -0.00317 V         ; 0.162 V                             ; 0.063 V                             ; 3.54e-09 s                 ; 3.41e-09 s                 ; Yes                       ; Yes                       ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Y0            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y1            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y2            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y3            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y4            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y5            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y6            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
-; Y7            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
-; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
-; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths                            ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 3     ; 3    ;
-; Unconstrained Input Port Paths  ; 24    ; 24   ;
-; Unconstrained Output Ports      ; 8     ; 8    ;
-; Unconstrained Output Port Paths ; 24    ; 24   ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
-    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Oct 24 21:57:55 2019
-Info: Command: quartus_sta three_line_to_eight_decimal_decoder -c three_line_to_eight_decimal_decoder
-Info: qsta_default_script.tcl version: #1
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (21077): Core supply voltage is 1.2V
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'three_line_to_eight_decimal_decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 383 megabytes
-    Info: Processing ended: Thu Oct 24 21:57:58 2019
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.sta.summary b/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.sta.summary
deleted file mode 100644
index 33f74363..00000000
--- a/CH6/CH6-1/output_files/three_line_to_eight_decimal_decoder.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder.sft b/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder.sft
deleted file mode 100644
index 9df8a729..00000000
--- a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder.sft
+++ /dev/null
@@ -1,6 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
-set corner_file_list {
-	{{"Slow -6 1.2V 85 Model"} {BCD_to_decimal_decoder_6_1200mv_85c_slow.vho BCD_to_decimal_decoder_6_1200mv_85c_vhd_slow.sdo}}
-	{{"Slow -6 1.2V 0 Model"} {BCD_to_decimal_decoder_6_1200mv_0c_slow.vho BCD_to_decimal_decoder_6_1200mv_0c_vhd_slow.sdo}}
-	{{"Fast -M 1.2V 0 Model"} {BCD_to_decimal_decoder_min_1200mv_0c_fast.vho BCD_to_decimal_decoder_min_1200mv_0c_vhd_fast.sdo}}
-}
diff --git a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder.vho b/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder.vho
deleted file mode 100644
index a8ffc54c..00000000
--- a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder.vho
+++ /dev/null
@@ -1,494 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/17/2019 22:55:15"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	BCD_to_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	D : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic;
-	Y8 : OUT std_logic;
-	Y9 : OUT std_logic
-	);
-END BCD_to_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_V6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_R10,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_P3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_V3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y8	=>  Location: PIN_T9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y9	=>  Location: PIN_T3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_Y1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_T8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_T4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF BCD_to_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL ww_Y8 : std_logic;
-SIGNAL ww_Y9 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \Y8~output_o\ : std_logic;
-SIGNAL \Y9~output_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \D~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \inst~combout\ : std_logic;
-SIGNAL \inst1~combout\ : std_logic;
-SIGNAL \inst2~combout\ : std_logic;
-SIGNAL \inst3~combout\ : std_logic;
-SIGNAL \inst4~combout\ : std_logic;
-SIGNAL \inst5~combout\ : std_logic;
-SIGNAL \inst6~combout\ : std_logic;
-SIGNAL \inst7~combout\ : std_logic;
-SIGNAL \inst8~combout\ : std_logic;
-SIGNAL \inst9~combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-ww_D <= D;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-Y8 <= ww_Y8;
-Y9 <= ww_Y9;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X0_Y7_N9
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst~combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y9_N16
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst1~combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y12_N9
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst2~combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X1_Y0_N2
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst3~combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X1_Y0_N16
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst4~combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y8_N9
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst5~combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y9_N2
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst6~combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X0_Y4_N2
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst7~combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOOBUF_X1_Y0_N9
-\Y8~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst8~combout\,
-	devoe => ww_devoe,
-	o => \Y8~output_o\);
-
--- Location: IOOBUF_X0_Y6_N16
-\Y9~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst9~combout\,
-	devoe => ww_devoe,
-	o => \Y9~output_o\);
-
--- Location: IOIBUF_X0_Y4_N22
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: IOIBUF_X0_Y10_N15
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y6_N8
-\D~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_D,
-	o => \D~input_o\);
-
--- Location: IOIBUF_X1_Y0_N22
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: LCCOMB_X1_Y4_N0
-inst : cycloneiii_lcell_comb
--- Equation(s):
--- \inst~combout\ = (!\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000001",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst~combout\);
-
--- Location: LCCOMB_X1_Y4_N10
-inst1 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst1~combout\ = (!\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst1~combout\);
-
--- Location: LCCOMB_X1_Y4_N12
-inst2 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst2~combout\ = (!\B~input_o\ & (\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst2~combout\);
-
--- Location: LCCOMB_X1_Y4_N30
-inst3 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst3~combout\ = (!\B~input_o\ & (\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst3~combout\);
-
--- Location: LCCOMB_X1_Y4_N16
-inst4 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst4~combout\ = (\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst4~combout\);
-
--- Location: LCCOMB_X1_Y4_N26
-inst5 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst5~combout\ = (\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst5~combout\);
-
--- Location: LCCOMB_X1_Y4_N4
-inst6 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst6~combout\ = (\B~input_o\ & (\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst6~combout\);
-
--- Location: LCCOMB_X1_Y4_N14
-inst7 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst7~combout\ = (\B~input_o\ & (\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst7~combout\);
-
--- Location: LCCOMB_X1_Y4_N24
-inst8 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst8~combout\ = (!\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst8~combout\);
-
--- Location: LCCOMB_X1_Y4_N2
-inst9 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst9~combout\ = (!\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst9~combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-
-ww_Y8 <= \Y8~output_o\;
-
-ww_Y9 <= \Y9~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_0c_slow.vho b/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_0c_slow.vho
deleted file mode 100644
index a8ffc54c..00000000
--- a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_0c_slow.vho
+++ /dev/null
@@ -1,494 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/17/2019 22:55:15"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	BCD_to_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	D : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic;
-	Y8 : OUT std_logic;
-	Y9 : OUT std_logic
-	);
-END BCD_to_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_V6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_R10,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_P3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_V3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y8	=>  Location: PIN_T9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y9	=>  Location: PIN_T3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_Y1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_T8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_T4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF BCD_to_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL ww_Y8 : std_logic;
-SIGNAL ww_Y9 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \Y8~output_o\ : std_logic;
-SIGNAL \Y9~output_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \D~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \inst~combout\ : std_logic;
-SIGNAL \inst1~combout\ : std_logic;
-SIGNAL \inst2~combout\ : std_logic;
-SIGNAL \inst3~combout\ : std_logic;
-SIGNAL \inst4~combout\ : std_logic;
-SIGNAL \inst5~combout\ : std_logic;
-SIGNAL \inst6~combout\ : std_logic;
-SIGNAL \inst7~combout\ : std_logic;
-SIGNAL \inst8~combout\ : std_logic;
-SIGNAL \inst9~combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-ww_D <= D;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-Y8 <= ww_Y8;
-Y9 <= ww_Y9;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X0_Y7_N9
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst~combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y9_N16
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst1~combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y12_N9
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst2~combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X1_Y0_N2
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst3~combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X1_Y0_N16
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst4~combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y8_N9
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst5~combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y9_N2
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst6~combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X0_Y4_N2
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst7~combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOOBUF_X1_Y0_N9
-\Y8~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst8~combout\,
-	devoe => ww_devoe,
-	o => \Y8~output_o\);
-
--- Location: IOOBUF_X0_Y6_N16
-\Y9~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst9~combout\,
-	devoe => ww_devoe,
-	o => \Y9~output_o\);
-
--- Location: IOIBUF_X0_Y4_N22
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: IOIBUF_X0_Y10_N15
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y6_N8
-\D~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_D,
-	o => \D~input_o\);
-
--- Location: IOIBUF_X1_Y0_N22
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: LCCOMB_X1_Y4_N0
-inst : cycloneiii_lcell_comb
--- Equation(s):
--- \inst~combout\ = (!\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000001",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst~combout\);
-
--- Location: LCCOMB_X1_Y4_N10
-inst1 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst1~combout\ = (!\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst1~combout\);
-
--- Location: LCCOMB_X1_Y4_N12
-inst2 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst2~combout\ = (!\B~input_o\ & (\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst2~combout\);
-
--- Location: LCCOMB_X1_Y4_N30
-inst3 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst3~combout\ = (!\B~input_o\ & (\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst3~combout\);
-
--- Location: LCCOMB_X1_Y4_N16
-inst4 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst4~combout\ = (\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst4~combout\);
-
--- Location: LCCOMB_X1_Y4_N26
-inst5 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst5~combout\ = (\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst5~combout\);
-
--- Location: LCCOMB_X1_Y4_N4
-inst6 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst6~combout\ = (\B~input_o\ & (\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst6~combout\);
-
--- Location: LCCOMB_X1_Y4_N14
-inst7 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst7~combout\ = (\B~input_o\ & (\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst7~combout\);
-
--- Location: LCCOMB_X1_Y4_N24
-inst8 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst8~combout\ = (!\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst8~combout\);
-
--- Location: LCCOMB_X1_Y4_N2
-inst9 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst9~combout\ = (!\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst9~combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-
-ww_Y8 <= \Y8~output_o\;
-
-ww_Y9 <= \Y9~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_0c_vhd_slow.sdo b/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_0c_vhd_slow.sdo
deleted file mode 100644
index 18fff727..00000000
--- a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_0c_vhd_slow.sdo
+++ /dev/null
@@ -1,335 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "BCD_to_decimal_decoder")
-  (DATE "10/17/2019 22:55:15")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y0\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (547:547:547) (544:544:544))
-        (IOPATH i o (2236:2236:2236) (2224:2224:2224))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y1\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (825:825:825) (837:837:837))
-        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y2\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (837:837:837) (855:855:855))
-        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y3\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (513:513:513) (513:513:513))
-        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y4\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (537:537:537) (537:537:537))
-        (IOPATH i o (2080:2080:2080) (2029:2029:2029))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y5\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (594:594:594) (604:604:604))
-        (IOPATH i o (2147:2147:2147) (2105:2105:2105))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y6\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (820:820:820) (815:815:815))
-        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y7\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (299:299:299) (295:295:295))
-        (IOPATH i o (2157:2157:2157) (2115:2115:2115))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y8\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (517:517:517) (517:517:517))
-        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y9\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (576:576:576) (587:587:587))
-        (IOPATH i o (3426:3426:3426) (3527:3527:3527))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\B\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\C\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (715:715:715) (876:876:876))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\D\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (775:775:775) (936:936:936))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\A\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (689:689:689) (852:852:852))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2208:2208:2208) (2443:2443:2443))
-        (PORT datab (2706:2706:2706) (2945:2945:2945))
-        (PORT datac (2414:2414:2414) (2625:2625:2625))
-        (PORT datad (2433:2433:2433) (2634:2634:2634))
-        (IOPATH dataa combout (309:309:309) (326:326:326))
-        (IOPATH datab combout (309:309:309) (328:328:328))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst1)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2201:2201:2201) (2442:2442:2442))
-        (PORT datab (2706:2706:2706) (2943:2943:2943))
-        (PORT datac (2413:2413:2413) (2625:2625:2625))
-        (PORT datad (2427:2427:2427) (2636:2636:2636))
-        (IOPATH dataa combout (299:299:299) (304:304:304))
-        (IOPATH datab combout (300:300:300) (312:312:312))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst2)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2202:2202:2202) (2440:2440:2440))
-        (PORT datab (2705:2705:2705) (2941:2941:2941))
-        (PORT datac (2412:2412:2412) (2628:2628:2628))
-        (PORT datad (2428:2428:2428) (2635:2635:2635))
-        (IOPATH dataa combout (329:329:329) (332:332:332))
-        (IOPATH datab combout (319:319:319) (307:307:307))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst3)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2210:2210:2210) (2444:2444:2444))
-        (PORT datab (2690:2690:2690) (2926:2926:2926))
-        (PORT datac (2405:2405:2405) (2619:2619:2619))
-        (PORT datad (2426:2426:2426) (2632:2632:2632))
-        (IOPATH dataa combout (318:318:318) (327:327:327))
-        (IOPATH datab combout (308:308:308) (281:281:281))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst4)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2206:2206:2206) (2446:2446:2446))
-        (PORT datab (2700:2700:2700) (2938:2938:2938))
-        (PORT datac (2411:2411:2411) (2623:2623:2623))
-        (PORT datad (2432:2432:2432) (2634:2634:2634))
-        (IOPATH dataa combout (318:318:318) (307:307:307))
-        (IOPATH datab combout (336:336:336) (337:337:337))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst5)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2208:2208:2208) (2443:2443:2443))
-        (PORT datab (2689:2689:2689) (2925:2925:2925))
-        (PORT datac (2404:2404:2404) (2618:2618:2618))
-        (PORT datad (2426:2426:2426) (2632:2632:2632))
-        (IOPATH dataa combout (307:307:307) (280:280:280))
-        (IOPATH datab combout (325:325:325) (332:332:332))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst6)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2207:2207:2207) (2438:2438:2438))
-        (PORT datab (2705:2705:2705) (2948:2948:2948))
-        (PORT datac (2412:2412:2412) (2626:2626:2626))
-        (PORT datad (2431:2431:2431) (2635:2635:2635))
-        (IOPATH dataa combout (300:300:300) (323:323:323))
-        (IOPATH datab combout (306:306:306) (324:324:324))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst7)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2203:2203:2203) (2438:2438:2438))
-        (PORT datab (2704:2704:2704) (2944:2944:2944))
-        (PORT datac (2411:2411:2411) (2624:2624:2624))
-        (PORT datad (2429:2429:2429) (2639:2639:2639))
-        (IOPATH dataa combout (290:290:290) (306:306:306))
-        (IOPATH datab combout (295:295:295) (300:300:300))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst8)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2207:2207:2207) (2444:2444:2444))
-        (PORT datab (2689:2689:2689) (2932:2932:2932))
-        (PORT datac (2403:2403:2403) (2618:2618:2618))
-        (PORT datad (2426:2426:2426) (2628:2628:2628))
-        (IOPATH dataa combout (265:265:265) (273:273:273))
-        (IOPATH datab combout (265:265:265) (275:275:275))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst9)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2208:2208:2208) (2443:2443:2443))
-        (PORT datab (2706:2706:2706) (2945:2945:2945))
-        (PORT datac (2413:2413:2413) (2625:2625:2625))
-        (PORT datad (2432:2432:2432) (2633:2633:2633))
-        (IOPATH dataa combout (267:267:267) (269:269:269))
-        (IOPATH datab combout (267:267:267) (275:275:275))
-        (IOPATH datac combout (218:218:218) (216:216:216))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_85c_slow.vho b/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_85c_slow.vho
deleted file mode 100644
index e7f2a2e7..00000000
--- a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_85c_slow.vho
+++ /dev/null
@@ -1,494 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/17/2019 22:55:14"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	BCD_to_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	D : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic;
-	Y8 : OUT std_logic;
-	Y9 : OUT std_logic
-	);
-END BCD_to_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_V6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_R10,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_P3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_V3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y8	=>  Location: PIN_T9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y9	=>  Location: PIN_T3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_Y1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_T8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_T4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF BCD_to_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL ww_Y8 : std_logic;
-SIGNAL ww_Y9 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \Y8~output_o\ : std_logic;
-SIGNAL \Y9~output_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \D~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \inst~combout\ : std_logic;
-SIGNAL \inst1~combout\ : std_logic;
-SIGNAL \inst2~combout\ : std_logic;
-SIGNAL \inst3~combout\ : std_logic;
-SIGNAL \inst4~combout\ : std_logic;
-SIGNAL \inst5~combout\ : std_logic;
-SIGNAL \inst6~combout\ : std_logic;
-SIGNAL \inst7~combout\ : std_logic;
-SIGNAL \inst8~combout\ : std_logic;
-SIGNAL \inst9~combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-ww_D <= D;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-Y8 <= ww_Y8;
-Y9 <= ww_Y9;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X0_Y7_N9
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst~combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y9_N16
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst1~combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y12_N9
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst2~combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X1_Y0_N2
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst3~combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X1_Y0_N16
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst4~combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y8_N9
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst5~combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y9_N2
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst6~combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X0_Y4_N2
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst7~combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOOBUF_X1_Y0_N9
-\Y8~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst8~combout\,
-	devoe => ww_devoe,
-	o => \Y8~output_o\);
-
--- Location: IOOBUF_X0_Y6_N16
-\Y9~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst9~combout\,
-	devoe => ww_devoe,
-	o => \Y9~output_o\);
-
--- Location: IOIBUF_X0_Y4_N22
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: IOIBUF_X0_Y10_N15
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y6_N8
-\D~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_D,
-	o => \D~input_o\);
-
--- Location: IOIBUF_X1_Y0_N22
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: LCCOMB_X1_Y4_N0
-inst : cycloneiii_lcell_comb
--- Equation(s):
--- \inst~combout\ = (!\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000001",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst~combout\);
-
--- Location: LCCOMB_X1_Y4_N10
-inst1 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst1~combout\ = (!\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst1~combout\);
-
--- Location: LCCOMB_X1_Y4_N12
-inst2 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst2~combout\ = (!\B~input_o\ & (\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst2~combout\);
-
--- Location: LCCOMB_X1_Y4_N30
-inst3 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst3~combout\ = (!\B~input_o\ & (\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst3~combout\);
-
--- Location: LCCOMB_X1_Y4_N16
-inst4 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst4~combout\ = (\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst4~combout\);
-
--- Location: LCCOMB_X1_Y4_N26
-inst5 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst5~combout\ = (\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst5~combout\);
-
--- Location: LCCOMB_X1_Y4_N4
-inst6 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst6~combout\ = (\B~input_o\ & (\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst6~combout\);
-
--- Location: LCCOMB_X1_Y4_N14
-inst7 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst7~combout\ = (\B~input_o\ & (\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst7~combout\);
-
--- Location: LCCOMB_X1_Y4_N24
-inst8 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst8~combout\ = (!\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst8~combout\);
-
--- Location: LCCOMB_X1_Y4_N2
-inst9 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst9~combout\ = (!\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst9~combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-
-ww_Y8 <= \Y8~output_o\;
-
-ww_Y9 <= \Y9~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_85c_vhd_slow.sdo b/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_85c_vhd_slow.sdo
deleted file mode 100644
index 6aa33d46..00000000
--- a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_6_1200mv_85c_vhd_slow.sdo
+++ /dev/null
@@ -1,335 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "BCD_to_decimal_decoder")
-  (DATE "10/17/2019 22:55:15")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y0\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (597:597:597) (619:619:619))
-        (IOPATH i o (2236:2236:2236) (2224:2224:2224))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y1\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (900:900:900) (928:928:928))
-        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y2\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (913:913:913) (966:966:966))
-        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y3\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (558:558:558) (580:580:580))
-        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y4\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (581:581:581) (604:604:604))
-        (IOPATH i o (2080:2080:2080) (2029:2029:2029))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y5\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (648:648:648) (684:684:684))
-        (IOPATH i o (2147:2147:2147) (2105:2105:2105))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y6\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (899:899:899) (928:928:928))
-        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y7\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (326:326:326) (333:333:333))
-        (IOPATH i o (2157:2157:2157) (2115:2115:2115))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y8\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (563:563:563) (585:585:585))
-        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y9\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (631:631:631) (646:646:646))
-        (IOPATH i o (3426:3426:3426) (3527:3527:3527))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\B\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\C\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (715:715:715) (876:876:876))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\D\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (775:775:775) (936:936:936))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\A\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (689:689:689) (852:852:852))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2584:2584:2584) (2870:2870:2870))
-        (PORT datab (3147:3147:3147) (3436:3436:3436))
-        (PORT datac (2814:2814:2814) (3080:3080:3080))
-        (PORT datad (2829:2829:2829) (3091:3091:3091))
-        (IOPATH dataa combout (350:350:350) (366:366:366))
-        (IOPATH datab combout (350:350:350) (368:368:368))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst1)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2576:2576:2576) (2875:2875:2875))
-        (PORT datab (3146:3146:3146) (3433:3433:3433))
-        (PORT datac (2812:2812:2812) (3080:3080:3080))
-        (PORT datad (2826:2826:2826) (3093:3093:3093))
-        (IOPATH dataa combout (337:337:337) (338:338:338))
-        (IOPATH datab combout (337:337:337) (348:348:348))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst2)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2577:2577:2577) (2874:2874:2874))
-        (PORT datab (3145:3145:3145) (3432:3432:3432))
-        (PORT datac (2811:2811:2811) (3082:3082:3082))
-        (PORT datad (2826:2826:2826) (3091:3091:3091))
-        (IOPATH dataa combout (371:371:371) (376:376:376))
-        (IOPATH datab combout (355:355:355) (349:349:349))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst3)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2587:2587:2587) (2872:2872:2872))
-        (PORT datab (3129:3129:3129) (3417:3417:3417))
-        (PORT datac (2807:2807:2807) (3073:3073:3073))
-        (PORT datad (2824:2824:2824) (3090:3090:3090))
-        (IOPATH dataa combout (356:356:356) (368:368:368))
-        (IOPATH datab combout (342:342:342) (318:318:318))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst4)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2583:2583:2583) (2876:2876:2876))
-        (PORT datab (3140:3140:3140) (3429:3429:3429))
-        (PORT datac (2807:2807:2807) (3079:3079:3079))
-        (PORT datad (2828:2828:2828) (3091:3091:3091))
-        (IOPATH dataa combout (354:354:354) (349:349:349))
-        (IOPATH datab combout (381:381:381) (380:380:380))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst5)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2583:2583:2583) (2871:2871:2871))
-        (PORT datab (3128:3128:3128) (3415:3415:3415))
-        (PORT datac (2806:2806:2806) (3072:3072:3072))
-        (PORT datad (2823:2823:2823) (3090:3090:3090))
-        (IOPATH dataa combout (341:341:341) (319:319:319))
-        (IOPATH datab combout (365:365:365) (373:373:373))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst6)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2582:2582:2582) (2866:2866:2866))
-        (PORT datab (3145:3145:3145) (3437:3437:3437))
-        (PORT datac (2812:2812:2812) (3081:3081:3081))
-        (PORT datad (2827:2827:2827) (3093:3093:3093))
-        (IOPATH dataa combout (339:339:339) (367:367:367))
-        (IOPATH datab combout (344:344:344) (369:369:369))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst7)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2578:2578:2578) (2876:2876:2876))
-        (PORT datab (3144:3144:3144) (3429:3429:3429))
-        (PORT datac (2810:2810:2810) (3080:3080:3080))
-        (PORT datad (2827:2827:2827) (3096:3096:3096))
-        (IOPATH dataa combout (327:327:327) (347:347:347))
-        (IOPATH datab combout (331:331:331) (342:342:342))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst8)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2582:2582:2582) (2871:2871:2871))
-        (PORT datab (3127:3127:3127) (3423:3423:3423))
-        (PORT datac (2805:2805:2805) (3074:3074:3074))
-        (PORT datad (2823:2823:2823) (3086:3086:3086))
-        (IOPATH dataa combout (300:300:300) (307:307:307))
-        (IOPATH datab combout (300:300:300) (310:310:310))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst9)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2583:2583:2583) (2870:2870:2870))
-        (PORT datab (3146:3146:3146) (3435:3435:3435))
-        (PORT datac (2813:2813:2813) (3080:3080:3080))
-        (PORT datad (2828:2828:2828) (3090:3090:3090))
-        (IOPATH dataa combout (301:301:301) (299:299:299))
-        (IOPATH datab combout (300:300:300) (308:308:308))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_min_1200mv_0c_fast.vho b/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_min_1200mv_0c_fast.vho
deleted file mode 100644
index a8ffc54c..00000000
--- a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_min_1200mv_0c_fast.vho
+++ /dev/null
@@ -1,494 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/17/2019 22:55:15"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	BCD_to_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	D : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic;
-	Y8 : OUT std_logic;
-	Y9 : OUT std_logic
-	);
-END BCD_to_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_V6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_R10,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_P3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_V3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y8	=>  Location: PIN_T9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y9	=>  Location: PIN_T3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_Y1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_T8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_T4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF BCD_to_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL ww_Y8 : std_logic;
-SIGNAL ww_Y9 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \Y8~output_o\ : std_logic;
-SIGNAL \Y9~output_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \D~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \inst~combout\ : std_logic;
-SIGNAL \inst1~combout\ : std_logic;
-SIGNAL \inst2~combout\ : std_logic;
-SIGNAL \inst3~combout\ : std_logic;
-SIGNAL \inst4~combout\ : std_logic;
-SIGNAL \inst5~combout\ : std_logic;
-SIGNAL \inst6~combout\ : std_logic;
-SIGNAL \inst7~combout\ : std_logic;
-SIGNAL \inst8~combout\ : std_logic;
-SIGNAL \inst9~combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-ww_D <= D;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-Y8 <= ww_Y8;
-Y9 <= ww_Y9;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X0_Y7_N9
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst~combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y9_N16
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst1~combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y12_N9
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst2~combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X1_Y0_N2
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst3~combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X1_Y0_N16
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst4~combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y8_N9
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst5~combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y9_N2
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst6~combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X0_Y4_N2
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst7~combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOOBUF_X1_Y0_N9
-\Y8~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst8~combout\,
-	devoe => ww_devoe,
-	o => \Y8~output_o\);
-
--- Location: IOOBUF_X0_Y6_N16
-\Y9~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst9~combout\,
-	devoe => ww_devoe,
-	o => \Y9~output_o\);
-
--- Location: IOIBUF_X0_Y4_N22
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: IOIBUF_X0_Y10_N15
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y6_N8
-\D~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_D,
-	o => \D~input_o\);
-
--- Location: IOIBUF_X1_Y0_N22
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: LCCOMB_X1_Y4_N0
-inst : cycloneiii_lcell_comb
--- Equation(s):
--- \inst~combout\ = (!\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000001",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst~combout\);
-
--- Location: LCCOMB_X1_Y4_N10
-inst1 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst1~combout\ = (!\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst1~combout\);
-
--- Location: LCCOMB_X1_Y4_N12
-inst2 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst2~combout\ = (!\B~input_o\ & (\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst2~combout\);
-
--- Location: LCCOMB_X1_Y4_N30
-inst3 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst3~combout\ = (!\B~input_o\ & (\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst3~combout\);
-
--- Location: LCCOMB_X1_Y4_N16
-inst4 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst4~combout\ = (\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst4~combout\);
-
--- Location: LCCOMB_X1_Y4_N26
-inst5 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst5~combout\ = (\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst5~combout\);
-
--- Location: LCCOMB_X1_Y4_N4
-inst6 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst6~combout\ = (\B~input_o\ & (\C~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst6~combout\);
-
--- Location: LCCOMB_X1_Y4_N14
-inst7 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst7~combout\ = (\B~input_o\ & (\C~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst7~combout\);
-
--- Location: LCCOMB_X1_Y4_N24
-inst8 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst8~combout\ = (!\B~input_o\ & (!\C~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst8~combout\);
-
--- Location: LCCOMB_X1_Y4_N2
-inst9 : cycloneiii_lcell_comb
--- Equation(s):
--- \inst9~combout\ = (!\B~input_o\ & (!\C~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \B~input_o\,
-	datab => \C~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst9~combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-
-ww_Y8 <= \Y8~output_o\;
-
-ww_Y9 <= \Y9~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_min_1200mv_0c_vhd_fast.sdo b/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_min_1200mv_0c_vhd_fast.sdo
deleted file mode 100644
index e37b394b..00000000
--- a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_min_1200mv_0c_vhd_fast.sdo
+++ /dev/null
@@ -1,335 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Fast Corner delays for the design using part EP3C16F484C6,
-// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
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-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
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-
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-    (INSTANCE \\Y4\~output\\)
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-    (INSTANCE \\Y5\~output\\)
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-    (INSTANCE \\Y6\~output\\)
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-    (CELLTYPE "cycloneiii_io_ibuf")
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-    (DELAY
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-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\C\~input\\)
-    (DELAY
-      (ABSOLUTE
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-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\D\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (431:431:431) (813:813:813))
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-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\A\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (362:362:362) (744:744:744))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1511:1511:1511) (1697:1697:1697))
-        (PORT datab (1846:1846:1846) (2067:2067:2067))
-        (PORT datac (1649:1649:1649) (1841:1841:1841))
-        (PORT datad (1653:1653:1653) (1846:1846:1846))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (120:120:120) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst1)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1510:1510:1510) (1691:1691:1691))
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-        (PORT datad (1651:1651:1651) (1843:1843:1843))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
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-    (INSTANCE inst2)
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-      (ABSOLUTE
-        (PORT dataa (1509:1509:1509) (1690:1690:1690))
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-        (PORT datad (1650:1650:1650) (1846:1846:1846))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (168:168:168) (167:167:167))
-        (IOPATH datac combout (120:120:120) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
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-    (INSTANCE inst3)
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-        (PORT datad (1649:1649:1649) (1844:1844:1844))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (168:168:168) (167:167:167))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
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-    (INSTANCE inst4)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1509:1509:1509) (1695:1695:1695))
-        (PORT datab (1839:1839:1839) (2060:2060:2060))
-        (PORT datac (1642:1642:1642) (1833:1833:1833))
-        (PORT datad (1649:1649:1649) (1844:1844:1844))
-        (IOPATH dataa combout (170:170:170) (163:163:163))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (120:120:120) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst5)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1511:1511:1511) (1692:1692:1692))
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-        (PORT datac (1641:1641:1641) (1832:1832:1832))
-        (PORT datad (1649:1649:1649) (1844:1844:1844))
-        (IOPATH dataa combout (170:170:170) (163:163:163))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
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-  )
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-        (IOPATH datab combout (168:168:168) (167:167:167))
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-      )
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-    (DELAY
-      (ABSOLUTE
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-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (119:119:119) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst9)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1511:1511:1511) (1696:1696:1696))
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-        (PORT datac (1648:1648:1648) (1840:1840:1840))
-        (PORT datad (1653:1653:1653) (1846:1846:1846))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_modelsim.xrf b/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_modelsim.xrf
deleted file mode 100644
index b5f19df9..00000000
--- a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_modelsim.xrf
+++ /dev/null
@@ -1,18 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/db/BCD_to_decimal_decoder.cbx.xml
-design_name = BCD_to_decimal_decoder
-instance = comp, \Y0~output\, Y0~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y1~output\, Y1~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y2~output\, Y2~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y3~output\, Y3~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y4~output\, Y4~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y5~output\, Y5~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y6~output\, Y6~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y7~output\, Y7~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y8~output\, Y8~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y9~output\, Y9~output, BCD_to_decimal_decoder, 1
-instance = comp, \B~input\, B~input, BCD_to_decimal_decoder, 1
-instance = comp, \C~input\, C~input, BCD_to_decimal_decoder, 1
-instance = comp, \D~input\, D~input, BCD_to_decimal_decoder, 1
-instance = comp, \A~input\, A~input, BCD_to_decimal_decoder, 1
diff --git a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_vhd.sdo b/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_vhd.sdo
deleted file mode 100644
index 6aa33d46..00000000
--- a/CH6/CH6-1/simulation/modelsim/BCD_to_decimal_decoder_vhd.sdo
+++ /dev/null
@@ -1,335 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "BCD_to_decimal_decoder")
-  (DATE "10/17/2019 22:55:15")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
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-
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-        (PORT datab (3145:3145:3145) (3432:3432:3432))
-        (PORT datac (2811:2811:2811) (3082:3082:3082))
-        (PORT datad (2826:2826:2826) (3091:3091:3091))
-        (IOPATH dataa combout (371:371:371) (376:376:376))
-        (IOPATH datab combout (355:355:355) (349:349:349))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst3)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2587:2587:2587) (2872:2872:2872))
-        (PORT datab (3129:3129:3129) (3417:3417:3417))
-        (PORT datac (2807:2807:2807) (3073:3073:3073))
-        (PORT datad (2824:2824:2824) (3090:3090:3090))
-        (IOPATH dataa combout (356:356:356) (368:368:368))
-        (IOPATH datab combout (342:342:342) (318:318:318))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst4)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2583:2583:2583) (2876:2876:2876))
-        (PORT datab (3140:3140:3140) (3429:3429:3429))
-        (PORT datac (2807:2807:2807) (3079:3079:3079))
-        (PORT datad (2828:2828:2828) (3091:3091:3091))
-        (IOPATH dataa combout (354:354:354) (349:349:349))
-        (IOPATH datab combout (381:381:381) (380:380:380))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst5)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2583:2583:2583) (2871:2871:2871))
-        (PORT datab (3128:3128:3128) (3415:3415:3415))
-        (PORT datac (2806:2806:2806) (3072:3072:3072))
-        (PORT datad (2823:2823:2823) (3090:3090:3090))
-        (IOPATH dataa combout (341:341:341) (319:319:319))
-        (IOPATH datab combout (365:365:365) (373:373:373))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst6)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2582:2582:2582) (2866:2866:2866))
-        (PORT datab (3145:3145:3145) (3437:3437:3437))
-        (PORT datac (2812:2812:2812) (3081:3081:3081))
-        (PORT datad (2827:2827:2827) (3093:3093:3093))
-        (IOPATH dataa combout (339:339:339) (367:367:367))
-        (IOPATH datab combout (344:344:344) (369:369:369))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst7)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2578:2578:2578) (2876:2876:2876))
-        (PORT datab (3144:3144:3144) (3429:3429:3429))
-        (PORT datac (2810:2810:2810) (3080:3080:3080))
-        (PORT datad (2827:2827:2827) (3096:3096:3096))
-        (IOPATH dataa combout (327:327:327) (347:347:347))
-        (IOPATH datab combout (331:331:331) (342:342:342))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst8)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2582:2582:2582) (2871:2871:2871))
-        (PORT datab (3127:3127:3127) (3423:3423:3423))
-        (PORT datac (2805:2805:2805) (3074:3074:3074))
-        (PORT datad (2823:2823:2823) (3086:3086:3086))
-        (IOPATH dataa combout (300:300:300) (307:307:307))
-        (IOPATH datab combout (300:300:300) (310:310:310))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE inst9)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2583:2583:2583) (2870:2870:2870))
-        (PORT datab (3146:3146:3146) (3435:3435:3435))
-        (PORT datac (2813:2813:2813) (3080:3080:3080))
-        (PORT datad (2828:2828:2828) (3090:3090:3090))
-        (IOPATH dataa combout (301:301:301) (299:299:299))
-        (IOPATH datab combout (300:300:300) (308:308:308))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder.sft b/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder.sft
deleted file mode 100644
index 0d25f1b9..00000000
--- a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder.sft
+++ /dev/null
@@ -1,6 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
-set corner_file_list {
-	{{"Slow -6 1.2V 85 Model"} {Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_slow.vho Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_vhd_slow.sdo}}
-	{{"Slow -6 1.2V 0 Model"} {Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_slow.vho Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_vhd_slow.sdo}}
-	{{"Fast -M 1.2V 0 Model"} {Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_fast.vho Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_vhd_fast.sdo}}
-}
diff --git a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder.vho b/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder.vho
deleted file mode 100644
index 9dc5f17d..00000000
--- a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder.vho
+++ /dev/null
@@ -1,382 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/01/2019 00:13:13"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	Ten_line_to_four_line_BCD_encoder IS
-    PORT (
-	A : OUT std_logic;
-	I1 : IN std_logic;
-	I5 : IN std_logic;
-	I3 : IN std_logic;
-	I9 : IN std_logic;
-	I7 : IN std_logic;
-	B : OUT std_logic;
-	I2 : IN std_logic;
-	I6 : IN std_logic;
-	C : OUT std_logic;
-	I4 : IN std_logic;
-	D : OUT std_logic;
-	I8 : IN std_logic;
-	I0 : IN std_logic
-	);
-END Ten_line_to_four_line_BCD_encoder;
-
--- Design Ports Information
--- A	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I0	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I9	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I5	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I7	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I1	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I3	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I2	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I6	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I4	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I8	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF Ten_line_to_four_line_BCD_encoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_I1 : std_logic;
-SIGNAL ww_I5 : std_logic;
-SIGNAL ww_I3 : std_logic;
-SIGNAL ww_I9 : std_logic;
-SIGNAL ww_I7 : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_I2 : std_logic;
-SIGNAL ww_I6 : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_I4 : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_I8 : std_logic;
-SIGNAL ww_I0 : std_logic;
-SIGNAL \I0~input_o\ : std_logic;
-SIGNAL \A~output_o\ : std_logic;
-SIGNAL \B~output_o\ : std_logic;
-SIGNAL \C~output_o\ : std_logic;
-SIGNAL \D~output_o\ : std_logic;
-SIGNAL \I9~input_o\ : std_logic;
-SIGNAL \I1~input_o\ : std_logic;
-SIGNAL \I3~input_o\ : std_logic;
-SIGNAL \I7~input_o\ : std_logic;
-SIGNAL \I5~input_o\ : std_logic;
-SIGNAL \or1~0_combout\ : std_logic;
-SIGNAL \or1~combout\ : std_logic;
-SIGNAL \I6~input_o\ : std_logic;
-SIGNAL \I2~input_o\ : std_logic;
-SIGNAL \or2~0_combout\ : std_logic;
-SIGNAL \I4~input_o\ : std_logic;
-SIGNAL \or3~0_combout\ : std_logic;
-SIGNAL \I8~input_o\ : std_logic;
-SIGNAL \or4~combout\ : std_logic;
-
-BEGIN
-
-A <= ww_A;
-ww_I1 <= I1;
-ww_I5 <= I5;
-ww_I3 <= I3;
-ww_I9 <= I9;
-ww_I7 <= I7;
-B <= ww_B;
-ww_I2 <= I2;
-ww_I6 <= I6;
-C <= ww_C;
-ww_I4 <= I4;
-D <= ww_D;
-ww_I8 <= I8;
-ww_I0 <= I0;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X0_Y26_N23
-\A~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or1~combout\,
-	devoe => ww_devoe,
-	o => \A~output_o\);
-
--- Location: IOOBUF_X0_Y26_N16
-\B~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or2~0_combout\,
-	devoe => ww_devoe,
-	o => \B~output_o\);
-
--- Location: IOOBUF_X0_Y27_N9
-\C~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or3~0_combout\,
-	devoe => ww_devoe,
-	o => \C~output_o\);
-
--- Location: IOOBUF_X0_Y27_N16
-\D~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or4~combout\,
-	devoe => ww_devoe,
-	o => \D~output_o\);
-
--- Location: IOIBUF_X0_Y24_N1
-\I9~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I9,
-	o => \I9~input_o\);
-
--- Location: IOIBUF_X0_Y26_N1
-\I1~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I1,
-	o => \I1~input_o\);
-
--- Location: IOIBUF_X0_Y25_N15
-\I3~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I3,
-	o => \I3~input_o\);
-
--- Location: IOIBUF_X0_Y25_N22
-\I7~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I7,
-	o => \I7~input_o\);
-
--- Location: IOIBUF_X0_Y27_N22
-\I5~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I5,
-	o => \I5~input_o\);
-
--- Location: LCCOMB_X1_Y27_N0
-\or1~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or1~0_combout\ = (\I1~input_o\) # ((\I3~input_o\) # ((\I7~input_o\) # (\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I1~input_o\,
-	datab => \I3~input_o\,
-	datac => \I7~input_o\,
-	datad => \I5~input_o\,
-	combout => \or1~0_combout\);
-
--- Location: LCCOMB_X1_Y27_N2
-or1 : cycloneiii_lcell_comb
--- Equation(s):
--- \or1~combout\ = (\I9~input_o\) # (\or1~0_combout\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111110000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \or1~0_combout\,
-	combout => \or1~combout\);
-
--- Location: IOIBUF_X0_Y23_N8
-\I6~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I6,
-	o => \I6~input_o\);
-
--- Location: IOIBUF_X0_Y26_N8
-\I2~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I2,
-	o => \I2~input_o\);
-
--- Location: LCCOMB_X1_Y27_N28
-\or2~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or2~0_combout\ = (\I6~input_o\) # ((\I3~input_o\) # ((\I7~input_o\) # (\I2~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I6~input_o\,
-	datab => \I3~input_o\,
-	datac => \I7~input_o\,
-	datad => \I2~input_o\,
-	combout => \or2~0_combout\);
-
--- Location: IOIBUF_X0_Y22_N15
-\I4~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I4,
-	o => \I4~input_o\);
-
--- Location: LCCOMB_X1_Y27_N14
-\or3~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or3~0_combout\ = (\I6~input_o\) # ((\I7~input_o\) # ((\I4~input_o\) # (\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I6~input_o\,
-	datab => \I7~input_o\,
-	datac => \I4~input_o\,
-	datad => \I5~input_o\,
-	combout => \or3~0_combout\);
-
--- Location: IOIBUF_X0_Y27_N1
-\I8~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I8,
-	o => \I8~input_o\);
-
--- Location: LCCOMB_X1_Y27_N16
-or4 : cycloneiii_lcell_comb
--- Equation(s):
--- \or4~combout\ = (\I9~input_o\) # (\I8~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111110000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \I8~input_o\,
-	combout => \or4~combout\);
-
--- Location: IOIBUF_X0_Y25_N1
-\I0~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I0,
-	o => \I0~input_o\);
-
-ww_A <= \A~output_o\;
-
-ww_B <= \B~output_o\;
-
-ww_C <= \C~output_o\;
-
-ww_D <= \D~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_slow.vho b/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_slow.vho
deleted file mode 100644
index 9dc5f17d..00000000
--- a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_slow.vho
+++ /dev/null
@@ -1,382 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/01/2019 00:13:13"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	Ten_line_to_four_line_BCD_encoder IS
-    PORT (
-	A : OUT std_logic;
-	I1 : IN std_logic;
-	I5 : IN std_logic;
-	I3 : IN std_logic;
-	I9 : IN std_logic;
-	I7 : IN std_logic;
-	B : OUT std_logic;
-	I2 : IN std_logic;
-	I6 : IN std_logic;
-	C : OUT std_logic;
-	I4 : IN std_logic;
-	D : OUT std_logic;
-	I8 : IN std_logic;
-	I0 : IN std_logic
-	);
-END Ten_line_to_four_line_BCD_encoder;
-
--- Design Ports Information
--- A	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I0	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I9	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I5	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I7	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I1	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I3	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I2	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I6	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I4	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I8	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF Ten_line_to_four_line_BCD_encoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_I1 : std_logic;
-SIGNAL ww_I5 : std_logic;
-SIGNAL ww_I3 : std_logic;
-SIGNAL ww_I9 : std_logic;
-SIGNAL ww_I7 : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_I2 : std_logic;
-SIGNAL ww_I6 : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_I4 : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_I8 : std_logic;
-SIGNAL ww_I0 : std_logic;
-SIGNAL \I0~input_o\ : std_logic;
-SIGNAL \A~output_o\ : std_logic;
-SIGNAL \B~output_o\ : std_logic;
-SIGNAL \C~output_o\ : std_logic;
-SIGNAL \D~output_o\ : std_logic;
-SIGNAL \I9~input_o\ : std_logic;
-SIGNAL \I1~input_o\ : std_logic;
-SIGNAL \I3~input_o\ : std_logic;
-SIGNAL \I7~input_o\ : std_logic;
-SIGNAL \I5~input_o\ : std_logic;
-SIGNAL \or1~0_combout\ : std_logic;
-SIGNAL \or1~combout\ : std_logic;
-SIGNAL \I6~input_o\ : std_logic;
-SIGNAL \I2~input_o\ : std_logic;
-SIGNAL \or2~0_combout\ : std_logic;
-SIGNAL \I4~input_o\ : std_logic;
-SIGNAL \or3~0_combout\ : std_logic;
-SIGNAL \I8~input_o\ : std_logic;
-SIGNAL \or4~combout\ : std_logic;
-
-BEGIN
-
-A <= ww_A;
-ww_I1 <= I1;
-ww_I5 <= I5;
-ww_I3 <= I3;
-ww_I9 <= I9;
-ww_I7 <= I7;
-B <= ww_B;
-ww_I2 <= I2;
-ww_I6 <= I6;
-C <= ww_C;
-ww_I4 <= I4;
-D <= ww_D;
-ww_I8 <= I8;
-ww_I0 <= I0;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X0_Y26_N23
-\A~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or1~combout\,
-	devoe => ww_devoe,
-	o => \A~output_o\);
-
--- Location: IOOBUF_X0_Y26_N16
-\B~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or2~0_combout\,
-	devoe => ww_devoe,
-	o => \B~output_o\);
-
--- Location: IOOBUF_X0_Y27_N9
-\C~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or3~0_combout\,
-	devoe => ww_devoe,
-	o => \C~output_o\);
-
--- Location: IOOBUF_X0_Y27_N16
-\D~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or4~combout\,
-	devoe => ww_devoe,
-	o => \D~output_o\);
-
--- Location: IOIBUF_X0_Y24_N1
-\I9~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I9,
-	o => \I9~input_o\);
-
--- Location: IOIBUF_X0_Y26_N1
-\I1~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I1,
-	o => \I1~input_o\);
-
--- Location: IOIBUF_X0_Y25_N15
-\I3~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I3,
-	o => \I3~input_o\);
-
--- Location: IOIBUF_X0_Y25_N22
-\I7~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I7,
-	o => \I7~input_o\);
-
--- Location: IOIBUF_X0_Y27_N22
-\I5~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I5,
-	o => \I5~input_o\);
-
--- Location: LCCOMB_X1_Y27_N0
-\or1~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or1~0_combout\ = (\I1~input_o\) # ((\I3~input_o\) # ((\I7~input_o\) # (\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I1~input_o\,
-	datab => \I3~input_o\,
-	datac => \I7~input_o\,
-	datad => \I5~input_o\,
-	combout => \or1~0_combout\);
-
--- Location: LCCOMB_X1_Y27_N2
-or1 : cycloneiii_lcell_comb
--- Equation(s):
--- \or1~combout\ = (\I9~input_o\) # (\or1~0_combout\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111110000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \or1~0_combout\,
-	combout => \or1~combout\);
-
--- Location: IOIBUF_X0_Y23_N8
-\I6~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I6,
-	o => \I6~input_o\);
-
--- Location: IOIBUF_X0_Y26_N8
-\I2~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I2,
-	o => \I2~input_o\);
-
--- Location: LCCOMB_X1_Y27_N28
-\or2~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or2~0_combout\ = (\I6~input_o\) # ((\I3~input_o\) # ((\I7~input_o\) # (\I2~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I6~input_o\,
-	datab => \I3~input_o\,
-	datac => \I7~input_o\,
-	datad => \I2~input_o\,
-	combout => \or2~0_combout\);
-
--- Location: IOIBUF_X0_Y22_N15
-\I4~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I4,
-	o => \I4~input_o\);
-
--- Location: LCCOMB_X1_Y27_N14
-\or3~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or3~0_combout\ = (\I6~input_o\) # ((\I7~input_o\) # ((\I4~input_o\) # (\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I6~input_o\,
-	datab => \I7~input_o\,
-	datac => \I4~input_o\,
-	datad => \I5~input_o\,
-	combout => \or3~0_combout\);
-
--- Location: IOIBUF_X0_Y27_N1
-\I8~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I8,
-	o => \I8~input_o\);
-
--- Location: LCCOMB_X1_Y27_N16
-or4 : cycloneiii_lcell_comb
--- Equation(s):
--- \or4~combout\ = (\I9~input_o\) # (\I8~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111110000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \I8~input_o\,
-	combout => \or4~combout\);
-
--- Location: IOIBUF_X0_Y25_N1
-\I0~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I0,
-	o => \I0~input_o\);
-
-ww_A <= \A~output_o\;
-
-ww_B <= \B~output_o\;
-
-ww_C <= \C~output_o\;
-
-ww_D <= \D~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_vhd_slow.sdo b/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_vhd_slow.sdo
deleted file mode 100644
index a88c8aae..00000000
--- a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_0c_vhd_slow.sdo
+++ /dev/null
@@ -1,232 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "Ten_line_to_four_line_BCD_encoder")
-  (DATE "10/01/2019 00:13:13")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\A\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (549:549:549) (544:544:544))
-        (IOPATH i o (2256:2256:2256) (2244:2244:2244))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\B\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (556:556:556) (547:547:547))
-        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\C\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (295:295:295) (292:292:292))
-        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\D\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (293:293:293) (287:287:287))
-        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I9\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I1\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I3\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I7\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I5\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or1\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2333:2333:2333) (2519:2519:2519))
-        (PORT datab (2386:2386:2386) (2601:2601:2601))
-        (PORT datac (2392:2392:2392) (2598:2598:2598))
-        (PORT datad (2127:2127:2127) (2324:2324:2324))
-        (IOPATH dataa combout (318:318:318) (307:307:307))
-        (IOPATH datab combout (319:319:319) (307:307:307))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE or1)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (2361:2361:2361) (2560:2560:2560))
-        (PORT datad (159:159:159) (180:180:180))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I6\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I2\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or2\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2432:2432:2432) (2647:2647:2647))
-        (PORT datab (2381:2381:2381) (2594:2594:2594))
-        (PORT datac (2396:2396:2396) (2603:2603:2603))
-        (PORT datad (2334:2334:2334) (2519:2519:2519))
-        (IOPATH dataa combout (318:318:318) (307:307:307))
-        (IOPATH datab combout (319:319:319) (307:307:307))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I4\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or3\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2433:2433:2433) (2650:2650:2650))
-        (PORT datab (2422:2422:2422) (2628:2628:2628))
-        (PORT datac (2608:2608:2608) (2811:2811:2811))
-        (PORT datad (2125:2125:2125) (2320:2320:2320))
-        (IOPATH dataa combout (318:318:318) (307:307:307))
-        (IOPATH datab combout (319:319:319) (307:307:307))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I8\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE or4)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (2362:2362:2362) (2563:2563:2563))
-        (PORT datad (2100:2100:2100) (2295:2295:2295))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_slow.vho b/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_slow.vho
deleted file mode 100644
index 9dc5f17d..00000000
--- a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_slow.vho
+++ /dev/null
@@ -1,382 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/01/2019 00:13:13"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	Ten_line_to_four_line_BCD_encoder IS
-    PORT (
-	A : OUT std_logic;
-	I1 : IN std_logic;
-	I5 : IN std_logic;
-	I3 : IN std_logic;
-	I9 : IN std_logic;
-	I7 : IN std_logic;
-	B : OUT std_logic;
-	I2 : IN std_logic;
-	I6 : IN std_logic;
-	C : OUT std_logic;
-	I4 : IN std_logic;
-	D : OUT std_logic;
-	I8 : IN std_logic;
-	I0 : IN std_logic
-	);
-END Ten_line_to_four_line_BCD_encoder;
-
--- Design Ports Information
--- A	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I0	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I9	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I5	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I7	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I1	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I3	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I2	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I6	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I4	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I8	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF Ten_line_to_four_line_BCD_encoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_I1 : std_logic;
-SIGNAL ww_I5 : std_logic;
-SIGNAL ww_I3 : std_logic;
-SIGNAL ww_I9 : std_logic;
-SIGNAL ww_I7 : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_I2 : std_logic;
-SIGNAL ww_I6 : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_I4 : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_I8 : std_logic;
-SIGNAL ww_I0 : std_logic;
-SIGNAL \I0~input_o\ : std_logic;
-SIGNAL \A~output_o\ : std_logic;
-SIGNAL \B~output_o\ : std_logic;
-SIGNAL \C~output_o\ : std_logic;
-SIGNAL \D~output_o\ : std_logic;
-SIGNAL \I9~input_o\ : std_logic;
-SIGNAL \I1~input_o\ : std_logic;
-SIGNAL \I3~input_o\ : std_logic;
-SIGNAL \I7~input_o\ : std_logic;
-SIGNAL \I5~input_o\ : std_logic;
-SIGNAL \or1~0_combout\ : std_logic;
-SIGNAL \or1~combout\ : std_logic;
-SIGNAL \I6~input_o\ : std_logic;
-SIGNAL \I2~input_o\ : std_logic;
-SIGNAL \or2~0_combout\ : std_logic;
-SIGNAL \I4~input_o\ : std_logic;
-SIGNAL \or3~0_combout\ : std_logic;
-SIGNAL \I8~input_o\ : std_logic;
-SIGNAL \or4~combout\ : std_logic;
-
-BEGIN
-
-A <= ww_A;
-ww_I1 <= I1;
-ww_I5 <= I5;
-ww_I3 <= I3;
-ww_I9 <= I9;
-ww_I7 <= I7;
-B <= ww_B;
-ww_I2 <= I2;
-ww_I6 <= I6;
-C <= ww_C;
-ww_I4 <= I4;
-D <= ww_D;
-ww_I8 <= I8;
-ww_I0 <= I0;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X0_Y26_N23
-\A~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or1~combout\,
-	devoe => ww_devoe,
-	o => \A~output_o\);
-
--- Location: IOOBUF_X0_Y26_N16
-\B~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or2~0_combout\,
-	devoe => ww_devoe,
-	o => \B~output_o\);
-
--- Location: IOOBUF_X0_Y27_N9
-\C~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or3~0_combout\,
-	devoe => ww_devoe,
-	o => \C~output_o\);
-
--- Location: IOOBUF_X0_Y27_N16
-\D~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or4~combout\,
-	devoe => ww_devoe,
-	o => \D~output_o\);
-
--- Location: IOIBUF_X0_Y24_N1
-\I9~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I9,
-	o => \I9~input_o\);
-
--- Location: IOIBUF_X0_Y26_N1
-\I1~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I1,
-	o => \I1~input_o\);
-
--- Location: IOIBUF_X0_Y25_N15
-\I3~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I3,
-	o => \I3~input_o\);
-
--- Location: IOIBUF_X0_Y25_N22
-\I7~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I7,
-	o => \I7~input_o\);
-
--- Location: IOIBUF_X0_Y27_N22
-\I5~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I5,
-	o => \I5~input_o\);
-
--- Location: LCCOMB_X1_Y27_N0
-\or1~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or1~0_combout\ = (\I1~input_o\) # ((\I3~input_o\) # ((\I7~input_o\) # (\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I1~input_o\,
-	datab => \I3~input_o\,
-	datac => \I7~input_o\,
-	datad => \I5~input_o\,
-	combout => \or1~0_combout\);
-
--- Location: LCCOMB_X1_Y27_N2
-or1 : cycloneiii_lcell_comb
--- Equation(s):
--- \or1~combout\ = (\I9~input_o\) # (\or1~0_combout\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111110000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \or1~0_combout\,
-	combout => \or1~combout\);
-
--- Location: IOIBUF_X0_Y23_N8
-\I6~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I6,
-	o => \I6~input_o\);
-
--- Location: IOIBUF_X0_Y26_N8
-\I2~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I2,
-	o => \I2~input_o\);
-
--- Location: LCCOMB_X1_Y27_N28
-\or2~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or2~0_combout\ = (\I6~input_o\) # ((\I3~input_o\) # ((\I7~input_o\) # (\I2~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I6~input_o\,
-	datab => \I3~input_o\,
-	datac => \I7~input_o\,
-	datad => \I2~input_o\,
-	combout => \or2~0_combout\);
-
--- Location: IOIBUF_X0_Y22_N15
-\I4~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I4,
-	o => \I4~input_o\);
-
--- Location: LCCOMB_X1_Y27_N14
-\or3~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or3~0_combout\ = (\I6~input_o\) # ((\I7~input_o\) # ((\I4~input_o\) # (\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I6~input_o\,
-	datab => \I7~input_o\,
-	datac => \I4~input_o\,
-	datad => \I5~input_o\,
-	combout => \or3~0_combout\);
-
--- Location: IOIBUF_X0_Y27_N1
-\I8~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I8,
-	o => \I8~input_o\);
-
--- Location: LCCOMB_X1_Y27_N16
-or4 : cycloneiii_lcell_comb
--- Equation(s):
--- \or4~combout\ = (\I9~input_o\) # (\I8~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111110000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \I8~input_o\,
-	combout => \or4~combout\);
-
--- Location: IOIBUF_X0_Y25_N1
-\I0~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I0,
-	o => \I0~input_o\);
-
-ww_A <= \A~output_o\;
-
-ww_B <= \B~output_o\;
-
-ww_C <= \C~output_o\;
-
-ww_D <= \D~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_vhd_slow.sdo b/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_vhd_slow.sdo
deleted file mode 100644
index 2eb593f9..00000000
--- a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_6_1200mv_85c_vhd_slow.sdo
+++ /dev/null
@@ -1,232 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "Ten_line_to_four_line_BCD_encoder")
-  (DATE "10/01/2019 00:13:13")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\A\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (601:601:601) (609:609:609))
-        (IOPATH i o (2256:2256:2256) (2244:2244:2244))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\B\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (607:607:607) (616:616:616))
-        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\C\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (324:324:324) (328:328:328))
-        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\D\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (321:321:321) (324:324:324))
-        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I9\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I1\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I3\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I7\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I5\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or1\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2712:2712:2712) (2966:2966:2966))
-        (PORT datab (2776:2776:2776) (3042:3042:3042))
-        (PORT datac (2788:2788:2788) (3040:3040:3040))
-        (PORT datad (2495:2495:2495) (2745:2745:2745))
-        (IOPATH dataa combout (354:354:354) (349:349:349))
-        (IOPATH datab combout (355:355:355) (349:349:349))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE or1)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (2746:2746:2746) (3018:3018:3018))
-        (PORT datad (173:173:173) (199:199:199))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I6\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I2\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or2\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2828:2828:2828) (3112:3112:3112))
-        (PORT datab (2771:2771:2771) (3036:3036:3036))
-        (PORT datac (2792:2792:2792) (3045:3045:3045))
-        (PORT datad (2720:2720:2720) (2958:2958:2958))
-        (IOPATH dataa combout (354:354:354) (349:349:349))
-        (IOPATH datab combout (355:355:355) (349:349:349))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I4\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or3\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2829:2829:2829) (3115:3115:3115))
-        (PORT datab (2819:2819:2819) (3076:3076:3076))
-        (PORT datac (3013:3013:3013) (3284:3284:3284))
-        (PORT datad (2492:2492:2492) (2742:2742:2742))
-        (IOPATH dataa combout (354:354:354) (349:349:349))
-        (IOPATH datab combout (355:355:355) (349:349:349))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I8\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE or4)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (2746:2746:2746) (3020:3020:3020))
-        (PORT datad (2465:2465:2465) (2714:2714:2714))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_fast.vho b/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_fast.vho
deleted file mode 100644
index 9dc5f17d..00000000
--- a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_fast.vho
+++ /dev/null
@@ -1,382 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/01/2019 00:13:13"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	Ten_line_to_four_line_BCD_encoder IS
-    PORT (
-	A : OUT std_logic;
-	I1 : IN std_logic;
-	I5 : IN std_logic;
-	I3 : IN std_logic;
-	I9 : IN std_logic;
-	I7 : IN std_logic;
-	B : OUT std_logic;
-	I2 : IN std_logic;
-	I6 : IN std_logic;
-	C : OUT std_logic;
-	I4 : IN std_logic;
-	D : OUT std_logic;
-	I8 : IN std_logic;
-	I0 : IN std_logic
-	);
-END Ten_line_to_four_line_BCD_encoder;
-
--- Design Ports Information
--- A	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I0	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I9	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I5	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I7	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I1	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I3	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I2	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I6	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I4	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I8	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF Ten_line_to_four_line_BCD_encoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_I1 : std_logic;
-SIGNAL ww_I5 : std_logic;
-SIGNAL ww_I3 : std_logic;
-SIGNAL ww_I9 : std_logic;
-SIGNAL ww_I7 : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_I2 : std_logic;
-SIGNAL ww_I6 : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_I4 : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_I8 : std_logic;
-SIGNAL ww_I0 : std_logic;
-SIGNAL \I0~input_o\ : std_logic;
-SIGNAL \A~output_o\ : std_logic;
-SIGNAL \B~output_o\ : std_logic;
-SIGNAL \C~output_o\ : std_logic;
-SIGNAL \D~output_o\ : std_logic;
-SIGNAL \I9~input_o\ : std_logic;
-SIGNAL \I1~input_o\ : std_logic;
-SIGNAL \I3~input_o\ : std_logic;
-SIGNAL \I7~input_o\ : std_logic;
-SIGNAL \I5~input_o\ : std_logic;
-SIGNAL \or1~0_combout\ : std_logic;
-SIGNAL \or1~combout\ : std_logic;
-SIGNAL \I6~input_o\ : std_logic;
-SIGNAL \I2~input_o\ : std_logic;
-SIGNAL \or2~0_combout\ : std_logic;
-SIGNAL \I4~input_o\ : std_logic;
-SIGNAL \or3~0_combout\ : std_logic;
-SIGNAL \I8~input_o\ : std_logic;
-SIGNAL \or4~combout\ : std_logic;
-
-BEGIN
-
-A <= ww_A;
-ww_I1 <= I1;
-ww_I5 <= I5;
-ww_I3 <= I3;
-ww_I9 <= I9;
-ww_I7 <= I7;
-B <= ww_B;
-ww_I2 <= I2;
-ww_I6 <= I6;
-C <= ww_C;
-ww_I4 <= I4;
-D <= ww_D;
-ww_I8 <= I8;
-ww_I0 <= I0;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X0_Y26_N23
-\A~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or1~combout\,
-	devoe => ww_devoe,
-	o => \A~output_o\);
-
--- Location: IOOBUF_X0_Y26_N16
-\B~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or2~0_combout\,
-	devoe => ww_devoe,
-	o => \B~output_o\);
-
--- Location: IOOBUF_X0_Y27_N9
-\C~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or3~0_combout\,
-	devoe => ww_devoe,
-	o => \C~output_o\);
-
--- Location: IOOBUF_X0_Y27_N16
-\D~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \or4~combout\,
-	devoe => ww_devoe,
-	o => \D~output_o\);
-
--- Location: IOIBUF_X0_Y24_N1
-\I9~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I9,
-	o => \I9~input_o\);
-
--- Location: IOIBUF_X0_Y26_N1
-\I1~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I1,
-	o => \I1~input_o\);
-
--- Location: IOIBUF_X0_Y25_N15
-\I3~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I3,
-	o => \I3~input_o\);
-
--- Location: IOIBUF_X0_Y25_N22
-\I7~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I7,
-	o => \I7~input_o\);
-
--- Location: IOIBUF_X0_Y27_N22
-\I5~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I5,
-	o => \I5~input_o\);
-
--- Location: LCCOMB_X1_Y27_N0
-\or1~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or1~0_combout\ = (\I1~input_o\) # ((\I3~input_o\) # ((\I7~input_o\) # (\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I1~input_o\,
-	datab => \I3~input_o\,
-	datac => \I7~input_o\,
-	datad => \I5~input_o\,
-	combout => \or1~0_combout\);
-
--- Location: LCCOMB_X1_Y27_N2
-or1 : cycloneiii_lcell_comb
--- Equation(s):
--- \or1~combout\ = (\I9~input_o\) # (\or1~0_combout\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111110000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \or1~0_combout\,
-	combout => \or1~combout\);
-
--- Location: IOIBUF_X0_Y23_N8
-\I6~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I6,
-	o => \I6~input_o\);
-
--- Location: IOIBUF_X0_Y26_N8
-\I2~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I2,
-	o => \I2~input_o\);
-
--- Location: LCCOMB_X1_Y27_N28
-\or2~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or2~0_combout\ = (\I6~input_o\) # ((\I3~input_o\) # ((\I7~input_o\) # (\I2~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I6~input_o\,
-	datab => \I3~input_o\,
-	datac => \I7~input_o\,
-	datad => \I2~input_o\,
-	combout => \or2~0_combout\);
-
--- Location: IOIBUF_X0_Y22_N15
-\I4~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I4,
-	o => \I4~input_o\);
-
--- Location: LCCOMB_X1_Y27_N14
-\or3~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \or3~0_combout\ = (\I6~input_o\) # ((\I7~input_o\) # ((\I4~input_o\) # (\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111111110",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I6~input_o\,
-	datab => \I7~input_o\,
-	datac => \I4~input_o\,
-	datad => \I5~input_o\,
-	combout => \or3~0_combout\);
-
--- Location: IOIBUF_X0_Y27_N1
-\I8~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I8,
-	o => \I8~input_o\);
-
--- Location: LCCOMB_X1_Y27_N16
-or4 : cycloneiii_lcell_comb
--- Equation(s):
--- \or4~combout\ = (\I9~input_o\) # (\I8~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1111111111110000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \I8~input_o\,
-	combout => \or4~combout\);
-
--- Location: IOIBUF_X0_Y25_N1
-\I0~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I0,
-	o => \I0~input_o\);
-
-ww_A <= \A~output_o\;
-
-ww_B <= \B~output_o\;
-
-ww_C <= \C~output_o\;
-
-ww_D <= \D~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_vhd_fast.sdo b/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_vhd_fast.sdo
deleted file mode 100644
index 3eecfe76..00000000
--- a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_min_1200mv_0c_vhd_fast.sdo
+++ /dev/null
@@ -1,232 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Fast Corner delays for the design using part EP3C16F484C6,
-// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "Ten_line_to_four_line_BCD_encoder")
-  (DATE "10/01/2019 00:13:13")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\A\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (319:319:319) (361:361:361))
-        (IOPATH i o (1496:1496:1496) (1480:1480:1480))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\B\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (324:324:324) (366:366:366))
-        (IOPATH i o (1506:1506:1506) (1490:1490:1490))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\C\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (162:162:162) (183:183:183))
-        (IOPATH i o (1506:1506:1506) (1490:1490:1490))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\D\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (161:161:161) (181:181:181))
-        (IOPATH i o (1506:1506:1506) (1490:1490:1490))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I9\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (381:381:381) (763:763:763))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I1\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (391:391:391) (773:773:773))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I3\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (381:381:381) (763:763:763))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I7\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (381:381:381) (763:763:763))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I5\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (381:381:381) (763:763:763))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or1\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1573:1573:1573) (1755:1755:1755))
-        (PORT datab (1626:1626:1626) (1817:1817:1817))
-        (PORT datac (1626:1626:1626) (1805:1805:1805))
-        (PORT datad (1455:1455:1455) (1618:1618:1618))
-        (IOPATH dataa combout (170:170:170) (163:163:163))
-        (IOPATH datab combout (168:168:168) (167:167:167))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE or1)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (1611:1611:1611) (1787:1787:1787))
-        (PORT datad (90:90:90) (106:106:106))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I6\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (391:391:391) (773:773:773))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I2\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (391:391:391) (773:773:773))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or2\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1657:1657:1657) (1845:1845:1845))
-        (PORT datab (1621:1621:1621) (1811:1811:1811))
-        (PORT datac (1630:1630:1630) (1810:1810:1810))
-        (PORT datad (1574:1574:1574) (1753:1753:1753))
-        (IOPATH dataa combout (170:170:170) (163:163:163))
-        (IOPATH datab combout (168:168:168) (167:167:167))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I4\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (381:381:381) (763:763:763))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or3\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1658:1658:1658) (1848:1848:1848))
-        (PORT datab (1643:1643:1643) (1830:1830:1830))
-        (PORT datac (1773:1773:1773) (1965:1965:1965))
-        (PORT datad (1452:1452:1452) (1614:1614:1614))
-        (IOPATH dataa combout (170:170:170) (163:163:163))
-        (IOPATH datab combout (168:168:168) (167:167:167))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I8\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (381:381:381) (763:763:763))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE or4)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (1612:1612:1612) (1788:1788:1788))
-        (PORT datad (1438:1438:1438) (1596:1596:1596))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_modelsim.xrf b/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_modelsim.xrf
deleted file mode 100644
index 7ddbc0cd..00000000
--- a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_modelsim.xrf
+++ /dev/null
@@ -1,22 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/Ten_line_to_four_line_BCD_encoder.bdf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/output_files/Chain1.cdf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/db/Ten_line_to_four_line_BCD_encoder.cbx.xml
-design_name = Ten_line_to_four_line_BCD_encoder
-instance = comp, \A~output\, A~output, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \B~output\, B~output, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \C~output\, C~output, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \D~output\, D~output, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \I9~input\, I9~input, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \I1~input\, I1~input, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \I3~input\, I3~input, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \I7~input\, I7~input, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \I5~input\, I5~input, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \or1~0\, or1~0, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \I6~input\, I6~input, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \I2~input\, I2~input, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \or2~0\, or2~0, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \I4~input\, I4~input, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \or3~0\, or3~0, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \I8~input\, I8~input, Ten_line_to_four_line_BCD_encoder, 1
-instance = comp, \I0~input\, I0~input, Ten_line_to_four_line_BCD_encoder, 1
diff --git a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_vhd.sdo b/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_vhd.sdo
deleted file mode 100644
index 2eb593f9..00000000
--- a/CH6/CH6-1/simulation/modelsim/Ten_line_to_four_line_BCD_encoder_vhd.sdo
+++ /dev/null
@@ -1,232 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "Ten_line_to_four_line_BCD_encoder")
-  (DATE "10/01/2019 00:13:13")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\A\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (601:601:601) (609:609:609))
-        (IOPATH i o (2256:2256:2256) (2244:2244:2244))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\B\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (607:607:607) (616:616:616))
-        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\C\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (324:324:324) (328:328:328))
-        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\D\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (321:321:321) (324:324:324))
-        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I9\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I1\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I3\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I7\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I5\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or1\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2712:2712:2712) (2966:2966:2966))
-        (PORT datab (2776:2776:2776) (3042:3042:3042))
-        (PORT datac (2788:2788:2788) (3040:3040:3040))
-        (PORT datad (2495:2495:2495) (2745:2745:2745))
-        (IOPATH dataa combout (354:354:354) (349:349:349))
-        (IOPATH datab combout (355:355:355) (349:349:349))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE or1)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (2746:2746:2746) (3018:3018:3018))
-        (PORT datad (173:173:173) (199:199:199))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I6\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I2\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or2\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2828:2828:2828) (3112:3112:3112))
-        (PORT datab (2771:2771:2771) (3036:3036:3036))
-        (PORT datac (2792:2792:2792) (3045:3045:3045))
-        (PORT datad (2720:2720:2720) (2958:2958:2958))
-        (IOPATH dataa combout (354:354:354) (349:349:349))
-        (IOPATH datab combout (355:355:355) (349:349:349))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I4\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\or3\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2829:2829:2829) (3115:3115:3115))
-        (PORT datab (2819:2819:2819) (3076:3076:3076))
-        (PORT datac (3013:3013:3013) (3284:3284:3284))
-        (PORT datad (2492:2492:2492) (2742:2742:2742))
-        (IOPATH dataa combout (354:354:354) (349:349:349))
-        (IOPATH datab combout (355:355:355) (349:349:349))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I8\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE or4)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (2746:2746:2746) (3020:3020:3020))
-        (PORT datad (2465:2465:2465) (2714:2714:2714))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder.sft b/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder.sft
deleted file mode 100644
index 429d91bc..00000000
--- a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder.sft
+++ /dev/null
@@ -1,6 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
-set corner_file_list {
-	{{"Slow -6 1.2V 85 Model"} {four_line_to_sixteen_line_decimal_decoder_6_1200mv_85c_slow.vho four_line_to_sixteen_line_decimal_decoder_6_1200mv_85c_vhd_slow.sdo}}
-	{{"Slow -6 1.2V 0 Model"} {four_line_to_sixteen_line_decimal_decoder_6_1200mv_0c_slow.vho four_line_to_sixteen_line_decimal_decoder_6_1200mv_0c_vhd_slow.sdo}}
-	{{"Fast -M 1.2V 0 Model"} {four_line_to_sixteen_line_decimal_decoder_min_1200mv_0c_fast.vho four_line_to_sixteen_line_decimal_decoder_min_1200mv_0c_vhd_fast.sdo}}
-}
diff --git a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder.vho b/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder.vho
deleted file mode 100644
index f6690217..00000000
--- a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder.vho
+++ /dev/null
@@ -1,748 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/24/2019 22:11:45"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	four_line_to_sixteen_line_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	D : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic;
-	Y8 : OUT std_logic;
-	Y9 : OUT std_logic;
-	Y10 : OUT std_logic;
-	Y11 : OUT std_logic;
-	Y12 : OUT std_logic;
-	Y13 : OUT std_logic;
-	Y14 : OUT std_logic;
-	Y15 : OUT std_logic
-	);
-END four_line_to_sixteen_line_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_J4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_P7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_W1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_T7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_R6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_R9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y8	=>  Location: PIN_M5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y9	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y10	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y11	=>  Location: PIN_Y2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y12	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y13	=>  Location: PIN_W2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y14	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y15	=>  Location: PIN_P6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_T5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_Y1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_AB3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF four_line_to_sixteen_line_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL ww_Y8 : std_logic;
-SIGNAL ww_Y9 : std_logic;
-SIGNAL ww_Y10 : std_logic;
-SIGNAL ww_Y11 : std_logic;
-SIGNAL ww_Y12 : std_logic;
-SIGNAL ww_Y13 : std_logic;
-SIGNAL ww_Y14 : std_logic;
-SIGNAL ww_Y15 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \Y8~output_o\ : std_logic;
-SIGNAL \Y9~output_o\ : std_logic;
-SIGNAL \Y10~output_o\ : std_logic;
-SIGNAL \Y11~output_o\ : std_logic;
-SIGNAL \Y12~output_o\ : std_logic;
-SIGNAL \Y13~output_o\ : std_logic;
-SIGNAL \Y14~output_o\ : std_logic;
-SIGNAL \Y15~output_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \D~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \inst|15~0_combout\ : std_logic;
-SIGNAL \inst|15~1_combout\ : std_logic;
-SIGNAL \inst|15~2_combout\ : std_logic;
-SIGNAL \inst|15~3_combout\ : std_logic;
-SIGNAL \inst|15~4_combout\ : std_logic;
-SIGNAL \inst|15~5_combout\ : std_logic;
-SIGNAL \inst|15~6_combout\ : std_logic;
-SIGNAL \inst|15~7_combout\ : std_logic;
-SIGNAL \inst|15~8_combout\ : std_logic;
-SIGNAL \inst|15~9_combout\ : std_logic;
-SIGNAL \inst|15~10_combout\ : std_logic;
-SIGNAL \inst|15~11_combout\ : std_logic;
-SIGNAL \inst|15~12_combout\ : std_logic;
-SIGNAL \inst|15~13_combout\ : std_logic;
-SIGNAL \inst|15~14_combout\ : std_logic;
-SIGNAL \inst|15~15_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~15_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~14_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~13_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~12_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~11_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~10_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~9_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~8_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~6_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~5_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~4_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~3_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~2_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~1_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~0_combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-ww_D <= D;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-Y8 <= ww_Y8;
-Y9 <= ww_Y9;
-Y10 <= ww_Y10;
-Y11 <= ww_Y11;
-Y12 <= ww_Y12;
-Y13 <= ww_Y13;
-Y14 <= ww_Y14;
-Y15 <= ww_Y15;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\inst|ALT_INV_15~15_combout\ <= NOT \inst|15~15_combout\;
-\inst|ALT_INV_15~14_combout\ <= NOT \inst|15~14_combout\;
-\inst|ALT_INV_15~13_combout\ <= NOT \inst|15~13_combout\;
-\inst|ALT_INV_15~12_combout\ <= NOT \inst|15~12_combout\;
-\inst|ALT_INV_15~11_combout\ <= NOT \inst|15~11_combout\;
-\inst|ALT_INV_15~10_combout\ <= NOT \inst|15~10_combout\;
-\inst|ALT_INV_15~9_combout\ <= NOT \inst|15~9_combout\;
-\inst|ALT_INV_15~8_combout\ <= NOT \inst|15~8_combout\;
-\inst|ALT_INV_15~7_combout\ <= NOT \inst|15~7_combout\;
-\inst|ALT_INV_15~6_combout\ <= NOT \inst|15~6_combout\;
-\inst|ALT_INV_15~5_combout\ <= NOT \inst|15~5_combout\;
-\inst|ALT_INV_15~4_combout\ <= NOT \inst|15~4_combout\;
-\inst|ALT_INV_15~3_combout\ <= NOT \inst|15~3_combout\;
-\inst|ALT_INV_15~2_combout\ <= NOT \inst|15~2_combout\;
-\inst|ALT_INV_15~1_combout\ <= NOT \inst|15~1_combout\;
-\inst|ALT_INV_15~0_combout\ <= NOT \inst|15~0_combout\;
-
--- Location: IOOBUF_X0_Y11_N2
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~0_combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y21_N2
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~1_combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y5_N2
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~2_combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X0_Y7_N23
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~3_combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X0_Y2_N9
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~4_combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y8_N2
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~5_combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y3_N9
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~6_combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X1_Y0_N30
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~7_combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOOBUF_X0_Y11_N9
-\Y8~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~8_combout\,
-	devoe => ww_devoe,
-	o => \Y8~output_o\);
-
--- Location: IOOBUF_X0_Y12_N2
-\Y9~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~9_combout\,
-	devoe => ww_devoe,
-	o => \Y9~output_o\);
-
--- Location: IOOBUF_X0_Y8_N9
-\Y10~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~10_combout\,
-	devoe => ww_devoe,
-	o => \Y10~output_o\);
-
--- Location: IOOBUF_X0_Y6_N2
-\Y11~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~11_combout\,
-	devoe => ww_devoe,
-	o => \Y11~output_o\);
-
--- Location: IOOBUF_X0_Y8_N23
-\Y12~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~12_combout\,
-	devoe => ww_devoe,
-	o => \Y12~output_o\);
-
--- Location: IOOBUF_X0_Y7_N16
-\Y13~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~13_combout\,
-	devoe => ww_devoe,
-	o => \Y13~output_o\);
-
--- Location: IOOBUF_X0_Y12_N9
-\Y14~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~14_combout\,
-	devoe => ww_devoe,
-	o => \Y14~output_o\);
-
--- Location: IOOBUF_X0_Y4_N9
-\Y15~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~15_combout\,
-	devoe => ww_devoe,
-	o => \Y15~output_o\);
-
--- Location: IOIBUF_X0_Y6_N8
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y6_N22
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: IOIBUF_X0_Y3_N1
-\D~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_D,
-	o => \D~input_o\);
-
--- Location: IOIBUF_X7_Y0_N29
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: LCCOMB_X1_Y9_N24
-\inst|15~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~0_combout\ = (!\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000001",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~0_combout\);
-
--- Location: LCCOMB_X1_Y9_N2
-\inst|15~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~1_combout\ = (!\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~1_combout\);
-
--- Location: LCCOMB_X1_Y9_N4
-\inst|15~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~2_combout\ = (!\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~2_combout\);
-
--- Location: LCCOMB_X1_Y9_N22
-\inst|15~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~3_combout\ = (!\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000010000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~3_combout\);
-
--- Location: LCCOMB_X1_Y9_N16
-\inst|15~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~4_combout\ = (\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~4_combout\);
-
--- Location: LCCOMB_X1_Y9_N26
-\inst|15~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~5_combout\ = (\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000001000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~5_combout\);
-
--- Location: LCCOMB_X1_Y9_N28
-\inst|15~6\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~6_combout\ = (\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~6_combout\);
-
--- Location: LCCOMB_X1_Y9_N6
-\inst|15~7\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~7_combout\ = (\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000100000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~7_combout\);
-
--- Location: LCCOMB_X1_Y9_N0
-\inst|15~8\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~8_combout\ = (!\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~8_combout\);
-
--- Location: LCCOMB_X1_Y9_N10
-\inst|15~9\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~9_combout\ = (!\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~9_combout\);
-
--- Location: LCCOMB_X1_Y9_N20
-\inst|15~10\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~10_combout\ = (!\C~input_o\ & (\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~10_combout\);
-
--- Location: LCCOMB_X1_Y9_N14
-\inst|15~11\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~11_combout\ = (!\C~input_o\ & (\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0100000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~11_combout\);
-
--- Location: LCCOMB_X1_Y9_N8
-\inst|15~12\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~12_combout\ = (\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~12_combout\);
-
--- Location: LCCOMB_X1_Y9_N18
-\inst|15~13\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~13_combout\ = (\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0010000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~13_combout\);
-
--- Location: LCCOMB_X1_Y9_N12
-\inst|15~14\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~14_combout\ = (\C~input_o\ & (\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~14_combout\);
-
--- Location: LCCOMB_X1_Y9_N30
-\inst|15~15\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~15_combout\ = (\C~input_o\ & (\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1000000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~15_combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-
-ww_Y8 <= \Y8~output_o\;
-
-ww_Y9 <= \Y9~output_o\;
-
-ww_Y10 <= \Y10~output_o\;
-
-ww_Y11 <= \Y11~output_o\;
-
-ww_Y12 <= \Y12~output_o\;
-
-ww_Y13 <= \Y13~output_o\;
-
-ww_Y14 <= \Y14~output_o\;
-
-ww_Y15 <= \Y15~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_0c_slow.vho b/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_0c_slow.vho
deleted file mode 100644
index f6690217..00000000
--- a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_0c_slow.vho
+++ /dev/null
@@ -1,748 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/24/2019 22:11:45"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	four_line_to_sixteen_line_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	D : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic;
-	Y8 : OUT std_logic;
-	Y9 : OUT std_logic;
-	Y10 : OUT std_logic;
-	Y11 : OUT std_logic;
-	Y12 : OUT std_logic;
-	Y13 : OUT std_logic;
-	Y14 : OUT std_logic;
-	Y15 : OUT std_logic
-	);
-END four_line_to_sixteen_line_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_J4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_P7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_W1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_T7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_R6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_R9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y8	=>  Location: PIN_M5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y9	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y10	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y11	=>  Location: PIN_Y2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y12	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y13	=>  Location: PIN_W2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y14	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y15	=>  Location: PIN_P6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_T5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_Y1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_AB3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF four_line_to_sixteen_line_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL ww_Y8 : std_logic;
-SIGNAL ww_Y9 : std_logic;
-SIGNAL ww_Y10 : std_logic;
-SIGNAL ww_Y11 : std_logic;
-SIGNAL ww_Y12 : std_logic;
-SIGNAL ww_Y13 : std_logic;
-SIGNAL ww_Y14 : std_logic;
-SIGNAL ww_Y15 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \Y8~output_o\ : std_logic;
-SIGNAL \Y9~output_o\ : std_logic;
-SIGNAL \Y10~output_o\ : std_logic;
-SIGNAL \Y11~output_o\ : std_logic;
-SIGNAL \Y12~output_o\ : std_logic;
-SIGNAL \Y13~output_o\ : std_logic;
-SIGNAL \Y14~output_o\ : std_logic;
-SIGNAL \Y15~output_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \D~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \inst|15~0_combout\ : std_logic;
-SIGNAL \inst|15~1_combout\ : std_logic;
-SIGNAL \inst|15~2_combout\ : std_logic;
-SIGNAL \inst|15~3_combout\ : std_logic;
-SIGNAL \inst|15~4_combout\ : std_logic;
-SIGNAL \inst|15~5_combout\ : std_logic;
-SIGNAL \inst|15~6_combout\ : std_logic;
-SIGNAL \inst|15~7_combout\ : std_logic;
-SIGNAL \inst|15~8_combout\ : std_logic;
-SIGNAL \inst|15~9_combout\ : std_logic;
-SIGNAL \inst|15~10_combout\ : std_logic;
-SIGNAL \inst|15~11_combout\ : std_logic;
-SIGNAL \inst|15~12_combout\ : std_logic;
-SIGNAL \inst|15~13_combout\ : std_logic;
-SIGNAL \inst|15~14_combout\ : std_logic;
-SIGNAL \inst|15~15_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~15_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~14_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~13_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~12_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~11_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~10_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~9_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~8_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~6_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~5_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~4_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~3_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~2_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~1_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~0_combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-ww_D <= D;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-Y8 <= ww_Y8;
-Y9 <= ww_Y9;
-Y10 <= ww_Y10;
-Y11 <= ww_Y11;
-Y12 <= ww_Y12;
-Y13 <= ww_Y13;
-Y14 <= ww_Y14;
-Y15 <= ww_Y15;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\inst|ALT_INV_15~15_combout\ <= NOT \inst|15~15_combout\;
-\inst|ALT_INV_15~14_combout\ <= NOT \inst|15~14_combout\;
-\inst|ALT_INV_15~13_combout\ <= NOT \inst|15~13_combout\;
-\inst|ALT_INV_15~12_combout\ <= NOT \inst|15~12_combout\;
-\inst|ALT_INV_15~11_combout\ <= NOT \inst|15~11_combout\;
-\inst|ALT_INV_15~10_combout\ <= NOT \inst|15~10_combout\;
-\inst|ALT_INV_15~9_combout\ <= NOT \inst|15~9_combout\;
-\inst|ALT_INV_15~8_combout\ <= NOT \inst|15~8_combout\;
-\inst|ALT_INV_15~7_combout\ <= NOT \inst|15~7_combout\;
-\inst|ALT_INV_15~6_combout\ <= NOT \inst|15~6_combout\;
-\inst|ALT_INV_15~5_combout\ <= NOT \inst|15~5_combout\;
-\inst|ALT_INV_15~4_combout\ <= NOT \inst|15~4_combout\;
-\inst|ALT_INV_15~3_combout\ <= NOT \inst|15~3_combout\;
-\inst|ALT_INV_15~2_combout\ <= NOT \inst|15~2_combout\;
-\inst|ALT_INV_15~1_combout\ <= NOT \inst|15~1_combout\;
-\inst|ALT_INV_15~0_combout\ <= NOT \inst|15~0_combout\;
-
--- Location: IOOBUF_X0_Y11_N2
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~0_combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y21_N2
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~1_combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y5_N2
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~2_combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X0_Y7_N23
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~3_combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X0_Y2_N9
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~4_combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y8_N2
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~5_combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y3_N9
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~6_combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X1_Y0_N30
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~7_combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOOBUF_X0_Y11_N9
-\Y8~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~8_combout\,
-	devoe => ww_devoe,
-	o => \Y8~output_o\);
-
--- Location: IOOBUF_X0_Y12_N2
-\Y9~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~9_combout\,
-	devoe => ww_devoe,
-	o => \Y9~output_o\);
-
--- Location: IOOBUF_X0_Y8_N9
-\Y10~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~10_combout\,
-	devoe => ww_devoe,
-	o => \Y10~output_o\);
-
--- Location: IOOBUF_X0_Y6_N2
-\Y11~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~11_combout\,
-	devoe => ww_devoe,
-	o => \Y11~output_o\);
-
--- Location: IOOBUF_X0_Y8_N23
-\Y12~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~12_combout\,
-	devoe => ww_devoe,
-	o => \Y12~output_o\);
-
--- Location: IOOBUF_X0_Y7_N16
-\Y13~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~13_combout\,
-	devoe => ww_devoe,
-	o => \Y13~output_o\);
-
--- Location: IOOBUF_X0_Y12_N9
-\Y14~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~14_combout\,
-	devoe => ww_devoe,
-	o => \Y14~output_o\);
-
--- Location: IOOBUF_X0_Y4_N9
-\Y15~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~15_combout\,
-	devoe => ww_devoe,
-	o => \Y15~output_o\);
-
--- Location: IOIBUF_X0_Y6_N8
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y6_N22
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: IOIBUF_X0_Y3_N1
-\D~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_D,
-	o => \D~input_o\);
-
--- Location: IOIBUF_X7_Y0_N29
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: LCCOMB_X1_Y9_N24
-\inst|15~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~0_combout\ = (!\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000001",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~0_combout\);
-
--- Location: LCCOMB_X1_Y9_N2
-\inst|15~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~1_combout\ = (!\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~1_combout\);
-
--- Location: LCCOMB_X1_Y9_N4
-\inst|15~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~2_combout\ = (!\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~2_combout\);
-
--- Location: LCCOMB_X1_Y9_N22
-\inst|15~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~3_combout\ = (!\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000010000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~3_combout\);
-
--- Location: LCCOMB_X1_Y9_N16
-\inst|15~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~4_combout\ = (\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~4_combout\);
-
--- Location: LCCOMB_X1_Y9_N26
-\inst|15~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~5_combout\ = (\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000001000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~5_combout\);
-
--- Location: LCCOMB_X1_Y9_N28
-\inst|15~6\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~6_combout\ = (\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~6_combout\);
-
--- Location: LCCOMB_X1_Y9_N6
-\inst|15~7\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~7_combout\ = (\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000100000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~7_combout\);
-
--- Location: LCCOMB_X1_Y9_N0
-\inst|15~8\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~8_combout\ = (!\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~8_combout\);
-
--- Location: LCCOMB_X1_Y9_N10
-\inst|15~9\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~9_combout\ = (!\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~9_combout\);
-
--- Location: LCCOMB_X1_Y9_N20
-\inst|15~10\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~10_combout\ = (!\C~input_o\ & (\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~10_combout\);
-
--- Location: LCCOMB_X1_Y9_N14
-\inst|15~11\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~11_combout\ = (!\C~input_o\ & (\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0100000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~11_combout\);
-
--- Location: LCCOMB_X1_Y9_N8
-\inst|15~12\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~12_combout\ = (\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~12_combout\);
-
--- Location: LCCOMB_X1_Y9_N18
-\inst|15~13\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~13_combout\ = (\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0010000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~13_combout\);
-
--- Location: LCCOMB_X1_Y9_N12
-\inst|15~14\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~14_combout\ = (\C~input_o\ & (\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~14_combout\);
-
--- Location: LCCOMB_X1_Y9_N30
-\inst|15~15\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~15_combout\ = (\C~input_o\ & (\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1000000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~15_combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-
-ww_Y8 <= \Y8~output_o\;
-
-ww_Y9 <= \Y9~output_o\;
-
-ww_Y10 <= \Y10~output_o\;
-
-ww_Y11 <= \Y11~output_o\;
-
-ww_Y12 <= \Y12~output_o\;
-
-ww_Y13 <= \Y13~output_o\;
-
-ww_Y14 <= \Y14~output_o\;
-
-ww_Y15 <= \Y15~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_0c_vhd_slow.sdo b/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_0c_vhd_slow.sdo
deleted file mode 100644
index 042e812d..00000000
--- a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_0c_vhd_slow.sdo
+++ /dev/null
@@ -1,491 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "four_line_to_sixteen_line_decimal_decoder")
-  (DATE "10/24/2019 22:11:45")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y0\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (550:550:550) (547:547:547))
-        (IOPATH i o (2095:2095:2095) (2137:2137:2137))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y1\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (918:918:918) (913:913:913))
-        (IOPATH i o (2095:2095:2095) (2137:2137:2137))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y2\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (555:555:555) (554:554:554))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y3\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (555:555:555) (555:555:555))
-        (IOPATH i o (2244:2244:2244) (2256:2256:2256))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y4\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (823:823:823) (822:822:822))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y5\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (553:553:553) (560:560:560))
-        (IOPATH i o (2244:2244:2244) (2256:2256:2256))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y6\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (859:859:859) (846:846:846))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y7\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (894:894:894) (910:910:910))
-        (IOPATH i o (2009:2009:2009) (2060:2060:2060))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y8\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (545:545:545) (549:549:549))
-        (IOPATH i o (3517:3517:3517) (3416:3416:3416))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y9\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (566:566:566) (559:559:559))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y10\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (637:637:637) (674:674:674))
-        (IOPATH i o (2105:2105:2105) (2147:2147:2147))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y11\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (550:550:550) (550:550:550))
-        (IOPATH i o (2254:2254:2254) (2266:2266:2266))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y12\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (523:523:523) (540:540:540))
-        (IOPATH i o (2214:2214:2214) (2226:2226:2226))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y13\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (669:669:669) (713:713:713))
-        (IOPATH i o (2254:2254:2254) (2266:2266:2266))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y14\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (532:532:532) (538:538:538))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y15\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (686:686:686) (716:716:716))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\C\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (775:775:775) (936:936:936))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\B\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\D\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\A\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (739:739:739) (902:902:902))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2516:2516:2516) (2789:2789:2789))
-        (PORT datab (2535:2535:2535) (2787:2787:2787))
-        (PORT datac (2714:2714:2714) (2965:2965:2965))
-        (PORT datad (2834:2834:2834) (3055:3055:3055))
-        (IOPATH dataa combout (309:309:309) (326:326:326))
-        (IOPATH datab combout (309:309:309) (328:328:328))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~1\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2537:2537:2537) (2807:2807:2807))
-        (PORT datab (2556:2556:2556) (2802:2802:2802))
-        (PORT datac (2697:2697:2697) (2945:2945:2945))
-        (PORT datad (2830:2830:2830) (3047:3047:3047))
-        (IOPATH dataa combout (265:265:265) (273:273:273))
-        (IOPATH datab combout (265:265:265) (275:275:275))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~2\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2536:2536:2536) (2807:2807:2807))
-        (PORT datab (2555:2555:2555) (2804:2804:2804))
-        (PORT datac (2699:2699:2699) (2948:2948:2948))
-        (PORT datad (2829:2829:2829) (3044:3044:3044))
-        (IOPATH dataa combout (329:329:329) (332:332:332))
-        (IOPATH datab combout (319:319:319) (307:307:307))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~3\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2515:2515:2515) (2791:2791:2791))
-        (PORT datab (2535:2535:2535) (2790:2790:2790))
-        (PORT datac (2713:2713:2713) (2965:2965:2965))
-        (PORT datad (2833:2833:2833) (3054:3054:3054))
-        (IOPATH dataa combout (287:287:287) (280:280:280))
-        (IOPATH datab combout (273:273:273) (275:275:275))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~4\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2530:2530:2530) (2797:2797:2797))
-        (PORT datab (2550:2550:2550) (2795:2795:2795))
-        (PORT datac (2711:2711:2711) (2961:2961:2961))
-        (PORT datad (2832:2832:2832) (3055:3055:3055))
-        (IOPATH dataa combout (318:318:318) (307:307:307))
-        (IOPATH datab combout (336:336:336) (337:337:337))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2517:2517:2517) (2781:2781:2781))
-        (PORT datab (2536:2536:2536) (2778:2778:2778))
-        (PORT datac (2715:2715:2715) (2966:2966:2966))
-        (PORT datad (2836:2836:2836) (3052:3052:3052))
-        (IOPATH dataa combout (272:272:272) (269:269:269))
-        (IOPATH datab combout (295:295:295) (285:285:285))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~6\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2517:2517:2517) (2782:2782:2782))
-        (PORT datab (2537:2537:2537) (2779:2779:2779))
-        (PORT datac (2715:2715:2715) (2966:2966:2966))
-        (PORT datad (2837:2837:2837) (3052:3052:3052))
-        (IOPATH dataa combout (300:300:300) (323:323:323))
-        (IOPATH datab combout (306:306:306) (324:324:324))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~7\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2536:2536:2536) (2807:2807:2807))
-        (PORT datab (2554:2554:2554) (2803:2803:2803))
-        (PORT datac (2701:2701:2701) (2951:2951:2951))
-        (PORT datad (2828:2828:2828) (3047:3047:3047))
-        (IOPATH dataa combout (265:265:265) (269:269:269))
-        (IOPATH datab combout (265:265:265) (275:275:275))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~8\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2538:2538:2538) (2808:2808:2808))
-        (PORT datab (2557:2557:2557) (2802:2802:2802))
-        (PORT datac (2695:2695:2695) (2942:2942:2942))
-        (PORT datad (2831:2831:2831) (3048:3048:3048))
-        (IOPATH dataa combout (299:299:299) (304:304:304))
-        (IOPATH datab combout (300:300:300) (312:312:312))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~9\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2527:2527:2527) (2804:2804:2804))
-        (PORT datab (2546:2546:2546) (2800:2800:2800))
-        (PORT datac (2705:2705:2705) (2954:2954:2954))
-        (PORT datad (2824:2824:2824) (3049:3049:3049))
-        (IOPATH dataa combout (267:267:267) (269:269:269))
-        (IOPATH datab combout (267:267:267) (275:275:275))
-        (IOPATH datac combout (218:218:218) (216:216:216))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~10\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2527:2527:2527) (2790:2790:2790))
-        (PORT datab (2546:2546:2546) (2788:2788:2788))
-        (PORT datac (2712:2712:2712) (2964:2964:2964))
-        (PORT datad (2834:2834:2834) (3055:3055:3055))
-        (IOPATH dataa combout (318:318:318) (327:327:327))
-        (IOPATH datab combout (308:308:308) (281:281:281))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~11\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2530:2530:2530) (2797:2797:2797))
-        (PORT datab (2550:2550:2550) (2795:2795:2795))
-        (PORT datac (2709:2709:2709) (2958:2958:2958))
-        (PORT datad (2825:2825:2825) (3044:3044:3044))
-        (IOPATH dataa combout (287:287:287) (289:289:289))
-        (IOPATH datab combout (275:275:275) (275:275:275))
-        (IOPATH datac combout (218:218:218) (216:216:216))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~12\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2535:2535:2535) (2806:2806:2806))
-        (PORT datab (2554:2554:2554) (2803:2803:2803))
-        (PORT datac (2703:2703:2703) (2954:2954:2954))
-        (PORT datad (2828:2828:2828) (3050:3050:3050))
-        (IOPATH dataa combout (307:307:307) (280:280:280))
-        (IOPATH datab combout (325:325:325) (332:332:332))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~13\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2528:2528:2528) (2788:2788:2788))
-        (PORT datab (2548:2548:2548) (2786:2786:2786))
-        (PORT datac (2712:2712:2712) (2963:2963:2963))
-        (PORT datad (2833:2833:2833) (3054:3054:3054))
-        (IOPATH dataa combout (273:273:273) (269:269:269))
-        (IOPATH datab combout (295:295:295) (294:294:294))
-        (IOPATH datac combout (218:218:218) (216:216:216))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~14\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2528:2528:2528) (2803:2803:2803))
-        (PORT datab (2548:2548:2548) (2799:2799:2799))
-        (PORT datac (2707:2707:2707) (2956:2956:2956))
-        (PORT datad (2826:2826:2826) (3047:3047:3047))
-        (IOPATH dataa combout (290:290:290) (306:306:306))
-        (IOPATH datab combout (295:295:295) (300:300:300))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~15\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2518:2518:2518) (2783:2783:2783))
-        (PORT datab (2538:2538:2538) (2779:2779:2779))
-        (PORT datac (2716:2716:2716) (2967:2967:2967))
-        (PORT datad (2837:2837:2837) (3053:3053:3053))
-        (IOPATH dataa combout (265:265:265) (269:269:269))
-        (IOPATH datab combout (265:265:265) (275:275:275))
-        (IOPATH datac combout (218:218:218) (216:216:216))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_85c_slow.vho b/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_85c_slow.vho
deleted file mode 100644
index f6690217..00000000
--- a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_85c_slow.vho
+++ /dev/null
@@ -1,748 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/24/2019 22:11:45"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	four_line_to_sixteen_line_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	D : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic;
-	Y8 : OUT std_logic;
-	Y9 : OUT std_logic;
-	Y10 : OUT std_logic;
-	Y11 : OUT std_logic;
-	Y12 : OUT std_logic;
-	Y13 : OUT std_logic;
-	Y14 : OUT std_logic;
-	Y15 : OUT std_logic
-	);
-END four_line_to_sixteen_line_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_J4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_P7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_W1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_T7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_R6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_R9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y8	=>  Location: PIN_M5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y9	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y10	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y11	=>  Location: PIN_Y2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y12	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y13	=>  Location: PIN_W2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y14	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y15	=>  Location: PIN_P6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_T5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_Y1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_AB3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF four_line_to_sixteen_line_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL ww_Y8 : std_logic;
-SIGNAL ww_Y9 : std_logic;
-SIGNAL ww_Y10 : std_logic;
-SIGNAL ww_Y11 : std_logic;
-SIGNAL ww_Y12 : std_logic;
-SIGNAL ww_Y13 : std_logic;
-SIGNAL ww_Y14 : std_logic;
-SIGNAL ww_Y15 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \Y8~output_o\ : std_logic;
-SIGNAL \Y9~output_o\ : std_logic;
-SIGNAL \Y10~output_o\ : std_logic;
-SIGNAL \Y11~output_o\ : std_logic;
-SIGNAL \Y12~output_o\ : std_logic;
-SIGNAL \Y13~output_o\ : std_logic;
-SIGNAL \Y14~output_o\ : std_logic;
-SIGNAL \Y15~output_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \D~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \inst|15~0_combout\ : std_logic;
-SIGNAL \inst|15~1_combout\ : std_logic;
-SIGNAL \inst|15~2_combout\ : std_logic;
-SIGNAL \inst|15~3_combout\ : std_logic;
-SIGNAL \inst|15~4_combout\ : std_logic;
-SIGNAL \inst|15~5_combout\ : std_logic;
-SIGNAL \inst|15~6_combout\ : std_logic;
-SIGNAL \inst|15~7_combout\ : std_logic;
-SIGNAL \inst|15~8_combout\ : std_logic;
-SIGNAL \inst|15~9_combout\ : std_logic;
-SIGNAL \inst|15~10_combout\ : std_logic;
-SIGNAL \inst|15~11_combout\ : std_logic;
-SIGNAL \inst|15~12_combout\ : std_logic;
-SIGNAL \inst|15~13_combout\ : std_logic;
-SIGNAL \inst|15~14_combout\ : std_logic;
-SIGNAL \inst|15~15_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~15_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~14_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~13_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~12_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~11_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~10_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~9_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~8_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~6_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~5_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~4_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~3_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~2_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~1_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~0_combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-ww_D <= D;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-Y8 <= ww_Y8;
-Y9 <= ww_Y9;
-Y10 <= ww_Y10;
-Y11 <= ww_Y11;
-Y12 <= ww_Y12;
-Y13 <= ww_Y13;
-Y14 <= ww_Y14;
-Y15 <= ww_Y15;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\inst|ALT_INV_15~15_combout\ <= NOT \inst|15~15_combout\;
-\inst|ALT_INV_15~14_combout\ <= NOT \inst|15~14_combout\;
-\inst|ALT_INV_15~13_combout\ <= NOT \inst|15~13_combout\;
-\inst|ALT_INV_15~12_combout\ <= NOT \inst|15~12_combout\;
-\inst|ALT_INV_15~11_combout\ <= NOT \inst|15~11_combout\;
-\inst|ALT_INV_15~10_combout\ <= NOT \inst|15~10_combout\;
-\inst|ALT_INV_15~9_combout\ <= NOT \inst|15~9_combout\;
-\inst|ALT_INV_15~8_combout\ <= NOT \inst|15~8_combout\;
-\inst|ALT_INV_15~7_combout\ <= NOT \inst|15~7_combout\;
-\inst|ALT_INV_15~6_combout\ <= NOT \inst|15~6_combout\;
-\inst|ALT_INV_15~5_combout\ <= NOT \inst|15~5_combout\;
-\inst|ALT_INV_15~4_combout\ <= NOT \inst|15~4_combout\;
-\inst|ALT_INV_15~3_combout\ <= NOT \inst|15~3_combout\;
-\inst|ALT_INV_15~2_combout\ <= NOT \inst|15~2_combout\;
-\inst|ALT_INV_15~1_combout\ <= NOT \inst|15~1_combout\;
-\inst|ALT_INV_15~0_combout\ <= NOT \inst|15~0_combout\;
-
--- Location: IOOBUF_X0_Y11_N2
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~0_combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y21_N2
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~1_combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y5_N2
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~2_combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X0_Y7_N23
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~3_combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X0_Y2_N9
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~4_combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y8_N2
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~5_combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y3_N9
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~6_combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X1_Y0_N30
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~7_combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOOBUF_X0_Y11_N9
-\Y8~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~8_combout\,
-	devoe => ww_devoe,
-	o => \Y8~output_o\);
-
--- Location: IOOBUF_X0_Y12_N2
-\Y9~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~9_combout\,
-	devoe => ww_devoe,
-	o => \Y9~output_o\);
-
--- Location: IOOBUF_X0_Y8_N9
-\Y10~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~10_combout\,
-	devoe => ww_devoe,
-	o => \Y10~output_o\);
-
--- Location: IOOBUF_X0_Y6_N2
-\Y11~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~11_combout\,
-	devoe => ww_devoe,
-	o => \Y11~output_o\);
-
--- Location: IOOBUF_X0_Y8_N23
-\Y12~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~12_combout\,
-	devoe => ww_devoe,
-	o => \Y12~output_o\);
-
--- Location: IOOBUF_X0_Y7_N16
-\Y13~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~13_combout\,
-	devoe => ww_devoe,
-	o => \Y13~output_o\);
-
--- Location: IOOBUF_X0_Y12_N9
-\Y14~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~14_combout\,
-	devoe => ww_devoe,
-	o => \Y14~output_o\);
-
--- Location: IOOBUF_X0_Y4_N9
-\Y15~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~15_combout\,
-	devoe => ww_devoe,
-	o => \Y15~output_o\);
-
--- Location: IOIBUF_X0_Y6_N8
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y6_N22
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: IOIBUF_X0_Y3_N1
-\D~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_D,
-	o => \D~input_o\);
-
--- Location: IOIBUF_X7_Y0_N29
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: LCCOMB_X1_Y9_N24
-\inst|15~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~0_combout\ = (!\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000001",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~0_combout\);
-
--- Location: LCCOMB_X1_Y9_N2
-\inst|15~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~1_combout\ = (!\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~1_combout\);
-
--- Location: LCCOMB_X1_Y9_N4
-\inst|15~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~2_combout\ = (!\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~2_combout\);
-
--- Location: LCCOMB_X1_Y9_N22
-\inst|15~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~3_combout\ = (!\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000010000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~3_combout\);
-
--- Location: LCCOMB_X1_Y9_N16
-\inst|15~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~4_combout\ = (\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~4_combout\);
-
--- Location: LCCOMB_X1_Y9_N26
-\inst|15~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~5_combout\ = (\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000001000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~5_combout\);
-
--- Location: LCCOMB_X1_Y9_N28
-\inst|15~6\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~6_combout\ = (\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~6_combout\);
-
--- Location: LCCOMB_X1_Y9_N6
-\inst|15~7\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~7_combout\ = (\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000100000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~7_combout\);
-
--- Location: LCCOMB_X1_Y9_N0
-\inst|15~8\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~8_combout\ = (!\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~8_combout\);
-
--- Location: LCCOMB_X1_Y9_N10
-\inst|15~9\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~9_combout\ = (!\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~9_combout\);
-
--- Location: LCCOMB_X1_Y9_N20
-\inst|15~10\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~10_combout\ = (!\C~input_o\ & (\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~10_combout\);
-
--- Location: LCCOMB_X1_Y9_N14
-\inst|15~11\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~11_combout\ = (!\C~input_o\ & (\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0100000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~11_combout\);
-
--- Location: LCCOMB_X1_Y9_N8
-\inst|15~12\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~12_combout\ = (\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~12_combout\);
-
--- Location: LCCOMB_X1_Y9_N18
-\inst|15~13\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~13_combout\ = (\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0010000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~13_combout\);
-
--- Location: LCCOMB_X1_Y9_N12
-\inst|15~14\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~14_combout\ = (\C~input_o\ & (\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~14_combout\);
-
--- Location: LCCOMB_X1_Y9_N30
-\inst|15~15\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~15_combout\ = (\C~input_o\ & (\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1000000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~15_combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-
-ww_Y8 <= \Y8~output_o\;
-
-ww_Y9 <= \Y9~output_o\;
-
-ww_Y10 <= \Y10~output_o\;
-
-ww_Y11 <= \Y11~output_o\;
-
-ww_Y12 <= \Y12~output_o\;
-
-ww_Y13 <= \Y13~output_o\;
-
-ww_Y14 <= \Y14~output_o\;
-
-ww_Y15 <= \Y15~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_85c_vhd_slow.sdo b/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_85c_vhd_slow.sdo
deleted file mode 100644
index 2856a0c1..00000000
--- a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_6_1200mv_85c_vhd_slow.sdo
+++ /dev/null
@@ -1,491 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "four_line_to_sixteen_line_decimal_decoder")
-  (DATE "10/24/2019 22:11:45")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y0\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (605:605:605) (595:595:595))
-        (IOPATH i o (2095:2095:2095) (2137:2137:2137))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y1\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1027:1027:1027) (989:989:989))
-        (IOPATH i o (2095:2095:2095) (2137:2137:2137))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y2\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (631:631:631) (604:604:604))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y3\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (612:612:612) (606:606:606))
-        (IOPATH i o (2244:2244:2244) (2256:2256:2256))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y4\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (913:913:913) (896:896:896))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y5\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (623:623:623) (613:613:613))
-        (IOPATH i o (2244:2244:2244) (2256:2256:2256))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y6\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (954:954:954) (924:924:924))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y7\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (964:964:964) (981:981:981))
-        (IOPATH i o (2009:2009:2009) (2060:2060:2060))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y8\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (601:601:601) (599:599:599))
-        (IOPATH i o (3517:3517:3517) (3416:3416:3416))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y9\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (638:638:638) (610:610:610))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y10\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (716:716:716) (721:721:721))
-        (IOPATH i o (2105:2105:2105) (2147:2147:2147))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y11\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (623:623:623) (600:600:600))
-        (IOPATH i o (2254:2254:2254) (2266:2266:2266))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y12\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (589:589:589) (590:590:590))
-        (IOPATH i o (2214:2214:2214) (2226:2226:2226))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y13\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (758:758:758) (764:764:764))
-        (IOPATH i o (2254:2254:2254) (2266:2266:2266))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y14\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (606:606:606) (586:586:586))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y15\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (750:750:750) (766:766:766))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\C\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (775:775:775) (936:936:936))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\B\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\D\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\A\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (739:739:739) (902:902:902))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2919:2919:2919) (3262:3262:3262))
-        (PORT datab (2955:2955:2955) (3275:3275:3275))
-        (PORT datac (3158:3158:3158) (3487:3487:3487))
-        (PORT datad (3239:3239:3239) (3556:3556:3556))
-        (IOPATH dataa combout (350:350:350) (366:366:366))
-        (IOPATH datab combout (350:350:350) (368:368:368))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~1\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2942:2942:2942) (3278:3278:3278))
-        (PORT datab (2979:2979:2979) (3291:3291:3291))
-        (PORT datac (3140:3140:3140) (3467:3467:3467))
-        (PORT datad (3236:3236:3236) (3549:3549:3549))
-        (IOPATH dataa combout (300:300:300) (307:307:307))
-        (IOPATH datab combout (300:300:300) (310:310:310))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~2\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2941:2941:2941) (3278:3278:3278))
-        (PORT datab (2978:2978:2978) (3292:3292:3292))
-        (PORT datac (3142:3142:3142) (3470:3470:3470))
-        (PORT datad (3235:3235:3235) (3546:3546:3546))
-        (IOPATH dataa combout (371:371:371) (376:376:376))
-        (IOPATH datab combout (355:355:355) (349:349:349))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~3\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2918:2918:2918) (3264:3264:3264))
-        (PORT datab (2954:2954:2954) (3278:3278:3278))
-        (PORT datac (3158:3158:3158) (3487:3487:3487))
-        (PORT datad (3238:3238:3238) (3556:3556:3556))
-        (IOPATH dataa combout (325:325:325) (320:320:320))
-        (IOPATH datab combout (304:304:304) (308:308:308))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~4\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2934:2934:2934) (3269:3269:3269))
-        (PORT datab (2972:2972:2972) (3283:3283:3283))
-        (PORT datac (3155:3155:3155) (3483:3483:3483))
-        (PORT datad (3240:3240:3240) (3557:3557:3557))
-        (IOPATH dataa combout (354:354:354) (349:349:349))
-        (IOPATH datab combout (381:381:381) (380:380:380))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2920:2920:2920) (3254:3254:3254))
-        (PORT datab (2956:2956:2956) (3267:3267:3267))
-        (PORT datac (3159:3159:3159) (3488:3488:3488))
-        (PORT datad (3244:3244:3244) (3553:3553:3553))
-        (IOPATH dataa combout (303:303:303) (299:299:299))
-        (IOPATH datab combout (336:336:336) (325:325:325))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~6\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2921:2921:2921) (3255:3255:3255))
-        (PORT datab (2956:2956:2956) (3268:3268:3268))
-        (PORT datac (3160:3160:3160) (3488:3488:3488))
-        (PORT datad (3245:3245:3245) (3554:3554:3554))
-        (IOPATH dataa combout (339:339:339) (367:367:367))
-        (IOPATH datab combout (344:344:344) (369:369:369))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~7\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2940:2940:2940) (3277:3277:3277))
-        (PORT datab (2977:2977:2977) (3291:3291:3291))
-        (PORT datac (3144:3144:3144) (3472:3472:3472))
-        (PORT datad (3235:3235:3235) (3549:3549:3549))
-        (IOPATH dataa combout (300:300:300) (308:308:308))
-        (IOPATH datab combout (300:300:300) (311:311:311))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~8\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2943:2943:2943) (3278:3278:3278))
-        (PORT datab (2979:2979:2979) (3291:3291:3291))
-        (PORT datac (3138:3138:3138) (3464:3464:3464))
-        (PORT datad (3237:3237:3237) (3550:3550:3550))
-        (IOPATH dataa combout (337:337:337) (338:338:338))
-        (IOPATH datab combout (337:337:337) (348:348:348))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~9\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2931:2931:2931) (3275:3275:3275))
-        (PORT datab (2968:2968:2968) (3289:3289:3289))
-        (PORT datac (3149:3149:3149) (3476:3476:3476))
-        (PORT datad (3229:3229:3229) (3554:3554:3554))
-        (IOPATH dataa combout (301:301:301) (299:299:299))
-        (IOPATH datab combout (300:300:300) (308:308:308))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~10\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2931:2931:2931) (3262:3262:3262))
-        (PORT datab (2968:2968:2968) (3276:3276:3276))
-        (PORT datac (3157:3157:3157) (3486:3486:3486))
-        (PORT datad (3242:3242:3242) (3557:3557:3557))
-        (IOPATH dataa combout (356:356:356) (368:368:368))
-        (IOPATH datab combout (342:342:342) (318:318:318))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~11\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2935:2935:2935) (3269:3269:3269))
-        (PORT datab (2972:2972:2972) (3283:3283:3283))
-        (PORT datac (3153:3153:3153) (3480:3480:3480))
-        (PORT datad (3231:3231:3231) (3556:3556:3556))
-        (IOPATH dataa combout (324:324:324) (328:328:328))
-        (IOPATH datab combout (306:306:306) (308:308:308))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~12\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2939:2939:2939) (3277:3277:3277))
-        (PORT datab (2976:2976:2976) (3291:3291:3291))
-        (PORT datac (3147:3147:3147) (3475:3475:3475))
-        (PORT datad (3234:3234:3234) (3552:3552:3552))
-        (IOPATH dataa combout (341:341:341) (319:319:319))
-        (IOPATH datab combout (365:365:365) (373:373:373))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~13\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2933:2933:2933) (3260:3260:3260))
-        (PORT datab (2970:2970:2970) (3275:3275:3275))
-        (PORT datac (3156:3156:3156) (3484:3484:3484))
-        (PORT datad (3241:3241:3241) (3556:3556:3556))
-        (IOPATH dataa combout (304:304:304) (299:299:299))
-        (IOPATH datab combout (333:333:333) (332:332:332))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~14\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2933:2933:2933) (3274:3274:3274))
-        (PORT datab (2970:2970:2970) (3288:3288:3288))
-        (PORT datac (3151:3151:3151) (3478:3478:3478))
-        (PORT datad (3232:3232:3232) (3553:3553:3553))
-        (IOPATH dataa combout (327:327:327) (347:347:347))
-        (IOPATH datab combout (331:331:331) (342:342:342))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~15\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2922:2922:2922) (3255:3255:3255))
-        (PORT datab (2957:2957:2957) (3268:3268:3268))
-        (PORT datac (3161:3161:3161) (3489:3489:3489))
-        (PORT datad (3246:3246:3246) (3554:3554:3554))
-        (IOPATH dataa combout (300:300:300) (307:307:307))
-        (IOPATH datab combout (300:300:300) (308:308:308))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_min_1200mv_0c_fast.vho b/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_min_1200mv_0c_fast.vho
deleted file mode 100644
index f6690217..00000000
--- a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_min_1200mv_0c_fast.vho
+++ /dev/null
@@ -1,748 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/24/2019 22:11:45"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	four_line_to_sixteen_line_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	D : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic;
-	Y8 : OUT std_logic;
-	Y9 : OUT std_logic;
-	Y10 : OUT std_logic;
-	Y11 : OUT std_logic;
-	Y12 : OUT std_logic;
-	Y13 : OUT std_logic;
-	Y14 : OUT std_logic;
-	Y15 : OUT std_logic
-	);
-END four_line_to_sixteen_line_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_J4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_P7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_W1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_T7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_R6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_R9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y8	=>  Location: PIN_M5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y9	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y10	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y11	=>  Location: PIN_Y2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y12	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y13	=>  Location: PIN_W2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y14	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y15	=>  Location: PIN_P6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_T5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_Y1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_AB3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF four_line_to_sixteen_line_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL ww_Y8 : std_logic;
-SIGNAL ww_Y9 : std_logic;
-SIGNAL ww_Y10 : std_logic;
-SIGNAL ww_Y11 : std_logic;
-SIGNAL ww_Y12 : std_logic;
-SIGNAL ww_Y13 : std_logic;
-SIGNAL ww_Y14 : std_logic;
-SIGNAL ww_Y15 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \Y8~output_o\ : std_logic;
-SIGNAL \Y9~output_o\ : std_logic;
-SIGNAL \Y10~output_o\ : std_logic;
-SIGNAL \Y11~output_o\ : std_logic;
-SIGNAL \Y12~output_o\ : std_logic;
-SIGNAL \Y13~output_o\ : std_logic;
-SIGNAL \Y14~output_o\ : std_logic;
-SIGNAL \Y15~output_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \D~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \inst|15~0_combout\ : std_logic;
-SIGNAL \inst|15~1_combout\ : std_logic;
-SIGNAL \inst|15~2_combout\ : std_logic;
-SIGNAL \inst|15~3_combout\ : std_logic;
-SIGNAL \inst|15~4_combout\ : std_logic;
-SIGNAL \inst|15~5_combout\ : std_logic;
-SIGNAL \inst|15~6_combout\ : std_logic;
-SIGNAL \inst|15~7_combout\ : std_logic;
-SIGNAL \inst|15~8_combout\ : std_logic;
-SIGNAL \inst|15~9_combout\ : std_logic;
-SIGNAL \inst|15~10_combout\ : std_logic;
-SIGNAL \inst|15~11_combout\ : std_logic;
-SIGNAL \inst|15~12_combout\ : std_logic;
-SIGNAL \inst|15~13_combout\ : std_logic;
-SIGNAL \inst|15~14_combout\ : std_logic;
-SIGNAL \inst|15~15_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~15_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~14_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~13_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~12_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~11_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~10_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~9_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~8_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~6_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~5_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~4_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~3_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~2_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~1_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_15~0_combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-ww_D <= D;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-Y8 <= ww_Y8;
-Y9 <= ww_Y9;
-Y10 <= ww_Y10;
-Y11 <= ww_Y11;
-Y12 <= ww_Y12;
-Y13 <= ww_Y13;
-Y14 <= ww_Y14;
-Y15 <= ww_Y15;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\inst|ALT_INV_15~15_combout\ <= NOT \inst|15~15_combout\;
-\inst|ALT_INV_15~14_combout\ <= NOT \inst|15~14_combout\;
-\inst|ALT_INV_15~13_combout\ <= NOT \inst|15~13_combout\;
-\inst|ALT_INV_15~12_combout\ <= NOT \inst|15~12_combout\;
-\inst|ALT_INV_15~11_combout\ <= NOT \inst|15~11_combout\;
-\inst|ALT_INV_15~10_combout\ <= NOT \inst|15~10_combout\;
-\inst|ALT_INV_15~9_combout\ <= NOT \inst|15~9_combout\;
-\inst|ALT_INV_15~8_combout\ <= NOT \inst|15~8_combout\;
-\inst|ALT_INV_15~7_combout\ <= NOT \inst|15~7_combout\;
-\inst|ALT_INV_15~6_combout\ <= NOT \inst|15~6_combout\;
-\inst|ALT_INV_15~5_combout\ <= NOT \inst|15~5_combout\;
-\inst|ALT_INV_15~4_combout\ <= NOT \inst|15~4_combout\;
-\inst|ALT_INV_15~3_combout\ <= NOT \inst|15~3_combout\;
-\inst|ALT_INV_15~2_combout\ <= NOT \inst|15~2_combout\;
-\inst|ALT_INV_15~1_combout\ <= NOT \inst|15~1_combout\;
-\inst|ALT_INV_15~0_combout\ <= NOT \inst|15~0_combout\;
-
--- Location: IOOBUF_X0_Y11_N2
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~0_combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y21_N2
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~1_combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y5_N2
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~2_combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X0_Y7_N23
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~3_combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X0_Y2_N9
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~4_combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y8_N2
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~5_combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y3_N9
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~6_combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X1_Y0_N30
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~7_combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOOBUF_X0_Y11_N9
-\Y8~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~8_combout\,
-	devoe => ww_devoe,
-	o => \Y8~output_o\);
-
--- Location: IOOBUF_X0_Y12_N2
-\Y9~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~9_combout\,
-	devoe => ww_devoe,
-	o => \Y9~output_o\);
-
--- Location: IOOBUF_X0_Y8_N9
-\Y10~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~10_combout\,
-	devoe => ww_devoe,
-	o => \Y10~output_o\);
-
--- Location: IOOBUF_X0_Y6_N2
-\Y11~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~11_combout\,
-	devoe => ww_devoe,
-	o => \Y11~output_o\);
-
--- Location: IOOBUF_X0_Y8_N23
-\Y12~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~12_combout\,
-	devoe => ww_devoe,
-	o => \Y12~output_o\);
-
--- Location: IOOBUF_X0_Y7_N16
-\Y13~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~13_combout\,
-	devoe => ww_devoe,
-	o => \Y13~output_o\);
-
--- Location: IOOBUF_X0_Y12_N9
-\Y14~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~14_combout\,
-	devoe => ww_devoe,
-	o => \Y14~output_o\);
-
--- Location: IOOBUF_X0_Y4_N9
-\Y15~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_15~15_combout\,
-	devoe => ww_devoe,
-	o => \Y15~output_o\);
-
--- Location: IOIBUF_X0_Y6_N8
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y6_N22
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: IOIBUF_X0_Y3_N1
-\D~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_D,
-	o => \D~input_o\);
-
--- Location: IOIBUF_X7_Y0_N29
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: LCCOMB_X1_Y9_N24
-\inst|15~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~0_combout\ = (!\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000001",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~0_combout\);
-
--- Location: LCCOMB_X1_Y9_N2
-\inst|15~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~1_combout\ = (!\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~1_combout\);
-
--- Location: LCCOMB_X1_Y9_N4
-\inst|15~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~2_combout\ = (!\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~2_combout\);
-
--- Location: LCCOMB_X1_Y9_N22
-\inst|15~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~3_combout\ = (!\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000010000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~3_combout\);
-
--- Location: LCCOMB_X1_Y9_N16
-\inst|15~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~4_combout\ = (\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~4_combout\);
-
--- Location: LCCOMB_X1_Y9_N26
-\inst|15~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~5_combout\ = (\C~input_o\ & (!\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000001000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~5_combout\);
-
--- Location: LCCOMB_X1_Y9_N28
-\inst|15~6\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~6_combout\ = (\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~6_combout\);
-
--- Location: LCCOMB_X1_Y9_N6
-\inst|15~7\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~7_combout\ = (\C~input_o\ & (\B~input_o\ & (!\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000100000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~7_combout\);
-
--- Location: LCCOMB_X1_Y9_N0
-\inst|15~8\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~8_combout\ = (!\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~8_combout\);
-
--- Location: LCCOMB_X1_Y9_N10
-\inst|15~9\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~9_combout\ = (!\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~9_combout\);
-
--- Location: LCCOMB_X1_Y9_N20
-\inst|15~10\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~10_combout\ = (!\C~input_o\ & (\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~10_combout\);
-
--- Location: LCCOMB_X1_Y9_N14
-\inst|15~11\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~11_combout\ = (!\C~input_o\ & (\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0100000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~11_combout\);
-
--- Location: LCCOMB_X1_Y9_N8
-\inst|15~12\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~12_combout\ = (\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~12_combout\);
-
--- Location: LCCOMB_X1_Y9_N18
-\inst|15~13\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~13_combout\ = (\C~input_o\ & (!\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0010000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~13_combout\);
-
--- Location: LCCOMB_X1_Y9_N12
-\inst|15~14\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~14_combout\ = (\C~input_o\ & (\B~input_o\ & (\D~input_o\ & !\A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~14_combout\);
-
--- Location: LCCOMB_X1_Y9_N30
-\inst|15~15\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|15~15_combout\ = (\C~input_o\ & (\B~input_o\ & (\D~input_o\ & \A~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1000000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datab => \B~input_o\,
-	datac => \D~input_o\,
-	datad => \A~input_o\,
-	combout => \inst|15~15_combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-
-ww_Y8 <= \Y8~output_o\;
-
-ww_Y9 <= \Y9~output_o\;
-
-ww_Y10 <= \Y10~output_o\;
-
-ww_Y11 <= \Y11~output_o\;
-
-ww_Y12 <= \Y12~output_o\;
-
-ww_Y13 <= \Y13~output_o\;
-
-ww_Y14 <= \Y14~output_o\;
-
-ww_Y15 <= \Y15~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_min_1200mv_0c_vhd_fast.sdo b/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_min_1200mv_0c_vhd_fast.sdo
deleted file mode 100644
index d5484b59..00000000
--- a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_min_1200mv_0c_vhd_fast.sdo
+++ /dev/null
@@ -1,491 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Fast Corner delays for the design using part EP3C16F484C6,
-// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "four_line_to_sixteen_line_decimal_decoder")
-  (DATE "10/24/2019 22:11:45")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y0\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (368:368:368) (328:328:328))
-        (IOPATH i o (1368:1368:1368) (1348:1348:1348))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y1\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (638:638:638) (567:567:567))
-        (IOPATH i o (1368:1368:1368) (1348:1348:1348))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y2\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (374:374:374) (337:337:337))
-        (IOPATH i o (1440:1440:1440) (1456:1456:1456))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y3\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (372:372:372) (331:331:331))
-        (IOPATH i o (1480:1480:1480) (1496:1496:1496))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y4\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (557:557:557) (498:498:498))
-        (IOPATH i o (1440:1440:1440) (1456:1456:1456))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y5\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (371:371:371) (326:326:326))
-        (IOPATH i o (1480:1480:1480) (1496:1496:1496))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y6\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (580:580:580) (514:514:514))
-        (IOPATH i o (1440:1440:1440) (1456:1456:1456))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y7\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (615:615:615) (539:539:539))
-        (IOPATH i o (1291:1291:1291) (1300:1300:1300))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y8\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (365:365:365) (326:326:326))
-        (IOPATH i o (2397:2397:2397) (2268:2268:2268))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y9\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (380:380:380) (341:341:341))
-        (IOPATH i o (1440:1440:1440) (1456:1456:1456))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y10\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (426:426:426) (380:380:380))
-        (IOPATH i o (1378:1378:1378) (1358:1358:1358))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y11\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (369:369:369) (333:333:333))
-        (IOPATH i o (1490:1490:1490) (1506:1506:1506))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y12\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (353:353:353) (313:313:313))
-        (IOPATH i o (1450:1450:1450) (1466:1466:1466))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y13\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (452:452:452) (399:399:399))
-        (IOPATH i o (1490:1490:1490) (1506:1506:1506))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y14\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (357:357:357) (320:320:320))
-        (IOPATH i o (1440:1440:1440) (1456:1456:1456))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y15\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (451:451:451) (403:403:403))
-        (IOPATH i o (1440:1440:1440) (1456:1456:1456))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\C\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (431:431:431) (813:813:813))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\B\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (391:391:391) (773:773:773))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\D\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (381:381:381) (763:763:763))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\A\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (412:412:412) (794:794:794))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1721:1721:1721) (1936:1936:1936))
-        (PORT datab (1731:1731:1731) (1947:1947:1947))
-        (PORT datac (1872:1872:1872) (2101:2101:2101))
-        (PORT datad (1886:1886:1886) (2128:2128:2128))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (120:120:120) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~1\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1735:1735:1735) (1953:1953:1953))
-        (PORT datab (1744:1744:1744) (1962:1962:1962))
-        (PORT datac (1853:1853:1853) (2080:2080:2080))
-        (PORT datad (1880:1880:1880) (2121:2121:2121))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (119:119:119) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~2\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1735:1735:1735) (1953:1953:1953))
-        (PORT datab (1744:1744:1744) (1963:1963:1963))
-        (PORT datac (1855:1855:1855) (2083:2083:2083))
-        (PORT datad (1878:1878:1878) (2123:2123:2123))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (168:168:168) (167:167:167))
-        (IOPATH datac combout (120:120:120) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~3\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1723:1723:1723) (1938:1938:1938))
-        (PORT datab (1733:1733:1733) (1950:1950:1950))
-        (PORT datac (1871:1871:1871) (2100:2100:2100))
-        (PORT datad (1885:1885:1885) (2128:2128:2128))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (166:166:166) (158:158:158))
-        (IOPATH datac combout (119:119:119) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~4\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1727:1727:1727) (1943:1943:1943))
-        (PORT datab (1736:1736:1736) (1953:1953:1953))
-        (PORT datac (1868:1868:1868) (2097:2097:2097))
-        (PORT datad (1883:1883:1883) (2125:2125:2125))
-        (IOPATH dataa combout (170:170:170) (163:163:163))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (120:120:120) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1715:1715:1715) (1929:1929:1929))
-        (PORT datab (1724:1724:1724) (1939:1939:1939))
-        (PORT datac (1872:1872:1872) (2102:2102:2102))
-        (PORT datad (1884:1884:1884) (2126:2126:2126))
-        (IOPATH dataa combout (165:165:165) (159:159:159))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (119:119:119) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~6\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1715:1715:1715) (1929:1929:1929))
-        (PORT datab (1724:1724:1724) (1940:1940:1940))
-        (PORT datac (1873:1873:1873) (2102:2102:2102))
-        (PORT datad (1885:1885:1885) (2127:2127:2127))
-        (IOPATH dataa combout (170:170:170) (163:163:163))
-        (IOPATH datab combout (168:168:168) (167:167:167))
-        (IOPATH datac combout (120:120:120) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~7\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1734:1734:1734) (1952:1952:1952))
-        (PORT datab (1744:1744:1744) (1963:1963:1963))
-        (PORT datac (1857:1857:1857) (2085:2085:2085))
-        (PORT datad (1880:1880:1880) (2122:2122:2122))
-        (IOPATH dataa combout (158:158:158) (163:163:163))
-        (IOPATH datab combout (160:160:160) (167:167:167))
-        (IOPATH datac combout (119:119:119) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
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diff --git a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_modelsim.xrf b/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_modelsim.xrf
deleted file mode 100644
index e80ae9b2..00000000
--- a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_modelsim.xrf
+++ /dev/null
@@ -1,41 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cbx.xml
-source_file = 1, /home/timmy/altera/13.1/quartus/libraries/others/maxplus2/74138.bdf
-design_name = four_line_to_sixteen_line_decimal_decoder
-instance = comp, \Y0~output\, Y0~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y1~output\, Y1~output, four_line_to_sixteen_line_decimal_decoder, 1
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-instance = comp, \inst|15~0\, inst|15~0, four_line_to_sixteen_line_decimal_decoder, 1
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-instance = comp, \inst|15~2\, inst|15~2, four_line_to_sixteen_line_decimal_decoder, 1
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-instance = comp, \inst|15~15\, inst|15~15, four_line_to_sixteen_line_decimal_decoder, 1
diff --git a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_vhd.sdo b/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_vhd.sdo
deleted file mode 100644
index 2856a0c1..00000000
--- a/CH6/CH6-1/simulation/modelsim/four_line_to_sixteen_line_decimal_decoder_vhd.sdo
+++ /dev/null
@@ -1,491 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
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-  (DATE "10/24/2019 22:11:45")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
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-        (IOPATH datab combout (381:381:381) (380:380:380))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2920:2920:2920) (3254:3254:3254))
-        (PORT datab (2956:2956:2956) (3267:3267:3267))
-        (PORT datac (3159:3159:3159) (3488:3488:3488))
-        (PORT datad (3244:3244:3244) (3553:3553:3553))
-        (IOPATH dataa combout (303:303:303) (299:299:299))
-        (IOPATH datab combout (336:336:336) (325:325:325))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~6\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2921:2921:2921) (3255:3255:3255))
-        (PORT datab (2956:2956:2956) (3268:3268:3268))
-        (PORT datac (3160:3160:3160) (3488:3488:3488))
-        (PORT datad (3245:3245:3245) (3554:3554:3554))
-        (IOPATH dataa combout (339:339:339) (367:367:367))
-        (IOPATH datab combout (344:344:344) (369:369:369))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~7\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2940:2940:2940) (3277:3277:3277))
-        (PORT datab (2977:2977:2977) (3291:3291:3291))
-        (PORT datac (3144:3144:3144) (3472:3472:3472))
-        (PORT datad (3235:3235:3235) (3549:3549:3549))
-        (IOPATH dataa combout (300:300:300) (308:308:308))
-        (IOPATH datab combout (300:300:300) (311:311:311))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~8\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2943:2943:2943) (3278:3278:3278))
-        (PORT datab (2979:2979:2979) (3291:3291:3291))
-        (PORT datac (3138:3138:3138) (3464:3464:3464))
-        (PORT datad (3237:3237:3237) (3550:3550:3550))
-        (IOPATH dataa combout (337:337:337) (338:338:338))
-        (IOPATH datab combout (337:337:337) (348:348:348))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~9\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2931:2931:2931) (3275:3275:3275))
-        (PORT datab (2968:2968:2968) (3289:3289:3289))
-        (PORT datac (3149:3149:3149) (3476:3476:3476))
-        (PORT datad (3229:3229:3229) (3554:3554:3554))
-        (IOPATH dataa combout (301:301:301) (299:299:299))
-        (IOPATH datab combout (300:300:300) (308:308:308))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~10\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2931:2931:2931) (3262:3262:3262))
-        (PORT datab (2968:2968:2968) (3276:3276:3276))
-        (PORT datac (3157:3157:3157) (3486:3486:3486))
-        (PORT datad (3242:3242:3242) (3557:3557:3557))
-        (IOPATH dataa combout (356:356:356) (368:368:368))
-        (IOPATH datab combout (342:342:342) (318:318:318))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~11\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2935:2935:2935) (3269:3269:3269))
-        (PORT datab (2972:2972:2972) (3283:3283:3283))
-        (PORT datac (3153:3153:3153) (3480:3480:3480))
-        (PORT datad (3231:3231:3231) (3556:3556:3556))
-        (IOPATH dataa combout (324:324:324) (328:328:328))
-        (IOPATH datab combout (306:306:306) (308:308:308))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~12\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2939:2939:2939) (3277:3277:3277))
-        (PORT datab (2976:2976:2976) (3291:3291:3291))
-        (PORT datac (3147:3147:3147) (3475:3475:3475))
-        (PORT datad (3234:3234:3234) (3552:3552:3552))
-        (IOPATH dataa combout (341:341:341) (319:319:319))
-        (IOPATH datab combout (365:365:365) (373:373:373))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~13\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2933:2933:2933) (3260:3260:3260))
-        (PORT datab (2970:2970:2970) (3275:3275:3275))
-        (PORT datac (3156:3156:3156) (3484:3484:3484))
-        (PORT datad (3241:3241:3241) (3556:3556:3556))
-        (IOPATH dataa combout (304:304:304) (299:299:299))
-        (IOPATH datab combout (333:333:333) (332:332:332))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~14\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2933:2933:2933) (3274:3274:3274))
-        (PORT datab (2970:2970:2970) (3288:3288:3288))
-        (PORT datac (3151:3151:3151) (3478:3478:3478))
-        (PORT datad (3232:3232:3232) (3553:3553:3553))
-        (IOPATH dataa combout (327:327:327) (347:347:347))
-        (IOPATH datab combout (331:331:331) (342:342:342))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|15\~15\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2922:2922:2922) (3255:3255:3255))
-        (PORT datab (2957:2957:2957) (3268:3268:3268))
-        (PORT datac (3161:3161:3161) (3489:3489:3489))
-        (PORT datad (3246:3246:3246) (3554:3554:3554))
-        (IOPATH dataa combout (300:300:300) (307:307:307))
-        (IOPATH datab combout (300:300:300) (308:308:308))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder.sft b/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder.sft
deleted file mode 100644
index e18195f3..00000000
--- a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder.sft
+++ /dev/null
@@ -1,6 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
-set corner_file_list {
-	{{"Slow -6 1.2V 85 Model"} {ten_line_to_four_line_BCD_priority_encoder_6_1200mv_85c_slow.vho ten_line_to_four_line_BCD_priority_encoder_6_1200mv_85c_vhd_slow.sdo}}
-	{{"Slow -6 1.2V 0 Model"} {ten_line_to_four_line_BCD_priority_encoder_6_1200mv_0c_slow.vho ten_line_to_four_line_BCD_priority_encoder_6_1200mv_0c_vhd_slow.sdo}}
-	{{"Fast -M 1.2V 0 Model"} {ten_line_to_four_line_BCD_priority_encoder_min_1200mv_0c_fast.vho ten_line_to_four_line_BCD_priority_encoder_min_1200mv_0c_vhd_fast.sdo}}
-}
diff --git a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder.vho b/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder.vho
deleted file mode 100644
index bdf62f13..00000000
--- a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder.vho
+++ /dev/null
@@ -1,386 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/17/2019 09:29:37"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	ten_line_to_four_line_BCD_priority_encoder IS
-    PORT (
-	A : OUT std_logic;
-	I2 : IN std_logic;
-	I3 : IN std_logic;
-	I6 : IN std_logic;
-	I5 : IN std_logic;
-	I4 : IN std_logic;
-	I9 : IN std_logic;
-	I8 : IN std_logic;
-	I7 : IN std_logic;
-	B : OUT std_logic;
-	C : OUT std_logic;
-	D : OUT std_logic
-	);
-END ten_line_to_four_line_BCD_priority_encoder;
-
--- Design Ports Information
--- A	=>  Location: PIN_E6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_A5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_R9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I6	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I4	=>  Location: PIN_E13,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I3	=>  Location: PIN_P2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I5	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I7	=>  Location: PIN_M1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I9	=>  Location: PIN_N2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I8	=>  Location: PIN_M2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I2	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF ten_line_to_four_line_BCD_priority_encoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_I2 : std_logic;
-SIGNAL ww_I3 : std_logic;
-SIGNAL ww_I6 : std_logic;
-SIGNAL ww_I5 : std_logic;
-SIGNAL ww_I4 : std_logic;
-SIGNAL ww_I9 : std_logic;
-SIGNAL ww_I8 : std_logic;
-SIGNAL ww_I7 : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL \A~output_o\ : std_logic;
-SIGNAL \B~output_o\ : std_logic;
-SIGNAL \C~output_o\ : std_logic;
-SIGNAL \D~output_o\ : std_logic;
-SIGNAL \I7~input_o\ : std_logic;
-SIGNAL \I8~input_o\ : std_logic;
-SIGNAL \I9~input_o\ : std_logic;
-SIGNAL \I3~input_o\ : std_logic;
-SIGNAL \I6~input_o\ : std_logic;
-SIGNAL \I5~input_o\ : std_logic;
-SIGNAL \I4~input_o\ : std_logic;
-SIGNAL \inst|7~2_combout\ : std_logic;
-SIGNAL \inst|7~3_combout\ : std_logic;
-SIGNAL \I2~input_o\ : std_logic;
-SIGNAL \inst|8~4_combout\ : std_logic;
-SIGNAL \inst|67~combout\ : std_logic;
-SIGNAL \inst|8~5_combout\ : std_logic;
-SIGNAL \inst|9~0_combout\ : std_logic;
-SIGNAL \inst|9~1_combout\ : std_logic;
-
-BEGIN
-
-A <= ww_A;
-ww_I2 <= I2;
-ww_I3 <= I3;
-ww_I6 <= I6;
-ww_I5 <= I5;
-ww_I4 <= I4;
-ww_I9 <= I9;
-ww_I8 <= I8;
-ww_I7 <= I7;
-B <= ww_B;
-C <= ww_C;
-D <= ww_D;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X1_Y29_N23
-\A~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|7~3_combout\,
-	devoe => ww_devoe,
-	o => \A~output_o\);
-
--- Location: IOOBUF_X7_Y29_N9
-\B~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|8~5_combout\,
-	devoe => ww_devoe,
-	o => \B~output_o\);
-
--- Location: IOOBUF_X0_Y20_N9
-\C~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|9~1_combout\,
-	devoe => ww_devoe,
-	o => \C~output_o\);
-
--- Location: IOOBUF_X1_Y0_N30
-\D~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|67~combout\,
-	devoe => ww_devoe,
-	o => \D~output_o\);
-
--- Location: IOIBUF_X0_Y13_N22
-\I7~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I7,
-	o => \I7~input_o\);
-
--- Location: IOIBUF_X0_Y13_N15
-\I8~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I8,
-	o => \I8~input_o\);
-
--- Location: IOIBUF_X0_Y12_N15
-\I9~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I9,
-	o => \I9~input_o\);
-
--- Location: IOIBUF_X0_Y11_N15
-\I3~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I3,
-	o => \I3~input_o\);
-
--- Location: IOIBUF_X0_Y20_N1
-\I6~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I6,
-	o => \I6~input_o\);
-
--- Location: IOIBUF_X0_Y12_N1
-\I5~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I5,
-	o => \I5~input_o\);
-
--- Location: IOIBUF_X23_Y29_N15
-\I4~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I4,
-	o => \I4~input_o\);
-
--- Location: LCCOMB_X1_Y20_N0
-\inst|7~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|7~2_combout\ = (\I6~input_o\ & (((!\I3~input_o\ & \I4~input_o\)) # (!\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0100110000001100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I3~input_o\,
-	datab => \I6~input_o\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|7~2_combout\);
-
--- Location: LCCOMB_X1_Y20_N2
-\inst|7~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|7~3_combout\ = ((\I8~input_o\ & ((\inst|7~2_combout\) # (!\I7~input_o\)))) # (!\I9~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1100111101001111",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I7~input_o\,
-	datab => \I8~input_o\,
-	datac => \I9~input_o\,
-	datad => \inst|7~2_combout\,
-	combout => \inst|7~3_combout\);
-
--- Location: IOIBUF_X0_Y23_N8
-\I2~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I2,
-	o => \I2~input_o\);
-
--- Location: LCCOMB_X1_Y20_N12
-\inst|8~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|8~4_combout\ = (\I5~input_o\ & (\I4~input_o\ & ((!\I2~input_o\) # (!\I3~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0111000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I3~input_o\,
-	datab => \I2~input_o\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|8~4_combout\);
-
--- Location: LCCOMB_X1_Y20_N18
-\inst|67\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|67~combout\ = (!\I8~input_o\) # (!\I9~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000111111111111",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \I8~input_o\,
-	combout => \inst|67~combout\);
-
--- Location: LCCOMB_X1_Y20_N28
-\inst|8~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|8~5_combout\ = (!\inst|67~combout\ & ((\inst|8~4_combout\) # ((!\I7~input_o\) # (!\I6~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0010001100110011",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \inst|8~4_combout\,
-	datab => \inst|67~combout\,
-	datac => \I6~input_o\,
-	datad => \I7~input_o\,
-	combout => \inst|8~5_combout\);
-
--- Location: LCCOMB_X1_Y20_N6
-\inst|9~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|9~0_combout\ = (\I7~input_o\ & \I6~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1010101000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I7~input_o\,
-	datad => \I6~input_o\,
-	combout => \inst|9~0_combout\);
-
--- Location: LCCOMB_X1_Y20_N16
-\inst|9~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|9~1_combout\ = (!\inst|67~combout\ & (((!\I4~input_o\) # (!\I5~input_o\)) # (!\inst|9~0_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001001100110011",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \inst|9~0_combout\,
-	datab => \inst|67~combout\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|9~1_combout\);
-
-ww_A <= \A~output_o\;
-
-ww_B <= \B~output_o\;
-
-ww_C <= \C~output_o\;
-
-ww_D <= \D~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_0c_slow.vho b/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_0c_slow.vho
deleted file mode 100644
index bdf62f13..00000000
--- a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_0c_slow.vho
+++ /dev/null
@@ -1,386 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/17/2019 09:29:37"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	ten_line_to_four_line_BCD_priority_encoder IS
-    PORT (
-	A : OUT std_logic;
-	I2 : IN std_logic;
-	I3 : IN std_logic;
-	I6 : IN std_logic;
-	I5 : IN std_logic;
-	I4 : IN std_logic;
-	I9 : IN std_logic;
-	I8 : IN std_logic;
-	I7 : IN std_logic;
-	B : OUT std_logic;
-	C : OUT std_logic;
-	D : OUT std_logic
-	);
-END ten_line_to_four_line_BCD_priority_encoder;
-
--- Design Ports Information
--- A	=>  Location: PIN_E6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_A5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_R9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I6	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I4	=>  Location: PIN_E13,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I3	=>  Location: PIN_P2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I5	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I7	=>  Location: PIN_M1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I9	=>  Location: PIN_N2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I8	=>  Location: PIN_M2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I2	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF ten_line_to_four_line_BCD_priority_encoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_I2 : std_logic;
-SIGNAL ww_I3 : std_logic;
-SIGNAL ww_I6 : std_logic;
-SIGNAL ww_I5 : std_logic;
-SIGNAL ww_I4 : std_logic;
-SIGNAL ww_I9 : std_logic;
-SIGNAL ww_I8 : std_logic;
-SIGNAL ww_I7 : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL \A~output_o\ : std_logic;
-SIGNAL \B~output_o\ : std_logic;
-SIGNAL \C~output_o\ : std_logic;
-SIGNAL \D~output_o\ : std_logic;
-SIGNAL \I7~input_o\ : std_logic;
-SIGNAL \I8~input_o\ : std_logic;
-SIGNAL \I9~input_o\ : std_logic;
-SIGNAL \I3~input_o\ : std_logic;
-SIGNAL \I6~input_o\ : std_logic;
-SIGNAL \I5~input_o\ : std_logic;
-SIGNAL \I4~input_o\ : std_logic;
-SIGNAL \inst|7~2_combout\ : std_logic;
-SIGNAL \inst|7~3_combout\ : std_logic;
-SIGNAL \I2~input_o\ : std_logic;
-SIGNAL \inst|8~4_combout\ : std_logic;
-SIGNAL \inst|67~combout\ : std_logic;
-SIGNAL \inst|8~5_combout\ : std_logic;
-SIGNAL \inst|9~0_combout\ : std_logic;
-SIGNAL \inst|9~1_combout\ : std_logic;
-
-BEGIN
-
-A <= ww_A;
-ww_I2 <= I2;
-ww_I3 <= I3;
-ww_I6 <= I6;
-ww_I5 <= I5;
-ww_I4 <= I4;
-ww_I9 <= I9;
-ww_I8 <= I8;
-ww_I7 <= I7;
-B <= ww_B;
-C <= ww_C;
-D <= ww_D;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X1_Y29_N23
-\A~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|7~3_combout\,
-	devoe => ww_devoe,
-	o => \A~output_o\);
-
--- Location: IOOBUF_X7_Y29_N9
-\B~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|8~5_combout\,
-	devoe => ww_devoe,
-	o => \B~output_o\);
-
--- Location: IOOBUF_X0_Y20_N9
-\C~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|9~1_combout\,
-	devoe => ww_devoe,
-	o => \C~output_o\);
-
--- Location: IOOBUF_X1_Y0_N30
-\D~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|67~combout\,
-	devoe => ww_devoe,
-	o => \D~output_o\);
-
--- Location: IOIBUF_X0_Y13_N22
-\I7~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I7,
-	o => \I7~input_o\);
-
--- Location: IOIBUF_X0_Y13_N15
-\I8~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I8,
-	o => \I8~input_o\);
-
--- Location: IOIBUF_X0_Y12_N15
-\I9~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I9,
-	o => \I9~input_o\);
-
--- Location: IOIBUF_X0_Y11_N15
-\I3~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I3,
-	o => \I3~input_o\);
-
--- Location: IOIBUF_X0_Y20_N1
-\I6~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I6,
-	o => \I6~input_o\);
-
--- Location: IOIBUF_X0_Y12_N1
-\I5~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I5,
-	o => \I5~input_o\);
-
--- Location: IOIBUF_X23_Y29_N15
-\I4~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I4,
-	o => \I4~input_o\);
-
--- Location: LCCOMB_X1_Y20_N0
-\inst|7~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|7~2_combout\ = (\I6~input_o\ & (((!\I3~input_o\ & \I4~input_o\)) # (!\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0100110000001100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I3~input_o\,
-	datab => \I6~input_o\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|7~2_combout\);
-
--- Location: LCCOMB_X1_Y20_N2
-\inst|7~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|7~3_combout\ = ((\I8~input_o\ & ((\inst|7~2_combout\) # (!\I7~input_o\)))) # (!\I9~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1100111101001111",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I7~input_o\,
-	datab => \I8~input_o\,
-	datac => \I9~input_o\,
-	datad => \inst|7~2_combout\,
-	combout => \inst|7~3_combout\);
-
--- Location: IOIBUF_X0_Y23_N8
-\I2~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I2,
-	o => \I2~input_o\);
-
--- Location: LCCOMB_X1_Y20_N12
-\inst|8~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|8~4_combout\ = (\I5~input_o\ & (\I4~input_o\ & ((!\I2~input_o\) # (!\I3~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0111000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I3~input_o\,
-	datab => \I2~input_o\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|8~4_combout\);
-
--- Location: LCCOMB_X1_Y20_N18
-\inst|67\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|67~combout\ = (!\I8~input_o\) # (!\I9~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000111111111111",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \I8~input_o\,
-	combout => \inst|67~combout\);
-
--- Location: LCCOMB_X1_Y20_N28
-\inst|8~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|8~5_combout\ = (!\inst|67~combout\ & ((\inst|8~4_combout\) # ((!\I7~input_o\) # (!\I6~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0010001100110011",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \inst|8~4_combout\,
-	datab => \inst|67~combout\,
-	datac => \I6~input_o\,
-	datad => \I7~input_o\,
-	combout => \inst|8~5_combout\);
-
--- Location: LCCOMB_X1_Y20_N6
-\inst|9~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|9~0_combout\ = (\I7~input_o\ & \I6~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1010101000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I7~input_o\,
-	datad => \I6~input_o\,
-	combout => \inst|9~0_combout\);
-
--- Location: LCCOMB_X1_Y20_N16
-\inst|9~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|9~1_combout\ = (!\inst|67~combout\ & (((!\I4~input_o\) # (!\I5~input_o\)) # (!\inst|9~0_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001001100110011",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \inst|9~0_combout\,
-	datab => \inst|67~combout\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|9~1_combout\);
-
-ww_A <= \A~output_o\;
-
-ww_B <= \B~output_o\;
-
-ww_C <= \C~output_o\;
-
-ww_D <= \D~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_0c_vhd_slow.sdo b/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_0c_vhd_slow.sdo
deleted file mode 100644
index 7c86e158..00000000
--- a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_0c_vhd_slow.sdo
+++ /dev/null
@@ -1,255 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "ten_line_to_four_line_BCD_priority_encoder")
-  (DATE "10/17/2019 09:29:37")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\A\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (784:784:784) (778:778:778))
-        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\B\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1045:1045:1045) (981:981:981))
-        (IOPATH i o (2100:2100:2100) (2049:2049:2049))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\C\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (296:296:296) (291:291:291))
-        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\D\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1397:1397:1397) (1380:1380:1380))
-        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I7\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I8\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I9\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I3\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I6\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I5\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I4\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (679:679:679) (842:842:842))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|7\~2\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2660:2660:2660) (2865:2865:2865))
-        (PORT datab (2138:2138:2138) (2345:2345:2345))
-        (PORT datac (2491:2491:2491) (2689:2689:2689))
-        (PORT datad (2912:2912:2912) (3155:3155:3155))
-        (IOPATH dataa combout (287:287:287) (289:289:289))
-        (IOPATH datab combout (319:319:319) (324:324:324))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|7\~3\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2476:2476:2476) (2682:2682:2682))
-        (PORT datab (2501:2501:2501) (2689:2689:2689))
-        (PORT datac (2629:2629:2629) (2807:2807:2807))
-        (PORT datad (159:159:159) (180:180:180))
-        (IOPATH dataa combout (318:318:318) (327:327:327))
-        (IOPATH datab combout (308:308:308) (281:281:281))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I2\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|8\~4\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2659:2659:2659) (2867:2867:2867))
-        (PORT datab (2443:2443:2443) (2666:2666:2666))
-        (PORT datac (2494:2494:2494) (2693:2693:2693))
-        (PORT datad (2912:2912:2912) (3159:3159:3159))
-        (IOPATH dataa combout (287:287:287) (289:289:289))
-        (IOPATH datab combout (295:295:295) (294:294:294))
-        (IOPATH datac combout (218:218:218) (216:216:216))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|67\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (2630:2630:2630) (2809:2809:2809))
-        (PORT datad (2459:2459:2459) (2651:2651:2651))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|8\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (187:187:187) (225:225:225))
-        (PORT datab (210:210:210) (247:247:247))
-        (PORT datac (2106:2106:2106) (2298:2298:2298))
-        (PORT datad (2449:2449:2449) (2646:2646:2646))
-        (IOPATH dataa combout (273:273:273) (269:269:269))
-        (IOPATH datab combout (336:336:336) (337:337:337))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|9\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2476:2476:2476) (2681:2681:2681))
-        (PORT datad (2109:2109:2109) (2307:2307:2307))
-        (IOPATH dataa combout (273:273:273) (269:269:269))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|9\~1\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (186:186:186) (224:224:224))
-        (PORT datab (210:210:210) (249:249:249))
-        (PORT datac (2495:2495:2495) (2694:2694:2694))
-        (PORT datad (2912:2912:2912) (3158:3158:3158))
-        (IOPATH dataa combout (267:267:267) (269:269:269))
-        (IOPATH datab combout (336:336:336) (337:337:337))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_85c_slow.vho b/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_85c_slow.vho
deleted file mode 100644
index bdf62f13..00000000
--- a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_85c_slow.vho
+++ /dev/null
@@ -1,386 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/17/2019 09:29:37"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	ten_line_to_four_line_BCD_priority_encoder IS
-    PORT (
-	A : OUT std_logic;
-	I2 : IN std_logic;
-	I3 : IN std_logic;
-	I6 : IN std_logic;
-	I5 : IN std_logic;
-	I4 : IN std_logic;
-	I9 : IN std_logic;
-	I8 : IN std_logic;
-	I7 : IN std_logic;
-	B : OUT std_logic;
-	C : OUT std_logic;
-	D : OUT std_logic
-	);
-END ten_line_to_four_line_BCD_priority_encoder;
-
--- Design Ports Information
--- A	=>  Location: PIN_E6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_A5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_R9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I6	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I4	=>  Location: PIN_E13,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I3	=>  Location: PIN_P2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I5	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I7	=>  Location: PIN_M1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I9	=>  Location: PIN_N2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I8	=>  Location: PIN_M2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I2	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF ten_line_to_four_line_BCD_priority_encoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_I2 : std_logic;
-SIGNAL ww_I3 : std_logic;
-SIGNAL ww_I6 : std_logic;
-SIGNAL ww_I5 : std_logic;
-SIGNAL ww_I4 : std_logic;
-SIGNAL ww_I9 : std_logic;
-SIGNAL ww_I8 : std_logic;
-SIGNAL ww_I7 : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL \A~output_o\ : std_logic;
-SIGNAL \B~output_o\ : std_logic;
-SIGNAL \C~output_o\ : std_logic;
-SIGNAL \D~output_o\ : std_logic;
-SIGNAL \I7~input_o\ : std_logic;
-SIGNAL \I8~input_o\ : std_logic;
-SIGNAL \I9~input_o\ : std_logic;
-SIGNAL \I3~input_o\ : std_logic;
-SIGNAL \I6~input_o\ : std_logic;
-SIGNAL \I5~input_o\ : std_logic;
-SIGNAL \I4~input_o\ : std_logic;
-SIGNAL \inst|7~2_combout\ : std_logic;
-SIGNAL \inst|7~3_combout\ : std_logic;
-SIGNAL \I2~input_o\ : std_logic;
-SIGNAL \inst|8~4_combout\ : std_logic;
-SIGNAL \inst|67~combout\ : std_logic;
-SIGNAL \inst|8~5_combout\ : std_logic;
-SIGNAL \inst|9~0_combout\ : std_logic;
-SIGNAL \inst|9~1_combout\ : std_logic;
-
-BEGIN
-
-A <= ww_A;
-ww_I2 <= I2;
-ww_I3 <= I3;
-ww_I6 <= I6;
-ww_I5 <= I5;
-ww_I4 <= I4;
-ww_I9 <= I9;
-ww_I8 <= I8;
-ww_I7 <= I7;
-B <= ww_B;
-C <= ww_C;
-D <= ww_D;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X1_Y29_N23
-\A~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|7~3_combout\,
-	devoe => ww_devoe,
-	o => \A~output_o\);
-
--- Location: IOOBUF_X7_Y29_N9
-\B~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|8~5_combout\,
-	devoe => ww_devoe,
-	o => \B~output_o\);
-
--- Location: IOOBUF_X0_Y20_N9
-\C~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|9~1_combout\,
-	devoe => ww_devoe,
-	o => \C~output_o\);
-
--- Location: IOOBUF_X1_Y0_N30
-\D~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|67~combout\,
-	devoe => ww_devoe,
-	o => \D~output_o\);
-
--- Location: IOIBUF_X0_Y13_N22
-\I7~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I7,
-	o => \I7~input_o\);
-
--- Location: IOIBUF_X0_Y13_N15
-\I8~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I8,
-	o => \I8~input_o\);
-
--- Location: IOIBUF_X0_Y12_N15
-\I9~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I9,
-	o => \I9~input_o\);
-
--- Location: IOIBUF_X0_Y11_N15
-\I3~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I3,
-	o => \I3~input_o\);
-
--- Location: IOIBUF_X0_Y20_N1
-\I6~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I6,
-	o => \I6~input_o\);
-
--- Location: IOIBUF_X0_Y12_N1
-\I5~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I5,
-	o => \I5~input_o\);
-
--- Location: IOIBUF_X23_Y29_N15
-\I4~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I4,
-	o => \I4~input_o\);
-
--- Location: LCCOMB_X1_Y20_N0
-\inst|7~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|7~2_combout\ = (\I6~input_o\ & (((!\I3~input_o\ & \I4~input_o\)) # (!\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0100110000001100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I3~input_o\,
-	datab => \I6~input_o\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|7~2_combout\);
-
--- Location: LCCOMB_X1_Y20_N2
-\inst|7~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|7~3_combout\ = ((\I8~input_o\ & ((\inst|7~2_combout\) # (!\I7~input_o\)))) # (!\I9~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1100111101001111",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I7~input_o\,
-	datab => \I8~input_o\,
-	datac => \I9~input_o\,
-	datad => \inst|7~2_combout\,
-	combout => \inst|7~3_combout\);
-
--- Location: IOIBUF_X0_Y23_N8
-\I2~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I2,
-	o => \I2~input_o\);
-
--- Location: LCCOMB_X1_Y20_N12
-\inst|8~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|8~4_combout\ = (\I5~input_o\ & (\I4~input_o\ & ((!\I2~input_o\) # (!\I3~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0111000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I3~input_o\,
-	datab => \I2~input_o\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|8~4_combout\);
-
--- Location: LCCOMB_X1_Y20_N18
-\inst|67\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|67~combout\ = (!\I8~input_o\) # (!\I9~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000111111111111",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \I8~input_o\,
-	combout => \inst|67~combout\);
-
--- Location: LCCOMB_X1_Y20_N28
-\inst|8~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|8~5_combout\ = (!\inst|67~combout\ & ((\inst|8~4_combout\) # ((!\I7~input_o\) # (!\I6~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0010001100110011",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \inst|8~4_combout\,
-	datab => \inst|67~combout\,
-	datac => \I6~input_o\,
-	datad => \I7~input_o\,
-	combout => \inst|8~5_combout\);
-
--- Location: LCCOMB_X1_Y20_N6
-\inst|9~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|9~0_combout\ = (\I7~input_o\ & \I6~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1010101000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I7~input_o\,
-	datad => \I6~input_o\,
-	combout => \inst|9~0_combout\);
-
--- Location: LCCOMB_X1_Y20_N16
-\inst|9~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|9~1_combout\ = (!\inst|67~combout\ & (((!\I4~input_o\) # (!\I5~input_o\)) # (!\inst|9~0_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001001100110011",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \inst|9~0_combout\,
-	datab => \inst|67~combout\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|9~1_combout\);
-
-ww_A <= \A~output_o\;
-
-ww_B <= \B~output_o\;
-
-ww_C <= \C~output_o\;
-
-ww_D <= \D~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_85c_vhd_slow.sdo b/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_85c_vhd_slow.sdo
deleted file mode 100644
index 729529e2..00000000
--- a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_6_1200mv_85c_vhd_slow.sdo
+++ /dev/null
@@ -1,255 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "ten_line_to_four_line_BCD_priority_encoder")
-  (DATE "10/17/2019 09:29:37")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\A\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (845:845:845) (878:878:878))
-        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\B\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1122:1122:1122) (1104:1104:1104))
-        (IOPATH i o (2100:2100:2100) (2049:2049:2049))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\C\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (324:324:324) (328:328:328))
-        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\D\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1516:1516:1516) (1573:1573:1573))
-        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I7\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I8\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I9\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I3\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I6\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I5\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I4\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (679:679:679) (842:842:842))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|7\~2\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (3069:3069:3069) (3338:3338:3338))
-        (PORT datab (2506:2506:2506) (2769:2769:2769))
-        (PORT datac (2894:2894:2894) (3145:3145:3145))
-        (PORT datad (3345:3345:3345) (3682:3682:3682))
-        (IOPATH dataa combout (324:324:324) (328:328:328))
-        (IOPATH datab combout (355:355:355) (369:369:369))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|7\~3\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2869:2869:2869) (3140:3140:3140))
-        (PORT datab (2893:2893:2893) (3148:3148:3148))
-        (PORT datac (3034:3034:3034) (3274:3274:3274))
-        (PORT datad (173:173:173) (199:199:199))
-        (IOPATH dataa combout (356:356:356) (368:368:368))
-        (IOPATH datab combout (342:342:342) (318:318:318))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I2\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|8\~4\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (3069:3069:3069) (3340:3340:3340))
-        (PORT datab (2836:2836:2836) (3127:3127:3127))
-        (PORT datac (2896:2896:2896) (3148:3148:3148))
-        (PORT datad (3345:3345:3345) (3685:3685:3685))
-        (IOPATH dataa combout (324:324:324) (328:328:328))
-        (IOPATH datab combout (333:333:333) (332:332:332))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|67\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (3034:3034:3034) (3276:3276:3276))
-        (PORT datad (2852:2852:2852) (3105:3105:3105))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|8\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (205:205:205) (250:250:250))
-        (PORT datab (232:232:232) (274:274:274))
-        (PORT datac (2468:2468:2468) (2717:2717:2717))
-        (PORT datad (2839:2839:2839) (3097:3097:3097))
-        (IOPATH dataa combout (304:304:304) (299:299:299))
-        (IOPATH datab combout (381:381:381) (380:380:380))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|9\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2868:2868:2868) (3139:3139:3139))
-        (PORT datad (2477:2477:2477) (2727:2727:2727))
-        (IOPATH dataa combout (304:304:304) (308:308:308))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|9\~1\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (204:204:204) (249:249:249))
-        (PORT datab (233:233:233) (275:275:275))
-        (PORT datac (2897:2897:2897) (3150:3150:3150))
-        (PORT datad (3345:3345:3345) (3684:3684:3684))
-        (IOPATH dataa combout (301:301:301) (299:299:299))
-        (IOPATH datab combout (381:381:381) (380:380:380))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_min_1200mv_0c_fast.vho b/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_min_1200mv_0c_fast.vho
deleted file mode 100644
index bdf62f13..00000000
--- a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_min_1200mv_0c_fast.vho
+++ /dev/null
@@ -1,386 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/17/2019 09:29:37"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	ten_line_to_four_line_BCD_priority_encoder IS
-    PORT (
-	A : OUT std_logic;
-	I2 : IN std_logic;
-	I3 : IN std_logic;
-	I6 : IN std_logic;
-	I5 : IN std_logic;
-	I4 : IN std_logic;
-	I9 : IN std_logic;
-	I8 : IN std_logic;
-	I7 : IN std_logic;
-	B : OUT std_logic;
-	C : OUT std_logic;
-	D : OUT std_logic
-	);
-END ten_line_to_four_line_BCD_priority_encoder;
-
--- Design Ports Information
--- A	=>  Location: PIN_E6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_A5,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- D	=>  Location: PIN_R9,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I6	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I4	=>  Location: PIN_E13,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I3	=>  Location: PIN_P2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I5	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I7	=>  Location: PIN_M1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I9	=>  Location: PIN_N2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I8	=>  Location: PIN_M2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- I2	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF ten_line_to_four_line_BCD_priority_encoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_I2 : std_logic;
-SIGNAL ww_I3 : std_logic;
-SIGNAL ww_I6 : std_logic;
-SIGNAL ww_I5 : std_logic;
-SIGNAL ww_I4 : std_logic;
-SIGNAL ww_I9 : std_logic;
-SIGNAL ww_I8 : std_logic;
-SIGNAL ww_I7 : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_D : std_logic;
-SIGNAL \A~output_o\ : std_logic;
-SIGNAL \B~output_o\ : std_logic;
-SIGNAL \C~output_o\ : std_logic;
-SIGNAL \D~output_o\ : std_logic;
-SIGNAL \I7~input_o\ : std_logic;
-SIGNAL \I8~input_o\ : std_logic;
-SIGNAL \I9~input_o\ : std_logic;
-SIGNAL \I3~input_o\ : std_logic;
-SIGNAL \I6~input_o\ : std_logic;
-SIGNAL \I5~input_o\ : std_logic;
-SIGNAL \I4~input_o\ : std_logic;
-SIGNAL \inst|7~2_combout\ : std_logic;
-SIGNAL \inst|7~3_combout\ : std_logic;
-SIGNAL \I2~input_o\ : std_logic;
-SIGNAL \inst|8~4_combout\ : std_logic;
-SIGNAL \inst|67~combout\ : std_logic;
-SIGNAL \inst|8~5_combout\ : std_logic;
-SIGNAL \inst|9~0_combout\ : std_logic;
-SIGNAL \inst|9~1_combout\ : std_logic;
-
-BEGIN
-
-A <= ww_A;
-ww_I2 <= I2;
-ww_I3 <= I3;
-ww_I6 <= I6;
-ww_I5 <= I5;
-ww_I4 <= I4;
-ww_I9 <= I9;
-ww_I8 <= I8;
-ww_I7 <= I7;
-B <= ww_B;
-C <= ww_C;
-D <= ww_D;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
--- Location: IOOBUF_X1_Y29_N23
-\A~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|7~3_combout\,
-	devoe => ww_devoe,
-	o => \A~output_o\);
-
--- Location: IOOBUF_X7_Y29_N9
-\B~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|8~5_combout\,
-	devoe => ww_devoe,
-	o => \B~output_o\);
-
--- Location: IOOBUF_X0_Y20_N9
-\C~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|9~1_combout\,
-	devoe => ww_devoe,
-	o => \C~output_o\);
-
--- Location: IOOBUF_X1_Y0_N30
-\D~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|67~combout\,
-	devoe => ww_devoe,
-	o => \D~output_o\);
-
--- Location: IOIBUF_X0_Y13_N22
-\I7~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I7,
-	o => \I7~input_o\);
-
--- Location: IOIBUF_X0_Y13_N15
-\I8~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I8,
-	o => \I8~input_o\);
-
--- Location: IOIBUF_X0_Y12_N15
-\I9~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I9,
-	o => \I9~input_o\);
-
--- Location: IOIBUF_X0_Y11_N15
-\I3~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I3,
-	o => \I3~input_o\);
-
--- Location: IOIBUF_X0_Y20_N1
-\I6~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I6,
-	o => \I6~input_o\);
-
--- Location: IOIBUF_X0_Y12_N1
-\I5~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I5,
-	o => \I5~input_o\);
-
--- Location: IOIBUF_X23_Y29_N15
-\I4~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I4,
-	o => \I4~input_o\);
-
--- Location: LCCOMB_X1_Y20_N0
-\inst|7~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|7~2_combout\ = (\I6~input_o\ & (((!\I3~input_o\ & \I4~input_o\)) # (!\I5~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0100110000001100",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I3~input_o\,
-	datab => \I6~input_o\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|7~2_combout\);
-
--- Location: LCCOMB_X1_Y20_N2
-\inst|7~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|7~3_combout\ = ((\I8~input_o\ & ((\inst|7~2_combout\) # (!\I7~input_o\)))) # (!\I9~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1100111101001111",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I7~input_o\,
-	datab => \I8~input_o\,
-	datac => \I9~input_o\,
-	datad => \inst|7~2_combout\,
-	combout => \inst|7~3_combout\);
-
--- Location: IOIBUF_X0_Y23_N8
-\I2~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_I2,
-	o => \I2~input_o\);
-
--- Location: LCCOMB_X1_Y20_N12
-\inst|8~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|8~4_combout\ = (\I5~input_o\ & (\I4~input_o\ & ((!\I2~input_o\) # (!\I3~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0111000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I3~input_o\,
-	datab => \I2~input_o\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|8~4_combout\);
-
--- Location: LCCOMB_X1_Y20_N18
-\inst|67\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|67~combout\ = (!\I8~input_o\) # (!\I9~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000111111111111",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	datac => \I9~input_o\,
-	datad => \I8~input_o\,
-	combout => \inst|67~combout\);
-
--- Location: LCCOMB_X1_Y20_N28
-\inst|8~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|8~5_combout\ = (!\inst|67~combout\ & ((\inst|8~4_combout\) # ((!\I7~input_o\) # (!\I6~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0010001100110011",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \inst|8~4_combout\,
-	datab => \inst|67~combout\,
-	datac => \I6~input_o\,
-	datad => \I7~input_o\,
-	combout => \inst|8~5_combout\);
-
--- Location: LCCOMB_X1_Y20_N6
-\inst|9~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|9~0_combout\ = (\I7~input_o\ & \I6~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1010101000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \I7~input_o\,
-	datad => \I6~input_o\,
-	combout => \inst|9~0_combout\);
-
--- Location: LCCOMB_X1_Y20_N16
-\inst|9~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|9~1_combout\ = (!\inst|67~combout\ & (((!\I4~input_o\) # (!\I5~input_o\)) # (!\inst|9~0_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0001001100110011",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \inst|9~0_combout\,
-	datab => \inst|67~combout\,
-	datac => \I5~input_o\,
-	datad => \I4~input_o\,
-	combout => \inst|9~1_combout\);
-
-ww_A <= \A~output_o\;
-
-ww_B <= \B~output_o\;
-
-ww_C <= \C~output_o\;
-
-ww_D <= \D~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_min_1200mv_0c_vhd_fast.sdo b/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_min_1200mv_0c_vhd_fast.sdo
deleted file mode 100644
index 8e7fad1a..00000000
--- a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_min_1200mv_0c_vhd_fast.sdo
+++ /dev/null
@@ -1,255 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Fast Corner delays for the design using part EP3C16F484C6,
-// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "ten_line_to_four_line_BCD_priority_encoder")
-  (DATE "10/17/2019 09:29:37")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\A\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (465:465:465) (523:523:523))
-        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\B\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (596:596:596) (649:649:649))
-        (IOPATH i o (1340:1340:1340) (1331:1331:1331))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\C\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (163:163:163) (184:184:184))
-        (IOPATH i o (1466:1466:1466) (1450:1450:1450))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\D\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (885:885:885) (971:971:971))
-        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I7\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (391:391:391) (773:773:773))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I8\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (391:391:391) (773:773:773))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I9\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (391:391:391) (773:773:773))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I3\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (391:391:391) (773:773:773))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I6\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (391:391:391) (773:773:773))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I5\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (381:381:381) (763:763:763))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I4\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (352:352:352) (734:734:734))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|7\~2\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1807:1807:1807) (2014:2014:2014))
-        (PORT datab (1461:1461:1461) (1633:1633:1633))
-        (PORT datac (1691:1691:1691) (1883:1883:1883))
-        (PORT datad (1958:1958:1958) (2217:2217:2217))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (168:168:168) (167:167:167))
-        (IOPATH datac combout (120:120:120) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|7\~3\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1680:1680:1680) (1882:1882:1882))
-        (PORT datab (1691:1691:1691) (1888:1888:1888))
-        (PORT datac (1768:1768:1768) (1959:1959:1959))
-        (PORT datad (90:90:90) (106:106:106))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (168:168:168) (167:167:167))
-        (IOPATH datac combout (120:120:120) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I2\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (391:391:391) (773:773:773))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|8\~4\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1806:1806:1806) (2015:2015:2015))
-        (PORT datab (1666:1666:1666) (1861:1861:1861))
-        (PORT datac (1694:1694:1694) (1887:1887:1887))
-        (PORT datad (1958:1958:1958) (2216:2216:2216))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|67\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (1769:1769:1769) (1961:1961:1961))
-        (PORT datad (1670:1670:1670) (1858:1858:1858))
-        (IOPATH datac combout (119:119:119) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|8\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (105:105:105) (138:138:138))
-        (PORT datab (122:122:122) (151:151:151))
-        (PORT datac (1440:1440:1440) (1600:1600:1600))
-        (PORT datad (1667:1667:1667) (1857:1857:1857))
-        (IOPATH dataa combout (166:166:166) (157:157:157))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (119:119:119) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|9\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1678:1678:1678) (1882:1882:1882))
-        (PORT datad (1447:1447:1447) (1606:1606:1606))
-        (IOPATH dataa combout (166:166:166) (163:163:163))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|9\~1\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (105:105:105) (137:137:137))
-        (PORT datab (121:121:121) (151:151:151))
-        (PORT datac (1695:1695:1695) (1888:1888:1888))
-        (PORT datad (1958:1958:1958) (2216:2216:2216))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datab combout (160:160:160) (156:156:156))
-        (IOPATH datac combout (119:119:119) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_modelsim.xrf b/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_modelsim.xrf
deleted file mode 100644
index 9bc562a9..00000000
--- a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_modelsim.xrf
+++ /dev/null
@@ -1,25 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.vwf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cbx.xml
-source_file = 1, /home/timmy/altera/13.1/quartus/libraries/others/maxplus2/74147.bdf
-design_name = ten_line_to_four_line_BCD_priority_encoder
-instance = comp, \A~output\, A~output, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \B~output\, B~output, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \C~output\, C~output, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \D~output\, D~output, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I7~input\, I7~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I8~input\, I8~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I9~input\, I9~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I3~input\, I3~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I6~input\, I6~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I5~input\, I5~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I4~input\, I4~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|7~2\, inst|7~2, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|7~3\, inst|7~3, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I2~input\, I2~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|8~4\, inst|8~4, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|67\, inst|67, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|8~5\, inst|8~5, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|9~0\, inst|9~0, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|9~1\, inst|9~1, ten_line_to_four_line_BCD_priority_encoder, 1
diff --git a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_vhd.sdo b/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_vhd.sdo
deleted file mode 100644
index 729529e2..00000000
--- a/CH6/CH6-1/simulation/modelsim/ten_line_to_four_line_BCD_priority_encoder_vhd.sdo
+++ /dev/null
@@ -1,255 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "ten_line_to_four_line_BCD_priority_encoder")
-  (DATE "10/17/2019 09:29:37")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\A\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (845:845:845) (878:878:878))
-        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\B\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1122:1122:1122) (1104:1104:1104))
-        (IOPATH i o (2100:2100:2100) (2049:2049:2049))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\C\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (324:324:324) (328:328:328))
-        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\D\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1516:1516:1516) (1573:1573:1573))
-        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I7\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I8\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I9\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I3\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I6\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I5\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (725:725:725) (886:886:886))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I4\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (679:679:679) (842:842:842))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|7\~2\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (3069:3069:3069) (3338:3338:3338))
-        (PORT datab (2506:2506:2506) (2769:2769:2769))
-        (PORT datac (2894:2894:2894) (3145:3145:3145))
-        (PORT datad (3345:3345:3345) (3682:3682:3682))
-        (IOPATH dataa combout (324:324:324) (328:328:328))
-        (IOPATH datab combout (355:355:355) (369:369:369))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|7\~3\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2869:2869:2869) (3140:3140:3140))
-        (PORT datab (2893:2893:2893) (3148:3148:3148))
-        (PORT datac (3034:3034:3034) (3274:3274:3274))
-        (PORT datad (173:173:173) (199:199:199))
-        (IOPATH dataa combout (356:356:356) (368:368:368))
-        (IOPATH datab combout (342:342:342) (318:318:318))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\I2\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (735:735:735) (896:896:896))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|8\~4\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (3069:3069:3069) (3340:3340:3340))
-        (PORT datab (2836:2836:2836) (3127:3127:3127))
-        (PORT datac (2896:2896:2896) (3148:3148:3148))
-        (PORT datad (3345:3345:3345) (3685:3685:3685))
-        (IOPATH dataa combout (324:324:324) (328:328:328))
-        (IOPATH datab combout (333:333:333) (332:332:332))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|67\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT datac (3034:3034:3034) (3276:3276:3276))
-        (PORT datad (2852:2852:2852) (3105:3105:3105))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|8\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (205:205:205) (250:250:250))
-        (PORT datab (232:232:232) (274:274:274))
-        (PORT datac (2468:2468:2468) (2717:2717:2717))
-        (PORT datad (2839:2839:2839) (3097:3097:3097))
-        (IOPATH dataa combout (304:304:304) (299:299:299))
-        (IOPATH datab combout (381:381:381) (380:380:380))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|9\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2868:2868:2868) (3139:3139:3139))
-        (PORT datad (2477:2477:2477) (2727:2727:2727))
-        (IOPATH dataa combout (304:304:304) (308:308:308))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|9\~1\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (204:204:204) (249:249:249))
-        (PORT datab (233:233:233) (275:275:275))
-        (PORT datac (2897:2897:2897) (3150:3150:3150))
-        (PORT datad (3345:3345:3345) (3684:3684:3684))
-        (IOPATH dataa combout (301:301:301) (299:299:299))
-        (IOPATH datab combout (381:381:381) (380:380:380))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder.sft b/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder.sft
deleted file mode 100644
index b9ccdb18..00000000
--- a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder.sft
+++ /dev/null
@@ -1,6 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
-set corner_file_list {
-	{{"Slow -6 1.2V 85 Model"} {three_line_to_eight_decimal_decoder_6_1200mv_85c_slow.vho three_line_to_eight_decimal_decoder_6_1200mv_85c_vhd_slow.sdo}}
-	{{"Slow -6 1.2V 0 Model"} {three_line_to_eight_decimal_decoder_6_1200mv_0c_slow.vho three_line_to_eight_decimal_decoder_6_1200mv_0c_vhd_slow.sdo}}
-	{{"Fast -M 1.2V 0 Model"} {three_line_to_eight_decimal_decoder_min_1200mv_0c_fast.vho three_line_to_eight_decimal_decoder_min_1200mv_0c_vhd_fast.sdo}}
-}
diff --git a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder.vho b/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder.vho
deleted file mode 100644
index 833683ec..00000000
--- a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder.vho
+++ /dev/null
@@ -1,412 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/24/2019 21:52:24"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	three_line_to_eight_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic
-	);
-END three_line_to_eight_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_AB4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_M8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_W20,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_N1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_U2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_T11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF three_line_to_eight_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \inst|33~0_combout\ : std_logic;
-SIGNAL \inst|33~1_combout\ : std_logic;
-SIGNAL \inst|33~2_combout\ : std_logic;
-SIGNAL \inst|33~3_combout\ : std_logic;
-SIGNAL \inst|33~4_combout\ : std_logic;
-SIGNAL \inst|33~5_combout\ : std_logic;
-SIGNAL \inst|33~6_combout\ : std_logic;
-SIGNAL \inst|33~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~6_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~5_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~4_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~3_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~2_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~1_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~0_combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\inst|ALT_INV_33~7_combout\ <= NOT \inst|33~7_combout\;
-\inst|ALT_INV_33~6_combout\ <= NOT \inst|33~6_combout\;
-\inst|ALT_INV_33~5_combout\ <= NOT \inst|33~5_combout\;
-\inst|ALT_INV_33~4_combout\ <= NOT \inst|33~4_combout\;
-\inst|ALT_INV_33~3_combout\ <= NOT \inst|33~3_combout\;
-\inst|ALT_INV_33~2_combout\ <= NOT \inst|33~2_combout\;
-\inst|ALT_INV_33~1_combout\ <= NOT \inst|33~1_combout\;
-\inst|ALT_INV_33~0_combout\ <= NOT \inst|33~0_combout\;
-
--- Location: IOOBUF_X7_Y0_N2
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~0_combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y7_N2
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~1_combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y13_N9
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~2_combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X41_Y3_N16
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~3_combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X0_Y12_N23
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~4_combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y7_N9
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~5_combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y26_N2
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~6_combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X0_Y9_N16
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~7_combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOIBUF_X0_Y9_N8
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y11_N1
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: IOIBUF_X16_Y0_N15
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: LCCOMB_X1_Y9_N16
-\inst|33~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~0_combout\ = (!\C~input_o\ & (!\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000101",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~0_combout\);
-
--- Location: LCCOMB_X1_Y9_N26
-\inst|33~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~1_combout\ = (!\C~input_o\ & (\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~1_combout\);
-
--- Location: LCCOMB_X1_Y9_N12
-\inst|33~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~2_combout\ = (!\C~input_o\ & (!\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000010100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~2_combout\);
-
--- Location: LCCOMB_X1_Y9_N30
-\inst|33~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~3_combout\ = (!\C~input_o\ & (\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0101000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~3_combout\);
-
--- Location: LCCOMB_X1_Y9_N24
-\inst|33~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~4_combout\ = (\C~input_o\ & (!\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~4_combout\);
-
--- Location: LCCOMB_X1_Y9_N18
-\inst|33~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~5_combout\ = (\C~input_o\ & (\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~5_combout\);
-
--- Location: LCCOMB_X1_Y9_N28
-\inst|33~6\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~6_combout\ = (\C~input_o\ & (!\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000101000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~6_combout\);
-
--- Location: LCCOMB_X1_Y9_N14
-\inst|33~7\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~7_combout\ = (\C~input_o\ & (\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1010000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~7_combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_0c_slow.vho b/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_0c_slow.vho
deleted file mode 100644
index 833683ec..00000000
--- a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_0c_slow.vho
+++ /dev/null
@@ -1,412 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/24/2019 21:52:24"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	three_line_to_eight_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic
-	);
-END three_line_to_eight_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_AB4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_M8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_W20,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_N1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_U2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_T11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF three_line_to_eight_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \inst|33~0_combout\ : std_logic;
-SIGNAL \inst|33~1_combout\ : std_logic;
-SIGNAL \inst|33~2_combout\ : std_logic;
-SIGNAL \inst|33~3_combout\ : std_logic;
-SIGNAL \inst|33~4_combout\ : std_logic;
-SIGNAL \inst|33~5_combout\ : std_logic;
-SIGNAL \inst|33~6_combout\ : std_logic;
-SIGNAL \inst|33~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~6_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~5_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~4_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~3_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~2_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~1_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~0_combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\inst|ALT_INV_33~7_combout\ <= NOT \inst|33~7_combout\;
-\inst|ALT_INV_33~6_combout\ <= NOT \inst|33~6_combout\;
-\inst|ALT_INV_33~5_combout\ <= NOT \inst|33~5_combout\;
-\inst|ALT_INV_33~4_combout\ <= NOT \inst|33~4_combout\;
-\inst|ALT_INV_33~3_combout\ <= NOT \inst|33~3_combout\;
-\inst|ALT_INV_33~2_combout\ <= NOT \inst|33~2_combout\;
-\inst|ALT_INV_33~1_combout\ <= NOT \inst|33~1_combout\;
-\inst|ALT_INV_33~0_combout\ <= NOT \inst|33~0_combout\;
-
--- Location: IOOBUF_X7_Y0_N2
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~0_combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y7_N2
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~1_combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y13_N9
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~2_combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X41_Y3_N16
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~3_combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X0_Y12_N23
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~4_combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y7_N9
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~5_combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y26_N2
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~6_combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X0_Y9_N16
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~7_combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOIBUF_X0_Y9_N8
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y11_N1
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: IOIBUF_X16_Y0_N15
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: LCCOMB_X1_Y9_N16
-\inst|33~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~0_combout\ = (!\C~input_o\ & (!\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000101",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~0_combout\);
-
--- Location: LCCOMB_X1_Y9_N26
-\inst|33~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~1_combout\ = (!\C~input_o\ & (\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~1_combout\);
-
--- Location: LCCOMB_X1_Y9_N12
-\inst|33~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~2_combout\ = (!\C~input_o\ & (!\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000010100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~2_combout\);
-
--- Location: LCCOMB_X1_Y9_N30
-\inst|33~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~3_combout\ = (!\C~input_o\ & (\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0101000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~3_combout\);
-
--- Location: LCCOMB_X1_Y9_N24
-\inst|33~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~4_combout\ = (\C~input_o\ & (!\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~4_combout\);
-
--- Location: LCCOMB_X1_Y9_N18
-\inst|33~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~5_combout\ = (\C~input_o\ & (\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~5_combout\);
-
--- Location: LCCOMB_X1_Y9_N28
-\inst|33~6\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~6_combout\ = (\C~input_o\ & (!\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000101000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~6_combout\);
-
--- Location: LCCOMB_X1_Y9_N14
-\inst|33~7\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~7_combout\ = (\C~input_o\ & (\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1010000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~7_combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_0c_vhd_slow.sdo b/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_0c_vhd_slow.sdo
deleted file mode 100644
index 137ce2c6..00000000
--- a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_0c_vhd_slow.sdo
+++ /dev/null
@@ -1,258 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "three_line_to_eight_decimal_decoder")
-  (DATE "10/24/2019 21:52:24")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y0\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1035:1035:1035) (1100:1100:1100))
-        (IOPATH i o (2049:2049:2049) (2100:2100:2100))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y1\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (568:568:568) (563:563:563))
-        (IOPATH i o (2214:2214:2214) (2226:2226:2226))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y2\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (573:573:573) (559:559:559))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y3\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1801:1801:1801) (1804:1804:1804))
-        (IOPATH i o (2224:2224:2224) (2236:2236:2236))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y4\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (570:570:570) (574:574:574))
-        (IOPATH i o (2224:2224:2224) (2236:2236:2236))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y5\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (555:555:555) (555:555:555))
-        (IOPATH i o (2224:2224:2224) (2236:2236:2236))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y6\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1361:1361:1361) (1380:1380:1380))
-        (IOPATH i o (2214:2214:2214) (2226:2226:2226))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y7\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (295:295:295) (299:299:299))
-        (IOPATH i o (2234:2234:2234) (2246:2246:2246))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\C\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (765:765:765) (926:926:926))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\A\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (715:715:715) (876:876:876))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\B\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (699:699:699) (862:862:862))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2206:2206:2206) (2435:2435:2435))
-        (PORT datac (2398:2398:2398) (2605:2605:2605))
-        (PORT datad (2873:2873:2873) (3119:3119:3119))
-        (IOPATH dataa combout (329:329:329) (332:332:332))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~1\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2208:2208:2208) (2433:2433:2433))
-        (PORT datac (2396:2396:2396) (2602:2602:2602))
-        (PORT datad (2867:2867:2867) (3109:3109:3109))
-        (IOPATH dataa combout (318:318:318) (327:327:327))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~2\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2203:2203:2203) (2428:2428:2428))
-        (PORT datac (2395:2395:2395) (2605:2605:2605))
-        (PORT datad (2876:2876:2876) (3119:3119:3119))
-        (IOPATH dataa combout (287:287:287) (280:280:280))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~3\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2209:2209:2209) (2434:2434:2434))
-        (PORT datac (2398:2398:2398) (2603:2603:2603))
-        (PORT datad (2868:2868:2868) (3110:3110:3110))
-        (IOPATH dataa combout (287:287:287) (289:289:289))
-        (IOPATH datac combout (218:218:218) (216:216:216))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~4\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2208:2208:2208) (2434:2434:2434))
-        (PORT datac (2396:2396:2396) (2603:2603:2603))
-        (PORT datad (2866:2866:2866) (3115:3115:3115))
-        (IOPATH dataa combout (318:318:318) (323:323:323))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2206:2206:2206) (2433:2433:2433))
-        (PORT datac (2397:2397:2397) (2604:2604:2604))
-        (PORT datad (2873:2873:2873) (3111:3111:3111))
-        (IOPATH dataa combout (307:307:307) (306:306:306))
-        (IOPATH datac combout (220:220:220) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~6\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2209:2209:2209) (2433:2433:2433))
-        (PORT datac (2397:2397:2397) (2602:2602:2602))
-        (PORT datad (2868:2868:2868) (3110:3110:3110))
-        (IOPATH dataa combout (272:272:272) (269:269:269))
-        (IOPATH datac combout (218:218:218) (215:215:215))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~7\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2203:2203:2203) (2425:2425:2425))
-        (PORT datac (2395:2395:2395) (2606:2606:2606))
-        (PORT datad (2876:2876:2876) (3120:3120:3120))
-        (IOPATH dataa combout (273:273:273) (269:269:269))
-        (IOPATH datac combout (218:218:218) (216:216:216))
-        (IOPATH datad combout (119:119:119) (106:106:106))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_85c_slow.vho b/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_85c_slow.vho
deleted file mode 100644
index 833683ec..00000000
--- a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_85c_slow.vho
+++ /dev/null
@@ -1,412 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/24/2019 21:52:24"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	three_line_to_eight_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic
-	);
-END three_line_to_eight_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_AB4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_M8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_W20,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_N1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_U2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_T11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF three_line_to_eight_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \inst|33~0_combout\ : std_logic;
-SIGNAL \inst|33~1_combout\ : std_logic;
-SIGNAL \inst|33~2_combout\ : std_logic;
-SIGNAL \inst|33~3_combout\ : std_logic;
-SIGNAL \inst|33~4_combout\ : std_logic;
-SIGNAL \inst|33~5_combout\ : std_logic;
-SIGNAL \inst|33~6_combout\ : std_logic;
-SIGNAL \inst|33~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~6_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~5_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~4_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~3_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~2_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~1_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~0_combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\inst|ALT_INV_33~7_combout\ <= NOT \inst|33~7_combout\;
-\inst|ALT_INV_33~6_combout\ <= NOT \inst|33~6_combout\;
-\inst|ALT_INV_33~5_combout\ <= NOT \inst|33~5_combout\;
-\inst|ALT_INV_33~4_combout\ <= NOT \inst|33~4_combout\;
-\inst|ALT_INV_33~3_combout\ <= NOT \inst|33~3_combout\;
-\inst|ALT_INV_33~2_combout\ <= NOT \inst|33~2_combout\;
-\inst|ALT_INV_33~1_combout\ <= NOT \inst|33~1_combout\;
-\inst|ALT_INV_33~0_combout\ <= NOT \inst|33~0_combout\;
-
--- Location: IOOBUF_X7_Y0_N2
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~0_combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y7_N2
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~1_combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y13_N9
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~2_combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X41_Y3_N16
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~3_combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X0_Y12_N23
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~4_combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y7_N9
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~5_combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y26_N2
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~6_combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X0_Y9_N16
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~7_combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOIBUF_X0_Y9_N8
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y11_N1
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: IOIBUF_X16_Y0_N15
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: LCCOMB_X1_Y9_N16
-\inst|33~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~0_combout\ = (!\C~input_o\ & (!\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000101",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~0_combout\);
-
--- Location: LCCOMB_X1_Y9_N26
-\inst|33~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~1_combout\ = (!\C~input_o\ & (\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~1_combout\);
-
--- Location: LCCOMB_X1_Y9_N12
-\inst|33~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~2_combout\ = (!\C~input_o\ & (!\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000010100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~2_combout\);
-
--- Location: LCCOMB_X1_Y9_N30
-\inst|33~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~3_combout\ = (!\C~input_o\ & (\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0101000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~3_combout\);
-
--- Location: LCCOMB_X1_Y9_N24
-\inst|33~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~4_combout\ = (\C~input_o\ & (!\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~4_combout\);
-
--- Location: LCCOMB_X1_Y9_N18
-\inst|33~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~5_combout\ = (\C~input_o\ & (\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~5_combout\);
-
--- Location: LCCOMB_X1_Y9_N28
-\inst|33~6\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~6_combout\ = (\C~input_o\ & (!\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000101000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~6_combout\);
-
--- Location: LCCOMB_X1_Y9_N14
-\inst|33~7\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~7_combout\ = (\C~input_o\ & (\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1010000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~7_combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_85c_vhd_slow.sdo b/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_85c_vhd_slow.sdo
deleted file mode 100644
index 8930f205..00000000
--- a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_6_1200mv_85c_vhd_slow.sdo
+++ /dev/null
@@ -1,258 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "three_line_to_eight_decimal_decoder")
-  (DATE "10/24/2019 21:52:24")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y0\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1161:1161:1161) (1185:1185:1185))
-        (IOPATH i o (2049:2049:2049) (2100:2100:2100))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y1\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (627:627:627) (614:614:614))
-        (IOPATH i o (2214:2214:2214) (2226:2226:2226))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y2\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (625:625:625) (609:609:609))
-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y3\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (2026:2026:2026) (1949:1949:1949))
-        (IOPATH i o (2224:2224:2224) (2236:2236:2236))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y4\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (645:645:645) (627:627:627))
-        (IOPATH i o (2224:2224:2224) (2236:2236:2236))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y5\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (612:612:612) (606:606:606))
-        (IOPATH i o (2224:2224:2224) (2236:2236:2236))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y6\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1535:1535:1535) (1499:1499:1499))
-        (IOPATH i o (2214:2214:2214) (2226:2226:2226))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y7\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (333:333:333) (326:326:326))
-        (IOPATH i o (2234:2234:2234) (2246:2246:2246))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\C\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (765:765:765) (926:926:926))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\A\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (715:715:715) (876:876:876))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\B\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (699:699:699) (862:862:862))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2609:2609:2609) (2876:2876:2876))
-        (PORT datac (2792:2792:2792) (3056:3056:3056))
-        (PORT datad (3296:3296:3296) (3637:3637:3637))
-        (IOPATH dataa combout (371:371:371) (376:376:376))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~1\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2613:2613:2613) (2875:2875:2875))
-        (PORT datac (2792:2792:2792) (3053:3053:3053))
-        (PORT datad (3292:3292:3292) (3630:3630:3630))
-        (IOPATH dataa combout (356:356:356) (368:368:368))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~2\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2603:2603:2603) (2873:2873:2873))
-        (PORT datac (2791:2791:2791) (3056:3056:3056))
-        (PORT datad (3296:3296:3296) (3638:3638:3638))
-        (IOPATH dataa combout (325:325:325) (320:320:320))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~3\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2615:2615:2615) (2876:2876:2876))
-        (PORT datac (2793:2793:2793) (3054:3054:3054))
-        (PORT datad (3294:3294:3294) (3631:3631:3631))
-        (IOPATH dataa combout (324:324:324) (328:328:328))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~4\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2612:2612:2612) (2876:2876:2876))
-        (PORT datac (2791:2791:2791) (3054:3054:3054))
-        (PORT datad (3292:3292:3292) (3634:3634:3634))
-        (IOPATH dataa combout (354:354:354) (367:367:367))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2609:2609:2609) (2876:2876:2876))
-        (PORT datac (2792:2792:2792) (3056:3056:3056))
-        (PORT datad (3296:3296:3296) (3634:3634:3634))
-        (IOPATH dataa combout (341:341:341) (347:347:347))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~6\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2614:2614:2614) (2876:2876:2876))
-        (PORT datac (2792:2792:2792) (3053:3053:3053))
-        (PORT datad (3294:3294:3294) (3631:3631:3631))
-        (IOPATH dataa combout (303:303:303) (308:308:308))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~7\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2603:2603:2603) (2874:2874:2874))
-        (PORT datac (2791:2791:2791) (3057:3057:3057))
-        (PORT datad (3296:3296:3296) (3636:3636:3636))
-        (IOPATH dataa combout (304:304:304) (307:307:307))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_min_1200mv_0c_fast.vho b/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_min_1200mv_0c_fast.vho
deleted file mode 100644
index 833683ec..00000000
--- a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_min_1200mv_0c_fast.vho
+++ /dev/null
@@ -1,412 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus II 32-bit"
--- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
--- DATE "10/24/2019 21:52:24"
-
--- 
--- Device: Altera EP3C16F484C6 Package FBGA484
--- 
-
--- 
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
--- 
-
-LIBRARY CYCLONEIII;
-LIBRARY IEEE;
-USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY 	three_line_to_eight_decimal_decoder IS
-    PORT (
-	Y0 : OUT std_logic;
-	A : IN std_logic;
-	B : IN std_logic;
-	C : IN std_logic;
-	Y1 : OUT std_logic;
-	Y2 : OUT std_logic;
-	Y3 : OUT std_logic;
-	Y4 : OUT std_logic;
-	Y5 : OUT std_logic;
-	Y6 : OUT std_logic;
-	Y7 : OUT std_logic
-	);
-END three_line_to_eight_decimal_decoder;
-
--- Design Ports Information
--- Y0	=>  Location: PIN_AB4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y1	=>  Location: PIN_M8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y2	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y3	=>  Location: PIN_W20,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y4	=>  Location: PIN_N1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y5	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y6	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- Y7	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- C	=>  Location: PIN_U2,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- A	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- B	=>  Location: PIN_T11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-ARCHITECTURE structure OF three_line_to_eight_decimal_decoder IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Y0 : std_logic;
-SIGNAL ww_A : std_logic;
-SIGNAL ww_B : std_logic;
-SIGNAL ww_C : std_logic;
-SIGNAL ww_Y1 : std_logic;
-SIGNAL ww_Y2 : std_logic;
-SIGNAL ww_Y3 : std_logic;
-SIGNAL ww_Y4 : std_logic;
-SIGNAL ww_Y5 : std_logic;
-SIGNAL ww_Y6 : std_logic;
-SIGNAL ww_Y7 : std_logic;
-SIGNAL \Y0~output_o\ : std_logic;
-SIGNAL \Y1~output_o\ : std_logic;
-SIGNAL \Y2~output_o\ : std_logic;
-SIGNAL \Y3~output_o\ : std_logic;
-SIGNAL \Y4~output_o\ : std_logic;
-SIGNAL \Y5~output_o\ : std_logic;
-SIGNAL \Y6~output_o\ : std_logic;
-SIGNAL \Y7~output_o\ : std_logic;
-SIGNAL \C~input_o\ : std_logic;
-SIGNAL \A~input_o\ : std_logic;
-SIGNAL \B~input_o\ : std_logic;
-SIGNAL \inst|33~0_combout\ : std_logic;
-SIGNAL \inst|33~1_combout\ : std_logic;
-SIGNAL \inst|33~2_combout\ : std_logic;
-SIGNAL \inst|33~3_combout\ : std_logic;
-SIGNAL \inst|33~4_combout\ : std_logic;
-SIGNAL \inst|33~5_combout\ : std_logic;
-SIGNAL \inst|33~6_combout\ : std_logic;
-SIGNAL \inst|33~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~7_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~6_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~5_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~4_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~3_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~2_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~1_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_33~0_combout\ : std_logic;
-
-BEGIN
-
-Y0 <= ww_Y0;
-ww_A <= A;
-ww_B <= B;
-ww_C <= C;
-Y1 <= ww_Y1;
-Y2 <= ww_Y2;
-Y3 <= ww_Y3;
-Y4 <= ww_Y4;
-Y5 <= ww_Y5;
-Y6 <= ww_Y6;
-Y7 <= ww_Y7;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\inst|ALT_INV_33~7_combout\ <= NOT \inst|33~7_combout\;
-\inst|ALT_INV_33~6_combout\ <= NOT \inst|33~6_combout\;
-\inst|ALT_INV_33~5_combout\ <= NOT \inst|33~5_combout\;
-\inst|ALT_INV_33~4_combout\ <= NOT \inst|33~4_combout\;
-\inst|ALT_INV_33~3_combout\ <= NOT \inst|33~3_combout\;
-\inst|ALT_INV_33~2_combout\ <= NOT \inst|33~2_combout\;
-\inst|ALT_INV_33~1_combout\ <= NOT \inst|33~1_combout\;
-\inst|ALT_INV_33~0_combout\ <= NOT \inst|33~0_combout\;
-
--- Location: IOOBUF_X7_Y0_N2
-\Y0~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~0_combout\,
-	devoe => ww_devoe,
-	o => \Y0~output_o\);
-
--- Location: IOOBUF_X0_Y7_N2
-\Y1~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~1_combout\,
-	devoe => ww_devoe,
-	o => \Y1~output_o\);
-
--- Location: IOOBUF_X0_Y13_N9
-\Y2~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~2_combout\,
-	devoe => ww_devoe,
-	o => \Y2~output_o\);
-
--- Location: IOOBUF_X41_Y3_N16
-\Y3~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~3_combout\,
-	devoe => ww_devoe,
-	o => \Y3~output_o\);
-
--- Location: IOOBUF_X0_Y12_N23
-\Y4~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~4_combout\,
-	devoe => ww_devoe,
-	o => \Y4~output_o\);
-
--- Location: IOOBUF_X0_Y7_N9
-\Y5~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~5_combout\,
-	devoe => ww_devoe,
-	o => \Y5~output_o\);
-
--- Location: IOOBUF_X0_Y26_N2
-\Y6~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~6_combout\,
-	devoe => ww_devoe,
-	o => \Y6~output_o\);
-
--- Location: IOOBUF_X0_Y9_N16
-\Y7~output\ : cycloneiii_io_obuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
-	i => \inst|ALT_INV_33~7_combout\,
-	devoe => ww_devoe,
-	o => \Y7~output_o\);
-
--- Location: IOIBUF_X0_Y9_N8
-\C~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_C,
-	o => \C~input_o\);
-
--- Location: IOIBUF_X0_Y11_N1
-\A~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_A,
-	o => \A~input_o\);
-
--- Location: IOIBUF_X16_Y0_N15
-\B~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_B,
-	o => \B~input_o\);
-
--- Location: LCCOMB_X1_Y9_N16
-\inst|33~0\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~0_combout\ = (!\C~input_o\ & (!\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000000101",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~0_combout\);
-
--- Location: LCCOMB_X1_Y9_N26
-\inst|33~1\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~1_combout\ = (!\C~input_o\ & (\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000001010000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~1_combout\);
-
--- Location: LCCOMB_X1_Y9_N12
-\inst|33~2\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~2_combout\ = (!\C~input_o\ & (!\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000010100000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~2_combout\);
-
--- Location: LCCOMB_X1_Y9_N30
-\inst|33~3\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~3_combout\ = (!\C~input_o\ & (\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0101000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~3_combout\);
-
--- Location: LCCOMB_X1_Y9_N24
-\inst|33~4\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~4_combout\ = (\C~input_o\ & (!\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000000001010",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~4_combout\);
-
--- Location: LCCOMB_X1_Y9_N18
-\inst|33~5\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~5_combout\ = (\C~input_o\ & (\A~input_o\ & !\B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000000010100000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~5_combout\);
-
--- Location: LCCOMB_X1_Y9_N28
-\inst|33~6\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~6_combout\ = (\C~input_o\ & (!\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "0000101000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~6_combout\);
-
--- Location: LCCOMB_X1_Y9_N14
-\inst|33~7\ : cycloneiii_lcell_comb
--- Equation(s):
--- \inst|33~7_combout\ = (\C~input_o\ & (\A~input_o\ & \B~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
-	lut_mask => "1010000000000000",
-	sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
-	dataa => \C~input_o\,
-	datac => \A~input_o\,
-	datad => \B~input_o\,
-	combout => \inst|33~7_combout\);
-
-ww_Y0 <= \Y0~output_o\;
-
-ww_Y1 <= \Y1~output_o\;
-
-ww_Y2 <= \Y2~output_o\;
-
-ww_Y3 <= \Y3~output_o\;
-
-ww_Y4 <= \Y4~output_o\;
-
-ww_Y5 <= \Y5~output_o\;
-
-ww_Y6 <= \Y6~output_o\;
-
-ww_Y7 <= \Y7~output_o\;
-END structure;
-
-
diff --git a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_min_1200mv_0c_vhd_fast.sdo b/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_min_1200mv_0c_vhd_fast.sdo
deleted file mode 100644
index d29d93cf..00000000
--- a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_min_1200mv_0c_vhd_fast.sdo
+++ /dev/null
@@ -1,258 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Fast Corner delays for the design using part EP3C16F484C6,
-// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "three_line_to_eight_decimal_decoder")
-  (DATE "10/24/2019 21:52:24")
-  (VENDOR "Altera")
-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
-  (TIMESCALE 1 ps)
-
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y0\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (684:684:684) (624:624:624))
-        (IOPATH i o (1331:1331:1331) (1340:1340:1340))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y1\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (377:377:377) (334:334:334))
-        (IOPATH i o (1450:1450:1450) (1466:1466:1466))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y2\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (382:382:382) (334:334:334))
-        (IOPATH i o (1440:1440:1440) (1456:1456:1456))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y3\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1218:1218:1218) (1070:1070:1070))
-        (IOPATH i o (1460:1460:1460) (1476:1476:1476))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y4\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (381:381:381) (352:352:352))
-        (IOPATH i o (1460:1460:1460) (1476:1476:1476))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y5\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (372:372:372) (331:331:331))
-        (IOPATH i o (1460:1460:1460) (1476:1476:1476))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y6\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (943:943:943) (861:861:861))
-        (IOPATH i o (1450:1450:1450) (1466:1466:1466))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y7\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (185:185:185) (164:164:164))
-        (IOPATH i o (1470:1470:1470) (1486:1486:1486))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\C\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (421:421:421) (803:803:803))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\A\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (371:371:371) (753:753:753))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_ibuf")
-    (INSTANCE \\B\~input\\)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH i o (372:372:372) (754:754:754))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~0\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1500:1500:1500) (1695:1695:1695))
-        (PORT datac (1635:1635:1635) (1823:1823:1823))
-        (PORT datad (1936:1936:1936) (2183:2183:2183))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datac combout (120:120:120) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~1\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1504:1504:1504) (1696:1696:1696))
-        (PORT datac (1635:1635:1635) (1821:1821:1821))
-        (PORT datad (1930:1930:1930) (2174:2174:2174))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~2\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1499:1499:1499) (1691:1691:1691))
-        (PORT datac (1637:1637:1637) (1825:1825:1825))
-        (PORT datad (1937:1937:1937) (2184:2184:2184))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datac combout (119:119:119) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~3\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1505:1505:1505) (1697:1697:1697))
-        (PORT datac (1636:1636:1636) (1823:1823:1823))
-        (PORT datad (1931:1931:1931) (2175:2175:2175))
-        (IOPATH dataa combout (158:158:158) (157:157:157))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~4\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1503:1503:1503) (1698:1698:1698))
-        (PORT datac (1634:1634:1634) (1822:1822:1822))
-        (PORT datad (1933:1933:1933) (2180:2180:2180))
-        (IOPATH dataa combout (170:170:170) (163:163:163))
-        (IOPATH datac combout (120:120:120) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1503:1503:1503) (1693:1693:1693))
-        (PORT datac (1634:1634:1634) (1821:1821:1821))
-        (PORT datad (1933:1933:1933) (2178:2178:2178))
-        (IOPATH dataa combout (170:170:170) (163:163:163))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~6\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1505:1505:1505) (1697:1697:1697))
-        (PORT datac (1635:1635:1635) (1822:1822:1822))
-        (PORT datad (1930:1930:1930) (2175:2175:2175))
-        (IOPATH dataa combout (165:165:165) (163:163:163))
-        (IOPATH datac combout (119:119:119) (125:125:125))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~7\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (1500:1500:1500) (1689:1689:1689))
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-        (PORT datad (1938:1938:1938) (2184:2184:2184))
-        (IOPATH dataa combout (166:166:166) (163:163:163))
-        (IOPATH datac combout (119:119:119) (124:124:124))
-        (IOPATH datad combout (68:68:68) (63:63:63))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_modelsim.xrf b/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_modelsim.xrf
deleted file mode 100644
index 133c2faf..00000000
--- a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_modelsim.xrf
+++ /dev/null
@@ -1,25 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.vwf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cbx.xml
-source_file = 1, /home/timmy/altera/13.1/quartus/libraries/others/maxplus2/74139.bdf
-design_name = three_line_to_eight_decimal_decoder
-instance = comp, \Y0~output\, Y0~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y1~output\, Y1~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y2~output\, Y2~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y3~output\, Y3~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y4~output\, Y4~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y5~output\, Y5~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y6~output\, Y6~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y7~output\, Y7~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \C~input\, C~input, three_line_to_eight_decimal_decoder, 1
-instance = comp, \A~input\, A~input, three_line_to_eight_decimal_decoder, 1
-instance = comp, \B~input\, B~input, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~0\, inst|33~0, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~1\, inst|33~1, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~2\, inst|33~2, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~3\, inst|33~3, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~4\, inst|33~4, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~5\, inst|33~5, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~6\, inst|33~6, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~7\, inst|33~7, three_line_to_eight_decimal_decoder, 1
diff --git a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_vhd.sdo b/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_vhd.sdo
deleted file mode 100644
index 8930f205..00000000
--- a/CH6/CH6-1/simulation/modelsim/three_line_to_eight_decimal_decoder_vhd.sdo
+++ /dev/null
@@ -1,258 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-//
-// This file contains Slow Corner delays for the design using part EP3C16F484C6,
-// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
-//
-
-// 
-// This SDF file should be used for ModelSim-Altera (VHDL) only
-// 
-
-(DELAYFILE
-  (SDFVERSION "2.1")
-  (DESIGN "three_line_to_eight_decimal_decoder")
-  (DATE "10/24/2019 21:52:24")
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-  (PROGRAM "Quartus II 32-bit")
-  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
-  (DIVIDER .)
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-  )
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-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y2\~output\\)
-    (DELAY
-      (ABSOLUTE
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-        (IOPATH i o (2204:2204:2204) (2216:2216:2216))
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-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
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-  )
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-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y4\~output\\)
-    (DELAY
-      (ABSOLUTE
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-        (IOPATH i o (2224:2224:2224) (2236:2236:2236))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y5\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (612:612:612) (606:606:606))
-        (IOPATH i o (2224:2224:2224) (2236:2236:2236))
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-  )
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-    (CELLTYPE "cycloneiii_io_obuf")
-    (INSTANCE \\Y6\~output\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT i (1535:1535:1535) (1499:1499:1499))
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-  (CELL
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-    (DELAY
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-        (IOPATH datac combout (241:241:241) (241:241:241))
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-        (PORT dataa (2612:2612:2612) (2876:2876:2876))
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-        (PORT datad (3292:3292:3292) (3634:3634:3634))
-        (IOPATH dataa combout (354:354:354) (367:367:367))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~5\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2609:2609:2609) (2876:2876:2876))
-        (PORT datac (2792:2792:2792) (3056:3056:3056))
-        (PORT datad (3296:3296:3296) (3634:3634:3634))
-        (IOPATH dataa combout (341:341:341) (347:347:347))
-        (IOPATH datac combout (243:243:243) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~6\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2614:2614:2614) (2876:2876:2876))
-        (PORT datac (2792:2792:2792) (3053:3053:3053))
-        (PORT datad (3294:3294:3294) (3631:3631:3631))
-        (IOPATH dataa combout (303:303:303) (308:308:308))
-        (IOPATH datac combout (241:241:241) (241:241:241))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "cycloneiii_lcell_comb")
-    (INSTANCE \\inst\|33\~7\\)
-    (DELAY
-      (ABSOLUTE
-        (PORT dataa (2603:2603:2603) (2874:2874:2874))
-        (PORT datac (2791:2791:2791) (3057:3057:3057))
-        (PORT datad (3296:3296:3296) (3636:3636:3636))
-        (IOPATH dataa combout (304:304:304) (307:307:307))
-        (IOPATH datac combout (241:241:241) (242:242:242))
-        (IOPATH datad combout (130:130:130) (120:120:120))
-      )
-    )
-  )
-)
diff --git a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.do b/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.do
deleted file mode 100644
index 13e39b5a..00000000
--- a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.do
+++ /dev/null
@@ -1,10 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vlog -work work BCD_to_decimal_decoder.vo
-vlog -work work BCD_to_decimal_decoder.vwf.vt
-vsim -novopt -c -t 1ps -L cycloneiii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.BCD_to_decimal_decoder_vlg_vec_tst -voptargs="+acc"
-vcd file -direction BCD_to_decimal_decoder.msim.vcd
-vcd add -internal BCD_to_decimal_decoder_vlg_vec_tst/*
-vcd add -internal BCD_to_decimal_decoder_vlg_vec_tst/i1/*
-run -all
-quit -f
diff --git a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.msim.vcd b/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.msim.vcd
deleted file mode 100644
index 1f8cb21a..00000000
--- a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.msim.vcd
+++ /dev/null
@@ -1,216 +0,0 @@
-$comment
-	File created using the following command:
-		vcd file BCD_to_decimal_decoder.msim.vcd -direction
-$end
-$date
-	Thu Oct 17 23:24:17 2019
-$end
-$version
-	ModelSim Version 10.1d
-$end
-$timescale
-	1ps
-$end
-$scope module BCD_to_decimal_decoder_vlg_vec_tst $end
-$var reg 1 ! A $end
-$var reg 1 " B $end
-$var reg 1 # C $end
-$var reg 1 $ D $end
-$var wire 1 % Y0 $end
-$var wire 1 & Y1 $end
-$var wire 1 ' Y2 $end
-$var wire 1 ( Y3 $end
-$var wire 1 ) Y4 $end
-$var wire 1 * Y5 $end
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-$var wire 1 - Y8 $end
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-$var wire 1 / sampler $end
-$scope module i1 $end
-$var wire 1 0 gnd $end
-$var wire 1 1 vcc $end
-$var wire 1 2 unknown $end
-$var tri1 1 3 devclrn $end
-$var tri1 1 4 devpor $end
-$var tri1 1 5 devoe $end
-$var wire 1 6 Y0~output_o $end
-$var wire 1 7 Y1~output_o $end
-$var wire 1 8 Y2~output_o $end
-$var wire 1 9 Y3~output_o $end
-$var wire 1 : Y4~output_o $end
-$var wire 1 ; Y5~output_o $end
-$var wire 1 < Y6~output_o $end
-$var wire 1 = Y7~output_o $end
-$var wire 1 > Y8~output_o $end
-$var wire 1 ? Y9~output_o $end
-$var wire 1 @ C~input_o $end
-$var wire 1 A D~input_o $end
-$var wire 1 B A~input_o $end
-$var wire 1 C B~input_o $end
-$var wire 1 D inst~combout $end
-$var wire 1 E inst1~combout $end
-$var wire 1 F inst2~combout $end
-$var wire 1 G inst3~combout $end
-$var wire 1 H inst4~combout $end
-$var wire 1 I inst5~combout $end
-$var wire 1 J inst6~combout $end
-$var wire 1 K inst7~combout $end
-$var wire 1 L inst8~combout $end
-$var wire 1 M inst9~combout $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
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-$end
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diff --git a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.sft b/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.sft
deleted file mode 100644
index 06a2ca45..00000000
--- a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (Verilog)"
diff --git a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.sim.vwf b/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.sim.vwf
deleted file mode 100644
index e25f948d..00000000
--- a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.sim.vwf
+++ /dev/null
@@ -1,522 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-
-HEADER
-{
-	VERSION = 1;
-	TIME_UNIT = ns;
-	DATA_OFFSET = 0.0;
-	DATA_DURATION = 10000.0;
-	SIMULATION_TIME = 0.0;
-	GRID_PHASE = 0.0;
-	GRID_PERIOD = 1000.0;
-	GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("A")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("B")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("C")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("D")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y0")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y1")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y2")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y3")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y4")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y5")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y6")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y7")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y8")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y9")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-TRANSITION_LIST("A")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("B")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 2000.0;
-			LEVEL 1 FOR 2000.0;
-			LEVEL 0 FOR 2000.0;
-			LEVEL 1 FOR 2000.0;
-			LEVEL 0 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("C")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 4000.0;
-			LEVEL 1 FOR 4000.0;
-			LEVEL 0 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("D")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 8000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y0")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 9000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y1")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 8000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y2")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 2000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 7000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y3")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 3000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 6000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y4")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 4000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 5000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y5")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 5000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 4000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y6")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 6000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 3000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y7")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 7000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y8")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 8000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y9")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 9000.0;
-			LEVEL 1 FOR 1000.0;
-		}
-	}
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "A";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 0;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "B";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 1;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "C";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 2;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "D";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 3;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y0";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 4;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y1";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 5;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y2";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 6;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y3";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 7;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y4";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 8;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y5";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 9;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y6";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 10;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y7";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 11;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y8";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 12;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y9";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 13;
-	TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
-	TIME = 0;
-	MASTER = TRUE;
-}
-;
diff --git a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.vo b/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.vo
deleted file mode 100644
index 49d822fb..00000000
--- a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.vo
+++ /dev/null
@@ -1,475 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-// VENDOR "Altera"
-// PROGRAM "Quartus II 32-bit"
-// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
-// DATE "10/17/2019 23:25:08"
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-// 
-// This Verilog file should be used for ModelSim-Altera (Verilog) only
-// 
-
-`timescale 1 ps/ 1 ps
-
-module BCD_to_decimal_decoder (
-	Y0,
-	A,
-	B,
-	C,
-	D,
-	Y1,
-	Y2,
-	Y3,
-	Y4,
-	Y5,
-	Y6,
-	Y7,
-	Y8,
-	Y9);
-output 	Y0;
-input 	A;
-input 	B;
-input 	C;
-input 	D;
-output 	Y1;
-output 	Y2;
-output 	Y3;
-output 	Y4;
-output 	Y5;
-output 	Y6;
-output 	Y7;
-output 	Y8;
-output 	Y9;
-
-// Design Ports Information
-// Y0	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y1	=>  Location: PIN_U1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y2	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y3	=>  Location: PIN_V6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y4	=>  Location: PIN_R10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y5	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y6	=>  Location: PIN_P3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y7	=>  Location: PIN_V3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y8	=>  Location: PIN_T9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y9	=>  Location: PIN_T3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// A	=>  Location: PIN_Y1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// D	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// B	=>  Location: PIN_T8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// C	=>  Location: PIN_T4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-tri1 devclrn;
-tri1 devpor;
-tri1 devoe;
-wire \Y0~output_o ;
-wire \Y1~output_o ;
-wire \Y2~output_o ;
-wire \Y3~output_o ;
-wire \Y4~output_o ;
-wire \Y5~output_o ;
-wire \Y6~output_o ;
-wire \Y7~output_o ;
-wire \Y8~output_o ;
-wire \Y9~output_o ;
-wire \C~input_o ;
-wire \D~input_o ;
-wire \A~input_o ;
-wire \B~input_o ;
-wire \inst~combout ;
-wire \inst1~combout ;
-wire \inst2~combout ;
-wire \inst3~combout ;
-wire \inst4~combout ;
-wire \inst5~combout ;
-wire \inst6~combout ;
-wire \inst7~combout ;
-wire \inst8~combout ;
-wire \inst9~combout ;
-
-
-// Location: IOOBUF_X0_Y7_N9
-cycloneiii_io_obuf \Y0~output (
-	.i(\inst~combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y0~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y0~output .bus_hold = "false";
-defparam \Y0~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y9_N16
-cycloneiii_io_obuf \Y1~output (
-	.i(\inst1~combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y1~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y1~output .bus_hold = "false";
-defparam \Y1~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y12_N9
-cycloneiii_io_obuf \Y2~output (
-	.i(\inst2~combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y2~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y2~output .bus_hold = "false";
-defparam \Y2~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N2
-cycloneiii_io_obuf \Y3~output (
-	.i(\inst3~combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y3~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y3~output .bus_hold = "false";
-defparam \Y3~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N16
-cycloneiii_io_obuf \Y4~output (
-	.i(\inst4~combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y4~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y4~output .bus_hold = "false";
-defparam \Y4~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y8_N9
-cycloneiii_io_obuf \Y5~output (
-	.i(\inst5~combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y5~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y5~output .bus_hold = "false";
-defparam \Y5~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y9_N2
-cycloneiii_io_obuf \Y6~output (
-	.i(\inst6~combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y6~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y6~output .bus_hold = "false";
-defparam \Y6~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y4_N2
-cycloneiii_io_obuf \Y7~output (
-	.i(\inst7~combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y7~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y7~output .bus_hold = "false";
-defparam \Y7~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N9
-cycloneiii_io_obuf \Y8~output (
-	.i(\inst8~combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y8~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y8~output .bus_hold = "false";
-defparam \Y8~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y6_N16
-cycloneiii_io_obuf \Y9~output (
-	.i(\inst9~combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y9~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y9~output .bus_hold = "false";
-defparam \Y9~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y4_N22
-cycloneiii_io_ibuf \C~input (
-	.i(C),
-	.ibar(gnd),
-	.o(\C~input_o ));
-// synopsys translate_off
-defparam \C~input .bus_hold = "false";
-defparam \C~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y10_N15
-cycloneiii_io_ibuf \D~input (
-	.i(D),
-	.ibar(gnd),
-	.o(\D~input_o ));
-// synopsys translate_off
-defparam \D~input .bus_hold = "false";
-defparam \D~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y6_N8
-cycloneiii_io_ibuf \A~input (
-	.i(A),
-	.ibar(gnd),
-	.o(\A~input_o ));
-// synopsys translate_off
-defparam \A~input .bus_hold = "false";
-defparam \A~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N22
-cycloneiii_io_ibuf \B~input (
-	.i(B),
-	.ibar(gnd),
-	.o(\B~input_o ));
-// synopsys translate_off
-defparam \B~input .bus_hold = "false";
-defparam \B~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y4_N0
-cycloneiii_lcell_comb inst(
-// Equation(s):
-// \inst~combout  = (!\C~input_o  & (!\D~input_o  & (!\A~input_o  & !\B~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\D~input_o ),
-	.datac(\A~input_o ),
-	.datad(\B~input_o ),
-	.cin(gnd),
-	.combout(\inst~combout ),
-	.cout());
-// synopsys translate_off
-defparam inst.lut_mask = 16'h0001;
-defparam inst.sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y4_N10
-cycloneiii_lcell_comb inst1(
-// Equation(s):
-// \inst1~combout  = (!\C~input_o  & (!\D~input_o  & (\A~input_o  & !\B~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\D~input_o ),
-	.datac(\A~input_o ),
-	.datad(\B~input_o ),
-	.cin(gnd),
-	.combout(\inst1~combout ),
-	.cout());
-// synopsys translate_off
-defparam inst1.lut_mask = 16'h0010;
-defparam inst1.sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y4_N12
-cycloneiii_lcell_comb inst2(
-// Equation(s):
-// \inst2~combout  = (!\C~input_o  & (!\D~input_o  & (!\A~input_o  & \B~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\D~input_o ),
-	.datac(\A~input_o ),
-	.datad(\B~input_o ),
-	.cin(gnd),
-	.combout(\inst2~combout ),
-	.cout());
-// synopsys translate_off
-defparam inst2.lut_mask = 16'h0100;
-defparam inst2.sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y4_N30
-cycloneiii_lcell_comb inst3(
-// Equation(s):
-// \inst3~combout  = (!\C~input_o  & (!\D~input_o  & (\A~input_o  & \B~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\D~input_o ),
-	.datac(\A~input_o ),
-	.datad(\B~input_o ),
-	.cin(gnd),
-	.combout(\inst3~combout ),
-	.cout());
-// synopsys translate_off
-defparam inst3.lut_mask = 16'h1000;
-defparam inst3.sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y4_N16
-cycloneiii_lcell_comb inst4(
-// Equation(s):
-// \inst4~combout  = (\C~input_o  & (!\D~input_o  & (!\A~input_o  & !\B~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\D~input_o ),
-	.datac(\A~input_o ),
-	.datad(\B~input_o ),
-	.cin(gnd),
-	.combout(\inst4~combout ),
-	.cout());
-// synopsys translate_off
-defparam inst4.lut_mask = 16'h0002;
-defparam inst4.sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y4_N26
-cycloneiii_lcell_comb inst5(
-// Equation(s):
-// \inst5~combout  = (\C~input_o  & (!\D~input_o  & (\A~input_o  & !\B~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\D~input_o ),
-	.datac(\A~input_o ),
-	.datad(\B~input_o ),
-	.cin(gnd),
-	.combout(\inst5~combout ),
-	.cout());
-// synopsys translate_off
-defparam inst5.lut_mask = 16'h0020;
-defparam inst5.sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y4_N4
-cycloneiii_lcell_comb inst6(
-// Equation(s):
-// \inst6~combout  = (\C~input_o  & (!\D~input_o  & (!\A~input_o  & \B~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\D~input_o ),
-	.datac(\A~input_o ),
-	.datad(\B~input_o ),
-	.cin(gnd),
-	.combout(\inst6~combout ),
-	.cout());
-// synopsys translate_off
-defparam inst6.lut_mask = 16'h0200;
-defparam inst6.sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y4_N14
-cycloneiii_lcell_comb inst7(
-// Equation(s):
-// \inst7~combout  = (\C~input_o  & (!\D~input_o  & (\A~input_o  & \B~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\D~input_o ),
-	.datac(\A~input_o ),
-	.datad(\B~input_o ),
-	.cin(gnd),
-	.combout(\inst7~combout ),
-	.cout());
-// synopsys translate_off
-defparam inst7.lut_mask = 16'h2000;
-defparam inst7.sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y4_N24
-cycloneiii_lcell_comb inst8(
-// Equation(s):
-// \inst8~combout  = (!\C~input_o  & (\D~input_o  & (!\A~input_o  & !\B~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\D~input_o ),
-	.datac(\A~input_o ),
-	.datad(\B~input_o ),
-	.cin(gnd),
-	.combout(\inst8~combout ),
-	.cout());
-// synopsys translate_off
-defparam inst8.lut_mask = 16'h0004;
-defparam inst8.sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y4_N2
-cycloneiii_lcell_comb inst9(
-// Equation(s):
-// \inst9~combout  = (!\C~input_o  & (\D~input_o  & (\A~input_o  & !\B~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\D~input_o ),
-	.datac(\A~input_o ),
-	.datad(\B~input_o ),
-	.cin(gnd),
-	.combout(\inst9~combout ),
-	.cout());
-// synopsys translate_off
-defparam inst9.lut_mask = 16'h0040;
-defparam inst9.sum_lutc_input = "datac";
-// synopsys translate_on
-
-assign Y0 = \Y0~output_o ;
-
-assign Y1 = \Y1~output_o ;
-
-assign Y2 = \Y2~output_o ;
-
-assign Y3 = \Y3~output_o ;
-
-assign Y4 = \Y4~output_o ;
-
-assign Y5 = \Y5~output_o ;
-
-assign Y6 = \Y6~output_o ;
-
-assign Y7 = \Y7~output_o ;
-
-assign Y8 = \Y8~output_o ;
-
-assign Y9 = \Y9~output_o ;
-
-endmodule
diff --git a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.vwf.vt b/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.vwf.vt
deleted file mode 100644
index a2404dbf..00000000
--- a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder.vwf.vt
+++ /dev/null
@@ -1,513 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-// *****************************************************************************
-// This file contains a Verilog test bench with test vectors .The test vectors  
-// are exported from a vector file in the Quartus Waveform Editor and apply to  
-// the top level entity of the current Quartus project .The user can use this   
-// testbench to simulate his design using a third-party simulation tool .       
-// *****************************************************************************
-// Generated on "10/17/2019 23:24:11"
-                                                                        
-// Verilog Self-Checking Test Bench (with test vectors) for design :    BCD_to_decimal_decoder
-// 
-// Simulation tool : 3rd Party
-// 
-
-`timescale 1 ps/ 1 ps
-module BCD_to_decimal_decoder_vlg_sample_tst(
-	A,
-	B,
-	C,
-	D,
-	sampler_tx
-);
-input  A;
-input  B;
-input  C;
-input  D;
-output sampler_tx;
-
-reg sample;
-time current_time;
-always @(A or B or C or D)
-                                                                                
-begin                                                 
- if ($realtime > 0)                                   
- begin                                                
-	if ($realtime == 0 || $realtime != current_time)  
-	begin									          
-		if (sample === 1'bx)                          
-			sample = 0;                               
-		else                                          
-			sample = ~sample;                         
-	end										          
-	current_time = $realtime;					      
- end                                                  
-end                                                   
-
-assign sampler_tx = sample;
-endmodule
-
-module BCD_to_decimal_decoder_vlg_check_tst (
-	Y0,
-	Y1,
-	Y2,
-	Y3,
-	Y4,
-	Y5,
-	Y6,
-	Y7,
-	Y8,
-	Y9,
-	sampler_rx
-);
-input  Y0;
-input  Y1;
-input  Y2;
-input  Y3;
-input  Y4;
-input  Y5;
-input  Y6;
-input  Y7;
-input  Y8;
-input  Y9;
-input sampler_rx;
-
-reg  Y0_expected;
-reg  Y1_expected;
-reg  Y2_expected;
-reg  Y3_expected;
-reg  Y4_expected;
-reg  Y5_expected;
-reg  Y6_expected;
-reg  Y7_expected;
-reg  Y8_expected;
-reg  Y9_expected;
-
-reg  Y0_prev;
-reg  Y1_prev;
-reg  Y2_prev;
-reg  Y3_prev;
-reg  Y4_prev;
-reg  Y5_prev;
-reg  Y6_prev;
-reg  Y7_prev;
-reg  Y8_prev;
-reg  Y9_prev;
-
-reg  Y0_expected_prev;
-reg  Y1_expected_prev;
-reg  Y2_expected_prev;
-reg  Y3_expected_prev;
-reg  Y4_expected_prev;
-reg  Y5_expected_prev;
-reg  Y6_expected_prev;
-reg  Y7_expected_prev;
-reg  Y8_expected_prev;
-reg  Y9_expected_prev;
-
-reg  last_Y0_exp;
-reg  last_Y1_exp;
-reg  last_Y2_exp;
-reg  last_Y3_exp;
-reg  last_Y4_exp;
-reg  last_Y5_exp;
-reg  last_Y6_exp;
-reg  last_Y7_exp;
-reg  last_Y8_exp;
-reg  last_Y9_exp;
-
-reg trigger;
-
-integer i;
-integer nummismatches;
-
-reg [1:10] on_first_change ;
-
-
-initial
-begin
-trigger = 0;
-i = 0;
-nummismatches = 0;
-on_first_change = 10'b1;
-end
-
-// update real /o prevs
-
-always @(trigger)
-begin
-	Y0_prev = Y0;
-	Y1_prev = Y1;
-	Y2_prev = Y2;
-	Y3_prev = Y3;
-	Y4_prev = Y4;
-	Y5_prev = Y5;
-	Y6_prev = Y6;
-	Y7_prev = Y7;
-	Y8_prev = Y8;
-	Y9_prev = Y9;
-end
-
-// update expected /o prevs
-
-always @(trigger)
-begin
-	Y0_expected_prev = Y0_expected;
-	Y1_expected_prev = Y1_expected;
-	Y2_expected_prev = Y2_expected;
-	Y3_expected_prev = Y3_expected;
-	Y4_expected_prev = Y4_expected;
-	Y5_expected_prev = Y5_expected;
-	Y6_expected_prev = Y6_expected;
-	Y7_expected_prev = Y7_expected;
-	Y8_expected_prev = Y8_expected;
-	Y9_expected_prev = Y9_expected;
-end
-
-
-
-// expected Y0
-initial
-begin
-	Y0_expected = 1'bX;
-	Y0_expected = #999000 1'b0;
-end 
-
-// expected Y1
-initial
-begin
-	Y1_expected = 1'bX;
-	Y1_expected = #999000 1'b0;
-end 
-
-// expected Y2
-initial
-begin
-	Y2_expected = 1'bX;
-	Y2_expected = #999000 1'b0;
-end 
-
-// expected Y3
-initial
-begin
-	Y3_expected = 1'bX;
-	Y3_expected = #999000 1'b0;
-end 
-
-// expected Y4
-initial
-begin
-	Y4_expected = 1'bX;
-	Y4_expected = #999000 1'b0;
-end 
-
-// expected Y5
-initial
-begin
-	Y5_expected = 1'bX;
-	Y5_expected = #999000 1'b0;
-end 
-
-// expected Y6
-initial
-begin
-	Y6_expected = 1'bX;
-	Y6_expected = #999000 1'b0;
-end 
-
-// expected Y7
-initial
-begin
-	Y7_expected = 1'bX;
-	Y7_expected = #999000 1'b0;
-end 
-
-// expected Y8
-initial
-begin
-	Y8_expected = 1'bX;
-	Y8_expected = #999000 1'b0;
-end 
-
-// expected Y9
-initial
-begin
-	Y9_expected = 1'bX;
-	Y9_expected = #999000 1'b0;
-end 
-// generate trigger
-always @(Y0_expected or Y0 or Y1_expected or Y1 or Y2_expected or Y2 or Y3_expected or Y3 or Y4_expected or Y4 or Y5_expected or Y5 or Y6_expected or Y6 or Y7_expected or Y7 or Y8_expected or Y8 or Y9_expected or Y9)
-begin
-	trigger <= ~trigger;
-end
-
-always @(posedge sampler_rx or negedge sampler_rx)
-begin
-`ifdef debug_tbench
-	$display("Scanning pattern %d @time = %t",i,$realtime );
-	i = i + 1;
-	$display("| expected Y0 = %b | expected Y1 = %b | expected Y2 = %b | expected Y3 = %b | expected Y4 = %b | expected Y5 = %b | expected Y6 = %b | expected Y7 = %b | expected Y8 = %b | expected Y9 = %b | ",Y0_expected_prev,Y1_expected_prev,Y2_expected_prev,Y3_expected_prev,Y4_expected_prev,Y5_expected_prev,Y6_expected_prev,Y7_expected_prev,Y8_expected_prev,Y9_expected_prev);
-	$display("| real Y0 = %b | real Y1 = %b | real Y2 = %b | real Y3 = %b | real Y4 = %b | real Y5 = %b | real Y6 = %b | real Y7 = %b | real Y8 = %b | real Y9 = %b | ",Y0_prev,Y1_prev,Y2_prev,Y3_prev,Y4_prev,Y5_prev,Y6_prev,Y7_prev,Y8_prev,Y9_prev);
-`endif
-	if (
-		( Y0_expected_prev !== 1'bx ) && ( Y0_prev !== Y0_expected_prev )
-		&& ((Y0_expected_prev !== last_Y0_exp) ||
-			on_first_change[1])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y0 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y0_expected_prev);
-		$display ("     Real value = %b", Y0_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[1] = 1'b0;
-		last_Y0_exp = Y0_expected_prev;
-	end
-	if (
-		( Y1_expected_prev !== 1'bx ) && ( Y1_prev !== Y1_expected_prev )
-		&& ((Y1_expected_prev !== last_Y1_exp) ||
-			on_first_change[2])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y1 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y1_expected_prev);
-		$display ("     Real value = %b", Y1_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[2] = 1'b0;
-		last_Y1_exp = Y1_expected_prev;
-	end
-	if (
-		( Y2_expected_prev !== 1'bx ) && ( Y2_prev !== Y2_expected_prev )
-		&& ((Y2_expected_prev !== last_Y2_exp) ||
-			on_first_change[3])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y2 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y2_expected_prev);
-		$display ("     Real value = %b", Y2_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[3] = 1'b0;
-		last_Y2_exp = Y2_expected_prev;
-	end
-	if (
-		( Y3_expected_prev !== 1'bx ) && ( Y3_prev !== Y3_expected_prev )
-		&& ((Y3_expected_prev !== last_Y3_exp) ||
-			on_first_change[4])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y3 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y3_expected_prev);
-		$display ("     Real value = %b", Y3_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[4] = 1'b0;
-		last_Y3_exp = Y3_expected_prev;
-	end
-	if (
-		( Y4_expected_prev !== 1'bx ) && ( Y4_prev !== Y4_expected_prev )
-		&& ((Y4_expected_prev !== last_Y4_exp) ||
-			on_first_change[5])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y4 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y4_expected_prev);
-		$display ("     Real value = %b", Y4_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[5] = 1'b0;
-		last_Y4_exp = Y4_expected_prev;
-	end
-	if (
-		( Y5_expected_prev !== 1'bx ) && ( Y5_prev !== Y5_expected_prev )
-		&& ((Y5_expected_prev !== last_Y5_exp) ||
-			on_first_change[6])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y5 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y5_expected_prev);
-		$display ("     Real value = %b", Y5_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[6] = 1'b0;
-		last_Y5_exp = Y5_expected_prev;
-	end
-	if (
-		( Y6_expected_prev !== 1'bx ) && ( Y6_prev !== Y6_expected_prev )
-		&& ((Y6_expected_prev !== last_Y6_exp) ||
-			on_first_change[7])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y6 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y6_expected_prev);
-		$display ("     Real value = %b", Y6_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[7] = 1'b0;
-		last_Y6_exp = Y6_expected_prev;
-	end
-	if (
-		( Y7_expected_prev !== 1'bx ) && ( Y7_prev !== Y7_expected_prev )
-		&& ((Y7_expected_prev !== last_Y7_exp) ||
-			on_first_change[8])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y7 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y7_expected_prev);
-		$display ("     Real value = %b", Y7_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[8] = 1'b0;
-		last_Y7_exp = Y7_expected_prev;
-	end
-	if (
-		( Y8_expected_prev !== 1'bx ) && ( Y8_prev !== Y8_expected_prev )
-		&& ((Y8_expected_prev !== last_Y8_exp) ||
-			on_first_change[9])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y8 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y8_expected_prev);
-		$display ("     Real value = %b", Y8_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[9] = 1'b0;
-		last_Y8_exp = Y8_expected_prev;
-	end
-	if (
-		( Y9_expected_prev !== 1'bx ) && ( Y9_prev !== Y9_expected_prev )
-		&& ((Y9_expected_prev !== last_Y9_exp) ||
-			on_first_change[10])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y9 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y9_expected_prev);
-		$display ("     Real value = %b", Y9_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[10] = 1'b0;
-		last_Y9_exp = Y9_expected_prev;
-	end
-
-	trigger <= ~trigger;
-end
-initial 
-
-begin 
-$timeformat(-12,3," ps",6);
-#10000000;
-if (nummismatches > 0)
-	$display ("%d mismatched vectors : Simulation failed !",nummismatches);
-else
-	$display ("Simulation passed !");
-$finish;
-end 
-endmodule
-
-module BCD_to_decimal_decoder_vlg_vec_tst();
-// constants                                           
-// general purpose registers
-reg A;
-reg B;
-reg C;
-reg D;
-// wires                                               
-wire Y0;
-wire Y1;
-wire Y2;
-wire Y3;
-wire Y4;
-wire Y5;
-wire Y6;
-wire Y7;
-wire Y8;
-wire Y9;
-
-wire sampler;                             
-
-// assign statements (if any)                          
-BCD_to_decimal_decoder i1 (
-// port map - connection between master ports and signals/registers   
-	.A(A),
-	.B(B),
-	.C(C),
-	.D(D),
-	.Y0(Y0),
-	.Y1(Y1),
-	.Y2(Y2),
-	.Y3(Y3),
-	.Y4(Y4),
-	.Y5(Y5),
-	.Y6(Y6),
-	.Y7(Y7),
-	.Y8(Y8),
-	.Y9(Y9)
-);
-
-// A
-initial
-begin
-	A = 1'b0;
-	A = #1000000 1'b1;
-	A = #1000000 1'b0;
-	A = #1000000 1'b1;
-	A = #1000000 1'b0;
-	A = #1000000 1'b1;
-	A = #1000000 1'b0;
-	A = #1000000 1'b1;
-	A = #1000000 1'b0;
-	A = #1000000 1'b1;
-end 
-
-// B
-initial
-begin
-	B = 1'b0;
-	B = #2000000 1'b1;
-	B = #2000000 1'b0;
-	B = #2000000 1'b1;
-	B = #2000000 1'b0;
-end 
-
-// C
-initial
-begin
-	C = 1'b0;
-	C = #4000000 1'b1;
-	C = #4000000 1'b0;
-end 
-
-// D
-initial
-begin
-	D = 1'b0;
-	D = #8000000 1'b1;
-end 
-
-BCD_to_decimal_decoder_vlg_sample_tst tb_sample (
-	.A(A),
-	.B(B),
-	.C(C),
-	.D(D),
-	.sampler_tx(sampler)
-);
-
-BCD_to_decimal_decoder_vlg_check_tst tb_out(
-	.Y0(Y0),
-	.Y1(Y1),
-	.Y2(Y2),
-	.Y3(Y3),
-	.Y4(Y4),
-	.Y5(Y5),
-	.Y6(Y6),
-	.Y7(Y7),
-	.Y8(Y8),
-	.Y9(Y9),
-	.sampler_rx(sampler)
-);
-endmodule
-
diff --git a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder_modelsim.xrf b/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder_modelsim.xrf
deleted file mode 100644
index a42f59fd..00000000
--- a/CH6/CH6-1/simulation/qsim/BCD_to_decimal_decoder_modelsim.xrf
+++ /dev/null
@@ -1,19 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.bdf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/BCD_to_decimal_decoder.vwf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/db/BCD_to_decimal_decoder.cbx.xml
-design_name = BCD_to_decimal_decoder
-instance = comp, \Y0~output , Y0~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y1~output , Y1~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y2~output , Y2~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y3~output , Y3~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y4~output , Y4~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y5~output , Y5~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y6~output , Y6~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y7~output , Y7~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y8~output , Y8~output, BCD_to_decimal_decoder, 1
-instance = comp, \Y9~output , Y9~output, BCD_to_decimal_decoder, 1
-instance = comp, \C~input , C~input, BCD_to_decimal_decoder, 1
-instance = comp, \D~input , D~input, BCD_to_decimal_decoder, 1
-instance = comp, \A~input , A~input, BCD_to_decimal_decoder, 1
-instance = comp, \B~input , B~input, BCD_to_decimal_decoder, 1
diff --git a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.do b/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.do
deleted file mode 100644
index e611950d..00000000
--- a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.do
+++ /dev/null
@@ -1,10 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vlog -work work four_line_to_sixteen_line_decimal_decoder.vo
-vlog -work work four_line_to_sixteen_line_decimal_decoder.vwf.vt
-vsim -novopt -c -t 1ps -L cycloneiii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst -voptargs="+acc"
-vcd file -direction four_line_to_sixteen_line_decimal_decoder.msim.vcd
-vcd add -internal four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/*
-vcd add -internal four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/i1/*
-run -all
-quit -f
diff --git a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.msim.vcd b/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.msim.vcd
deleted file mode 100644
index 19d35174..00000000
--- a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.msim.vcd
+++ /dev/null
@@ -1,250 +0,0 @@
-$comment
-	File created using the following command:
-		vcd file four_line_to_sixteen_line_decimal_decoder.msim.vcd -direction
-$end
-$date
-	Thu Oct 24 22:24:54 2019
-$end
-$version
-	ModelSim Version 10.1d
-$end
-$timescale
-	1ps
-$end
-$scope module four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst $end
-$var reg 1 ! A $end
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-$var reg 1 $ D $end
-$var wire 1 % Y0 $end
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-$var wire 1 P inst|15~0_combout $end
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-$var wire 1 V inst|15~6_combout $end
-$var wire 1 W inst|15~7_combout $end
-$var wire 1 X inst|15~8_combout $end
-$var wire 1 Y inst|15~9_combout $end
-$var wire 1 Z inst|15~10_combout $end
-$var wire 1 [ inst|15~11_combout $end
-$var wire 1 \ inst|15~12_combout $end
-$var wire 1 ] inst|15~13_combout $end
-$var wire 1 ^ inst|15~14_combout $end
-$var wire 1 _ inst|15~15_combout $end
-$upscope $end
-$upscope $end
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-#0
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diff --git a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.sft b/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.sft
deleted file mode 100644
index 06a2ca45..00000000
--- a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (Verilog)"
diff --git a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.sim.vwf b/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.sim.vwf
deleted file mode 100644
index 17f9ecb8..00000000
--- a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.sim.vwf
+++ /dev/null
@@ -1,732 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-
-HEADER
-{
-	VERSION = 1;
-	TIME_UNIT = ns;
-	DATA_OFFSET = 0.0;
-	DATA_DURATION = 10000.0;
-	SIMULATION_TIME = 0.0;
-	GRID_PHASE = 0.0;
-	GRID_PERIOD = 1000.0;
-	GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("A")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("B")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("C")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("D")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y0")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y1")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y2")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
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-{
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-	SIGNAL_TYPE = SINGLE_BIT;
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-	PARENT = "";
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-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y5")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
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-{
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-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
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-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
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-	LSB_INDEX = -1;
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-
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-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
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-	LSB_INDEX = -1;
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-}
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-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y10")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
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-SIGNAL("Y11")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
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-}
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-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y13")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y14")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y15")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
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-{
-	MEMBERS = "A", "B", "C", "D";
-}
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-TRANSITION_LIST("A")
-{
-	NODE
-	{
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-		NODE
-		{
-			REPEAT = 1;
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-	}
-}
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-{
-	NODE
-	{
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-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 2000.0;
-			LEVEL 0 FOR 4000.0;
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-{
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-		{
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-{
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-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
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-			LEVEL 1 FOR 6000.0;
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-	}
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-TRANSITION_LIST("Y0")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 10000.0;
-		}
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-}
-
-TRANSITION_LIST("Y1")
-{
-	NODE
-	{
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-		{
-			REPEAT = 1;
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-{
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-	{
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-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 9000.0;
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-	}
-}
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-{
-	NODE
-	{
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-		{
-			REPEAT = 1;
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-		{
-			REPEAT = 1;
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-			LEVEL 0 FOR 1000.0;
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-}
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-TRANSITION_LIST("Y5")
-{
-	NODE
-	{
-		REPEAT = 1;
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-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 3000.0;
-			LEVEL 0 FOR 1000.0;
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-{
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-		{
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-{
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-		{
-			REPEAT = 1;
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-
-TRANSITION_LIST("Y8")
-{
-	NODE
-	{
-		REPEAT = 1;
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-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 4000.0;
-			LEVEL 0 FOR 1000.0;
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-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 5000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 4000.0;
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-	}
-}
-
-TRANSITION_LIST("Y10")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 6000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 3000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y11")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 7000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y12")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 10000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y13")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 10000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y14")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 8000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y15")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 9000.0;
-			LEVEL 0 FOR 1000.0;
-		}
-	}
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "IN";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 0;
-	TREE_LEVEL = 0;
-	CHILDREN = 1, 2, 3, 4;
-}
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-DISPLAY_LINE
-{
-	CHANNEL = "A";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 1;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "B";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 2;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "C";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 3;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "D";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 4;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y0";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 5;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y1";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 6;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y2";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 7;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y3";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 8;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y4";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 9;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y5";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 10;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y6";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 11;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y7";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 12;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y8";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 13;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y9";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 14;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y10";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 15;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y11";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 16;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y12";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 17;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y13";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 18;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y14";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 19;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y15";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 20;
-	TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
-	TIME = 0;
-	MASTER = TRUE;
-}
-;
diff --git a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.vo b/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.vo
deleted file mode 100644
index f4ad0f74..00000000
--- a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.vo
+++ /dev/null
@@ -1,697 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-// VENDOR "Altera"
-// PROGRAM "Quartus II 32-bit"
-// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
-// DATE "10/24/2019 22:24:53"
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-// 
-// This Verilog file should be used for ModelSim-Altera (Verilog) only
-// 
-
-`timescale 1 ps/ 1 ps
-
-module four_line_to_sixteen_line_decimal_decoder (
-	Y0,
-	A,
-	B,
-	C,
-	D,
-	Y1,
-	Y2,
-	Y3,
-	Y4,
-	Y5,
-	Y6,
-	Y7,
-	Y8,
-	Y9,
-	Y10,
-	Y11,
-	Y12,
-	Y13,
-	Y14,
-	Y15);
-output 	Y0;
-input 	A;
-input 	B;
-input 	C;
-input 	D;
-output 	Y1;
-output 	Y2;
-output 	Y3;
-output 	Y4;
-output 	Y5;
-output 	Y6;
-output 	Y7;
-output 	Y8;
-output 	Y9;
-output 	Y10;
-output 	Y11;
-output 	Y12;
-output 	Y13;
-output 	Y14;
-output 	Y15;
-
-// Design Ports Information
-// Y0	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y1	=>  Location: PIN_J4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y2	=>  Location: PIN_P7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y3	=>  Location: PIN_W1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y4	=>  Location: PIN_T7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y5	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y6	=>  Location: PIN_R6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y7	=>  Location: PIN_R9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y8	=>  Location: PIN_M5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y9	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y10	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y11	=>  Location: PIN_Y2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y12	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y13	=>  Location: PIN_W2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y14	=>  Location: PIN_M3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y15	=>  Location: PIN_P6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// D	=>  Location: PIN_T5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// C	=>  Location: PIN_Y1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// B	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// A	=>  Location: PIN_AB3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-tri1 devclrn;
-tri1 devpor;
-tri1 devoe;
-wire \Y0~output_o ;
-wire \Y1~output_o ;
-wire \Y2~output_o ;
-wire \Y3~output_o ;
-wire \Y4~output_o ;
-wire \Y5~output_o ;
-wire \Y6~output_o ;
-wire \Y7~output_o ;
-wire \Y8~output_o ;
-wire \Y9~output_o ;
-wire \Y10~output_o ;
-wire \Y11~output_o ;
-wire \Y12~output_o ;
-wire \Y13~output_o ;
-wire \Y14~output_o ;
-wire \Y15~output_o ;
-wire \C~input_o ;
-wire \B~input_o ;
-wire \D~input_o ;
-wire \A~input_o ;
-wire \inst|15~0_combout ;
-wire \inst|15~1_combout ;
-wire \inst|15~2_combout ;
-wire \inst|15~3_combout ;
-wire \inst|15~4_combout ;
-wire \inst|15~5_combout ;
-wire \inst|15~6_combout ;
-wire \inst|15~7_combout ;
-wire \inst|15~8_combout ;
-wire \inst|15~9_combout ;
-wire \inst|15~10_combout ;
-wire \inst|15~11_combout ;
-wire \inst|15~12_combout ;
-wire \inst|15~13_combout ;
-wire \inst|15~14_combout ;
-wire \inst|15~15_combout ;
-
-
-// Location: IOOBUF_X0_Y11_N2
-cycloneiii_io_obuf \Y0~output (
-	.i(!\inst|15~0_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y0~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y0~output .bus_hold = "false";
-defparam \Y0~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y21_N2
-cycloneiii_io_obuf \Y1~output (
-	.i(!\inst|15~1_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y1~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y1~output .bus_hold = "false";
-defparam \Y1~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y5_N2
-cycloneiii_io_obuf \Y2~output (
-	.i(!\inst|15~2_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y2~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y2~output .bus_hold = "false";
-defparam \Y2~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y7_N23
-cycloneiii_io_obuf \Y3~output (
-	.i(!\inst|15~3_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y3~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y3~output .bus_hold = "false";
-defparam \Y3~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y2_N9
-cycloneiii_io_obuf \Y4~output (
-	.i(!\inst|15~4_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y4~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y4~output .bus_hold = "false";
-defparam \Y4~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y8_N2
-cycloneiii_io_obuf \Y5~output (
-	.i(!\inst|15~5_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y5~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y5~output .bus_hold = "false";
-defparam \Y5~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y3_N9
-cycloneiii_io_obuf \Y6~output (
-	.i(!\inst|15~6_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y6~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y6~output .bus_hold = "false";
-defparam \Y6~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N30
-cycloneiii_io_obuf \Y7~output (
-	.i(!\inst|15~7_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y7~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y7~output .bus_hold = "false";
-defparam \Y7~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y11_N9
-cycloneiii_io_obuf \Y8~output (
-	.i(!\inst|15~8_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y8~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y8~output .bus_hold = "false";
-defparam \Y8~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y12_N2
-cycloneiii_io_obuf \Y9~output (
-	.i(!\inst|15~9_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y9~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y9~output .bus_hold = "false";
-defparam \Y9~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y8_N9
-cycloneiii_io_obuf \Y10~output (
-	.i(!\inst|15~10_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y10~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y10~output .bus_hold = "false";
-defparam \Y10~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y6_N2
-cycloneiii_io_obuf \Y11~output (
-	.i(!\inst|15~11_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y11~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y11~output .bus_hold = "false";
-defparam \Y11~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y8_N23
-cycloneiii_io_obuf \Y12~output (
-	.i(!\inst|15~12_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y12~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y12~output .bus_hold = "false";
-defparam \Y12~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y7_N16
-cycloneiii_io_obuf \Y13~output (
-	.i(!\inst|15~13_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y13~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y13~output .bus_hold = "false";
-defparam \Y13~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y12_N9
-cycloneiii_io_obuf \Y14~output (
-	.i(!\inst|15~14_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y14~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y14~output .bus_hold = "false";
-defparam \Y14~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y4_N9
-cycloneiii_io_obuf \Y15~output (
-	.i(!\inst|15~15_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y15~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y15~output .bus_hold = "false";
-defparam \Y15~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y6_N8
-cycloneiii_io_ibuf \C~input (
-	.i(C),
-	.ibar(gnd),
-	.o(\C~input_o ));
-// synopsys translate_off
-defparam \C~input .bus_hold = "false";
-defparam \C~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y6_N22
-cycloneiii_io_ibuf \B~input (
-	.i(B),
-	.ibar(gnd),
-	.o(\B~input_o ));
-// synopsys translate_off
-defparam \B~input .bus_hold = "false";
-defparam \B~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y3_N1
-cycloneiii_io_ibuf \D~input (
-	.i(D),
-	.ibar(gnd),
-	.o(\D~input_o ));
-// synopsys translate_off
-defparam \D~input .bus_hold = "false";
-defparam \D~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X7_Y0_N29
-cycloneiii_io_ibuf \A~input (
-	.i(A),
-	.ibar(gnd),
-	.o(\A~input_o ));
-// synopsys translate_off
-defparam \A~input .bus_hold = "false";
-defparam \A~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N24
-cycloneiii_lcell_comb \inst|15~0 (
-// Equation(s):
-// \inst|15~0_combout  = (!\C~input_o  & (!\B~input_o  & (!\D~input_o  & !\A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~0_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~0 .lut_mask = 16'h0001;
-defparam \inst|15~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N2
-cycloneiii_lcell_comb \inst|15~1 (
-// Equation(s):
-// \inst|15~1_combout  = (!\C~input_o  & (!\B~input_o  & (!\D~input_o  & \A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~1_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~1 .lut_mask = 16'h0100;
-defparam \inst|15~1 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N4
-cycloneiii_lcell_comb \inst|15~2 (
-// Equation(s):
-// \inst|15~2_combout  = (!\C~input_o  & (\B~input_o  & (!\D~input_o  & !\A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~2_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~2 .lut_mask = 16'h0004;
-defparam \inst|15~2 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N22
-cycloneiii_lcell_comb \inst|15~3 (
-// Equation(s):
-// \inst|15~3_combout  = (!\C~input_o  & (\B~input_o  & (!\D~input_o  & \A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~3_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~3 .lut_mask = 16'h0400;
-defparam \inst|15~3 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N16
-cycloneiii_lcell_comb \inst|15~4 (
-// Equation(s):
-// \inst|15~4_combout  = (\C~input_o  & (!\B~input_o  & (!\D~input_o  & !\A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~4_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~4 .lut_mask = 16'h0002;
-defparam \inst|15~4 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N26
-cycloneiii_lcell_comb \inst|15~5 (
-// Equation(s):
-// \inst|15~5_combout  = (\C~input_o  & (!\B~input_o  & (!\D~input_o  & \A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~5_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~5 .lut_mask = 16'h0200;
-defparam \inst|15~5 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N28
-cycloneiii_lcell_comb \inst|15~6 (
-// Equation(s):
-// \inst|15~6_combout  = (\C~input_o  & (\B~input_o  & (!\D~input_o  & !\A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~6_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~6 .lut_mask = 16'h0008;
-defparam \inst|15~6 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N6
-cycloneiii_lcell_comb \inst|15~7 (
-// Equation(s):
-// \inst|15~7_combout  = (\C~input_o  & (\B~input_o  & (!\D~input_o  & \A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~7_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~7 .lut_mask = 16'h0800;
-defparam \inst|15~7 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N0
-cycloneiii_lcell_comb \inst|15~8 (
-// Equation(s):
-// \inst|15~8_combout  = (!\C~input_o  & (!\B~input_o  & (\D~input_o  & !\A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~8_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~8 .lut_mask = 16'h0010;
-defparam \inst|15~8 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N10
-cycloneiii_lcell_comb \inst|15~9 (
-// Equation(s):
-// \inst|15~9_combout  = (!\C~input_o  & (!\B~input_o  & (\D~input_o  & \A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~9_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~9 .lut_mask = 16'h1000;
-defparam \inst|15~9 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N20
-cycloneiii_lcell_comb \inst|15~10 (
-// Equation(s):
-// \inst|15~10_combout  = (!\C~input_o  & (\B~input_o  & (\D~input_o  & !\A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~10_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~10 .lut_mask = 16'h0040;
-defparam \inst|15~10 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N14
-cycloneiii_lcell_comb \inst|15~11 (
-// Equation(s):
-// \inst|15~11_combout  = (!\C~input_o  & (\B~input_o  & (\D~input_o  & \A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~11_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~11 .lut_mask = 16'h4000;
-defparam \inst|15~11 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N8
-cycloneiii_lcell_comb \inst|15~12 (
-// Equation(s):
-// \inst|15~12_combout  = (\C~input_o  & (!\B~input_o  & (\D~input_o  & !\A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~12_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~12 .lut_mask = 16'h0020;
-defparam \inst|15~12 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N18
-cycloneiii_lcell_comb \inst|15~13 (
-// Equation(s):
-// \inst|15~13_combout  = (\C~input_o  & (!\B~input_o  & (\D~input_o  & \A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~13_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~13 .lut_mask = 16'h2000;
-defparam \inst|15~13 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N12
-cycloneiii_lcell_comb \inst|15~14 (
-// Equation(s):
-// \inst|15~14_combout  = (\C~input_o  & (\B~input_o  & (\D~input_o  & !\A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~14_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~14 .lut_mask = 16'h0080;
-defparam \inst|15~14 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y9_N30
-cycloneiii_lcell_comb \inst|15~15 (
-// Equation(s):
-// \inst|15~15_combout  = (\C~input_o  & (\B~input_o  & (\D~input_o  & \A~input_o )))
-
-	.dataa(\C~input_o ),
-	.datab(\B~input_o ),
-	.datac(\D~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|15~15_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|15~15 .lut_mask = 16'h8000;
-defparam \inst|15~15 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-assign Y0 = \Y0~output_o ;
-
-assign Y1 = \Y1~output_o ;
-
-assign Y2 = \Y2~output_o ;
-
-assign Y3 = \Y3~output_o ;
-
-assign Y4 = \Y4~output_o ;
-
-assign Y5 = \Y5~output_o ;
-
-assign Y6 = \Y6~output_o ;
-
-assign Y7 = \Y7~output_o ;
-
-assign Y8 = \Y8~output_o ;
-
-assign Y9 = \Y9~output_o ;
-
-assign Y10 = \Y10~output_o ;
-
-assign Y11 = \Y11~output_o ;
-
-assign Y12 = \Y12~output_o ;
-
-assign Y13 = \Y13~output_o ;
-
-assign Y14 = \Y14~output_o ;
-
-assign Y15 = \Y15~output_o ;
-
-endmodule
diff --git a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.vwf.vt b/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.vwf.vt
deleted file mode 100644
index 89d116a7..00000000
--- a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder.vwf.vt
+++ /dev/null
@@ -1,691 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-// *****************************************************************************
-// This file contains a Verilog test bench with test vectors .The test vectors  
-// are exported from a vector file in the Quartus Waveform Editor and apply to  
-// the top level entity of the current Quartus project .The user can use this   
-// testbench to simulate his design using a third-party simulation tool .       
-// *****************************************************************************
-// Generated on "10/24/2019 22:24:48"
-                                                                        
-// Verilog Self-Checking Test Bench (with test vectors) for design :    four_line_to_sixteen_line_decimal_decoder
-// 
-// Simulation tool : 3rd Party
-// 
-
-`timescale 1 ps/ 1 ps
-module four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst(
-	A,
-	B,
-	C,
-	D,
-	sampler_tx
-);
-input  A;
-input  B;
-input  C;
-input  D;
-output sampler_tx;
-
-reg sample;
-time current_time;
-always @(A or B or C or D)
-                                                                                
-begin                                                 
- if ($realtime > 0)                                   
- begin                                                
-	if ($realtime == 0 || $realtime != current_time)  
-	begin									          
-		if (sample === 1'bx)                          
-			sample = 0;                               
-		else                                          
-			sample = ~sample;                         
-	end										          
-	current_time = $realtime;					      
- end                                                  
-end                                                   
-
-assign sampler_tx = sample;
-endmodule
-
-module four_line_to_sixteen_line_decimal_decoder_vlg_check_tst (
-	Y0,
-	Y1,
-	Y2,
-	Y3,
-	Y4,
-	Y5,
-	Y6,
-	Y7,
-	Y8,
-	Y9,
-	Y10,
-	Y11,
-	Y12,
-	Y13,
-	Y14,
-	Y15,
-	sampler_rx
-);
-input  Y0;
-input  Y1;
-input  Y2;
-input  Y3;
-input  Y4;
-input  Y5;
-input  Y6;
-input  Y7;
-input  Y8;
-input  Y9;
-input  Y10;
-input  Y11;
-input  Y12;
-input  Y13;
-input  Y14;
-input  Y15;
-input sampler_rx;
-
-reg  Y0_expected;
-reg  Y1_expected;
-reg  Y2_expected;
-reg  Y3_expected;
-reg  Y4_expected;
-reg  Y5_expected;
-reg  Y6_expected;
-reg  Y7_expected;
-reg  Y8_expected;
-reg  Y9_expected;
-reg  Y10_expected;
-reg  Y11_expected;
-reg  Y12_expected;
-reg  Y13_expected;
-reg  Y14_expected;
-reg  Y15_expected;
-
-reg  Y0_prev;
-reg  Y1_prev;
-reg  Y2_prev;
-reg  Y3_prev;
-reg  Y4_prev;
-reg  Y5_prev;
-reg  Y6_prev;
-reg  Y7_prev;
-reg  Y8_prev;
-reg  Y9_prev;
-reg  Y10_prev;
-reg  Y11_prev;
-reg  Y12_prev;
-reg  Y13_prev;
-reg  Y14_prev;
-reg  Y15_prev;
-
-reg  Y0_expected_prev;
-reg  Y1_expected_prev;
-reg  Y2_expected_prev;
-reg  Y3_expected_prev;
-reg  Y4_expected_prev;
-reg  Y5_expected_prev;
-reg  Y6_expected_prev;
-reg  Y7_expected_prev;
-reg  Y8_expected_prev;
-reg  Y9_expected_prev;
-reg  Y10_expected_prev;
-reg  Y11_expected_prev;
-reg  Y12_expected_prev;
-reg  Y13_expected_prev;
-reg  Y14_expected_prev;
-reg  Y15_expected_prev;
-
-reg  last_Y0_exp;
-reg  last_Y1_exp;
-reg  last_Y2_exp;
-reg  last_Y3_exp;
-reg  last_Y4_exp;
-reg  last_Y5_exp;
-reg  last_Y6_exp;
-reg  last_Y7_exp;
-reg  last_Y8_exp;
-reg  last_Y9_exp;
-reg  last_Y10_exp;
-reg  last_Y11_exp;
-reg  last_Y12_exp;
-reg  last_Y13_exp;
-reg  last_Y14_exp;
-reg  last_Y15_exp;
-
-reg trigger;
-
-integer i;
-integer nummismatches;
-
-reg [1:16] on_first_change ;
-
-
-initial
-begin
-trigger = 0;
-i = 0;
-nummismatches = 0;
-on_first_change = 16'b1;
-end
-
-// update real /o prevs
-
-always @(trigger)
-begin
-	Y0_prev = Y0;
-	Y1_prev = Y1;
-	Y2_prev = Y2;
-	Y3_prev = Y3;
-	Y4_prev = Y4;
-	Y5_prev = Y5;
-	Y6_prev = Y6;
-	Y7_prev = Y7;
-	Y8_prev = Y8;
-	Y9_prev = Y9;
-	Y10_prev = Y10;
-	Y11_prev = Y11;
-	Y12_prev = Y12;
-	Y13_prev = Y13;
-	Y14_prev = Y14;
-	Y15_prev = Y15;
-end
-
-// update expected /o prevs
-
-always @(trigger)
-begin
-	Y0_expected_prev = Y0_expected;
-	Y1_expected_prev = Y1_expected;
-	Y2_expected_prev = Y2_expected;
-	Y3_expected_prev = Y3_expected;
-	Y4_expected_prev = Y4_expected;
-	Y5_expected_prev = Y5_expected;
-	Y6_expected_prev = Y6_expected;
-	Y7_expected_prev = Y7_expected;
-	Y8_expected_prev = Y8_expected;
-	Y9_expected_prev = Y9_expected;
-	Y10_expected_prev = Y10_expected;
-	Y11_expected_prev = Y11_expected;
-	Y12_expected_prev = Y12_expected;
-	Y13_expected_prev = Y13_expected;
-	Y14_expected_prev = Y14_expected;
-	Y15_expected_prev = Y15_expected;
-end
-
-
-
-// expected Y0
-initial
-begin
-	Y0_expected = 1'bX;
-	Y0_expected = #999000 1'b0;
-end 
-
-// expected Y1
-initial
-begin
-	Y1_expected = 1'bX;
-	Y1_expected = #999000 1'b0;
-end 
-
-// expected Y2
-initial
-begin
-	Y2_expected = 1'bX;
-	Y2_expected = #999000 1'b0;
-end 
-
-// expected Y3
-initial
-begin
-	Y3_expected = 1'bX;
-	Y3_expected = #999000 1'b0;
-end 
-
-// expected Y4
-initial
-begin
-	Y4_expected = 1'bX;
-	Y4_expected = #999000 1'b0;
-end 
-
-// expected Y5
-initial
-begin
-	Y5_expected = 1'bX;
-	Y5_expected = #999000 1'b0;
-end 
-
-// expected Y6
-initial
-begin
-	Y6_expected = 1'bX;
-	Y6_expected = #999000 1'b0;
-end 
-
-// expected Y7
-initial
-begin
-	Y7_expected = 1'bX;
-	Y7_expected = #999000 1'b0;
-end 
-
-// expected Y8
-initial
-begin
-	Y8_expected = 1'bX;
-	Y8_expected = #999000 1'b0;
-end 
-
-// expected Y9
-initial
-begin
-	Y9_expected = 1'bX;
-	Y9_expected = #999000 1'b0;
-end 
-
-// expected Y10
-initial
-begin
-	Y10_expected = 1'bX;
-	Y10_expected = #999000 1'b0;
-end 
-
-// expected Y11
-initial
-begin
-	Y11_expected = 1'bX;
-	Y11_expected = #999000 1'b0;
-end 
-
-// expected Y12
-initial
-begin
-	Y12_expected = 1'bX;
-	Y12_expected = #999000 1'b0;
-end 
-
-// expected Y13
-initial
-begin
-	Y13_expected = 1'bX;
-	Y13_expected = #999000 1'b0;
-end 
-
-// expected Y14
-initial
-begin
-	Y14_expected = 1'bX;
-	Y14_expected = #999000 1'b0;
-end 
-
-// expected Y15
-initial
-begin
-	Y15_expected = 1'bX;
-	Y15_expected = #999000 1'b0;
-end 
-// generate trigger
-always @(Y0_expected or Y0 or Y1_expected or Y1 or Y2_expected or Y2 or Y3_expected or Y3 or Y4_expected or Y4 or Y5_expected or Y5 or Y6_expected or Y6 or Y7_expected or Y7 or Y8_expected or Y8 or Y9_expected or Y9 or Y10_expected or Y10 or Y11_expected or Y11 or Y12_expected or Y12 or Y13_expected or Y13 or Y14_expected or Y14 or Y15_expected or Y15)
-begin
-	trigger <= ~trigger;
-end
-
-always @(posedge sampler_rx or negedge sampler_rx)
-begin
-`ifdef debug_tbench
-	$display("Scanning pattern %d @time = %t",i,$realtime );
-	i = i + 1;
-	$display("| expected Y0 = %b | expected Y1 = %b | expected Y2 = %b | expected Y3 = %b | expected Y4 = %b | expected Y5 = %b | expected Y6 = %b | expected Y7 = %b | expected Y8 = %b | expected Y9 = %b | expected Y10 = %b | expected Y11 = %b | expected Y12 = %b | expected Y13 = %b | expected Y14 = %b | expected Y15 = %b | ",Y0_expected_prev,Y1_expected_prev,Y2_expected_prev,Y3_expected_prev,Y4_expected_prev,Y5_expected_prev,Y6_expected_prev,Y7_expected_prev,Y8_expected_prev,Y9_expected_prev,Y10_expected_prev,Y11_expected_prev,Y12_expected_prev,Y13_expected_prev,Y14_expected_prev,Y15_expected_prev);
-	$display("| real Y0 = %b | real Y1 = %b | real Y2 = %b | real Y3 = %b | real Y4 = %b | real Y5 = %b | real Y6 = %b | real Y7 = %b | real Y8 = %b | real Y9 = %b | real Y10 = %b | real Y11 = %b | real Y12 = %b | real Y13 = %b | real Y14 = %b | real Y15 = %b | ",Y0_prev,Y1_prev,Y2_prev,Y3_prev,Y4_prev,Y5_prev,Y6_prev,Y7_prev,Y8_prev,Y9_prev,Y10_prev,Y11_prev,Y12_prev,Y13_prev,Y14_prev,Y15_prev);
-`endif
-	if (
-		( Y0_expected_prev !== 1'bx ) && ( Y0_prev !== Y0_expected_prev )
-		&& ((Y0_expected_prev !== last_Y0_exp) ||
-			on_first_change[1])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y0 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y0_expected_prev);
-		$display ("     Real value = %b", Y0_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[1] = 1'b0;
-		last_Y0_exp = Y0_expected_prev;
-	end
-	if (
-		( Y1_expected_prev !== 1'bx ) && ( Y1_prev !== Y1_expected_prev )
-		&& ((Y1_expected_prev !== last_Y1_exp) ||
-			on_first_change[2])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y1 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y1_expected_prev);
-		$display ("     Real value = %b", Y1_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[2] = 1'b0;
-		last_Y1_exp = Y1_expected_prev;
-	end
-	if (
-		( Y2_expected_prev !== 1'bx ) && ( Y2_prev !== Y2_expected_prev )
-		&& ((Y2_expected_prev !== last_Y2_exp) ||
-			on_first_change[3])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y2 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y2_expected_prev);
-		$display ("     Real value = %b", Y2_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[3] = 1'b0;
-		last_Y2_exp = Y2_expected_prev;
-	end
-	if (
-		( Y3_expected_prev !== 1'bx ) && ( Y3_prev !== Y3_expected_prev )
-		&& ((Y3_expected_prev !== last_Y3_exp) ||
-			on_first_change[4])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y3 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y3_expected_prev);
-		$display ("     Real value = %b", Y3_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[4] = 1'b0;
-		last_Y3_exp = Y3_expected_prev;
-	end
-	if (
-		( Y4_expected_prev !== 1'bx ) && ( Y4_prev !== Y4_expected_prev )
-		&& ((Y4_expected_prev !== last_Y4_exp) ||
-			on_first_change[5])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y4 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y4_expected_prev);
-		$display ("     Real value = %b", Y4_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[5] = 1'b0;
-		last_Y4_exp = Y4_expected_prev;
-	end
-	if (
-		( Y5_expected_prev !== 1'bx ) && ( Y5_prev !== Y5_expected_prev )
-		&& ((Y5_expected_prev !== last_Y5_exp) ||
-			on_first_change[6])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y5 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y5_expected_prev);
-		$display ("     Real value = %b", Y5_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[6] = 1'b0;
-		last_Y5_exp = Y5_expected_prev;
-	end
-	if (
-		( Y6_expected_prev !== 1'bx ) && ( Y6_prev !== Y6_expected_prev )
-		&& ((Y6_expected_prev !== last_Y6_exp) ||
-			on_first_change[7])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y6 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y6_expected_prev);
-		$display ("     Real value = %b", Y6_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[7] = 1'b0;
-		last_Y6_exp = Y6_expected_prev;
-	end
-	if (
-		( Y7_expected_prev !== 1'bx ) && ( Y7_prev !== Y7_expected_prev )
-		&& ((Y7_expected_prev !== last_Y7_exp) ||
-			on_first_change[8])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y7 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y7_expected_prev);
-		$display ("     Real value = %b", Y7_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[8] = 1'b0;
-		last_Y7_exp = Y7_expected_prev;
-	end
-	if (
-		( Y8_expected_prev !== 1'bx ) && ( Y8_prev !== Y8_expected_prev )
-		&& ((Y8_expected_prev !== last_Y8_exp) ||
-			on_first_change[9])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y8 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y8_expected_prev);
-		$display ("     Real value = %b", Y8_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[9] = 1'b0;
-		last_Y8_exp = Y8_expected_prev;
-	end
-	if (
-		( Y9_expected_prev !== 1'bx ) && ( Y9_prev !== Y9_expected_prev )
-		&& ((Y9_expected_prev !== last_Y9_exp) ||
-			on_first_change[10])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y9 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y9_expected_prev);
-		$display ("     Real value = %b", Y9_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[10] = 1'b0;
-		last_Y9_exp = Y9_expected_prev;
-	end
-	if (
-		( Y10_expected_prev !== 1'bx ) && ( Y10_prev !== Y10_expected_prev )
-		&& ((Y10_expected_prev !== last_Y10_exp) ||
-			on_first_change[11])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y10 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y10_expected_prev);
-		$display ("     Real value = %b", Y10_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[11] = 1'b0;
-		last_Y10_exp = Y10_expected_prev;
-	end
-	if (
-		( Y11_expected_prev !== 1'bx ) && ( Y11_prev !== Y11_expected_prev )
-		&& ((Y11_expected_prev !== last_Y11_exp) ||
-			on_first_change[12])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y11 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y11_expected_prev);
-		$display ("     Real value = %b", Y11_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[12] = 1'b0;
-		last_Y11_exp = Y11_expected_prev;
-	end
-	if (
-		( Y12_expected_prev !== 1'bx ) && ( Y12_prev !== Y12_expected_prev )
-		&& ((Y12_expected_prev !== last_Y12_exp) ||
-			on_first_change[13])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y12 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y12_expected_prev);
-		$display ("     Real value = %b", Y12_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[13] = 1'b0;
-		last_Y12_exp = Y12_expected_prev;
-	end
-	if (
-		( Y13_expected_prev !== 1'bx ) && ( Y13_prev !== Y13_expected_prev )
-		&& ((Y13_expected_prev !== last_Y13_exp) ||
-			on_first_change[14])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y13 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y13_expected_prev);
-		$display ("     Real value = %b", Y13_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[14] = 1'b0;
-		last_Y13_exp = Y13_expected_prev;
-	end
-	if (
-		( Y14_expected_prev !== 1'bx ) && ( Y14_prev !== Y14_expected_prev )
-		&& ((Y14_expected_prev !== last_Y14_exp) ||
-			on_first_change[15])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y14 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y14_expected_prev);
-		$display ("     Real value = %b", Y14_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[15] = 1'b0;
-		last_Y14_exp = Y14_expected_prev;
-	end
-	if (
-		( Y15_expected_prev !== 1'bx ) && ( Y15_prev !== Y15_expected_prev )
-		&& ((Y15_expected_prev !== last_Y15_exp) ||
-			on_first_change[16])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y15 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y15_expected_prev);
-		$display ("     Real value = %b", Y15_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[16] = 1'b0;
-		last_Y15_exp = Y15_expected_prev;
-	end
-
-	trigger <= ~trigger;
-end
-initial 
-
-begin 
-$timeformat(-12,3," ps",6);
-#10000000;
-if (nummismatches > 0)
-	$display ("%d mismatched vectors : Simulation failed !",nummismatches);
-else
-	$display ("Simulation passed !");
-$finish;
-end 
-endmodule
-
-module four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst();
-// constants                                           
-// general purpose registers
-reg A;
-reg B;
-reg C;
-reg D;
-// wires                                               
-wire Y0;
-wire Y1;
-wire Y2;
-wire Y3;
-wire Y4;
-wire Y5;
-wire Y6;
-wire Y7;
-wire Y8;
-wire Y9;
-wire Y10;
-wire Y11;
-wire Y12;
-wire Y13;
-wire Y14;
-wire Y15;
-
-wire sampler;                             
-
-// assign statements (if any)                          
-four_line_to_sixteen_line_decimal_decoder i1 (
-// port map - connection between master ports and signals/registers   
-	.A(A),
-	.B(B),
-	.C(C),
-	.D(D),
-	.Y0(Y0),
-	.Y1(Y1),
-	.Y2(Y2),
-	.Y3(Y3),
-	.Y4(Y4),
-	.Y5(Y5),
-	.Y6(Y6),
-	.Y7(Y7),
-	.Y8(Y8),
-	.Y9(Y9),
-	.Y10(Y10),
-	.Y11(Y11),
-	.Y12(Y12),
-	.Y13(Y13),
-	.Y14(Y14),
-	.Y15(Y15)
-);
-
-// A
-always
-begin
-	A = 1'b0;
-	A = #1000000 1'b1;
-	#1000000;
-end 
-
-// B
-initial
-begin
-	B = 1'b1;
-	B = #2000000 1'b0;
-	B = #4000000 1'b1;
-end 
-
-// C
-initial
-begin
-	C = 1'b0;
-	C = #2000000 1'b1;
-	C = #2000000 1'b0;
-	C = #4000000 1'b1;
-end 
-
-// D
-initial
-begin
-	D = 1'b0;
-	D = #4000000 1'b1;
-end 
-
-four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst tb_sample (
-	.A(A),
-	.B(B),
-	.C(C),
-	.D(D),
-	.sampler_tx(sampler)
-);
-
-four_line_to_sixteen_line_decimal_decoder_vlg_check_tst tb_out(
-	.Y0(Y0),
-	.Y1(Y1),
-	.Y2(Y2),
-	.Y3(Y3),
-	.Y4(Y4),
-	.Y5(Y5),
-	.Y6(Y6),
-	.Y7(Y7),
-	.Y8(Y8),
-	.Y9(Y9),
-	.Y10(Y10),
-	.Y11(Y11),
-	.Y12(Y12),
-	.Y13(Y13),
-	.Y14(Y14),
-	.Y15(Y15),
-	.sampler_rx(sampler)
-);
-endmodule
-
diff --git a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder_modelsim.xrf b/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder_modelsim.xrf
deleted file mode 100644
index b22be673..00000000
--- a/CH6/CH6-1/simulation/qsim/four_line_to_sixteen_line_decimal_decoder_modelsim.xrf
+++ /dev/null
@@ -1,42 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.bdf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/four_line_to_sixteen_line_decimal_decoder.vwf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/db/four_line_to_sixteen_line_decimal_decoder.cbx.xml
-source_file = 1, /home/timmy/altera/13.1/quartus/libraries/others/maxplus2/74138.bdf
-design_name = four_line_to_sixteen_line_decimal_decoder
-instance = comp, \Y0~output , Y0~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y1~output , Y1~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y2~output , Y2~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y3~output , Y3~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y4~output , Y4~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y5~output , Y5~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y6~output , Y6~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y7~output , Y7~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y8~output , Y8~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y9~output , Y9~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y10~output , Y10~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y11~output , Y11~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y12~output , Y12~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y13~output , Y13~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y14~output , Y14~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \Y15~output , Y15~output, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \C~input , C~input, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \B~input , B~input, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \D~input , D~input, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \A~input , A~input, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~0 , inst|15~0, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~1 , inst|15~1, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~2 , inst|15~2, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~3 , inst|15~3, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~4 , inst|15~4, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~5 , inst|15~5, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~6 , inst|15~6, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~7 , inst|15~7, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~8 , inst|15~8, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~9 , inst|15~9, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~10 , inst|15~10, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~11 , inst|15~11, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~12 , inst|15~12, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~13 , inst|15~13, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~14 , inst|15~14, four_line_to_sixteen_line_decimal_decoder, 1
-instance = comp, \inst|15~15 , inst|15~15, four_line_to_sixteen_line_decimal_decoder, 1
diff --git a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.do b/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.do
deleted file mode 100644
index 78151498..00000000
--- a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.do
+++ /dev/null
@@ -1,10 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vlog -work work ten_line_to_four_line_BCD_priority_encoder.vo
-vlog -work work ten_line_to_four_line_BCD_priority_encoder.vwf.vt
-vsim -novopt -c -t 1ps -L cycloneiii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.ten_line_to_four_line_BCD_priority_encoder_vlg_vec_tst -voptargs="+acc"
-vcd file -direction ten_line_to_four_line_BCD_priority_encoder.msim.vcd
-vcd add -internal ten_line_to_four_line_BCD_priority_encoder_vlg_vec_tst/*
-vcd add -internal ten_line_to_four_line_BCD_priority_encoder_vlg_vec_tst/i1/*
-run -all
-quit -f
diff --git a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.msim.vcd b/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.msim.vcd
deleted file mode 100644
index 50ee1b35..00000000
--- a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.msim.vcd
+++ /dev/null
@@ -1,196 +0,0 @@
-$comment
-	File created using the following command:
-		vcd file ten_line_to_four_line_BCD_priority_encoder.msim.vcd -direction
-$end
-$date
-	Thu Oct 17 21:16:28 2019
-$end
-$version
-	ModelSim Version 10.1d
-$end
-$timescale
-	1ps
-$end
-$scope module ten_line_to_four_line_BCD_priority_encoder_vlg_vec_tst $end
-$var reg 1 ! I2 $end
-$var reg 1 " I3 $end
-$var reg 1 # I4 $end
-$var reg 1 $ I5 $end
-$var reg 1 % I6 $end
-$var reg 1 & I7 $end
-$var reg 1 ' I8 $end
-$var reg 1 ( I9 $end
-$var wire 1 ) A $end
-$var wire 1 * B $end
-$var wire 1 + C $end
-$var wire 1 , D $end
-$var wire 1 - sampler $end
-$scope module i1 $end
-$var wire 1 . gnd $end
-$var wire 1 / vcc $end
-$var wire 1 0 unknown $end
-$var tri1 1 1 devclrn $end
-$var tri1 1 2 devpor $end
-$var tri1 1 3 devoe $end
-$var wire 1 4 A~output_o $end
-$var wire 1 5 B~output_o $end
-$var wire 1 6 C~output_o $end
-$var wire 1 7 D~output_o $end
-$var wire 1 8 I7~input_o $end
-$var wire 1 9 I8~input_o $end
-$var wire 1 : I9~input_o $end
-$var wire 1 ; I3~input_o $end
-$var wire 1 < I6~input_o $end
-$var wire 1 = I5~input_o $end
-$var wire 1 > I4~input_o $end
-$var wire 1 ? inst|7~2_combout $end
-$var wire 1 @ inst|7~3_combout $end
-$var wire 1 A I2~input_o $end
-$var wire 1 B inst|8~4_combout $end
-$var wire 1 C inst|67~combout $end
-$var wire 1 D inst|8~5_combout $end
-$var wire 1 E inst|9~0_combout $end
-$var wire 1 F inst|9~1_combout $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0!
-1"
-1#
-1$
-1%
-1&
-1'
-1(
-0)
-1*
-0+
-0,
-x-
-0.
-1/
-x0
-11
-12
-13
-04
-15
-06
-07
-18
-19
-1:
-1;
-1<
-1=
-1>
-0?
-0@
-0A
-1B
-0C
-1D
-1E
-0F
-$end
-#1000000
-0"
-0;
-0-
-1?
-1@
-14
-1)
-#2000000
-0#
-0>
-1-
-0B
-0?
-1F
-16
-1+
-0D
-0@
-05
-04
-0*
-0)
-#3000000
-0$
-0=
-0-
-1?
-1@
-14
-1)
-#4000000
-0%
-0<
-1-
-0E
-0?
-1D
-15
-1*
-0@
-04
-0)
-#5000000
-0&
-08
-0-
-1@
-14
-1)
-#6000000
-0'
-09
-1-
-1C
-0@
-17
-04
-1,
-0)
-0F
-0D
-06
-05
-0+
-0*
-#7000000
-1!
-0(
-1"
-1#
-1$
-1%
-1&
-1'
-1A
-0:
-1;
-1>
-1=
-1<
-18
-19
-0-
-1E
-1@
-14
-1)
-#8000000
-1(
-1:
-1-
-0C
-0@
-07
-04
-0,
-0)
-#9000000
diff --git a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.sft b/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.sft
deleted file mode 100644
index 06a2ca45..00000000
--- a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (Verilog)"
diff --git a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.sim.vwf b/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.sim.vwf
deleted file mode 100644
index 5c2a2fe9..00000000
--- a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.sim.vwf
+++ /dev/null
@@ -1,454 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-
-HEADER
-{
-	VERSION = 1;
-	TIME_UNIT = ns;
-	DATA_OFFSET = 0.0;
-	DATA_DURATION = 9000.0;
-	SIMULATION_TIME = 0.0;
-	GRID_PHASE = 0.0;
-	GRID_PERIOD = 1000.0;
-	GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("A")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("B")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("C")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("D")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("I2")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("I3")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("I4")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("I5")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("I6")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("I7")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("I8")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("I9")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-TRANSITION_LIST("A")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("B")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 2000.0;
-			LEVEL 0 FOR 2000.0;
-			LEVEL 1 FOR 2000.0;
-			LEVEL 0 FOR 3000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("C")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 2000.0;
-			LEVEL 1 FOR 4000.0;
-			LEVEL 0 FOR 3000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("D")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 6000.0;
-			LEVEL 1 FOR 2000.0;
-			LEVEL 0 FOR 1000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("I2")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 7000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("I3")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 6000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("I4")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 2000.0;
-			LEVEL 0 FOR 5000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("I5")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 3000.0;
-			LEVEL 0 FOR 4000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("I6")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 4000.0;
-			LEVEL 0 FOR 3000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("I7")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 5000.0;
-			LEVEL 0 FOR 2000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("I8")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 6000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("I9")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 7000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-		}
-	}
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "A";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 0;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "B";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 1;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "C";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 2;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "D";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 3;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I2";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 4;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I3";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 5;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I4";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 6;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I5";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 7;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I6";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 8;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I7";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 9;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I8";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 10;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I9";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 11;
-	TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
-	TIME = 0;
-	MASTER = TRUE;
-}
-;
diff --git a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.vo b/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.vo
deleted file mode 100644
index 7cdf41ee..00000000
--- a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.vo
+++ /dev/null
@@ -1,363 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-// VENDOR "Altera"
-// PROGRAM "Quartus II 32-bit"
-// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
-// DATE "10/17/2019 21:26:34"
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-// 
-// This Verilog file should be used for ModelSim-Altera (Verilog) only
-// 
-
-`timescale 1 ps/ 1 ps
-
-module ten_line_to_four_line_BCD_priority_encoder (
-	A,
-	I2,
-	I3,
-	I6,
-	I5,
-	I4,
-	I9,
-	I8,
-	I7,
-	B,
-	C,
-	D);
-output 	A;
-input 	I2;
-input 	I3;
-input 	I6;
-input 	I5;
-input 	I4;
-input 	I9;
-input 	I8;
-input 	I7;
-output 	B;
-output 	C;
-output 	D;
-
-// Design Ports Information
-// A	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// B	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// C	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// D	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// I6	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// I4	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// I3	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// I5	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// I7	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// I9	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// I8	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// I2	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-tri1 devclrn;
-tri1 devpor;
-tri1 devoe;
-wire \A~output_o ;
-wire \B~output_o ;
-wire \C~output_o ;
-wire \D~output_o ;
-wire \I9~input_o ;
-wire \I7~input_o ;
-wire \I8~input_o ;
-wire \I3~input_o ;
-wire \I6~input_o ;
-wire \I5~input_o ;
-wire \I4~input_o ;
-wire \inst|7~2_combout ;
-wire \inst|7~3_combout ;
-wire \I2~input_o ;
-wire \inst|8~4_combout ;
-wire \inst|67~combout ;
-wire \inst|8~5_combout ;
-wire \inst|9~0_combout ;
-wire \inst|9~1_combout ;
-
-
-// Location: IOOBUF_X0_Y26_N23
-cycloneiii_io_obuf \A~output (
-	.i(\inst|7~3_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\A~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \A~output .bus_hold = "false";
-defparam \A~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y26_N16
-cycloneiii_io_obuf \B~output (
-	.i(\inst|8~5_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\B~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \B~output .bus_hold = "false";
-defparam \B~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y27_N9
-cycloneiii_io_obuf \C~output (
-	.i(\inst|9~1_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\C~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \C~output .bus_hold = "false";
-defparam \C~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y27_N16
-cycloneiii_io_obuf \D~output (
-	.i(\inst|67~combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\D~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \D~output .bus_hold = "false";
-defparam \D~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y25_N22
-cycloneiii_io_ibuf \I9~input (
-	.i(I9),
-	.ibar(gnd),
-	.o(\I9~input_o ));
-// synopsys translate_off
-defparam \I9~input .bus_hold = "false";
-defparam \I9~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y27_N22
-cycloneiii_io_ibuf \I7~input (
-	.i(I7),
-	.ibar(gnd),
-	.o(\I7~input_o ));
-// synopsys translate_off
-defparam \I7~input .bus_hold = "false";
-defparam \I7~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N8
-cycloneiii_io_ibuf \I8~input (
-	.i(I8),
-	.ibar(gnd),
-	.o(\I8~input_o ));
-// synopsys translate_off
-defparam \I8~input .bus_hold = "false";
-defparam \I8~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y26_N1
-cycloneiii_io_ibuf \I3~input (
-	.i(I3),
-	.ibar(gnd),
-	.o(\I3~input_o ));
-// synopsys translate_off
-defparam \I3~input .bus_hold = "false";
-defparam \I3~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y22_N15
-cycloneiii_io_ibuf \I6~input (
-	.i(I6),
-	.ibar(gnd),
-	.o(\I6~input_o ));
-// synopsys translate_off
-defparam \I6~input .bus_hold = "false";
-defparam \I6~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y25_N15
-cycloneiii_io_ibuf \I5~input (
-	.i(I5),
-	.ibar(gnd),
-	.o(\I5~input_o ));
-// synopsys translate_off
-defparam \I5~input .bus_hold = "false";
-defparam \I5~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y26_N8
-cycloneiii_io_ibuf \I4~input (
-	.i(I4),
-	.ibar(gnd),
-	.o(\I4~input_o ));
-// synopsys translate_off
-defparam \I4~input .bus_hold = "false";
-defparam \I4~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y26_N24
-cycloneiii_lcell_comb \inst|7~2 (
-// Equation(s):
-// \inst|7~2_combout  = (\I6~input_o  & (((!\I3~input_o  & \I4~input_o )) # (!\I5~input_o )))
-
-	.dataa(\I3~input_o ),
-	.datab(\I6~input_o ),
-	.datac(\I5~input_o ),
-	.datad(\I4~input_o ),
-	.cin(gnd),
-	.combout(\inst|7~2_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|7~2 .lut_mask = 16'h4C0C;
-defparam \inst|7~2 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y26_N18
-cycloneiii_lcell_comb \inst|7~3 (
-// Equation(s):
-// \inst|7~3_combout  = ((\I8~input_o  & ((\inst|7~2_combout ) # (!\I7~input_o )))) # (!\I9~input_o )
-
-	.dataa(\I9~input_o ),
-	.datab(\I7~input_o ),
-	.datac(\I8~input_o ),
-	.datad(\inst|7~2_combout ),
-	.cin(gnd),
-	.combout(\inst|7~3_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|7~3 .lut_mask = 16'hF575;
-defparam \inst|7~3 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y25_N1
-cycloneiii_io_ibuf \I2~input (
-	.i(I2),
-	.ibar(gnd),
-	.o(\I2~input_o ));
-// synopsys translate_off
-defparam \I2~input .bus_hold = "false";
-defparam \I2~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y26_N12
-cycloneiii_lcell_comb \inst|8~4 (
-// Equation(s):
-// \inst|8~4_combout  = (\I5~input_o  & (\I4~input_o  & ((!\I2~input_o ) # (!\I3~input_o ))))
-
-	.dataa(\I3~input_o ),
-	.datab(\I2~input_o ),
-	.datac(\I5~input_o ),
-	.datad(\I4~input_o ),
-	.cin(gnd),
-	.combout(\inst|8~4_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|8~4 .lut_mask = 16'h7000;
-defparam \inst|8~4 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y26_N2
-cycloneiii_lcell_comb \inst|67 (
-// Equation(s):
-// \inst|67~combout  = (!\I9~input_o ) # (!\I8~input_o )
-
-	.dataa(gnd),
-	.datab(gnd),
-	.datac(\I8~input_o ),
-	.datad(\I9~input_o ),
-	.cin(gnd),
-	.combout(\inst|67~combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|67 .lut_mask = 16'h0FFF;
-defparam \inst|67 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y26_N20
-cycloneiii_lcell_comb \inst|8~5 (
-// Equation(s):
-// \inst|8~5_combout  = (!\inst|67~combout  & ((\inst|8~4_combout ) # ((!\I7~input_o ) # (!\I6~input_o ))))
-
-	.dataa(\inst|8~4_combout ),
-	.datab(\I6~input_o ),
-	.datac(\I7~input_o ),
-	.datad(\inst|67~combout ),
-	.cin(gnd),
-	.combout(\inst|8~5_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|8~5 .lut_mask = 16'h00BF;
-defparam \inst|8~5 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y26_N6
-cycloneiii_lcell_comb \inst|9~0 (
-// Equation(s):
-// \inst|9~0_combout  = (\I6~input_o  & \I7~input_o )
-
-	.dataa(gnd),
-	.datab(\I6~input_o ),
-	.datac(\I7~input_o ),
-	.datad(gnd),
-	.cin(gnd),
-	.combout(\inst|9~0_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|9~0 .lut_mask = 16'hC0C0;
-defparam \inst|9~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y26_N0
-cycloneiii_lcell_comb \inst|9~1 (
-// Equation(s):
-// \inst|9~1_combout  = (!\inst|67~combout  & (((!\inst|9~0_combout ) # (!\I5~input_o )) # (!\I4~input_o )))
-
-	.dataa(\I4~input_o ),
-	.datab(\inst|67~combout ),
-	.datac(\I5~input_o ),
-	.datad(\inst|9~0_combout ),
-	.cin(gnd),
-	.combout(\inst|9~1_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|9~1 .lut_mask = 16'h1333;
-defparam \inst|9~1 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-assign A = \A~output_o ;
-
-assign B = \B~output_o ;
-
-assign C = \C~output_o ;
-
-assign D = \D~output_o ;
-
-endmodule
diff --git a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.vwf.vt b/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.vwf.vt
deleted file mode 100644
index eea80dd6..00000000
--- a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder.vwf.vt
+++ /dev/null
@@ -1,370 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-// *****************************************************************************
-// This file contains a Verilog test bench with test vectors .The test vectors  
-// are exported from a vector file in the Quartus Waveform Editor and apply to  
-// the top level entity of the current Quartus project .The user can use this   
-// testbench to simulate his design using a third-party simulation tool .       
-// *****************************************************************************
-// Generated on "10/17/2019 21:16:23"
-                                                                        
-// Verilog Self-Checking Test Bench (with test vectors) for design :    ten_line_to_four_line_BCD_priority_encoder
-// 
-// Simulation tool : 3rd Party
-// 
-
-`timescale 1 ps/ 1 ps
-module ten_line_to_four_line_BCD_priority_encoder_vlg_sample_tst(
-	I2,
-	I3,
-	I4,
-	I5,
-	I6,
-	I7,
-	I8,
-	I9,
-	sampler_tx
-);
-input  I2;
-input  I3;
-input  I4;
-input  I5;
-input  I6;
-input  I7;
-input  I8;
-input  I9;
-output sampler_tx;
-
-reg sample;
-time current_time;
-always @(I2 or I3 or I4 or I5 or I6 or I7 or I8 or I9)
-                                                                                
-begin                                                 
- if ($realtime > 0)                                   
- begin                                                
-	if ($realtime == 0 || $realtime != current_time)  
-	begin									          
-		if (sample === 1'bx)                          
-			sample = 0;                               
-		else                                          
-			sample = ~sample;                         
-	end										          
-	current_time = $realtime;					      
- end                                                  
-end                                                   
-
-assign sampler_tx = sample;
-endmodule
-
-module ten_line_to_four_line_BCD_priority_encoder_vlg_check_tst (
-	A,
-	B,
-	C,
-	D,
-	sampler_rx
-);
-input  A;
-input  B;
-input  C;
-input  D;
-input sampler_rx;
-
-reg  A_expected;
-reg  B_expected;
-reg  C_expected;
-reg  D_expected;
-
-reg  A_prev;
-reg  B_prev;
-reg  C_prev;
-reg  D_prev;
-
-reg  A_expected_prev;
-reg  B_expected_prev;
-reg  C_expected_prev;
-reg  D_expected_prev;
-
-reg  last_A_exp;
-reg  last_B_exp;
-reg  last_C_exp;
-reg  last_D_exp;
-
-reg trigger;
-
-integer i;
-integer nummismatches;
-
-reg [1:4] on_first_change ;
-
-
-initial
-begin
-trigger = 0;
-i = 0;
-nummismatches = 0;
-on_first_change = 4'b1;
-end
-
-// update real /o prevs
-
-always @(trigger)
-begin
-	A_prev = A;
-	B_prev = B;
-	C_prev = C;
-	D_prev = D;
-end
-
-// update expected /o prevs
-
-always @(trigger)
-begin
-	A_expected_prev = A_expected;
-	B_expected_prev = B_expected;
-	C_expected_prev = C_expected;
-	D_expected_prev = D_expected;
-end
-
-
-
-// expected A
-initial
-begin
-	A_expected = 1'bX;
-	A_expected = #999000 1'b0;
-end 
-
-// expected B
-initial
-begin
-	B_expected = 1'bX;
-	B_expected = #999000 1'b0;
-end 
-
-// expected C
-initial
-begin
-	C_expected = 1'bX;
-	C_expected = #999000 1'b0;
-end 
-
-// expected D
-initial
-begin
-	D_expected = 1'bX;
-	D_expected = #999000 1'b0;
-end 
-// generate trigger
-always @(A_expected or A or B_expected or B or C_expected or C or D_expected or D)
-begin
-	trigger <= ~trigger;
-end
-
-always @(posedge sampler_rx or negedge sampler_rx)
-begin
-`ifdef debug_tbench
-	$display("Scanning pattern %d @time = %t",i,$realtime );
-	i = i + 1;
-	$display("| expected A = %b | expected B = %b | expected C = %b | expected D = %b | ",A_expected_prev,B_expected_prev,C_expected_prev,D_expected_prev);
-	$display("| real A = %b | real B = %b | real C = %b | real D = %b | ",A_prev,B_prev,C_prev,D_prev);
-`endif
-	if (
-		( A_expected_prev !== 1'bx ) && ( A_prev !== A_expected_prev )
-		&& ((A_expected_prev !== last_A_exp) ||
-			on_first_change[1])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port A :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", A_expected_prev);
-		$display ("     Real value = %b", A_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[1] = 1'b0;
-		last_A_exp = A_expected_prev;
-	end
-	if (
-		( B_expected_prev !== 1'bx ) && ( B_prev !== B_expected_prev )
-		&& ((B_expected_prev !== last_B_exp) ||
-			on_first_change[2])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port B :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", B_expected_prev);
-		$display ("     Real value = %b", B_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[2] = 1'b0;
-		last_B_exp = B_expected_prev;
-	end
-	if (
-		( C_expected_prev !== 1'bx ) && ( C_prev !== C_expected_prev )
-		&& ((C_expected_prev !== last_C_exp) ||
-			on_first_change[3])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port C :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", C_expected_prev);
-		$display ("     Real value = %b", C_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[3] = 1'b0;
-		last_C_exp = C_expected_prev;
-	end
-	if (
-		( D_expected_prev !== 1'bx ) && ( D_prev !== D_expected_prev )
-		&& ((D_expected_prev !== last_D_exp) ||
-			on_first_change[4])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port D :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", D_expected_prev);
-		$display ("     Real value = %b", D_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[4] = 1'b0;
-		last_D_exp = D_expected_prev;
-	end
-
-	trigger <= ~trigger;
-end
-initial 
-
-begin 
-$timeformat(-12,3," ps",6);
-#9000000;
-if (nummismatches > 0)
-	$display ("%d mismatched vectors : Simulation failed !",nummismatches);
-else
-	$display ("Simulation passed !");
-$finish;
-end 
-endmodule
-
-module ten_line_to_four_line_BCD_priority_encoder_vlg_vec_tst();
-// constants                                           
-// general purpose registers
-reg I2;
-reg I3;
-reg I4;
-reg I5;
-reg I6;
-reg I7;
-reg I8;
-reg I9;
-// wires                                               
-wire A;
-wire B;
-wire C;
-wire D;
-
-wire sampler;                             
-
-// assign statements (if any)                          
-ten_line_to_four_line_BCD_priority_encoder i1 (
-// port map - connection between master ports and signals/registers   
-	.A(A),
-	.B(B),
-	.C(C),
-	.D(D),
-	.I2(I2),
-	.I3(I3),
-	.I4(I4),
-	.I5(I5),
-	.I6(I6),
-	.I7(I7),
-	.I8(I8),
-	.I9(I9)
-);
-
-// I2
-initial
-begin
-	I2 = 1'b0;
-	I2 = #7000000 1'b1;
-end 
-
-// I3
-initial
-begin
-	I3 = 1'b1;
-	I3 = #1000000 1'b0;
-	I3 = #6000000 1'b1;
-end 
-
-// I4
-initial
-begin
-	I4 = 1'b1;
-	I4 = #2000000 1'b0;
-	I4 = #5000000 1'b1;
-end 
-
-// I5
-initial
-begin
-	I5 = 1'b1;
-	I5 = #3000000 1'b0;
-	I5 = #4000000 1'b1;
-end 
-
-// I6
-initial
-begin
-	I6 = 1'b1;
-	I6 = #4000000 1'b0;
-	I6 = #3000000 1'b1;
-end 
-
-// I7
-initial
-begin
-	I7 = 1'b1;
-	I7 = #5000000 1'b0;
-	I7 = #2000000 1'b1;
-end 
-
-// I8
-initial
-begin
-	I8 = 1'b1;
-	I8 = #6000000 1'b0;
-	I8 = #1000000 1'b1;
-end 
-
-// I9
-initial
-begin
-	I9 = 1'b1;
-	I9 = #7000000 1'b0;
-	I9 = #1000000 1'b1;
-end 
-
-ten_line_to_four_line_BCD_priority_encoder_vlg_sample_tst tb_sample (
-	.I2(I2),
-	.I3(I3),
-	.I4(I4),
-	.I5(I5),
-	.I6(I6),
-	.I7(I7),
-	.I8(I8),
-	.I9(I9),
-	.sampler_tx(sampler)
-);
-
-ten_line_to_four_line_BCD_priority_encoder_vlg_check_tst tb_out(
-	.A(A),
-	.B(B),
-	.C(C),
-	.D(D),
-	.sampler_rx(sampler)
-);
-endmodule
-
diff --git a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder_modelsim.xrf b/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder_modelsim.xrf
deleted file mode 100644
index 3ede13bf..00000000
--- a/CH6/CH6-1/simulation/qsim/ten_line_to_four_line_BCD_priority_encoder_modelsim.xrf
+++ /dev/null
@@ -1,25 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.vwf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/db/ten_line_to_four_line_BCD_priority_encoder.cbx.xml
-source_file = 1, /home/timmy/altera/13.1/quartus/libraries/others/maxplus2/74147.bdf
-design_name = ten_line_to_four_line_BCD_priority_encoder
-instance = comp, \A~output , A~output, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \B~output , B~output, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \C~output , C~output, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \D~output , D~output, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I9~input , I9~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I7~input , I7~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I8~input , I8~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I3~input , I3~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I6~input , I6~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I5~input , I5~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I4~input , I4~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|7~2 , inst|7~2, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|7~3 , inst|7~3, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \I2~input , I2~input, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|8~4 , inst|8~4, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|67 , inst|67, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|8~5 , inst|8~5, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|9~0 , inst|9~0, ten_line_to_four_line_BCD_priority_encoder, 1
-instance = comp, \inst|9~1 , inst|9~1, ten_line_to_four_line_BCD_priority_encoder, 1
diff --git a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.do b/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.do
deleted file mode 100644
index 02ca1432..00000000
--- a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.do
+++ /dev/null
@@ -1,10 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vlog -work work three_line_to_eight_decimal_decoder.vo
-vlog -work work three_line_to_eight_decimal_decoder.vwf.vt
-vsim -novopt -c -t 1ps -L cycloneiii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.three_line_to_eight_decimal_decoder_vlg_vec_tst -voptargs="+acc"
-vcd file -direction three_line_to_eight_decimal_decoder.msim.vcd
-vcd add -internal three_line_to_eight_decimal_decoder_vlg_vec_tst/*
-vcd add -internal three_line_to_eight_decimal_decoder_vlg_vec_tst/i1/*
-run -all
-quit -f
diff --git a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.msim.vcd b/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.msim.vcd
deleted file mode 100644
index d26b8f7a..00000000
--- a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.msim.vcd
+++ /dev/null
@@ -1,174 +0,0 @@
-$comment
-	File created using the following command:
-		vcd file three_line_to_eight_decimal_decoder.msim.vcd -direction
-$end
-$date
-	Thu Oct 24 21:53:31 2019
-$end
-$version
-	ModelSim Version 10.1d
-$end
-$timescale
-	1ps
-$end
-$scope module three_line_to_eight_decimal_decoder_vlg_vec_tst $end
-$var reg 1 ! A $end
-$var reg 1 " B $end
-$var reg 1 # C $end
-$var wire 1 $ Y0 $end
-$var wire 1 % Y1 $end
-$var wire 1 & Y2 $end
-$var wire 1 ' Y3 $end
-$var wire 1 ( Y4 $end
-$var wire 1 ) Y5 $end
-$var wire 1 * Y6 $end
-$var wire 1 + Y7 $end
-$var wire 1 , sampler $end
-$scope module i1 $end
-$var wire 1 - gnd $end
-$var wire 1 . vcc $end
-$var wire 1 / unknown $end
-$var tri1 1 0 devclrn $end
-$var tri1 1 1 devpor $end
-$var tri1 1 2 devoe $end
-$var wire 1 3 Y0~output_o $end
-$var wire 1 4 Y1~output_o $end
-$var wire 1 5 Y2~output_o $end
-$var wire 1 6 Y3~output_o $end
-$var wire 1 7 Y4~output_o $end
-$var wire 1 8 Y5~output_o $end
-$var wire 1 9 Y6~output_o $end
-$var wire 1 : Y7~output_o $end
-$var wire 1 ; C~input_o $end
-$var wire 1 < A~input_o $end
-$var wire 1 = B~input_o $end
-$var wire 1 > inst|33~0_combout $end
-$var wire 1 ? inst|33~1_combout $end
-$var wire 1 @ inst|33~2_combout $end
-$var wire 1 A inst|33~3_combout $end
-$var wire 1 B inst|33~4_combout $end
-$var wire 1 C inst|33~5_combout $end
-$var wire 1 D inst|33~6_combout $end
-$var wire 1 E inst|33~7_combout $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0!
-0"
-0#
-0$
-1%
-1&
-1'
-1(
-1)
-1*
-1+
-x,
-0-
-1.
-x/
-10
-11
-12
-03
-14
-15
-16
-17
-18
-19
-1:
-0;
-0<
-0=
-1>
-0?
-0@
-0A
-0B
-0C
-0D
-0E
-$end
-#1000000
-1!
-1<
-0,
-1?
-0>
-04
-13
-0%
-1$
-#2000000
-1"
-0!
-1=
-0<
-1,
-1@
-0?
-05
-14
-0&
-1%
-#3000000
-1!
-1<
-0,
-1A
-0@
-06
-15
-0'
-1&
-#4000000
-1#
-0"
-0!
-1;
-0=
-0<
-1,
-1B
-0A
-07
-16
-0(
-1'
-#5000000
-1!
-1<
-0,
-1C
-0B
-08
-17
-0)
-1(
-#6000000
-1"
-0!
-1=
-0<
-1,
-1D
-0C
-09
-18
-0*
-1)
-#7000000
-1!
-1<
-0,
-1E
-0D
-0:
-19
-0+
-1*
-#8000000
diff --git a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.sft b/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.sft
deleted file mode 100644
index 06a2ca45..00000000
--- a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (Verilog)"
diff --git a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.sim.vwf b/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.sim.vwf
deleted file mode 100644
index 40185dd4..00000000
--- a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.sim.vwf
+++ /dev/null
@@ -1,417 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-
-HEADER
-{
-	VERSION = 1;
-	TIME_UNIT = ns;
-	DATA_OFFSET = 0.0;
-	DATA_DURATION = 8000.0;
-	SIMULATION_TIME = 0.0;
-	GRID_PHASE = 0.0;
-	GRID_PERIOD = 1000.0;
-	GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("A")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("B")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("C")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y0")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y1")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y2")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y3")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y4")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y5")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y6")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("Y7")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-TRANSITION_LIST("A")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("B")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 2000.0;
-			LEVEL 1 FOR 2000.0;
-			LEVEL 0 FOR 2000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("C")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 4000.0;
-			LEVEL 1 FOR 4000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y0")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 7000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y1")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 1000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 6000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y2")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 2000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 5000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y3")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 3000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 4000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y4")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 4000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 3000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y5")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 5000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y6")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 6000.0;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y7")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 1 FOR 7000.0;
-			LEVEL 0 FOR 1000.0;
-		}
-	}
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "A";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 0;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "B";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 1;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "C";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 2;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y0";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 3;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y1";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 4;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y2";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 5;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y3";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 6;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y4";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 7;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y5";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 8;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y6";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 9;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y7";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 10;
-	TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
-	TIME = 0;
-	MASTER = TRUE;
-}
-;
diff --git a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.vo b/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.vo
deleted file mode 100644
index a628f2e0..00000000
--- a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.vo
+++ /dev/null
@@ -1,387 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-// VENDOR "Altera"
-// PROGRAM "Quartus II 32-bit"
-// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
-// DATE "10/24/2019 21:58:03"
-
-// 
-// Device: Altera EP3C16F484C6 Package FBGA484
-// 
-
-// 
-// This Verilog file should be used for ModelSim-Altera (Verilog) only
-// 
-
-`timescale 1 ps/ 1 ps
-
-module three_line_to_eight_decimal_decoder (
-	Y0,
-	A,
-	B,
-	C,
-	Y1,
-	Y2,
-	Y3,
-	Y4,
-	Y5,
-	Y6,
-	Y7);
-output 	Y0;
-input 	A;
-input 	B;
-input 	C;
-output 	Y1;
-output 	Y2;
-output 	Y3;
-output 	Y4;
-output 	Y5;
-output 	Y6;
-output 	Y7;
-
-// Design Ports Information
-// Y0	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y1	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y2	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y3	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y4	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y5	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y6	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// Y7	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// C	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// A	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-// B	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-tri1 devclrn;
-tri1 devpor;
-tri1 devoe;
-wire \Y0~output_o ;
-wire \Y1~output_o ;
-wire \Y2~output_o ;
-wire \Y3~output_o ;
-wire \Y4~output_o ;
-wire \Y5~output_o ;
-wire \Y6~output_o ;
-wire \Y7~output_o ;
-wire \C~input_o ;
-wire \B~input_o ;
-wire \A~input_o ;
-wire \inst|33~0_combout ;
-wire \inst|33~1_combout ;
-wire \inst|33~2_combout ;
-wire \inst|33~3_combout ;
-wire \inst|33~4_combout ;
-wire \inst|33~5_combout ;
-wire \inst|33~6_combout ;
-wire \inst|33~7_combout ;
-
-
-// Location: IOOBUF_X0_Y27_N16
-cycloneiii_io_obuf \Y0~output (
-	.i(!\inst|33~0_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y0~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y0~output .bus_hold = "false";
-defparam \Y0~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y27_N9
-cycloneiii_io_obuf \Y1~output (
-	.i(!\inst|33~1_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y1~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y1~output .bus_hold = "false";
-defparam \Y1~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y26_N16
-cycloneiii_io_obuf \Y2~output (
-	.i(!\inst|33~2_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y2~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y2~output .bus_hold = "false";
-defparam \Y2~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y26_N23
-cycloneiii_io_obuf \Y3~output (
-	.i(!\inst|33~3_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y3~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y3~output .bus_hold = "false";
-defparam \Y3~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y24_N16
-cycloneiii_io_obuf \Y4~output (
-	.i(!\inst|33~4_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y4~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y4~output .bus_hold = "false";
-defparam \Y4~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y24_N23
-cycloneiii_io_obuf \Y5~output (
-	.i(!\inst|33~5_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y5~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y5~output .bus_hold = "false";
-defparam \Y5~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y21_N16
-cycloneiii_io_obuf \Y6~output (
-	.i(!\inst|33~6_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y6~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y6~output .bus_hold = "false";
-defparam \Y6~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y21_N23
-cycloneiii_io_obuf \Y7~output (
-	.i(!\inst|33~7_combout ),
-	.oe(vcc),
-	.seriesterminationcontrol(16'b0000000000000000),
-	.devoe(devoe),
-	.o(\Y7~output_o ),
-	.obar());
-// synopsys translate_off
-defparam \Y7~output .bus_hold = "false";
-defparam \Y7~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y25_N1
-cycloneiii_io_ibuf \C~input (
-	.i(C),
-	.ibar(gnd),
-	.o(\C~input_o ));
-// synopsys translate_off
-defparam \C~input .bus_hold = "false";
-defparam \C~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y26_N1
-cycloneiii_io_ibuf \B~input (
-	.i(B),
-	.ibar(gnd),
-	.o(\B~input_o ));
-// synopsys translate_off
-defparam \B~input .bus_hold = "false";
-defparam \B~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y26_N8
-cycloneiii_io_ibuf \A~input (
-	.i(A),
-	.ibar(gnd),
-	.o(\A~input_o ));
-// synopsys translate_off
-defparam \A~input .bus_hold = "false";
-defparam \A~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y25_N0
-cycloneiii_lcell_comb \inst|33~0 (
-// Equation(s):
-// \inst|33~0_combout  = (!\C~input_o  & (!\B~input_o  & !\A~input_o ))
-
-	.dataa(\C~input_o ),
-	.datab(gnd),
-	.datac(\B~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|33~0_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|33~0 .lut_mask = 16'h0005;
-defparam \inst|33~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y25_N10
-cycloneiii_lcell_comb \inst|33~1 (
-// Equation(s):
-// \inst|33~1_combout  = (!\C~input_o  & (!\B~input_o  & \A~input_o ))
-
-	.dataa(\C~input_o ),
-	.datab(gnd),
-	.datac(\B~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|33~1_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|33~1 .lut_mask = 16'h0500;
-defparam \inst|33~1 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y25_N12
-cycloneiii_lcell_comb \inst|33~2 (
-// Equation(s):
-// \inst|33~2_combout  = (!\C~input_o  & (\B~input_o  & !\A~input_o ))
-
-	.dataa(\C~input_o ),
-	.datab(gnd),
-	.datac(\B~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|33~2_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|33~2 .lut_mask = 16'h0050;
-defparam \inst|33~2 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y25_N14
-cycloneiii_lcell_comb \inst|33~3 (
-// Equation(s):
-// \inst|33~3_combout  = (!\C~input_o  & (\B~input_o  & \A~input_o ))
-
-	.dataa(\C~input_o ),
-	.datab(gnd),
-	.datac(\B~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|33~3_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|33~3 .lut_mask = 16'h5000;
-defparam \inst|33~3 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y25_N8
-cycloneiii_lcell_comb \inst|33~4 (
-// Equation(s):
-// \inst|33~4_combout  = (\C~input_o  & (!\B~input_o  & !\A~input_o ))
-
-	.dataa(\C~input_o ),
-	.datab(gnd),
-	.datac(\B~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|33~4_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|33~4 .lut_mask = 16'h000A;
-defparam \inst|33~4 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y25_N18
-cycloneiii_lcell_comb \inst|33~5 (
-// Equation(s):
-// \inst|33~5_combout  = (\C~input_o  & (!\B~input_o  & \A~input_o ))
-
-	.dataa(\C~input_o ),
-	.datab(gnd),
-	.datac(\B~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|33~5_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|33~5 .lut_mask = 16'h0A00;
-defparam \inst|33~5 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y25_N20
-cycloneiii_lcell_comb \inst|33~6 (
-// Equation(s):
-// \inst|33~6_combout  = (\C~input_o  & (\B~input_o  & !\A~input_o ))
-
-	.dataa(\C~input_o ),
-	.datab(gnd),
-	.datac(\B~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|33~6_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|33~6 .lut_mask = 16'h00A0;
-defparam \inst|33~6 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X1_Y25_N22
-cycloneiii_lcell_comb \inst|33~7 (
-// Equation(s):
-// \inst|33~7_combout  = (\C~input_o  & (\B~input_o  & \A~input_o ))
-
-	.dataa(\C~input_o ),
-	.datab(gnd),
-	.datac(\B~input_o ),
-	.datad(\A~input_o ),
-	.cin(gnd),
-	.combout(\inst|33~7_combout ),
-	.cout());
-// synopsys translate_off
-defparam \inst|33~7 .lut_mask = 16'hA000;
-defparam \inst|33~7 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-assign Y0 = \Y0~output_o ;
-
-assign Y1 = \Y1~output_o ;
-
-assign Y2 = \Y2~output_o ;
-
-assign Y3 = \Y3~output_o ;
-
-assign Y4 = \Y4~output_o ;
-
-assign Y5 = \Y5~output_o ;
-
-assign Y6 = \Y6~output_o ;
-
-assign Y7 = \Y7~output_o ;
-
-endmodule
diff --git a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.vwf.vt b/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.vwf.vt
deleted file mode 100644
index 0ab2b8d3..00000000
--- a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder.vwf.vt
+++ /dev/null
@@ -1,430 +0,0 @@
-// Copyright (C) 1991-2013 Altera Corporation
-// Your use of Altera Corporation's design tools, logic functions 
-// and other software and tools, and its AMPP partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License 
-// Subscription Agreement, Altera MegaCore Function License 
-// Agreement, or other applicable license agreement, including, 
-// without limitation, that your use is for the sole purpose of 
-// programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the 
-// applicable agreement for further details.
-
-// *****************************************************************************
-// This file contains a Verilog test bench with test vectors .The test vectors  
-// are exported from a vector file in the Quartus Waveform Editor and apply to  
-// the top level entity of the current Quartus project .The user can use this   
-// testbench to simulate his design using a third-party simulation tool .       
-// *****************************************************************************
-// Generated on "10/24/2019 21:53:25"
-                                                                        
-// Verilog Self-Checking Test Bench (with test vectors) for design :    three_line_to_eight_decimal_decoder
-// 
-// Simulation tool : 3rd Party
-// 
-
-`timescale 1 ps/ 1 ps
-module three_line_to_eight_decimal_decoder_vlg_sample_tst(
-	A,
-	B,
-	C,
-	sampler_tx
-);
-input  A;
-input  B;
-input  C;
-output sampler_tx;
-
-reg sample;
-time current_time;
-always @(A or B or C)
-                                                                                
-begin                                                 
- if ($realtime > 0)                                   
- begin                                                
-	if ($realtime == 0 || $realtime != current_time)  
-	begin									          
-		if (sample === 1'bx)                          
-			sample = 0;                               
-		else                                          
-			sample = ~sample;                         
-	end										          
-	current_time = $realtime;					      
- end                                                  
-end                                                   
-
-assign sampler_tx = sample;
-endmodule
-
-module three_line_to_eight_decimal_decoder_vlg_check_tst (
-	Y0,
-	Y1,
-	Y2,
-	Y3,
-	Y4,
-	Y5,
-	Y6,
-	Y7,
-	sampler_rx
-);
-input  Y0;
-input  Y1;
-input  Y2;
-input  Y3;
-input  Y4;
-input  Y5;
-input  Y6;
-input  Y7;
-input sampler_rx;
-
-reg  Y0_expected;
-reg  Y1_expected;
-reg  Y2_expected;
-reg  Y3_expected;
-reg  Y4_expected;
-reg  Y5_expected;
-reg  Y6_expected;
-reg  Y7_expected;
-
-reg  Y0_prev;
-reg  Y1_prev;
-reg  Y2_prev;
-reg  Y3_prev;
-reg  Y4_prev;
-reg  Y5_prev;
-reg  Y6_prev;
-reg  Y7_prev;
-
-reg  Y0_expected_prev;
-reg  Y1_expected_prev;
-reg  Y2_expected_prev;
-reg  Y3_expected_prev;
-reg  Y4_expected_prev;
-reg  Y5_expected_prev;
-reg  Y6_expected_prev;
-reg  Y7_expected_prev;
-
-reg  last_Y0_exp;
-reg  last_Y1_exp;
-reg  last_Y2_exp;
-reg  last_Y3_exp;
-reg  last_Y4_exp;
-reg  last_Y5_exp;
-reg  last_Y6_exp;
-reg  last_Y7_exp;
-
-reg trigger;
-
-integer i;
-integer nummismatches;
-
-reg [1:8] on_first_change ;
-
-
-initial
-begin
-trigger = 0;
-i = 0;
-nummismatches = 0;
-on_first_change = 8'b1;
-end
-
-// update real /o prevs
-
-always @(trigger)
-begin
-	Y0_prev = Y0;
-	Y1_prev = Y1;
-	Y2_prev = Y2;
-	Y3_prev = Y3;
-	Y4_prev = Y4;
-	Y5_prev = Y5;
-	Y6_prev = Y6;
-	Y7_prev = Y7;
-end
-
-// update expected /o prevs
-
-always @(trigger)
-begin
-	Y0_expected_prev = Y0_expected;
-	Y1_expected_prev = Y1_expected;
-	Y2_expected_prev = Y2_expected;
-	Y3_expected_prev = Y3_expected;
-	Y4_expected_prev = Y4_expected;
-	Y5_expected_prev = Y5_expected;
-	Y6_expected_prev = Y6_expected;
-	Y7_expected_prev = Y7_expected;
-end
-
-
-
-// expected Y0
-initial
-begin
-	Y0_expected = 1'bX;
-	Y0_expected = #999000 1'b0;
-end 
-
-// expected Y1
-initial
-begin
-	Y1_expected = 1'bX;
-	Y1_expected = #999000 1'b0;
-end 
-
-// expected Y2
-initial
-begin
-	Y2_expected = 1'bX;
-	Y2_expected = #999000 1'b0;
-end 
-
-// expected Y3
-initial
-begin
-	Y3_expected = 1'bX;
-	Y3_expected = #999000 1'b0;
-end 
-
-// expected Y4
-initial
-begin
-	Y4_expected = 1'bX;
-	Y4_expected = #999000 1'b0;
-end 
-
-// expected Y5
-initial
-begin
-	Y5_expected = 1'bX;
-	Y5_expected = #999000 1'b0;
-end 
-
-// expected Y6
-initial
-begin
-	Y6_expected = 1'bX;
-	Y6_expected = #999000 1'b0;
-end 
-
-// expected Y7
-initial
-begin
-	Y7_expected = 1'bX;
-	Y7_expected = #999000 1'b0;
-end 
-// generate trigger
-always @(Y0_expected or Y0 or Y1_expected or Y1 or Y2_expected or Y2 or Y3_expected or Y3 or Y4_expected or Y4 or Y5_expected or Y5 or Y6_expected or Y6 or Y7_expected or Y7)
-begin
-	trigger <= ~trigger;
-end
-
-always @(posedge sampler_rx or negedge sampler_rx)
-begin
-`ifdef debug_tbench
-	$display("Scanning pattern %d @time = %t",i,$realtime );
-	i = i + 1;
-	$display("| expected Y0 = %b | expected Y1 = %b | expected Y2 = %b | expected Y3 = %b | expected Y4 = %b | expected Y5 = %b | expected Y6 = %b | expected Y7 = %b | ",Y0_expected_prev,Y1_expected_prev,Y2_expected_prev,Y3_expected_prev,Y4_expected_prev,Y5_expected_prev,Y6_expected_prev,Y7_expected_prev);
-	$display("| real Y0 = %b | real Y1 = %b | real Y2 = %b | real Y3 = %b | real Y4 = %b | real Y5 = %b | real Y6 = %b | real Y7 = %b | ",Y0_prev,Y1_prev,Y2_prev,Y3_prev,Y4_prev,Y5_prev,Y6_prev,Y7_prev);
-`endif
-	if (
-		( Y0_expected_prev !== 1'bx ) && ( Y0_prev !== Y0_expected_prev )
-		&& ((Y0_expected_prev !== last_Y0_exp) ||
-			on_first_change[1])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y0 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y0_expected_prev);
-		$display ("     Real value = %b", Y0_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[1] = 1'b0;
-		last_Y0_exp = Y0_expected_prev;
-	end
-	if (
-		( Y1_expected_prev !== 1'bx ) && ( Y1_prev !== Y1_expected_prev )
-		&& ((Y1_expected_prev !== last_Y1_exp) ||
-			on_first_change[2])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y1 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y1_expected_prev);
-		$display ("     Real value = %b", Y1_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[2] = 1'b0;
-		last_Y1_exp = Y1_expected_prev;
-	end
-	if (
-		( Y2_expected_prev !== 1'bx ) && ( Y2_prev !== Y2_expected_prev )
-		&& ((Y2_expected_prev !== last_Y2_exp) ||
-			on_first_change[3])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y2 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y2_expected_prev);
-		$display ("     Real value = %b", Y2_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[3] = 1'b0;
-		last_Y2_exp = Y2_expected_prev;
-	end
-	if (
-		( Y3_expected_prev !== 1'bx ) && ( Y3_prev !== Y3_expected_prev )
-		&& ((Y3_expected_prev !== last_Y3_exp) ||
-			on_first_change[4])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y3 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y3_expected_prev);
-		$display ("     Real value = %b", Y3_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[4] = 1'b0;
-		last_Y3_exp = Y3_expected_prev;
-	end
-	if (
-		( Y4_expected_prev !== 1'bx ) && ( Y4_prev !== Y4_expected_prev )
-		&& ((Y4_expected_prev !== last_Y4_exp) ||
-			on_first_change[5])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y4 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y4_expected_prev);
-		$display ("     Real value = %b", Y4_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[5] = 1'b0;
-		last_Y4_exp = Y4_expected_prev;
-	end
-	if (
-		( Y5_expected_prev !== 1'bx ) && ( Y5_prev !== Y5_expected_prev )
-		&& ((Y5_expected_prev !== last_Y5_exp) ||
-			on_first_change[6])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y5 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y5_expected_prev);
-		$display ("     Real value = %b", Y5_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[6] = 1'b0;
-		last_Y5_exp = Y5_expected_prev;
-	end
-	if (
-		( Y6_expected_prev !== 1'bx ) && ( Y6_prev !== Y6_expected_prev )
-		&& ((Y6_expected_prev !== last_Y6_exp) ||
-			on_first_change[7])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y6 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y6_expected_prev);
-		$display ("     Real value = %b", Y6_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[7] = 1'b0;
-		last_Y6_exp = Y6_expected_prev;
-	end
-	if (
-		( Y7_expected_prev !== 1'bx ) && ( Y7_prev !== Y7_expected_prev )
-		&& ((Y7_expected_prev !== last_Y7_exp) ||
-			on_first_change[8])
-	)
-	begin
-		$display ("ERROR! Vector Mismatch for output port Y7 :: @time = %t",  $realtime);
-		$display ("     Expected value = %b", Y7_expected_prev);
-		$display ("     Real value = %b", Y7_prev);
-		nummismatches = nummismatches + 1;
-		on_first_change[8] = 1'b0;
-		last_Y7_exp = Y7_expected_prev;
-	end
-
-	trigger <= ~trigger;
-end
-initial 
-
-begin 
-$timeformat(-12,3," ps",6);
-#8000000;
-if (nummismatches > 0)
-	$display ("%d mismatched vectors : Simulation failed !",nummismatches);
-else
-	$display ("Simulation passed !");
-$finish;
-end 
-endmodule
-
-module three_line_to_eight_decimal_decoder_vlg_vec_tst();
-// constants                                           
-// general purpose registers
-reg A;
-reg B;
-reg C;
-// wires                                               
-wire Y0;
-wire Y1;
-wire Y2;
-wire Y3;
-wire Y4;
-wire Y5;
-wire Y6;
-wire Y7;
-
-wire sampler;                             
-
-// assign statements (if any)                          
-three_line_to_eight_decimal_decoder i1 (
-// port map - connection between master ports and signals/registers   
-	.A(A),
-	.B(B),
-	.C(C),
-	.Y0(Y0),
-	.Y1(Y1),
-	.Y2(Y2),
-	.Y3(Y3),
-	.Y4(Y4),
-	.Y5(Y5),
-	.Y6(Y6),
-	.Y7(Y7)
-);
-
-// A
-always
-begin
-	A = 1'b0;
-	A = #1000000 1'b1;
-	#1000000;
-end 
-
-// B
-always
-begin
-	B = 1'b0;
-	B = #2000000 1'b1;
-	#2000000;
-end 
-
-// C
-always
-begin
-	C = 1'b0;
-	C = #4000000 1'b1;
-	#4000000;
-end 
-
-three_line_to_eight_decimal_decoder_vlg_sample_tst tb_sample (
-	.A(A),
-	.B(B),
-	.C(C),
-	.sampler_tx(sampler)
-);
-
-three_line_to_eight_decimal_decoder_vlg_check_tst tb_out(
-	.Y0(Y0),
-	.Y1(Y1),
-	.Y2(Y2),
-	.Y3(Y3),
-	.Y4(Y4),
-	.Y5(Y5),
-	.Y6(Y6),
-	.Y7(Y7),
-	.sampler_rx(sampler)
-);
-endmodule
-
diff --git a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder_modelsim.xrf b/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder_modelsim.xrf
deleted file mode 100644
index 1e5a2212..00000000
--- a/CH6/CH6-1/simulation/qsim/three_line_to_eight_decimal_decoder_modelsim.xrf
+++ /dev/null
@@ -1,25 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/three_line_to_eight_decimal_decoder.vwf
-source_file = 1, /home/timmy/Git/Learn-VHDL/CH6/CH6-1/db/three_line_to_eight_decimal_decoder.cbx.xml
-source_file = 1, /home/timmy/altera/13.1/quartus/libraries/others/maxplus2/74139.bdf
-design_name = three_line_to_eight_decimal_decoder
-instance = comp, \Y0~output , Y0~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y1~output , Y1~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y2~output , Y2~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y3~output , Y3~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y4~output , Y4~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y5~output , Y5~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y6~output , Y6~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \Y7~output , Y7~output, three_line_to_eight_decimal_decoder, 1
-instance = comp, \C~input , C~input, three_line_to_eight_decimal_decoder, 1
-instance = comp, \B~input , B~input, three_line_to_eight_decimal_decoder, 1
-instance = comp, \A~input , A~input, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~0 , inst|33~0, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~1 , inst|33~1, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~2 , inst|33~2, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~3 , inst|33~3, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~4 , inst|33~4, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~5 , inst|33~5, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~6 , inst|33~6, three_line_to_eight_decimal_decoder, 1
-instance = comp, \inst|33~7 , inst|33~7, three_line_to_eight_decimal_decoder, 1
diff --git a/CH6/CH6-1/simulation/qsim/transcript b/CH6/CH6-1/simulation/qsim/transcript
deleted file mode 100644
index 7301c4f4..00000000
--- a/CH6/CH6-1/simulation/qsim/transcript
+++ /dev/null
@@ -1,73 +0,0 @@
-# do four_line_to_sixteen_line_decimal_decoder.do 
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
-# -- Compiling module four_line_to_sixteen_line_decimal_decoder
-# 
-# Top level modules:
-# 	four_line_to_sixteen_line_decimal_decoder
-# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
-# -- Compiling module four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst
-# -- Compiling module four_line_to_sixteen_line_decimal_decoder_vlg_check_tst
-# -- Compiling module four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst
-# 
-# Top level modules:
-# 	four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst
-# vsim -L cycloneiii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate -c -voptargs=\"+acc\" -t 1ps -novopt work.four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst 
-# Loading work.four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst
-# Loading work.four_line_to_sixteen_line_decimal_decoder
-# Loading cycloneiii_ver.cycloneiii_io_obuf
-# Loading cycloneiii_ver.cycloneiii_io_ibuf
-# Loading cycloneiii_ver.cycloneiii_lcell_comb
-# Loading work.four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst
-# Loading work.four_line_to_sixteen_line_decimal_decoder_vlg_check_tst
-# ERROR! Vector Mismatch for output port Y0 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y1 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y3 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y4 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y5 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y6 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y7 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y8 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y9 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y10 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y11 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y12 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y13 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y14 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y15 :: @time = 1000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-# ERROR! Vector Mismatch for output port Y2 :: @time = 2000000.000 ps
-#      Expected value = 0
-#      Real value = 1
-#          16 mismatched vectors : Simulation failed !
-# ** Note: $finish    : four_line_to_sixteen_line_decimal_decoder.vwf.vt(575)
-#    Time: 10 us  Iteration: 0  Instance: /four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/tb_out
diff --git a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder/_primary.dat b/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder/_primary.dat
deleted file mode 100644
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diff --git a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder/_primary.vhd
deleted file mode 100644
index 23133e46..00000000
--- a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder/_primary.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity BCD_to_decimal_decoder is
-    port(
-        Y0              : out    vl_logic;
-        A               : in     vl_logic;
-        B               : in     vl_logic;
-        C               : in     vl_logic;
-        D               : in     vl_logic;
-        Y1              : out    vl_logic;
-        Y2              : out    vl_logic;
-        Y3              : out    vl_logic;
-        Y4              : out    vl_logic;
-        Y5              : out    vl_logic;
-        Y6              : out    vl_logic;
-        Y7              : out    vl_logic;
-        Y8              : out    vl_logic;
-        Y9              : out    vl_logic
-    );
-end BCD_to_decimal_decoder;
diff --git a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder/verilog.prw b/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder/verilog.prw
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diff --git a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_check_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_check_tst/_primary.vhd
deleted file mode 100644
index 045545db..00000000
--- a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_check_tst/_primary.vhd
+++ /dev/null
@@ -1,17 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity BCD_to_decimal_decoder_vlg_check_tst is
-    port(
-        Y0              : in     vl_logic;
-        Y1              : in     vl_logic;
-        Y2              : in     vl_logic;
-        Y3              : in     vl_logic;
-        Y4              : in     vl_logic;
-        Y5              : in     vl_logic;
-        Y6              : in     vl_logic;
-        Y7              : in     vl_logic;
-        Y8              : in     vl_logic;
-        Y9              : in     vl_logic;
-        sampler_rx      : in     vl_logic
-    );
-end BCD_to_decimal_decoder_vlg_check_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_check_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_check_tst/verilog.prw
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diff --git a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_sample_tst/_primary.dat b/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_sample_tst/_primary.dat
deleted file mode 100644
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diff --git a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_sample_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_sample_tst/_primary.vhd
deleted file mode 100644
index e3b19d1e..00000000
--- a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_sample_tst/_primary.vhd
+++ /dev/null
@@ -1,11 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity BCD_to_decimal_decoder_vlg_sample_tst is
-    port(
-        A               : in     vl_logic;
-        B               : in     vl_logic;
-        C               : in     vl_logic;
-        D               : in     vl_logic;
-        sampler_tx      : out    vl_logic
-    );
-end BCD_to_decimal_decoder_vlg_sample_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_sample_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_sample_tst/verilog.prw
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diff --git a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_vec_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_vec_tst/_primary.vhd
deleted file mode 100644
index cb2486de..00000000
--- a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_vec_tst/_primary.vhd
+++ /dev/null
@@ -1,4 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity BCD_to_decimal_decoder_vlg_vec_tst is
-end BCD_to_decimal_decoder_vlg_vec_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_vec_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/@b@c@d_to_decimal_decoder_vlg_vec_tst/verilog.prw
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder/_primary.vhd
deleted file mode 100644
index 9f1da7d9..00000000
--- a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder/_primary.vhd
+++ /dev/null
@@ -1,26 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity four_line_to_sixteen_line_decimal_decoder is
-    port(
-        Y0              : out    vl_logic;
-        A               : in     vl_logic;
-        B               : in     vl_logic;
-        C               : in     vl_logic;
-        D               : in     vl_logic;
-        Y1              : out    vl_logic;
-        Y2              : out    vl_logic;
-        Y3              : out    vl_logic;
-        Y4              : out    vl_logic;
-        Y5              : out    vl_logic;
-        Y6              : out    vl_logic;
-        Y7              : out    vl_logic;
-        Y8              : out    vl_logic;
-        Y9              : out    vl_logic;
-        Y10             : out    vl_logic;
-        Y11             : out    vl_logic;
-        Y12             : out    vl_logic;
-        Y13             : out    vl_logic;
-        Y14             : out    vl_logic;
-        Y15             : out    vl_logic
-    );
-end four_line_to_sixteen_line_decimal_decoder;
diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder/verilog.prw b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder/verilog.prw
deleted file mode 100644
index 59457307713cd62ee70719022e7e0d2ef10f434f..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder/verilog.psm b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder/verilog.psm
deleted file mode 100644
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GIT binary patch
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_check_tst/_primary.dbs b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_check_tst/_primary.dbs
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_check_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_check_tst/_primary.vhd
deleted file mode 100644
index 289d80ec..00000000
--- a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_check_tst/_primary.vhd
+++ /dev/null
@@ -1,23 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity four_line_to_sixteen_line_decimal_decoder_vlg_check_tst is
-    port(
-        Y0              : in     vl_logic;
-        Y1              : in     vl_logic;
-        Y2              : in     vl_logic;
-        Y3              : in     vl_logic;
-        Y4              : in     vl_logic;
-        Y5              : in     vl_logic;
-        Y6              : in     vl_logic;
-        Y7              : in     vl_logic;
-        Y8              : in     vl_logic;
-        Y9              : in     vl_logic;
-        Y10             : in     vl_logic;
-        Y11             : in     vl_logic;
-        Y12             : in     vl_logic;
-        Y13             : in     vl_logic;
-        Y14             : in     vl_logic;
-        Y15             : in     vl_logic;
-        sampler_rx      : in     vl_logic
-    );
-end four_line_to_sixteen_line_decimal_decoder_vlg_check_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_check_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_check_tst/verilog.prw
deleted file mode 100644
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GIT binary patch
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_check_tst/verilog.psm b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_check_tst/verilog.psm
deleted file mode 100644
index cfd8971d192fa9792f92f27a6f77d31837169457..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst/_primary.dat b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst/_primary.dat
deleted file mode 100644
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst/_primary.dbs b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst/_primary.dbs
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst/_primary.vhd
deleted file mode 100644
index 1c793a90..00000000
--- a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst/_primary.vhd
+++ /dev/null
@@ -1,11 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst is
-    port(
-        A               : in     vl_logic;
-        B               : in     vl_logic;
-        C               : in     vl_logic;
-        D               : in     vl_logic;
-        sampler_tx      : out    vl_logic
-    );
-end four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst/verilog.prw
deleted file mode 100644
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GIT binary patch
literal 0
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst/verilog.psm b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_sample_tst/verilog.psm
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/_primary.dat b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/_primary.dat
deleted file mode 100644
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/_primary.vhd
deleted file mode 100644
index 5294db4a..00000000
--- a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/_primary.vhd
+++ /dev/null
@@ -1,4 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst is
-end four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/verilog.prw
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diff --git a/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/verilog.psm b/CH6/CH6-1/simulation/qsim/work/four_line_to_sixteen_line_decimal_decoder_vlg_vec_tst/verilog.psm
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diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder/_primary.vhd
deleted file mode 100644
index 6248c82c..00000000
--- a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder/_primary.vhd
+++ /dev/null
@@ -1,18 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity ten_line_to_four_line_BCD_priority_encoder is
-    port(
-        A               : out    vl_logic;
-        I2              : in     vl_logic;
-        I3              : in     vl_logic;
-        I6              : in     vl_logic;
-        I5              : in     vl_logic;
-        I4              : in     vl_logic;
-        I9              : in     vl_logic;
-        I8              : in     vl_logic;
-        I7              : in     vl_logic;
-        B               : out    vl_logic;
-        C               : out    vl_logic;
-        D               : out    vl_logic
-    );
-end ten_line_to_four_line_BCD_priority_encoder;
diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder/verilog.prw b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder/verilog.prw
deleted file mode 100644
index e2e5fdf7f38f6ec34b117c2688d5a21cdb0329ce..0000000000000000000000000000000000000000
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diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder/verilog.psm b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder/verilog.psm
deleted file mode 100644
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diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_check_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_check_tst/_primary.vhd
deleted file mode 100644
index ca2c4e74..00000000
--- a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_check_tst/_primary.vhd
+++ /dev/null
@@ -1,11 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity ten_line_to_four_line_BCD_priority_encoder_vlg_check_tst is
-    port(
-        A               : in     vl_logic;
-        B               : in     vl_logic;
-        C               : in     vl_logic;
-        D               : in     vl_logic;
-        sampler_rx      : in     vl_logic
-    );
-end ten_line_to_four_line_BCD_priority_encoder_vlg_check_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_check_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_check_tst/verilog.prw
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diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_sample_tst/_primary.dat b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_sample_tst/_primary.dat
deleted file mode 100644
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diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_sample_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_sample_tst/_primary.vhd
deleted file mode 100644
index f65fae82..00000000
--- a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_sample_tst/_primary.vhd
+++ /dev/null
@@ -1,15 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity ten_line_to_four_line_BCD_priority_encoder_vlg_sample_tst is
-    port(
-        I2              : in     vl_logic;
-        I3              : in     vl_logic;
-        I4              : in     vl_logic;
-        I5              : in     vl_logic;
-        I6              : in     vl_logic;
-        I7              : in     vl_logic;
-        I8              : in     vl_logic;
-        I9              : in     vl_logic;
-        sampler_tx      : out    vl_logic
-    );
-end ten_line_to_four_line_BCD_priority_encoder_vlg_sample_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_sample_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_sample_tst/verilog.prw
deleted file mode 100644
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literal 0
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diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_sample_tst/verilog.psm b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_sample_tst/verilog.psm
deleted file mode 100644
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literal 0
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diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_vec_tst/_primary.dbs b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_vec_tst/_primary.dbs
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diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_vec_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_vec_tst/_primary.vhd
deleted file mode 100644
index 002f157d..00000000
--- a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_vec_tst/_primary.vhd
+++ /dev/null
@@ -1,4 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity ten_line_to_four_line_BCD_priority_encoder_vlg_vec_tst is
-end ten_line_to_four_line_BCD_priority_encoder_vlg_vec_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_vec_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_vec_tst/verilog.prw
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literal 0
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diff --git a/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_vec_tst/verilog.psm b/CH6/CH6-1/simulation/qsim/work/ten_line_to_four_line_@b@c@d_priority_encoder_vlg_vec_tst/verilog.psm
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diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder/_primary.vhd
deleted file mode 100644
index 2a3a0045..00000000
--- a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder/_primary.vhd
+++ /dev/null
@@ -1,17 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity three_line_to_eight_decimal_decoder is
-    port(
-        Y0              : out    vl_logic;
-        A               : in     vl_logic;
-        B               : in     vl_logic;
-        C               : in     vl_logic;
-        Y1              : out    vl_logic;
-        Y2              : out    vl_logic;
-        Y3              : out    vl_logic;
-        Y4              : out    vl_logic;
-        Y5              : out    vl_logic;
-        Y6              : out    vl_logic;
-        Y7              : out    vl_logic
-    );
-end three_line_to_eight_decimal_decoder;
diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder/verilog.prw b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder/verilog.prw
deleted file mode 100644
index de56aa20e2cb9bf156ff54a14831385e58c6f9da..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder/verilog.psm b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder/verilog.psm
deleted file mode 100644
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diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_check_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_check_tst/_primary.vhd
deleted file mode 100644
index 991358a0..00000000
--- a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_check_tst/_primary.vhd
+++ /dev/null
@@ -1,15 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity three_line_to_eight_decimal_decoder_vlg_check_tst is
-    port(
-        Y0              : in     vl_logic;
-        Y1              : in     vl_logic;
-        Y2              : in     vl_logic;
-        Y3              : in     vl_logic;
-        Y4              : in     vl_logic;
-        Y5              : in     vl_logic;
-        Y6              : in     vl_logic;
-        Y7              : in     vl_logic;
-        sampler_rx      : in     vl_logic
-    );
-end three_line_to_eight_decimal_decoder_vlg_check_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_check_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_check_tst/verilog.prw
deleted file mode 100644
index a95571bb4cbeaf902608285f30972005a171788a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_check_tst/verilog.psm b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_check_tst/verilog.psm
deleted file mode 100644
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diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_sample_tst/_primary.dat b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_sample_tst/_primary.dat
deleted file mode 100644
index 94c504eb935de7c10c0ecdc27bf1215defba50fb..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_sample_tst/_primary.dbs b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_sample_tst/_primary.dbs
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diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_sample_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_sample_tst/_primary.vhd
deleted file mode 100644
index 015d49dc..00000000
--- a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_sample_tst/_primary.vhd
+++ /dev/null
@@ -1,10 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity three_line_to_eight_decimal_decoder_vlg_sample_tst is
-    port(
-        A               : in     vl_logic;
-        B               : in     vl_logic;
-        C               : in     vl_logic;
-        sampler_tx      : out    vl_logic
-    );
-end three_line_to_eight_decimal_decoder_vlg_sample_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_sample_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_sample_tst/verilog.prw
deleted file mode 100644
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diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_sample_tst/verilog.psm b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_sample_tst/verilog.psm
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diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_vec_tst/_primary.dat b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_vec_tst/_primary.dat
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diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_vec_tst/_primary.vhd b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_vec_tst/_primary.vhd
deleted file mode 100644
index 3c50445f..00000000
--- a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_vec_tst/_primary.vhd
+++ /dev/null
@@ -1,4 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity three_line_to_eight_decimal_decoder_vlg_vec_tst is
-end three_line_to_eight_decimal_decoder_vlg_vec_tst;
diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_vec_tst/verilog.prw b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_vec_tst/verilog.prw
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diff --git a/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_vec_tst/verilog.psm b/CH6/CH6-1/simulation/qsim/work/three_line_to_eight_decimal_decoder_vlg_vec_tst/verilog.psm
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diff --git a/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf b/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf
deleted file mode 100644
index 85d4f753..00000000
--- a/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.bdf
+++ /dev/null
@@ -1,612 +0,0 @@
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diff --git a/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.ipinfo b/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.ipinfo
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diff --git a/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.qpf b/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.qpf
deleted file mode 100644
index 71a0e33a..00000000
--- a/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 23:25:57  October 16, 2019
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "23:25:57  October 16, 2019"
-
-# Revisions
-
-PROJECT_REVISION = "ten_line_to_four_line_BCD_priority_encoder"
diff --git a/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.qsf b/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.qsf
deleted file mode 100644
index 8d1cbf74..00000000
--- a/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.qsf
+++ /dev/null
@@ -1,72 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 23:25:57  October 16, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		ten_line_to_four_line_BCD_priority_encoder_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE EP3C16F484C6
-set_global_assignment -name TOP_LEVEL_ENTITY ten_line_to_four_line_BCD_priority_encoder
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:25:57  OCTOBER 16, 2019"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
-set_global_assignment -name BDF_FILE ten_line_to_four_line_BCD_priority_encoder.bdf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VECTOR_WAVEFORM_FILE ten_line_to_four_line_BCD_priority_encoder.vwf
-set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/" -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-set_location_assignment PIN_C1 -to A
-set_location_assignment PIN_C2 -to B
-set_location_assignment PIN_B2 -to C
-set_location_assignment PIN_B1 -to D
-set_location_assignment PIN_D2 -to I2
-set_location_assignment PIN_E4 -to I3
-set_location_assignment PIN_E3 -to I4
-set_location_assignment PIN_H7 -to I5
-set_location_assignment PIN_J7 -to I6
-set_location_assignment PIN_G5 -to I7
-set_location_assignment PIN_G4 -to I8
-set_location_assignment PIN_H6 -to I9
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.vwf b/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.vwf
deleted file mode 100644
index dc24869a..00000000
--- a/CH6/CH6-1/ten_line_to_four_line_BCD_priority_encoder.vwf
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
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-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-
-HEADER
-{
-	VERSION = 1;
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-{
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-{
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-SIGNAL("C")
-{
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-{
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-{
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-{
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-{
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-{
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-}
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-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
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-{
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-{
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-SIGNAL("I9")
-{
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-
-TRANSITION_LIST("A")
-{
-	NODE
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-{
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-{
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-{
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-{
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-{
-	NODE
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-{
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-{
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-{
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-		LEVEL 0 FOR 2000.0;
-		LEVEL 1 FOR 1000.0;
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-{
-	NODE
-	{
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-{
-	CHANNEL = "A";
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-{
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-	RADIX = Unsigned;
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-}
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-DISPLAY_LINE
-{
-	CHANNEL = "I2";
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-	RADIX = Unsigned;
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-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I3";
-	EXPAND_STATUS = COLLAPSED;
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-
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-{
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-{
-	CHANNEL = "I5";
-	EXPAND_STATUS = COLLAPSED;
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-	TREE_INDEX = 7;
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-}
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-DISPLAY_LINE
-{
-	CHANNEL = "I6";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
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-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I7";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 9;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I8";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 10;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "I9";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
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-}
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-TIME_BAR
-{
-	TIME = 0;
-	MASTER = TRUE;
-}
-;
diff --git a/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf b/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf
deleted file mode 100644
index 32d21e57..00000000
--- a/CH6/CH6-1/three_line_to_eight_decimal_decoder.bdf
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-(header "graphic" (version "1.4"))
-(pin
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-	(pt 168 8)
-	(drawing
-		(line (pt 84 12)(pt 109 12))
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diff --git a/CH6/CH6-1/three_line_to_eight_decimal_decoder.qpf b/CH6/CH6-1/three_line_to_eight_decimal_decoder.qpf
deleted file mode 100644
index fb93f26d..00000000
--- a/CH6/CH6-1/three_line_to_eight_decimal_decoder.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 21:43:41  October 24, 2019
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "21:43:41  October 24, 2019"
-
-# Revisions
-
-PROJECT_REVISION = "three_line_to_eight_decimal_decoder"
diff --git a/CH6/CH6-1/three_line_to_eight_decimal_decoder.qsf b/CH6/CH6-1/three_line_to_eight_decimal_decoder.qsf
deleted file mode 100644
index 15441f27..00000000
--- a/CH6/CH6-1/three_line_to_eight_decimal_decoder.qsf
+++ /dev/null
@@ -1,71 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 21:43:41  October 24, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		three_line_to_eight_decimal_decoder_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE EP3C16F484C6
-set_global_assignment -name TOP_LEVEL_ENTITY three_line_to_eight_decimal_decoder
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:43:41  OCTOBER 24, 2019"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
-set_global_assignment -name BDF_FILE three_line_to_eight_decimal_decoder.bdf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VECTOR_WAVEFORM_FILE three_line_to_eight_decimal_decoder.vwf
-set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "/home/timmy/Git/Learn-VHDL/CH6/CH6-1/simulation/qsim/" -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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-set_location_assignment PIN_E1 -to Y4
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diff --git a/CH6/CH6-1/three_line_to_eight_decimal_decoder.vwf b/CH6/CH6-1/three_line_to_eight_decimal_decoder.vwf
deleted file mode 100644
index 372b285f..00000000
--- a/CH6/CH6-1/three_line_to_eight_decimal_decoder.vwf
+++ /dev/null
@@ -1,371 +0,0 @@
-/*
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-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
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-	GRID_PERIOD = 1000.0;
-	GRID_DUTY_CYCLE = 50;
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-
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-{
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-{
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-{
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-{
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-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-TRANSITION_LIST("A")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 4;
-			LEVEL 0 FOR 1000.0;
-			LEVEL 1 FOR 1000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("B")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 2;
-			LEVEL 0 FOR 2000.0;
-			LEVEL 1 FOR 2000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("C")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 1;
-			LEVEL 0 FOR 4000.0;
-			LEVEL 1 FOR 4000.0;
-		}
-	}
-}
-
-TRANSITION_LIST("Y0")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 999.0;
-		LEVEL 0 FOR 7001.0;
-	}
-}
-
-TRANSITION_LIST("Y1")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 999.0;
-		LEVEL 0 FOR 7001.0;
-	}
-}
-
-TRANSITION_LIST("Y2")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 999.0;
-		LEVEL 0 FOR 7001.0;
-	}
-}
-
-TRANSITION_LIST("Y3")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 999.0;
-		LEVEL 0 FOR 7001.0;
-	}
-}
-
-TRANSITION_LIST("Y4")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 999.0;
-		LEVEL 0 FOR 7001.0;
-	}
-}
-
-TRANSITION_LIST("Y5")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 999.0;
-		LEVEL 0 FOR 7001.0;
-	}
-}
-
-TRANSITION_LIST("Y6")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 999.0;
-		LEVEL 0 FOR 7001.0;
-	}
-}
-
-TRANSITION_LIST("Y7")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 999.0;
-		LEVEL 0 FOR 7001.0;
-	}
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "A";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 0;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "B";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 1;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "C";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 2;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y0";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 3;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y1";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 4;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y2";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 5;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y3";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 6;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y4";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 7;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y5";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 8;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y6";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 9;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "Y7";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Unsigned;
-	TREE_INDEX = 10;
-	TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
-	TIME = 0;
-	MASTER = TRUE;
-}
-;