{"payload":{"header_redesign_enabled":false,"results":[{"id":"444733289","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"MundaneImmortal/ECE385_Final_BOXHEAD3","hl_trunc_description":"This is our ECE385 Final Project (Fall 2022) based on FPGA (DE2-115 development board)","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":444733289,"name":"ECE385_Final_BOXHEAD3","owner_id":68594013,"owner_login":"MundaneImmortal","updated_at":"2022-01-16T16:38:20.889Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":72,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AMundaneImmortal%252FECE385_Final_BOXHEAD3%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/MundaneImmortal/ECE385_Final_BOXHEAD3/star":{"post":"HpUK2GFsEKqV4rqC4o9m4tZ5PqCBDZZQJlRNxiF9unpJNKwd2x_NtoOOh4zqKXDROrCBGxAx_3nFR1FT07rLfA"},"/MundaneImmortal/ECE385_Final_BOXHEAD3/unstar":{"post":"ejAxg2gS0uR3DuOi-kwHt-BvYVHQJf7kgSiQy_7CnpV2JK_bbfYQeYhBSTu4bWgy14UkjVFDRpQABroxSD-ipQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"Ejvw5t2parbRJTV6sU8u3e6YHM5q_YqHOIRDQ2h6wy8-oYd5UGbaivKpWVd2XRAF6xlDg1D3E9Zu06o5I5uzeg"}}},"title":"Repository search results"}