os: remove including files from yuzu_video_core inside of nxemu-os

Author: N3xoX1

src/nxemu-os/core/hle/service/nvdrv/devices/nvhost_as_gpu.cpp

@@ -15,10 +15,6 @@
 #include "core/hle/service/nvdrv/devices/nvhost_as_gpu.h"
 #include "core/hle/service/nvdrv/devices/nvhost_gpu.h"
 #include "core/hle/service/nvdrv/nvdrv.h"
-#include "yuzu_video_core/control/channel_state.h"
-#include "yuzu_video_core/gpu.h"
-#include "yuzu_video_core/memory_manager.h"
-#include "yuzu_video_core/rasterizer_interface.h"
 
 namespace Service::Nvidia::Devices {
 
@@ -172,8 +168,7 @@ NvResult nvhost_as_gpu::UnmapBuffer(IoctlUnmapBuffer& params) {
 NvResult nvhost_as_gpu::BindChannel(IoctlBindChannel& params) {
     LOG_DEBUG(Service_NVDRV, "called, fd={:X}", params.fd);
 
-    auto gpu_channel_device = module.GetDevice<nvhost_gpu>(params.fd);
-    gpu_channel_device->channel_state->memory_manager = gmmu;
+    UNIMPLEMENTED();
     return NvResult::Success;
 }
 

src/nxemu-os/core/hle/service/nvdrv/devices/nvhost_gpu.cpp

@@ -13,15 +13,70 @@
 #include "core/hle/service/nvdrv/devices/nvhost_gpu.h"
 #include "core/hle/service/nvdrv/nvdrv.h"
 #include "core/memory.h"
-#include "yuzu_video_core/control/channel_state.h"
-#include "yuzu_video_core/engines/puller.h"
-#include "yuzu_video_core/gpu.h"
-#include "yuzu_video_core/host1x/host1x.h"
+
+namespace Tegra {
+
+// Note that, traditionally, methods are treated as 4-byte addressable locations, and hence
+// their numbers are written down multiplied by 4 in Docs. Here we are not multiply by 4.
+// So the values you see in docs might be multiplied by 4.
+// Register documentation:
+// https://github.com/NVIDIA/open-gpu-doc/blob/ab27fc22db5de0d02a4cabe08e555663b62db4d4/classes/host/cla26f.h
+//
+// Register Description (approx):
+// https://github.com/NVIDIA/open-gpu-doc/blob/ab27fc22db5de0d02a4cabe08e555663b62db4d4/manuals/volta/gv100/dev_pbdma.ref.txt
+enum class BufferMethods : u32 {
+    BindObject = 0x0,
+    Illegal = 0x1,
+    Nop = 0x2,
+    SemaphoreAddressHigh = 0x4,
+    SemaphoreAddressLow = 0x5,
+    SemaphoreSequencePayload = 0x6,
+    SemaphoreOperation = 0x7,
+    NonStallInterrupt = 0x8,
+    WrcacheFlush = 0x9,
+    MemOpA = 0xA,
+    MemOpB = 0xB,
+    MemOpC = 0xC,
+    MemOpD = 0xD,
+    RefCnt = 0x14,
+    SemaphoreAcquire = 0x1A,
+    SemaphoreRelease = 0x1B,
+    SyncpointPayload = 0x1C,
+    SyncpointOperation = 0x1D,
+    WaitForIdle = 0x1E,
+    CRCCheck = 0x1F,
+    Yield = 0x20,
+    NonPullerMethods = 0x40,
+};
+
+inline CommandHeader BuildCommandHeader(BufferMethods method, u32 arg_count, SubmissionMode mode) {
+    CommandHeader result{};
+    result.method.Assign(static_cast<u32>(method));
+    result.arg_count.Assign(arg_count);
+    result.mode.Assign(mode);
+    return result;
+}
+} // namespace Tegra
+
+namespace Tegra::Engines {
+
+enum class FenceOperation : u32 {
+    Acquire = 0,
+    Increment = 1,
+};
+
+union FenceAction {
+    u32 raw;
+    BitField<0, 1, FenceOperation> op;
+    BitField<8, 24, u32> syncpoint_id;
+};
+
+} // namespace Tegra::Engines
 
 namespace Service::Nvidia::Devices {
 namespace {
-Tegra::CommandHeader BuildFenceAction(Tegra::Engines::Puller::FenceOperation op, u32 syncpoint_id) {
-    Tegra::Engines::Puller::FenceAction result{};
+Tegra::CommandHeader BuildFenceAction(Tegra::Engines::FenceOperation op, u32 syncpoint_id) {
+    Tegra::Engines::FenceAction result{};
     result.op.Assign(op);
     result.syncpoint_id.Assign(syncpoint_id);
     return {result.raw};
@@ -189,7 +244,7 @@ static boost::container::small_vector<Tegra::CommandHeader, 512> BuildWaitComman
         {fence.value},
         Tegra::BuildCommandHeader(Tegra::BufferMethods::SyncpointOperation, 1,
                                   Tegra::SubmissionMode::Increasing),
-        BuildFenceAction(Tegra::Engines::Puller::FenceOperation::Acquire, fence.id),
+        BuildFenceAction(Tegra::Engines::FenceOperation::Acquire, fence.id),
     };
 }
 
@@ -204,7 +259,7 @@ static boost::container::small_vector<Tegra::CommandHeader, 512> BuildIncrementC
         result.push_back(Tegra::BuildCommandHeader(Tegra::BufferMethods::SyncpointOperation, 1,
                                                    Tegra::SubmissionMode::Increasing));
         result.push_back(
-            BuildFenceAction(Tegra::Engines::Puller::FenceOperation::Increment, fence.id));
+            BuildFenceAction(Tegra::Engines::FenceOperation::Increment, fence.id));
     }
 
     return result;

src/nxemu-os/core/hle/service/nvdrv/devices/nvhost_gpu.h

@@ -3,6 +3,7 @@
 
 #pragma once
 
+#include <boost/container/small_vector.hpp>
 #include <memory>
 #include <vector>
 #include "yuzu_common/bit_field.h"
@@ -12,12 +13,54 @@
 #include "yuzu_common/nvdata.h"
 #include "yuzu_common/swap.h"
 #include "core/hle/service/nvdrv/devices/nvdevice.h"
-#include "yuzu_video_core/dma_pusher.h"
 
 namespace Tegra {
 namespace Control {
 struct ChannelState;
 }
+
+enum class SubmissionMode : u32 {
+    IncreasingOld = 0,
+    Increasing = 1,
+    NonIncreasingOld = 2,
+    NonIncreasing = 3,
+    Inline = 4,
+    IncreaseOnce = 5
+};
+
+union CommandHeader {
+    u32 argument;
+    BitField<0, 13, u32> method;
+    BitField<0, 24, u32> method_count_;
+    BitField<13, 3, u32> subchannel;
+    BitField<16, 13, u32> arg_count;
+    BitField<16, 13, u32> method_count;
+    BitField<29, 3, SubmissionMode> mode;
+};
+static_assert(std::is_standard_layout_v<CommandHeader>, "CommandHeader is not standard layout");
+static_assert(sizeof(CommandHeader) == sizeof(u32), "CommandHeader has incorrect size!");
+
+struct CommandListHeader {
+    union {
+        u64 raw;
+        BitField<0, 40, GPUVAddr> addr;
+        BitField<41, 1, u64> is_non_main;
+        BitField<42, 21, u64> size;
+    };
+};
+static_assert(sizeof(CommandListHeader) == sizeof(u64), "CommandListHeader is incorrect size");
+
+struct CommandList final {
+    CommandList() = default;
+    explicit CommandList(std::size_t size) : command_lists(size) {}
+    explicit CommandList(
+        boost::container::small_vector<CommandHeader, 512>&& prefetch_command_list_)
+        : prefetch_command_list{ std::move(prefetch_command_list_) } {
+    }
+
+    boost::container::small_vector<CommandListHeader, 512> command_lists;
+    boost::container::small_vector<CommandHeader, 512> prefetch_command_list;
+};
 } // namespace Tegra
 
 namespace Service::Nvidia {

src/nxemu-os/core/hle/service/nvdrv/devices/nvhost_nvdec.cpp

@@ -7,7 +7,6 @@
 #include "core/hle/service/nvdrv/core/container.h"
 #include "core/hle/service/nvdrv/devices/ioctl_serialization.h"
 #include "core/hle/service/nvdrv/devices/nvhost_nvdec.h"
-#include "yuzu_video_core/renderer_base.h"
 
 namespace Service::Nvidia::Devices {
 

src/nxemu-os/core/hle/service/nvdrv/devices/nvhost_nvdec_common.cpp

@@ -14,9 +14,6 @@
 #include "core/hle/service/nvdrv/core/syncpoint_manager.h"
 #include "core/hle/service/nvdrv/devices/nvhost_nvdec_common.h"
 #include "core/memory.h"
-#include "yuzu_video_core/host1x/host1x.h"
-#include "yuzu_video_core/memory_manager.h"
-#include "yuzu_video_core/renderer_base.h"
 
 namespace Service::Nvidia::Devices {
 

src/nxemu-os/core/hle/service/nvdrv/devices/nvhost_vic.cpp

@@ -7,7 +7,6 @@
 #include "core/hle/service/nvdrv/core/container.h"
 #include "core/hle/service/nvdrv/devices/ioctl_serialization.h"
 #include "core/hle/service/nvdrv/devices/nvhost_vic.h"
-#include "yuzu_video_core/renderer_base.h"
 
 namespace Service::Nvidia::Devices {