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Commits on Jan 16, 2013
Commits on Jan 7, 2013
  1. CACHE: Transcribing expected coverage for BIOS code

    Manually decoded and executed BIOS dump to identify landing sites
    and instructions. This data should be usable as a starting point
    for generating LLVM blocks, as it is functionally equivalent to
    execution in a regular cartridge.
    committed Jan 7, 2013
  2. CACHE: Structure to store traversal information

    Record information about which memory locations have been visited,
    and whether they hold instructions, immediate-mode data, or are (by
    inference) not executable or have not yet been executed.
    committed Jan 7, 2013
Commits on Jan 5, 2013
Commits on Jan 4, 2013
Commits on Jan 1, 2013
  1. Cleaner generator for LDRR instructions

    Use xargs to format 7 instructions per line.
    committed Jan 1, 2013
Commits on Feb 27, 2011
  1. Change header to References.

    jbueza committed Feb 27, 2011
  2. Add a few more ignores.

    jbueza committed Feb 27, 2011
  3. Markdown fixes.

    jbueza committed Feb 27, 2011
  4. Code blocks are not aligned.

    jbueza committed Feb 27, 2011
  5. More doc fixes. Probably should look into markdown parser or possibly…

    … sphinx or naturaldocs.
    jbueza committed Feb 27, 2011
  6. Fix up documentation, add test folder to separate them out of the src…

    … folder (makes it cleaner).
    jbueza committed Feb 27, 2011
Commits on Feb 9, 2011
Commits on Feb 8, 2011
Commits on Feb 5, 2011
  1. MMU: Removing redundant memory segments

    As the full memory has been consolidated into a single array, the seperate memory arrays can be removed
    committed Feb 5, 2011
  2. TEST: Partial system integration test

    Added missing entries for LDrn operations.
    
    Running BIOS is partially successful, with execution continuing toward
    the infinite loops. Failure is caused by a lack of proper signature in
    the cartridge header.
    committed Feb 5, 2011
Commits on Feb 4, 2011
  1. CPU: Register XOR opreations

    committed Feb 4, 2011
  2. CPU: Register Subtraction ops

    committed Feb 4, 2011
  3. CPU: Rotate Left operations

    committed Feb 4, 2011
  4. CPU: Interrupt enable/disable

    committed Feb 4, 2011
Commits on Jan 30, 2011
  1. CPU: Increment operations

    committed Jan 30, 2011
  2. CPU: Decrement operations

    committed Jan 30, 2011