From de6b8f7a1125239352be682a4565b1cc15451f3b Mon Sep 17 00:00:00 2001
From: 1fHu <simonhu125@gmail.com>
Date: Sun, 21 Sep 2025 15:45:15 -0400
Subject: [PATCH] update weekly notebook

---
 src/design_notebooks/2025fall/yh4970.md | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/design_notebooks/2025fall/yh4970.md b/src/design_notebooks/2025fall/yh4970.md
index f8cc70b1..bf4d19a1 100644
--- a/src/design_notebooks/2025fall/yh4970.md
+++ b/src/design_notebooks/2025fall/yh4970.md
@@ -1,5 +1,14 @@
 # Simon Hu - Design Notebook (Fall 2025)
 
+## Week 2 (Sep 15- Sep 21)
+- Read Risc 16 datasheet
+- Understood Program counter
+- Wrote code for p.c. of Risc 16
+- Compared the code with group partners
+- Uploaded the code to github repo 
+    (https://github.com/1fHu/ProcessorDesign/blob/main/pc16.v)
+- Finished HDLBits Vector
+
 ## Week 1 (Sep 9–Sep 14)
 - Doing onboarding and finshed repo setup
 - finished HDLBits Getting Started and Verilog language basics