From a24ad88114da3fc3c0eaf7a225f3fa6dee56953a Mon Sep 17 00:00:00 2001 From: Ghqlq Date: Sat, 13 Sep 2025 20:21:18 -0400 Subject: [PATCH 1/6] updated notebook From 6a79fac6899f33611fc8a10fdf6cb533c11234f5 Mon Sep 17 00:00:00 2001 From: Ghqlq Date: Sun, 28 Sep 2025 18:13:36 -0400 Subject: [PATCH 2/6] week3 --- src/design_notebooks/2025fall/gb2789.md | 31 ++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/src/design_notebooks/2025fall/gb2789.md b/src/design_notebooks/2025fall/gb2789.md index 2d5168c3..934dee9f 100644 --- a/src/design_notebooks/2025fall/gb2789.md +++ b/src/design_notebooks/2025fall/gb2789.md @@ -1,7 +1,5 @@ Ghala's Design Notebook: Processor Design VIP - -### Week1: 09/08/25 - 09/14/25 ---- ## Week1: 09/08/25 - 09/14/25 - Attended the first meeting of the semester. - Created this notebook. @@ -14,13 +12,15 @@ Ghala's Design Notebook: Processor Design VIP - Met with partner [Lucy Zheng](https://github.com/Tyjihn) to work on the RiSC-16 module Program Counter. - Solved the Vectors practice on HDLBits. -[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) +[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: program_counter.v My partner and I had different approach to write the PC module but very similar logic. However I am not sure how correct it is since there is no way to test it. We faced some difficulty with figuring out the logic of the module because it is unclear what are the given inputs and which operations should the PC do or not do. ## Week3: 09/22/25 - 09/28/25 - Matched my program counter code to the testbench provided to us. - Created the ALU for the RiSC-16 processor. + +[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: alu.v **Changes done to pc:** 1. I had the opCode as an input, now I'm using MUX_output which decides which operation for the pc to do in upstream logic. That made it simpler because I removed opcode decoding inside PC. @@ -29,3 +29,28 @@ My partner and I had different approach to write the PC module but very similar 4. reset is now active-low to match the testbench. **Discuss ALU:** My implementation of the ALU is similar to the implementation uploaded by Noah. However, I used mux using the conditional operator instead of an always block. I'm not familiar with how to use the always block for mux and the differences. + +## Week4: 09/29/25 - 10/05/25 +- Created the register file. + +[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: register_file.v + +**Discussion:** I thought it was easier than creating the ALU, the logic was straightforward. I learned how to do a for loop at compile time, which I did not know was possible. At first I didn't initiate the registers to zero so I got some errors when I ran the testbench, then I corrected the mistake. + +## Week5: 10/06/25 - 10/12/25 +- Met with Noah and my partner Lucy to discuss our progress. + +**Discussion:** I had some issues previously with the PRs and my previous PRs weren't accepted so I wasn't able to push my recent updates to the design notebook. + +## Week6: 10/13/25 - 10/19/25 +- Created a testbench to test + +[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: data_memory_tb.v + +**Discussion:** I took so long writing this tb and used past TBs Noah provided us with as well as the internet to help me write it. The tb I designed consists of 4 tests. They test for + 1) Initial value. + 2) write and read + 3) Read when write enable is low + 4) overwrite + +The hardest part is figuring out how to set up the testbench and write the first test, but then it got easier. \ No newline at end of file From 3541992342a58dd0dfedbbcc4a9405d9f53a6cca Mon Sep 17 00:00:00 2001 From: Ghqlq Date: Wed, 10 Sep 2025 17:42:16 -0400 Subject: [PATCH 3/6] update design notebook --- src/design_notebooks/2025fall/gb2789.md | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/src/design_notebooks/2025fall/gb2789.md b/src/design_notebooks/2025fall/gb2789.md index 934dee9f..de506e2e 100644 --- a/src/design_notebooks/2025fall/gb2789.md +++ b/src/design_notebooks/2025fall/gb2789.md @@ -1,10 +1,18 @@ +<<<<<<< HEAD Ghala's Design Notebook: Processor Design VIP - ## Week1: 09/08/25 - 09/14/25 +======= +Ghala Buarish Design Notebook: Processor Design VIP +- +--- +### 08/09/25 - 14/09/25 +>>>>>>> a6a8a6c (update design notebook) - Attended the first meeting of the semester. - Created this notebook. - Read "Design Notebooks and Git" and "Development Environment". - Completed necessary downloads (Homebrew,CMake, Verilator). Didn't download VirtualBox because it says in the guide I don't need it if I have a macOS. +<<<<<<< HEAD - Downloaded VSCode and suggested add-ons. - Made a profile in HDLBits and completed “Getting Started” and “Verilog Language Basics”. @@ -53,4 +61,13 @@ My partner and I had different approach to write the PC module but very similar 3) Read when write enable is low 4) overwrite -The hardest part is figuring out how to set up the testbench and write the first test, but then it got easier. \ No newline at end of file +The hardest part is figuring out how to set up the testbench and write the first test, but then it got easier. +======= +- [ ] VSCode download +- [ ] Useful Extensions for VSCode +- [ ] “Getting Started” and “Verilog Language Basics” on HDLBits problems sets. https://hdlbits.01xz.net/wiki/Problem_sets + + + + +>>>>>>> a6a8a6c (update design notebook) From 351a3bb7a54cb6d36f7e453171b3624fd4eaee8c Mon Sep 17 00:00:00 2001 From: Ghqlq Date: Sat, 13 Sep 2025 20:21:57 -0400 Subject: [PATCH 4/6] updated here From e427872bacf6beb4073ece16470be5dd9d1103cb Mon Sep 17 00:00:00 2001 From: Ghqlq Date: Sun, 28 Sep 2025 18:25:30 -0400 Subject: [PATCH 5/6] deleted --- src/design_notebooks/2025fall/gb2789.md | 46 +------------------------ 1 file changed, 1 insertion(+), 45 deletions(-) diff --git a/src/design_notebooks/2025fall/gb2789.md b/src/design_notebooks/2025fall/gb2789.md index de506e2e..f27f44b5 100644 --- a/src/design_notebooks/2025fall/gb2789.md +++ b/src/design_notebooks/2025fall/gb2789.md @@ -1,18 +1,10 @@ -<<<<<<< HEAD Ghala's Design Notebook: Processor Design VIP - ## Week1: 09/08/25 - 09/14/25 -======= -Ghala Buarish Design Notebook: Processor Design VIP -- ---- -### 08/09/25 - 14/09/25 ->>>>>>> a6a8a6c (update design notebook) - Attended the first meeting of the semester. - Created this notebook. - Read "Design Notebooks and Git" and "Development Environment". - Completed necessary downloads (Homebrew,CMake, Verilator). Didn't download VirtualBox because it says in the guide I don't need it if I have a macOS. -<<<<<<< HEAD - Downloaded VSCode and suggested add-ons. - Made a profile in HDLBits and completed “Getting Started” and “Verilog Language Basics”. @@ -20,15 +12,13 @@ Ghala Buarish Design Notebook: Processor Design VIP - Met with partner [Lucy Zheng](https://github.com/Tyjihn) to work on the RiSC-16 module Program Counter. - Solved the Vectors practice on HDLBits. -[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: program_counter.v +[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) My partner and I had different approach to write the PC module but very similar logic. However I am not sure how correct it is since there is no way to test it. We faced some difficulty with figuring out the logic of the module because it is unclear what are the given inputs and which operations should the PC do or not do. ## Week3: 09/22/25 - 09/28/25 - Matched my program counter code to the testbench provided to us. - Created the ALU for the RiSC-16 processor. - -[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: alu.v **Changes done to pc:** 1. I had the opCode as an input, now I'm using MUX_output which decides which operation for the pc to do in upstream logic. That made it simpler because I removed opcode decoding inside PC. @@ -37,37 +27,3 @@ My partner and I had different approach to write the PC module but very similar 4. reset is now active-low to match the testbench. **Discuss ALU:** My implementation of the ALU is similar to the implementation uploaded by Noah. However, I used mux using the conditional operator instead of an always block. I'm not familiar with how to use the always block for mux and the differences. - -## Week4: 09/29/25 - 10/05/25 -- Created the register file. - -[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: register_file.v - -**Discussion:** I thought it was easier than creating the ALU, the logic was straightforward. I learned how to do a for loop at compile time, which I did not know was possible. At first I didn't initiate the registers to zero so I got some errors when I ran the testbench, then I corrected the mistake. - -## Week5: 10/06/25 - 10/12/25 -- Met with Noah and my partner Lucy to discuss our progress. - -**Discussion:** I had some issues previously with the PRs and my previous PRs weren't accepted so I wasn't able to push my recent updates to the design notebook. - -## Week6: 10/13/25 - 10/19/25 -- Created a testbench to test - -[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: data_memory_tb.v - -**Discussion:** I took so long writing this tb and used past TBs Noah provided us with as well as the internet to help me write it. The tb I designed consists of 4 tests. They test for - 1) Initial value. - 2) write and read - 3) Read when write enable is low - 4) overwrite - -The hardest part is figuring out how to set up the testbench and write the first test, but then it got easier. -======= -- [ ] VSCode download -- [ ] Useful Extensions for VSCode -- [ ] “Getting Started” and “Verilog Language Basics” on HDLBits problems sets. https://hdlbits.01xz.net/wiki/Problem_sets - - - - ->>>>>>> a6a8a6c (update design notebook) From 67598215b58caa1fb294765f76c3e607142e13b9 Mon Sep 17 00:00:00 2001 From: Ghqlq Date: Sun, 19 Oct 2025 15:01:40 -0400 Subject: [PATCH 6/6] doc(dn)-Ghala-Buarish-09/19/25 --- src/design_notebooks/2025fall/gb2789.md | 29 ++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/src/design_notebooks/2025fall/gb2789.md b/src/design_notebooks/2025fall/gb2789.md index f27f44b5..9acb1cea 100644 --- a/src/design_notebooks/2025fall/gb2789.md +++ b/src/design_notebooks/2025fall/gb2789.md @@ -12,13 +12,15 @@ Ghala's Design Notebook: Processor Design VIP - Met with partner [Lucy Zheng](https://github.com/Tyjihn) to work on the RiSC-16 module Program Counter. - Solved the Vectors practice on HDLBits. -[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) +[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: program_counter.v My partner and I had different approach to write the PC module but very similar logic. However I am not sure how correct it is since there is no way to test it. We faced some difficulty with figuring out the logic of the module because it is unclear what are the given inputs and which operations should the PC do or not do. ## Week3: 09/22/25 - 09/28/25 - Matched my program counter code to the testbench provided to us. - Created the ALU for the RiSC-16 processor. + +[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: alu.v **Changes done to pc:** 1. I had the opCode as an input, now I'm using MUX_output which decides which operation for the pc to do in upstream logic. That made it simpler because I removed opcode decoding inside PC. @@ -27,3 +29,28 @@ My partner and I had different approach to write the PC module but very similar 4. reset is now active-low to match the testbench. **Discuss ALU:** My implementation of the ALU is similar to the implementation uploaded by Noah. However, I used mux using the conditional operator instead of an always block. I'm not familiar with how to use the always block for mux and the differences. + +## Week4: 09/29/25 - 10/05/25 +- Created the register file. + +[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: register_file.v + +**Discussion:** I thought it was easier than creating the ALU, the logic was straightforward. I learned how to do a for loop at compile time, which I did not know was possible. At first I didn't initiate the registers to zero so I got some errors when I ran the testbench, then I corrected the mistake. + +## Week5: 10/06/25 - 10/12/25 +- Met with Noah and my partner Lucy to discuss our progress. + +**Discussion:** I had some issues previously with the PRs and my previous PRs weren't accepted so I wasn't able to push my recent updates to the design notebook. + +## Week6: 10/13/25 - 10/19/25 +- Created a testbench to test + +[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: data_memory_tb.v + +**Discussion:** I took so long writing this tb and used past TBs Noah provided us with as well as the internet to help me write it. The tb I designed consists of 4 tests. They test for + 1) Initial value. + 2) write and read + 3) Read when write enable is low + 4) overwrite + +The hardest part is figuring out how to set up the testbench and write the first test, but then it got easier.