From c8e7917fd3843a90fe3ccd9236c47615195ea1f3 Mon Sep 17 00:00:00 2001 From: Lucy Zheng Date: Sun, 9 Nov 2025 22:23:00 -0500 Subject: [PATCH] docs(dn): Lucy Zheng 11/09/2025 --- src/design_notebooks/2025fall/lz3007.md | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/design_notebooks/2025fall/lz3007.md b/src/design_notebooks/2025fall/lz3007.md index 58c9ab2..22fad49 100644 --- a/src/design_notebooks/2025fall/lz3007.md +++ b/src/design_notebooks/2025fall/lz3007.md @@ -107,4 +107,15 @@ The Control module selects the value of the output signals: WErf, WEdmem, MUXalu [GitHub: Control Module Code](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/control2.v) +[GitHub: Instruction Memory Code](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/instruction_mem2.v) + **Notes:** There were some modules that were not used for some instructions and I was not sure if I needed to set the value of the signals that corrolate to the unused modules. + + +## Week 8: 10/27/2025 - 11/02/2025 + +No tasks were assigned this week. + +## Week 9: 10/03/2025 - 10/09/2025 + +Did not work on onboarding labs this week. \ No newline at end of file