From 7f999a0648f1a2d99b9775609f201a43a2a355db Mon Sep 17 00:00:00 2001 From: HongtaiDu <98723841+HongtaiDu@users.noreply.github.com> Date: Thu, 6 Nov 2025 00:46:40 -0500 Subject: [PATCH] Docs(dn):Hongtai_Du_11_05_2025 --- src/design_notebooks/2025fall/hd2609.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/design_notebooks/2025fall/hd2609.md b/src/design_notebooks/2025fall/hd2609.md index d01cf974..45474a25 100644 --- a/src/design_notebooks/2025fall/hd2609.md +++ b/src/design_notebooks/2025fall/hd2609.md @@ -48,8 +48,29 @@ Summary: Now all labs are finished. For next week, I will find meeting time with ## Week of October 12th +### Project Work + * Did more Verilog practice questions on the HDLBits. I finished until "Connecting to poarts by position" problem. Summary: This week I did not meet with team because I was busy with midterms and presentations. I did not have time to meet with team. I have one more midterm next week on Wednesday. I plan to meet with team on Friday or on weekend. +## Week of October 19th + +### Project Work + +* Did more Verilog practice questions on the HDLBits. I finished until "Adder 1" problem. +* Finished reading lab 5, even if it is incomplete. + +Summary: I have one midterm and a presentation to prepare this week, so not a lot progress. Howver, this week I met with team and discussed the next step. I should work on the rest of the labs. Then I will assist other memebers in the future. + +## Week of October 26th + +### Project Work + +* Did more Verilog practice questions on the HDLBits. I finished until "Adder-substractor" problem. +* Started testing some code of Lab 5 in VScode, but met some bugs. It seems due to the version of Verilog. Some code are not supported by the current version installed in my VScode. + +Summary: This week I met with team on Wednesday, which is the weekly meeting in this semester. The team will work on Lab 1 and Lab 2 next week. I will prepare to assist on them. Also, due to the bug I met, I plan to debug it next week. + +