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Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)
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/* $NetBSD: acpi_pci_layerscape_gen4.c,v 1.1 2020/02/01 13:26:43 jmcneill Exp $ */
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/*-
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* Copyright (c) 2020 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jared McNeill <jmcneill@invisible.ca>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* NXP Layerscape PCIe Gen4 controller (not ECAM compliant)
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: acpi_pci_layerscape_gen4.c,v 1.1 2020/02/01 13:26:43 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/extent.h>
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#include <sys/kmem.h>
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#include <sys/mutex.h>
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#include <machine/cpu.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciconf.h>
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#include <dev/acpi/acpivar.h>
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#include <dev/acpi/acpi_pci.h>
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#include <dev/acpi/acpi_mcfg.h>
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#include <arm/acpi/acpi_pci_machdep.h>
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#define PAB_CTRL 0x808
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#define PAB_CTRL_PAGE_SEL __BITS(18,13)
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#define PAB_AXI_AMAP_PEX_WIN_L(x) (0xba8 + 0x10 * (x))
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#define PAB_AXI_AMAP_PEX_WIN_H(x) (0xbac + 0x10 * (x))
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#define INDIRECT_ADDR_BOUNDARY 0xc00
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#define LUT_BASE 0x80000
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#define LUT_GCR 0x28
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#define LUT_GCR_RRE __BIT(0)
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#define REG_TO_PAGE_INDEX(reg) (((reg) >> 10) & 0x3ff)
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#define REG_TO_PAGE_ADDR(reg) (((reg) & 0x3ff) | INDIRECT_ADDR_BOUNDARY)
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#define PAB_TARGET_BUS(b) ((b) << 24)
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#define PAB_TARGET_DEV(d) ((d) << 19)
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#define PAB_TARGET_FUNC(f) ((f) << 16)
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struct acpi_pci_layerscape_gen4 {
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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uint8_t rev;
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kmutex_t lock;
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};
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static void
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acpi_pci_layerscape_gen4_ccsr_setpage(struct acpi_pci_layerscape_gen4 *pcie, u_int page_index)
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{
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uint32_t val;
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val = bus_space_read_4(pcie->bst, pcie->bsh, PAB_CTRL);
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val &= ~PAB_CTRL_PAGE_SEL;
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val |= __SHIFTIN(page_index, PAB_CTRL_PAGE_SEL);
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bus_space_write_4(pcie->bst, pcie->bsh, PAB_CTRL, val);
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}
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static uint32_t
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acpi_pci_layerscape_gen4_ccsr_read4(struct acpi_pci_layerscape_gen4 *pcie, bus_size_t reg)
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{
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const bool indirect = reg >= INDIRECT_ADDR_BOUNDARY;
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const u_int page_index = indirect ? REG_TO_PAGE_INDEX(reg) : 0;
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const bus_size_t page_addr = indirect ? REG_TO_PAGE_ADDR(reg) : reg;
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acpi_pci_layerscape_gen4_ccsr_setpage(pcie, page_index);
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return bus_space_read_4(pcie->bst, pcie->bsh, page_addr);
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}
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static void
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acpi_pci_layerscape_gen4_ccsr_write4(struct acpi_pci_layerscape_gen4 *pcie,
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bus_size_t reg, pcireg_t data)
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{
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const bool indirect = reg >= INDIRECT_ADDR_BOUNDARY;
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const u_int page_index = indirect ? REG_TO_PAGE_INDEX(reg) : 0;
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const bus_size_t page_addr = indirect ? REG_TO_PAGE_ADDR(reg) : reg;
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acpi_pci_layerscape_gen4_ccsr_setpage(pcie, page_index);
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bus_space_write_4(pcie->bst, pcie->bsh, page_addr, data);
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}
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static void
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acpi_pci_layerscape_gen4_select_target(struct acpi_pci_layerscape_gen4 *pcie,
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pci_chipset_tag_t pc, pcitag_t tag)
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{
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struct acpi_pci_context *ap = pc->pc_conf_v;
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int b, d, f;
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pci_decompose_tag(pc, tag, &b, &d, &f);
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const uint32_t target = PAB_TARGET_BUS(b - ap->ap_bus) |
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PAB_TARGET_DEV(d) | PAB_TARGET_FUNC(f);
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acpi_pci_layerscape_gen4_ccsr_write4(pcie, PAB_AXI_AMAP_PEX_WIN_L(0), target);
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acpi_pci_layerscape_gen4_ccsr_write4(pcie, PAB_AXI_AMAP_PEX_WIN_H(0), 0);
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}
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static bool
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acpi_pci_layerscape_gen4_is_tag_okay(pci_chipset_tag_t pc, pcitag_t tag)
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{
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struct acpi_pci_context *ap = pc->pc_conf_v;
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int b, d, f;
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pci_decompose_tag(pc, tag, &b, &d, &f);
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if (b <= ap->ap_bus + 1 && d > 0)
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return false;
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return true;
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}
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static int
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acpi_pci_layerscape_gen4_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *data)
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{
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struct acpi_pci_context *ap = pc->pc_conf_v;
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struct acpi_pci_layerscape_gen4 *pcie = ap->ap_conf_priv;
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int b, d, f;
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int error;
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pci_decompose_tag(pc, tag, &b, &d, &f);
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if (!acpi_pci_layerscape_gen4_is_tag_okay(pc, tag)) {
160+
*data = -1;
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return EINVAL;
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}
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mutex_enter(&pcie->lock);
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if (pcie->rev == 0x10 && reg == PCI_ID_REG)
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bus_space_write_4(pcie->bst, pcie->bsh, LUT_BASE + LUT_GCR, 0);
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if (b == ap->ap_bus) {
170+
*data = acpi_pci_layerscape_gen4_ccsr_read4(pcie, reg);
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error = 0;
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} else {
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acpi_pci_layerscape_gen4_select_target(pcie, pc, tag);
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error = acpimcfg_conf_read(pc, pci_make_tag(pc, 0, 0, 0), reg, data);
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}
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if (pcie->rev == 0x10 && reg == PCI_ID_REG)
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bus_space_write_4(pcie->bst, pcie->bsh, LUT_BASE + LUT_GCR, LUT_GCR_RRE);
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mutex_exit(&pcie->lock);
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return error;
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}
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static int
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acpi_pci_layerscape_gen4_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
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{
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struct acpi_pci_context *ap = pc->pc_conf_v;
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struct acpi_pci_layerscape_gen4 *pcie = ap->ap_conf_priv;
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int b, d, f;
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int error;
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pci_decompose_tag(pc, tag, &b, &d, &f);
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if (!acpi_pci_layerscape_gen4_is_tag_okay(pc, tag))
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return EINVAL;
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mutex_enter(&pcie->lock);
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if (b == ap->ap_bus) {
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acpi_pci_layerscape_gen4_ccsr_write4(pcie, reg, data);
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error = 0;
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} else {
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acpi_pci_layerscape_gen4_select_target(pcie, pc, tag);
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error = acpimcfg_conf_write(pc, pci_make_tag(pc, 0, 0, 0), reg, data);
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}
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mutex_exit(&pcie->lock);
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return error;
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}
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static ACPI_STATUS
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acpi_pci_layerscape_gen4_map(ACPI_HANDLE handle, UINT32 level, void *ctx, void **retval)
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{
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struct acpi_pci_context *ap = ctx;
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struct acpi_resources res;
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struct acpi_mem *mem;
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struct acpi_pci_layerscape_gen4 *pcie;
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bus_space_handle_t bsh;
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ACPI_HANDLE parent;
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ACPI_INTEGER seg;
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ACPI_STATUS rv;
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int error;
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rv = AcpiGetParent(handle, &parent);
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if (ACPI_FAILURE(rv))
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return rv;
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rv = acpi_eval_integer(parent, "_SEG", &seg);
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if (ACPI_FAILURE(rv))
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seg = 0;
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if (ap->ap_seg != seg)
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return AE_OK;
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rv = acpi_resource_parse(ap->ap_dev, handle, "_CRS", &res, &acpi_resource_parse_ops_quiet);
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if (ACPI_FAILURE(rv))
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return rv;
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mem = acpi_res_mem(&res, 0);
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if (mem == NULL) {
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acpi_resource_cleanup(&res);
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return AE_NOT_FOUND;
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}
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error = bus_space_map(ap->ap_bst, mem->ar_base, mem->ar_length,
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_ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &bsh);
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if (error != 0)
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return AE_NO_MEMORY;
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pcie = kmem_alloc(sizeof(*pcie), KM_SLEEP);
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pcie->bst = ap->ap_bst;
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pcie->bsh = bsh;
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mutex_init(&pcie->lock, MUTEX_DEFAULT, IPL_HIGH);
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const pcireg_t cr = bus_space_read_4(pcie->bst, pcie->bsh, PCI_CLASS_REG);
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pcie->rev = PCI_REVISION(cr);
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ap->ap_conf_read = acpi_pci_layerscape_gen4_conf_read;
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ap->ap_conf_write = acpi_pci_layerscape_gen4_conf_write;
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ap->ap_conf_priv = pcie;
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aprint_verbose_dev(ap->ap_dev,
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"PCIe segment %lu: Layerscape Gen4 rev. %#x found at %#lx-%#lx\n",
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seg, pcie->rev, mem->ar_base, mem->ar_base + mem->ar_length - 1);
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return AE_CTRL_TERMINATE;
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}
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void
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acpi_pci_layerscape_gen4_init(struct acpi_pci_context *ap)
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{
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ACPI_STATUS rv;
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rv = AcpiGetDevices(__UNCONST("NXP0016"), acpi_pci_layerscape_gen4_map, ap, NULL);
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if (ACPI_FAILURE(rv))
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return;
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}

sys/arch/arm/acpi/acpi_pci_machdep.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
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/* $NetBSD: acpi_pci_machdep.c,v 1.14 2020/01/23 11:59:37 jmcneill Exp $ */
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/* $NetBSD: acpi_pci_machdep.c,v 1.15 2020/02/01 13:26:43 jmcneill Exp $ */
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33
/*-
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* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
3232
#define _INTR_PRIVATE
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3434
#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: acpi_pci_machdep.c,v 1.14 2020/01/23 11:59:37 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: acpi_pci_machdep.c,v 1.15 2020/02/01 13:26:43 jmcneill Exp $");
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3737
#include <sys/param.h>
3838
#include <sys/bus.h>
@@ -101,6 +101,7 @@ static const struct acpi_pci_quirk acpi_pci_quirks[] = {
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{ "AMAZON", "GRAVITON", 0, -1, acpi_pci_graviton_init },
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{ "ARMLTD", "ARMN1SDP", 0x20181101, 0, acpi_pci_n1sdp_init },
103103
{ "ARMLTD", "ARMN1SDP", 0x20181101, 1, acpi_pci_n1sdp_init },
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{ "NXP ", "LX2160 ", 0, -1, acpi_pci_layerscape_gen4_init },
104105
};
105106

106107
pci_chipset_tag_t acpi_pci_md_get_chipset_tag(struct acpi_softc *, int, int);

sys/arch/arm/acpi/acpi_pci_machdep.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
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/* $NetBSD: acpi_pci_machdep.h,v 1.6 2020/01/17 17:06:33 jmcneill Exp $ */
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/* $NetBSD: acpi_pci_machdep.h,v 1.7 2020/02/01 13:26:43 jmcneill Exp $ */
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/*-
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* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -43,6 +43,7 @@ struct acpi_pci_context {
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bus_space_handle_t ap_conf_bsh;
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int (*ap_conf_read)(pci_chipset_tag_t, pcitag_t, int, pcireg_t *);
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int (*ap_conf_write)(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
46+
void *ap_conf_priv;
4647
int ap_pciflags_clear;
4748
};
4849

@@ -57,6 +58,7 @@ struct acpi_pci_quirk {
5758
const struct acpi_pci_quirk * acpi_pci_md_find_quirk(int);
5859

5960
void acpi_pci_graviton_init(struct acpi_pci_context *);
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void acpi_pci_layerscape_gen4_init(struct acpi_pci_context *);
6062
void acpi_pci_n1sdp_init(struct acpi_pci_context *);
6163

6264
#endif /* !_ARM_ACPI_PCI_MACHDEP_H */

sys/arch/arm/acpi/files.acpi

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# $NetBSD: files.acpi,v 1.9 2020/01/17 17:06:33 jmcneill Exp $
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# $NetBSD: files.acpi,v 1.10 2020/02/01 13:26:43 jmcneill Exp $
22
#
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# Configuration info for ACPI compliant ARM boards.
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#
@@ -14,6 +14,7 @@ file arch/arm/acpi/acpi_iort.c acpi
1414
file arch/arm/acpi/acpi_machdep.c acpi
1515
file arch/arm/acpi/acpi_pci_machdep.c acpi & pci
1616
file arch/arm/acpi/acpi_pci_graviton.c acpi & pci
17+
file arch/arm/acpi/acpi_pci_layerscape_gen4.c acpi & pci
1718
file arch/arm/acpi/acpi_pci_n1sdp.c acpi & pci
1819
file arch/arm/acpi/acpi_platform.c acpi
1920
file arch/arm/acpi/acpi_simplefb.c acpi & wsdisplay & genfb

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