10G MAC Interface
M_AXIS: Master AXI4-Stream (RX) bus, 64bit
S_AXIS: Slave AXI4-Stream (TX) bus, 64bit
M_AXIS_ERR: Master AXI4-Stream (ERR) bus, 0bit, handshake only
C_XAUI_REVERSE: Must be 1 for Port 0, 1, 2; 0 for Port 3. Please consult the schematic for more information
C_XAUI_CONFIGURATION: XAUI configuration vector. See Xilinx XAUI core documentation for more information.
C_XGMAC_CONFIGURATION: 10G Ethernet MAC configuration vector. See Xilinx 10G Ethernet MAC core documentation for more information.
C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream (RX) bus. Must be 64
C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream (TX) bus. Must be 64
No registers are implemented for v1.00a.
This pcore is a combination of Xilinx XAUI and 10G MAC IP cores, in addition to an AXI4-Stream adapter. Incoming XAUI signals from AEL2005 are firstly transformed into XGMII signals by Xilinx XAUI core. The XGMII signals are read in by Xilinx 10G MAC and finally transformed into AXI4-Stream. The TX side follows the exact same path but in the opposite direction.
There is one additional AXI4-Stream bus for transmitting bad_frame signal provided by Xilinx 10G MAC. For more information about NetFPGA Standard IP Interfaces, please see here.
To build a bistream with this core included, the end-user must obtain a license for the Xilinx 10G MAC. Universities can usually obtain a free license through the Xilinx University Program. Please follow the procedure as described in Licensing.