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AXI4 Stream Width Converter

mshahbaz edited this page Jul 16, 2012 · 2 revisions

Name

nf10_axis_converter

Version

v1.00a

Author

James Hongyi Zeng (hyzeng_at_stanford.edu)

Type

pcore (HW)

Location

netfpga-10g/lib/hw/std/pcores/nf10_axis_converter_v1_00_a/

Interface Types

AXI4-Stream

Busses

S_AXIS: Slave AXI4-Stream bus, Variable width

M_AXIS: Master AXI4-Stream bus, Variable width

Parameters

C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream bus.

C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream bus.

C_DEFAULT_VALUE_ENABLE: Enable default DPT and SPT metadata

C_DEFAULT_DST_PORT: Default Destination port

C_DEFAULT_SRC_PORT: Default source port

Register map

No registers are implemented for v1.00a.

Description

This block converts the width of AXI stream (only integer ratio is supported in this version). For example, when used in 10G reference NIC, it converts 64bit datapath of 10G MAC to 256bit NetFPGA datapath. Optionally, it can set up the default metadata, e.g. destination port, source port etc in the TUSER metadata field. It also calculates the length of packets and put it in TUSER field.

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