Skip to content

BRAM Output Queues

mshahbaz edited this page Jul 15, 2012 · 2 revisions

Name

nf10_bram_output_queues

Version

v1.00a

Author

James Hongyi Zeng (hyzeng_at_stanford.edu)

Karthik Swamy, Algo-Logic (kswamy2012_at_gmail.com)

Type

pcore (HW)

Location

netfpga-10g/lib/hw/std/pcores/nf10_bram_output_queues_v1_00_a/

Interface Types

AXI4-Stream

Busses

S_AXIS: Slave AXI4-Stream bus, Variable width M_AXIS_0: Master AXI4-Stream bus, Variable width M_AXIS_1: Master AXI4-Stream bus, Variable width M_AXIS_2: Master AXI4-Stream bus, Variable width M_AXIS_3: Master AXI4-Stream bus, Variable width M_AXIS_4: Master AXI4-Stream bus, Variable width

Parameters

C_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.

Register map

No registers are implemented for v1.00a.

Description

The function of this block is to dispatch packets from one input stream to a number of output streams whereby the DPT sub-band channel determines to which output the packets are routed. All input interfaces need to have the same bandwidth (and therefore width) as the output stream to ensure that maximum throughput can be achieved. The arbiter can operate in 1G or 10G mode; this is setup through selecting the data width accordingly.

Clone this wiki locally
You can’t perform that action at this time.