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Input arbiter with registers

Neelakandan Manihatty Bojan edited this page Feb 27, 2014 · 1 revision

Name

nf10_input_arbiter

Version

v1.10a

Author

Adam Covington (gcoving_at_stanford.edu)

James Hongyi Zeng (hyzeng_at_stanford.edu)

Type

pcore (HW)

Location

netfpga-10g/lib/hw/std/pcores/nf10_input_arbiter_v1_10_a/

Interface Types

AXI4-Stream

Busses

M_AXIS: Master AXI4-Stream bus, Variable width S_AXIS_0: Slave AXI4-Stream bus, Variable width S_AXIS_1: Slave AXI4-Stream bus, Variable width S_AXIS_2: Slave AXI4-Stream bus, Variable width S_AXIS_3: Slave AXI4-Stream bus, Variable width S_AXIS_4: Slave AXI4-Stream bus, Variable width S_AXI: Slave AXI4-Lite

Parameters

C_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.

C_BASEADDR: Base address value of the core.

C_HIGHADDR: High address value of the core.

Register map

0x0 : RESET_CNTRS_OFFSET

0x4 : NUM_PKTS_PROCESSED_OFFSET

Description

The function of this block is to merge a number of input streams into one output stream. All input interface share the same bandwidth (and therefore width) as the output stream to ensure that maximum throughput can be achieved. The input port buffering will be handled in the AXI Converter block. The arbiter can operate in 1G or 10G mode; this is setup through selecting the data width accordingly.

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