Skip to content

Memory Mapped RLDRAM by Muhammad Shahbaz

mshahbaz edited this page Jan 23, 2013 · 2 revisions





IP Cores


This is a memory mapped RLDRAM project using the DMA engine. It includes many of the standard NetFPGA modules (microblaze, AXI interconnect, nf10_interface), but in addition it uses a new pcore that provides a memory mapped interface to the RLDRAM controllers over the AXI bus. Two instances of this pcore are instantiated in the project that allow independent access to a pair (A & B) of the four on-board RLDRAM controllers at a clock rate of 200 MHz.

Block Diagram

Steps to implement rldram_mmap

  1. Download the application note from Xilinx website (XAPP852)

  2. Extract the contents of under the project's pcores directory (rldram_mmap/hw/pcores/nf10_rldram_mmap_v1_00_a)

  3. In the rldram_mmap/hw/pcores/nf10_rldram_mmap_v1_00_a folder run make - this will create, copy and patch neccessary Xilinx files for the rldram core

  4. Run the project makefile to implement and generate bitstream

  5. Program the FPGA

  6. Reboot the system

  7. Build and load the driver under the contrib-projects/nic/sw/host/drivers

    make insmod nf10.ko

  8. Build the 'wraxi' and 'rdaxi' located under the contrib-projects/nic/sw/host/apps directory


  9. Read and write RLDRAM A & B

Base address of RLDRAM A = 0x80000000

Base address of RLDRAM B = 0x84000000

./wraxi 80000000 12345678
./rdaxi 80000000

For successful operation, you should get the same value back!

Clone this wiki locally
You can’t perform that action at this time.