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NetFPGA 1G Port Template

Muhammad Shahbaz edited this page May 3, 2012 · 1 revision

Name

nf1g_template

Version

v1.00a

Author

Muhammad Shahbaz (muhammad.shahbaz_at_cl.cam.ac.uk)

Type

pcore (HW)

Location

netfpga-10g/lib/hw/contrib/pcores/nf1g_template_v1_00_a/

Interface Types

Packet-Stream

Register-Stream

Busses

S_PBS: Slave Packet-Stream bus, Variable width

M_PBS: Master Packet-Stream bus, Variable width

S_RBS: Slave Register-Stream bus, Variable width

M_RBS: Master Register-Stream bus, Variable width

Parameters

C_M_PBS_DATA_WIDTH: Data width of the master Packet-Stream bus.

C_S_PBS_DATA_WIDTH: Data width of the slave Packet-Stream bus.

C_RBS_ADDR_WIDTH: Address width of the Register-Stream bus.

C_RBS_DATA_WIDTH: Data width of the Register-Stream bus.

C_RBS_SRC_WIDTH: Source width of the Register-Stream bus.

Register map

No registers are implemented for v1.00a.

Description

This block serves as a template for porting NetFPGA-1G modules to the new 10G platform. It provides necessary .mpd, .pao, .bbd and .v mappings for smooth integration into the Xilinx EDK suite.

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