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Old Standard IP Interfaces

Andrew W. Moore edited this page Mar 13, 2012 · 2 revisions

Document Description

This document describes the standard set of interfaces used by NetFPGA-10G platform IP.

Version: 0.4

Reference Documentation

AMBA 4 AXI4-Stream Protocol Specification v 1.0

Xilinx AXI Streaming Protocol Specification v 1.9

UG761 AXI Reference Guide

Background

Use of interface standards is essential to the platform's goal of enabling rapid prototyping of networking applications. It increases IP interoperability, and therefore IP reuse. Developers are strongly encouraged to employ these interfaces whenever possible.

The NetFPGA-10G platform's standard interfaces themselves strictly adhere to a widely used interface standard released originally by ARM called AXI4, and later refined by Xilinx. The language used in this document to describe the platform's standard interfaces is inherited from these documents. Readers are encouraged to read the AMBA AXI4-Stream Protocol Specification which defines the original standard, as well as the Xilinx AXI Streaming Protocol Specification which places some restrictions on the original AMBA AXI4-Stream Specification for Xilinx applications (staying within the bounds of the original AMBA AXI4-Stream Spec).

Standard Interfaces

We currently specify and support the following set of interfaces:

  • Control & status interface: We use the Xilinx standardized AXI4 lite interface which is derived from the AMBA4 bus specification

  • Data path interface: We use the Xilinx AXI4 streaming interface (contiguous and aligned strobes) which is derived from the AMBA4 bus specification. We use specific default settings for different type of bandwidth requirements and added conventions for the transport of packet meta data in sub-band channels. This is described in more detail below.

We suggest that for debug 32bit vectors of type out are added to the modules (named "debug"). These can then be connected on the top level to LEDs or Chipscope pcores.

Background material on AXI4 interfaces can be found at:

http://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf

Control & Status Interface

We use an AXI4 lite protocol which is a simple read/write interface, single beat access, with 32bit address and 32bit data. It is basically implemented through 5 FIFO channels: read data, read address, write data, write address and write response. Components inside the FPGA design with AXI lite interface can be connected to the AXI4 lite interconnect in which all peripherals reside within a flat address space. Both PCIe and micorblaze act as masters on this interconnect and can write and read all peripherals. Addresses can be assigned manually, however EDK can automatically create an address map for all peripherals connected to this control/status network.

AXI lite interface signals:

Channel **Signal ** **Status ** **Description **

write address AWADDR required write address - see AXI spec.

AWVALID required write address valid - see AXI spec.

AWREADY required

write address flow control - see AXI spec

write data WDATA required write data - see AXI spec

WSTRB required write data byte strobe - see AXI spec

WVALID required write data valid - see AXI spec

WREADY required write data flow control - see AXI spec

write response BRESP required write response - see AXI spec

BVALID required write response valid - see AXI spec

BREADY required write response flow control - see AXI spec

read address ARADDR required read address - see AXI spec

ARVALID required read address valid - see AXI spec

ARREADY required read address flow control - see AXI spec

read data RDATA required read data - see AXI spec

RRESP required read response - see AXI spec

RVALID required read data valid - see AXI spec

RREADY required read data flow control - see AXI spec

clock/reset ACLK required clock - see AXI spec., can be shared between multiple interfaces on the same components

ARESETN required low active reset - see AXI spec, can be shared between multiple interfaces on the same components

The interface can be parameterized in the following way:

**Parameter name ** **Description ** Default Type

C_BASEADDR AXI Base Address

integer

C_HIGHADDR

AXI High Address

integer

C_AXI_ADDR_WIDTH

AXI address bus width

32

integer

C_AXI_DATA_WIDTH AXI data bus width 32 integer

C_AXI_PROTOCOL AXI flavour AXI4LITE string

The following table summarizes the naming conventions: ( refers to the names in the table above)

**AXI Type ** **Direction ** **Signal name **

AXI Lite Master M_AXI_

Slave S_AXI_

Data Path Interface

A data path interface is a group of five tightly coupled "channels". Each channel is a pre-configured Xilinx AXI4 Streaming Protocol v1.9 compliant stream. One of these channels is called the "data" channel. It is responsible for moving data from master to slave. All other channels included in a data path interface are for conveying metadata. These channels are referred to as "sub-band channels", and are "length", "source port", "destination port", and "error". They are described in more detail below. Data channel and associated sub-band channels share the same clock and reset. Sub-band channels are optional however we do strongly encourage the user to implement them.

Each sub-band channel on the master side of a data path interface can be one of two types: "active producer", or a "passive producer". Being an active producer means that the IP block is producing valid metadata in the sub-band channel for every packet. A passive producer covers all other cases. It is expected that these other cases mostly consist of IP blocks that pass along metadata from other input channels, possibly modifying it along the way, and do not make the guarantee to downstream slaves of providing metadata for every packet.

Each sub-band channel if present on the slave side of a data path interface is called a "consumer".

The following is a specification for each of the five data path interface channels. Each channel is introduced in two ways: the first being a compact and precise form (called Spec Savy Description) for those who have read the Xilinx AXI Streaming Protocol Specification v 1.9, and the second (called Quick Synopsis) being a quick listing of the required signals, parameters, and notes. For some channels there may be additional notes at the bottom that impose additional restrictions or specifications on the channel that go beyond what is described in official specification documents. For the sub-band channels, these specifications apply to requirements imposed on generators of metadata. These specifications apply to the "active producer" and "consumer" type of sub-band channels.

Clock and Reset:

Clock and reset are common to all channels within a single data path interface, so between the data path and all its sub-band channels.

Required Signals:

**Signal ** **Status ** **Description **

ACLK required clock - see AXI spec., can be shared between multiple interfaces on the same components

ARESETN required active low reset - see AXI spec., can be shared between multiple interfaces on the same components

Data Channel (DAT):

The "data" channel is responsible for moving data from master to slave.

Spec Savy Description:

Xilinx AXI Stream Configuration:

Layer Number Layer Name Configuration Number Configuration Name

0 Handshake Signaling 0.2 Forward and Backward Flow Control

1 Data Signals 1.2 Payload with Aligned Strobes

2 User Signals 2.0 Not Present

3 Packetization 3.1 Packetized or Framed Data

4 Multi-Threaded Data 4.0 Single Threaded Stream

5 Data Routing 5.0 No Stream Data Routing

6 Null Bytes 6.0 Data and Position Bytes Only

Quick Synopsis:

Required Signals:

Signal Bit Width **Description **

TVALID 1 master to slave flow control signal - see AXI spec.

TDATA C_DAT_DATA_WIDTH data signal - see AXI spec.

TREADY 1 slave to master flow control signal - see AXI spec.

TSTRB C_DAT_DATA_WIDTH/8 byte enable signal - see AXI spec.

TLAST 1 indicates end of packet - see AXI spec.

Parameters:

**Parameter name ** **Description ** Details Type Default(s)

C_DAT_DATA_WIDTH bit width of TDATA (see AXI spec.) must be a multiple of 8 integer

8,32,64,256

Notes:

* TSTRB is an "aligned strobe" (see Xilinx AXI spec.). Translation: Within a packet transfer, invalid bytes (indicated by TSTRB LOW) may ONLY be sent contiguously together at the tail end of a packet.
* C_DAT_DATA_WIDTH is: 8 for 1Gbps transport, 32 for 4Gbps transport, 64 for 10Gbps transport, 256 and 40Gbps transport.

All Sub-band Channels (XYZ):

The following applies to all sub-band channels, unless otherwise noted.

Spec Savy Description:

Xilinx AXI Stream Configuration:

Layer Number Layer Name Configuration Number Configuration Name

0 Handshake Signaling 0.1 Forward Flow Control

1 Data Signals 1.1 Payload Only

2 User Signals 2.0 Not Present

3 Packetization 3.0 Non-Packetized, Continuous Data or No Data

4 Multi-Threaded Data 4.0 Single Threaded Stream

5 Data Routing 5.0 No Stream Data Routing

6 Null Bytes 6.0 Data and Position Bytes Only

Quick Synopsis:

Required Signals:

Signal Bit Width **Description **

TVALID 1 master to slave flow control signal - see AXI spec.

TDATA C_XYZ_DATA_WIDTH data signal - see AXI spec.

Parameters:

**Parameter name ** **Description ** Details Type

C_XYZ_DATA_WIDTH bit width of TDATA (see AXI spec.) must be a multiple of 8 integer

Extremely Important Note:

* All sub-band channel signals are required to behave precisely as if they were additional bits of TDATA in the data channel. TSTRB, however, has no effect on sub-band channel signals.

Length Sub-and Channel (LEN):

The "length" sub-band channel is meant for carrying metadata concerning the length of the packet being transfered in the data channel.

Additional Specification:

* C_LEN_DATA_WIDTH >= 16
* Length metadata is required to be present for every packet.
* Length metadata must be transferred on the first beat of a packet.
* When valid, the value of TDATA[C_LEN_DATA_WIDTH-1:0] is the length of the packet in bytes.

Source Port Sub-band Channel (SPT):

The "source port" sub-band channel is meant for carrying metadata concerning the source port of the packet being transfered in the data channel.

Additional Specification:

* C_SPT_DATA_WIDTH >= 8
* Source port metadata is required to be presented for every packet.
* Source port metadata must be transferred on the first beat of a packet.
* When valid, the value of TDATA[7:0] has the following encoding:

**TDATA[7:0] ** **Meaning **

8'bxxxx_xxx1 Ethernet Port 0 (closest to PCIe slot)

8'bxxxx_xx1x Ethernet Port 1 (next to Ethernet Port 0)

8'bxxxx_x1xx Ethernet Port 2 (next to Ethernet Port 3)

8'bxxxx_1xxx Ethernet Port 3 (furthest from PCIe slot)

8'bxxx1_xxxx PCIe Logical Port 0 (1)

8'bxx1x_xxxx PCIe Logical Port 1 (1)

8'bx1xx_xxxx PCIe Logical Port 2 (1)

8'b1xxx_xxxx PCIe Logical Port 3 (1)

1 Although there exists only one physical PCIe interface to the FPGA, the NetFPGA-10G application infrastructure, which brokers most off-chip communication via standard AXI interfaces, virtualizes this resource and presents four logical PCIe "ports" to the application.

Destination Port Sub-band Channel (DPT):

The "destination port" sub-band channel is meant for carrying metadata concerning the destination port of the packet being transfered in the data channel.

It has exactly the same configuration as the SPT channel above.

Note:

* The encoding of ports as given in the table above may help IP designers to implement multicasting functionality. Whether or not this is supported by IP should be specified in the IP datasheet (else no support should be assumed).

Error Sub-band Channel (ERR):

The "error" sub-band channel is meant for carrying metadata concerning the result of validating the packet being transfered in the data channel. For example, in the case that the packet being transferred is an Ethernet packet, one could use the error sub-band channel to indicate a bad checksum.

It differs from normal sub-band channels in that it does NOT include the TDATA signal:

** Spec Savy Description:**

Xilinx AXI Stream Configuration:

Layer Number Layer Name Configuration Number Configuration Name

1 Data Signals 1.1 no payload

Quick Synopsis:

Required Signals:

Signal Bit Width **Description **

TVALID 1 master to slave flow control signal - see AXI spec.

Additional Specification:

* TVALID being HIGH for ANY transfer encodes that the packet to which the current transfer belongs failed validation.

Signal Naming for Stream Interfaces:

The Xilinx AXI Streaming Protocol Specification v 1.9 suggests the following naming conventions for AXI Stream ports on IP:** **

_

Where:

::= []

::= [][_n]

Without confusion, ChannelName can be omitted in DAT channel.

Where for NetFPGA-10G:

  • ::= "M" | "S" ;
  • ::= "AXIS" ;
  • ::= ;
  • ::=;
  • ::= "TVALID" | "TDATA" | "TSTRB" | "TREADY" | "TLAST" ;
  • ::= , ;

Bus Interface Name Examples:

M_AXIS_DPI0

M_AXIS_ENCRYPT

S_AXIS_VIDEO

S_AXIS_AUDIO

Port Name Examples:

TDATA

LEN_TDATA

SRCPRT_TDATA

DSTPRT_TDATA

ERR_TVALID

Full Name Example:

M_AXIS_VIDEO

M_AXIS_VIDEO_LEN

However, please note that this is a changing specification, and already newly released IP is following a different grammar. For instance, they sometimes swap the ordering of the ClassName and Role (creating AXIS_M instead of M_AXIS), and sometimes omit the BusName completely.

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