Register System

Gianni Antichi edited this page Dec 11, 2013 · 7 revisions
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This page describes the register system that is introduced with the NetFPGA-10G 4.5.0 release.


The register system collates and generates addresses for all the registers and memories in an NF10 project. The system (as may perceived from its name) is not limited to generating base address information only but can be used to provide logic (core) specific software api's and libraries. The system utilises Xilinx EDK suite - library generation utility [1][2] to collect and create software level api's and register information for a project.

Each project in NetFPGA-10G is composed of multiple peripheral cores (pcores) connected together using interfaces based on AXI4, AXI-LITE (for memory mapped IO) or AXIS (for data streaming) protocols. For the register system, we are only concern with the memory mapped IOs over AXI4 and AXI-LITE interfaces. For more information on project organisation and directory structure visit here.

Accessing Register/Memory

A project built in EDK is provided with a contiguous map of memory, normally 4GB in range, with all instantiated cores mapped to a unique range inside this map. Individual registers and memories, inside the core, are allocated offsets from within this range.

In order to access a register/memory from host, two sets of information are required:

  1. Base address of the range assigned to a core (BA)

    These values are assigned at time of instantiating a core and are local to the project. The Xilinx EDK suite will automatically assign a unique address value for the core, if not already assigned by the user.

  2. Offset of the register inside the core (RO)

    These values are assigned and hard coded within the verilog/vhdl code by the developer of a core. The offset values for registers and memories inside a core always remain the same for all the projects but base address of the core itself may vary from project to project, as mentioned earlier. (Note: It's the responsibility of the developer to provide this information in the form of driver/library for the given core - see section on Building driver/library for a Peripheral Core below.)

The register address is calculated as: Register address (RA) = BA + RO

So, the purpose of the register system is to collect this base address and register offset information and provide them as software accessible C/C++ code files. The next section provides instructions for users and developers on using the register system and providing relevant register (offset) information in the form of a driver/library respectively.

Step required to obtain the reg_defines.h:

EDK provides a complete infrastructure to get this. Please refer to the external references for more details on how it is done.

Every time a new PCORE is created and added to a project, there are some simple steps that are required in order to expose the registers in the reg_defines.h file:

  1. Specify the offset of the register in the MPD file of the PCORE in this way,:


where NAME represent the name of your register. Remember to assign the correct offset to the parameter accordingly to the Verilog code.

  1. Write the SW Driver for the PCORE you are working on. Remember to add in the TCL file, all the registers you want to be included in the reg_defines.h.

    Take as example the nf10_switch_v1_00_a driver and the nf10_switch_output_port_lookup PCORE.

    go in the projects/project_name/hw and run the following in the command line:

    make regs

    When you do make regs, the Xilinx tool libgen, generates xparameters.h which gives a register map of the design (contains the base address and the offset). This xparameters.h is fed as input to the python file, that generates reg_defines.h file which has the complete address map (baseaddress+offfset for each register).

    Finally the reg_defines.h file is created in projects/project_name/sw/host


For Users': Using the Register System

For Developers': Building driver/library for a Peripheral Core

External References

  1. Embedded System Tools Reference Manual:

  2. Platform Specification Format Reference Manual: