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The NetFPGA is a low-cost platform, primarily designed as a tool for teaching networking hardware and router design. It has also proved to be a useful tool for networking researchers. Through partnerships and donations from sponsor of the project, the NetFPGA is widely available to students, teachers, researchers, andNF anyone else interested in experimenting with new ideas in high-speed networking hardware.
At a high level, the board contains four 1 Gigabit/second Ethernet (GigE) interfaces, a user programmable Field Programmable Gate Array (FPGA), and four banks of locally-attached Static and Dynamic Random Access Memory (SRAM and DRAM). It has a standard PCI interface allowing it to be connected to a desktop PC or server. A reference design can be downloaded from the http://NetFPGA.org website that contains a hardware-accelerated Network Interface Card (NIC) or an Internet Protocol Version 4 (IPv4) router that can be readily configured into the NetFPGA hardware. The router kit allows the NetFPGA to interoperate with other IPv4 routers.
The NetFPGA offloads processing from a host processor. The host's CPU has access to main memory and can DMA to read and write registers and memories on the NetFPGA. Unlike other open-source projects, the NetFPGA provides a hardware-accelerated hardware datapath. The NetFPGA provides a direct hardware interface connected to four GigE ports and multiple banks of local memory installed on the card.
NetFPGA packages (NFPs) are available that contain source code (both for hardware and software) that implement networking functions. Using the reference router as an example, there are three main ways that a developer can use the NFP. In the first usage model, the default router hardware can be configured into the FPGA and the software can be modified to implement a custom protocol.
Another way to modify the NetFPGA is to start with the reference router and extend the design with a custom user module. Finally, it is also possible to implement a completely new design where the user can place their own logic and data processing functions directly in the FPGA.
- Use the hardware as is as an accelerator and modify the software to implement new protocols. In this scenario, the NetFPGA board is programmed with IPv4 hardware and the Linux host uses the Router Kit Software distributed in the NFP. The Router Kit daemon mirrors the routing table and ARP cache from software to the tables in the hardware allowing for IPv4 routing at line rate. The user can modify Linux to implement new protocols and test them using the full system.
- Start with the provided hardware from the official NFP (or from a third-party NFP), modify it by using modules from the NFP's library or by writing your own Verilog code, then compile the source code using industry standard design tools. The implemented bitfile can then be downloaded to the FPGA. The new functionality can be complemented by additional software or modifications to the existing software. For the IPv4 router, an example of this would be implementing a Trie longest prefix match (LPM) lookup instead of the currently implemented CAM LPM lookup for the hardware routing table. Another example would be to modify the router to implement NAT or a firewall.
- Implement a new design from scratch: The design can use modules from the official NFP's library or third party modules to implement the needed functionality or can use completely new source code.
A block diagram that shows the major components of NetFPGA platform is shown below.
The NetFPGA platform contains one large Xilinx Virtex2-Pro 50 FPGA which is programmed with user-defined logic and has a core clock that runs at 125MHz. The NetFPGA platform also contains one small Xilinx Spartan II FPGA holding the logic that implements the control logic for the PCI interface to the host processor.
Two 18 MBit external Cypress SRAMs are arranged in a configuration of 512k words by 36 bits (4.5 Mbytes total) and operate synchronously with the FPGA logic at 125 MHz. One bank of external Micron DDR2 SDRAM is arranged in a configuration of 16M words by 32 bits (64 MBytes total). Using both edges of a separate 200 MHz clock, the memory has a bandwidth of 400 MWords/second (1,600 MBytes/s = 12,800 Mbits/s).
The Broadcom BCM5464SR Gigabit/second external physical-layer transceiver (PHY) sends packets over standard category 5, 5e, or 6 twisted-pair cables. The quad PHY interfaces with four Gigabit Ethernet Media Access Controllers (MACs) instantiated as a soft core on the FPGA. The NetFPGA also includes two interfaces with Serial ATA (SATA) connectors that enable multiple NetFPGA boards in a system to exchange traffic directly without use of the PCI bus. In order to get
More information about BCM5464SR chip.
Depending on your goals, you may find certain chapters of this guide more relevant than others.
If you already have NetFPGA systems up and running in your laboratory and want to understand how it works, read the walkthroughs of the Reference Designs to understand the operation of the reference NIC, the software component of the router (SCONE), the router kit, the reference router hardware, and the buffer monitoring system.
We encourage feedback and discussion about the progress and problems with the NetFPGA. A bug-tracking system called Bugzilla is available to read about and post bugs. A forum is available to communicate with other members of the community and submit patches.
We track and maintain bugs using GitHub issues GitHub-issues
We've created a forum where users can post their questions and have them answered. The forum is easily searchable and anyone can register. It is available here.
- Feel free to use the forum for:
- Announcements on progress with the NetFPGA
- General questions about the scripts and code
- Answers to questions (feel free to contribute)
- Submit patches! We always welcome these :)
We do not guarantee that any or all of the NetFPGA components will work for you. FPGAs allow for an enormous range of freedom in the implementation of circuits. We do not guarantee that anything you get from us will not damage the hardware on the NetFPGA, the software on the PC, or anything else. And finally we do not guarantee that you will get support. However, we do guarantee that we did/will do our best. Hence, the license.
The first thing to be done is putting the board in the the box and making sure it runs. To get started, you'll need to perform the following steps:
- Obtaining NetFPGA Hardware: How you can acquire NetFPGA hardware
- Obtaining a Host PC for the NetFPGA : How you can buy or build your Host PC.
- Obtaining Gateware/Software Package: How you can get an account and download the Beta package from NetFPGA.org
- Installing an Operating System on the Host PC: Describes how to install CentOS on the host computer
- Software Installation: Install the NetFPGA device driver and self-test program & bitfile
- Install CAD Tools: Install Computer Aided Design tools to enable synthesis and simulation of hardware circuits (Optional)
- Compile and Load Driver: Run the makefile to build the executables
- Run Selftest: Verify the functionality of your NetFPGA system
Run Regression Tests: Each project has a set of regression tests that verify the functionality of the distributed code.
These should be run before starting to use any of the projects from the NFP.
This section describes some walkthroughs to help in using the distributed source code. Each walkthrough will deal with a different aspect of using the reference designs. Some sections will be marked as optional reading. These sections explain what is going on behind the scenes to put things together and are not within the main focus of the walkthrough. The walkthroughs are the following:
Reference NIC Walkthrough: Mainly an introduction to the software/hardware interface. How to make software talk to the hardware.
SCONE Walkthrough: More complex example of user process communicating to hardware. How to talk to the router and set entries.
Router Kit Walkthrough: How to install and use the router kit.
Reference Router Walkthrough: Introduces more details about the hardware, and how to modify it.
Buffer Monitoring System: Describes how a circuits was added to measure the lengths of buffers.
The schematic of the NetFPGA board is available as both a PDF and an Orcad Capture file:
- Revision 2:
- Revision 3:
- Allegro layout will be released when we have a confirmed working revision 3 board
Contains Tutorial setup instructions
- Register Map - Information on all available registers and how to use them.
- Verilog Library Modules - Place holder
The NetFPGA code is distributed under a BSD-style license shown below. Please make sure you read and understand it. The design of the board itself is also available freely.
Copyright (c) 2006-2012 The Board of Trustees of The Leland Stanford Junior University We are making the NetFPGA tools and associated documentation (Software) available for public use and benefit with the expectation that others will use, modify and enhance the Software and contribute those enhancements back to the community. However, since we would like to make the Software available for broadest use, with as few restrictions as possible permission is hereby granted, free of charge, to any person obtaining a copy of this Software) to deal in the Software under the copyrights without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
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