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fix comparaisons between var and float

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commit bc97b8e239f862585f1c226266e3ebf5985241ea 1 parent e16bea6
@NotFound authored
Showing with 20 additions and 0 deletions.
  1. +10 −0 winxedst1.winxed
  2. +10 −0 winxedst2.winxed
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10 winxedst1.winxed
@@ -3970,6 +3970,16 @@ class ComparatorBaseExpr : OpBinaryExpr
e.emitset(aux, regr);
regr = aux;
break;
+ case rr == REGfloat && rl == REGvar:
+ aux = self.tempreg(REGfloat);
+ e.emitset( aux, regl);
+ regl = aux;
+ break;
+ case rr == REGvar && rl == REGfloat:
+ aux = self.tempreg(REGfloat);
+ e.emitset(aux, regr);
+ regr = aux;
+ break;
case rr == REGstring && rl == REGvar:
aux = self.tempreg(REGstring);
e.emitset(aux, regl);
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10 winxedst2.winxed
@@ -4961,6 +4961,16 @@ class ComparatorBaseExpr : OpBinaryExpr, ConditionFriendlyExpr
e.emitset(aux, regr);
regr = aux;
break;
+ case rr == REGfloat && rl == REGvar:
+ aux = self.tempreg(REGfloat);
+ e.emitset( aux, regl);
+ regl = aux;
+ break;
+ case rr == REGvar && rl == REGfloat:
+ aux = self.tempreg(REGfloat);
+ e.emitset(aux, regr);
+ regr = aux;
+ break;
case rr == REGstring && rl == REGvar:
aux = self.tempreg(REGstring);
e.emitset(aux, regl);
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