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hdl, libbladeRF: Bumped FPGA version to v0.1.0
Minor revision bumped to denote the addition of backwards-compatible features: - Added divide-by-two option for sample counter - TX_NOW operation
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hdl/CHANGELOG

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@@ -4,9 +4,23 @@ bladeRF HDL Change Log Summary
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For more detailed information, please see the git change log and issue tracker
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hosted on GitHub: https://github.com/nuand/bladeRF
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================================================================================
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v0.1.0 (2014-10-21)
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--------------------------------
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* Backwards-compatible features introduced:
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- Added option to divide sample counter by 2.
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- Added "TX_NOW"
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* Fixes:
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- Addessed data/timestamp slipping
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- Fixed readback of current timestamp value
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- Send zero samples TX module to mitigate effect of default output power
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from the LMS after intialization.
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v0.0.6 (2014-07-20)
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--------------------------------
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* Fixed FPGA correction for gain/phase
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* Fixed FPGA correction for gain/phase
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v0.0.5 (2014-06-21)
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--------------------------------

hdl/fpga/ip/altera/nios_system/software/lms_spi_controller/lms_spi_controller.c

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@@ -46,8 +46,8 @@
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//when version id is moved to a qsys port these will be removed
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#define FPGA_VERSION_ID 0x7777
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#define FPGA_VERSION_MAJOR 0
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#define FPGA_VERSION_MINOR 0
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#define FPGA_VERSION_PATCH 6
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#define FPGA_VERSION_MINOR 1
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#define FPGA_VERSION_PATCH 0
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#define FPGA_VERSION (FPGA_VERSION_MAJOR | (FPGA_VERSION_MINOR << 8) | (FPGA_VERSION_PATCH << 16))
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#define TIME_TAMER TIME_TAMER_0_BASE

host/libraries/libbladeRF/src/version_compat.c

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@@ -48,6 +48,7 @@ static const struct compat fw_compat_tbl[] = {
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static const struct compat fpga_compat_tbl[] = {
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/* FPGA requires >= Firmware */
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{ VERSION(0, 1, 0), VERSION(1, 6, 1) },
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{ VERSION(0, 0, 6), VERSION(1, 6, 1) },
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{ VERSION(0, 0, 5), VERSION(1, 6, 1) },
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{ VERSION(0, 0, 4), VERSION(1, 6, 1) },

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