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hdl, libbladeRF: Bumped FPGA version to v0.1.0

Minor revision bumped to denote the addition of backwards-compatible
features:
    - Added divide-by-two option for sample counter
    - TX_NOW operation
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jynik committed Oct 21, 2014
1 parent 36e37df commit 58fc84105cf1f543f57edce483cddbedbbcf38d7
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@@ -4,9 +4,23 @@ bladeRF HDL Change Log Summary
For more detailed information, please see the git change log and issue tracker
hosted on GitHub: https://github.com/nuand/bladeRF
================================================================================
v0.1.0 (2014-10-21)
--------------------------------
* Backwards-compatible features introduced:
- Added option to divide sample counter by 2.
- Added "TX_NOW"
* Fixes:
- Addessed data/timestamp slipping
- Fixed readback of current timestamp value
- Send zero samples TX module to mitigate effect of default output power
from the LMS after intialization.
v0.0.6 (2014-07-20)
--------------------------------
* Fixed FPGA correction for gain/phase
* Fixed FPGA correction for gain/phase
v0.0.5 (2014-06-21)
--------------------------------
@@ -46,8 +46,8 @@
//when version id is moved to a qsys port these will be removed
#define FPGA_VERSION_ID 0x7777
#define FPGA_VERSION_MAJOR 0
#define FPGA_VERSION_MINOR 0
#define FPGA_VERSION_PATCH 6
#define FPGA_VERSION_MINOR 1
#define FPGA_VERSION_PATCH 0
#define FPGA_VERSION (FPGA_VERSION_MAJOR | (FPGA_VERSION_MINOR << 8) | (FPGA_VERSION_PATCH << 16))
#define TIME_TAMER TIME_TAMER_0_BASE
@@ -48,6 +48,7 @@ static const struct compat fw_compat_tbl[] = {
static const struct compat fpga_compat_tbl[] = {
/* FPGA requires >= Firmware */
{ VERSION(0, 1, 0), VERSION(1, 6, 1) },
{ VERSION(0, 0, 6), VERSION(1, 6, 1) },
{ VERSION(0, 0, 5), VERSION(1, 6, 1) },
{ VERSION(0, 0, 4), VERSION(1, 6, 1) },

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