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fpga: Fixing latches, TX NOW accumulation and sample FIFOs.
Removed some warnings about latches. Fixed a bug where multiple TX NOW bursts would accumulate samples in the RX FIFO and was causing a slip in metadata headers versus samples. Modifying the sample FIFOs to have under/overflow checking to them. Registering the FIFO reader output.
1 parent 74a3977 commit 68c617b

8 files changed

Lines changed: 177 additions & 42 deletions

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‎hdl/fpga/ip/altera/nios_system/software/bladeRF_nios/src/fpga_version.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
#define FPGA_VERSION_ID 0x7777
99
#define FPGA_VERSION_MAJOR 0
1010
#define FPGA_VERSION_MINOR 3
11-
#define FPGA_VERSION_PATCH 3
11+
#define FPGA_VERSION_PATCH 4
1212
#define FPGA_VERSION ((uint32_t)( FPGA_VERSION_MAJOR | \
1313
(FPGA_VERSION_MINOR << 8) | \
1414
(FPGA_VERSION_PATCH << 16) ) )

‎hdl/fpga/ip/altera/rx_fifo/rx_fifo.vhd‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -122,10 +122,10 @@ BEGIN
122122
lpm_type => "dcfifo",
123123
lpm_width => 32,
124124
lpm_widthu => 12,
125-
overflow_checking => "OFF",
125+
overflow_checking => "ON",
126126
rdsync_delaypipe => 5,
127127
read_aclr_synch => "ON",
128-
underflow_checking => "OFF",
128+
underflow_checking => "ON",
129129
use_eab => "ON",
130130
write_aclr_synch => "ON",
131131
wrsync_delaypipe => 5

‎hdl/fpga/ip/altera/tx_fifo/tx_fifo.vhd‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -122,10 +122,10 @@ BEGIN
122122
lpm_type => "dcfifo",
123123
lpm_width => 32,
124124
lpm_widthu => 12,
125-
overflow_checking => "OFF",
125+
overflow_checking => "ON",
126126
rdsync_delaypipe => 5,
127127
read_aclr_synch => "ON",
128-
underflow_checking => "OFF",
128+
underflow_checking => "ON",
129129
use_eab => "ON",
130130
write_aclr_synch => "ON",
131131
wrsync_delaypipe => 5

‎hdl/fpga/ip/nuand/nuand.do‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,5 +33,17 @@ proc compile_nuand { root } {
3333

3434
vcom -work nuand -2008 [file join $root ./simulation/fx3_model.vhd]
3535
vcom -work nuand -2008 [file join $root ./simulation/lms6002d_model.vhd]
36+
37+
vcom -work nuand -2008 [file join $root ./synthesis/lms6002d/vhdl/lms6002d.vhd]
38+
vcom -work nuand -2008 [file join $root ./synthesis/lms6002d/vhdl/tb/lms6002d_tb.vhd]
39+
40+
vcom -work nuand -2008 [file join $root ../altera/rx_fifo/rx_fifo.vhd]
41+
vcom -work nuand -2008 [file join $root ../altera/tx_fifo/tx_fifo.vhd]
42+
vcom -work nuand -2008 [file join $root ../altera/rx_meta_fifo/rx_meta_fifo.vhd]
43+
vcom -work nuand -2008 [file join $root ../altera/tx_meta_fifo/tx_meta_fifo.vhd]
44+
45+
vcom -work nuand -2008 [file join $root ./synthesis/fifo_reader.vhd]
46+
vcom -work nuand -2008 [file join $root ./synthesis/fifo_writer.vhd]
47+
vcom -work nuand -2008 [file join $root ./simulation/sample_stream_tb.vhd]
3648
}
3749

‎hdl/fpga/ip/nuand/simulation/sample_stream_tb.vhd‎

Lines changed: 145 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@ architecture arch of sample_stream_tb is
2121

2222
-- Clock half periods
2323
constant FX3_HALF_PERIOD : time := 1.0/(100.0e6)/2.0*1 sec ;
24-
constant TX_HALF_PERIOD : time := 1.0/(40.0e6)/2.0*1 sec ;
25-
constant RX_HALF_PERIOD : time := 1.0/(40.0e6)/2.0*1 sec ;
24+
constant TX_HALF_PERIOD : time := 1.0/(9.0e6)/2.0*1 sec ;
25+
constant RX_HALF_PERIOD : time := 1.0/(9.0e6)/2.0*1 sec ;
2626

2727
-- Clocks
2828
signal fx3_clock : std_logic := '1' ;
@@ -31,6 +31,12 @@ architecture arch of sample_stream_tb is
3131

3232
signal reset : std_logic := '1' ;
3333

34+
-- Configuration
35+
signal usb_speed : std_logic ;
36+
signal meta_en : std_logic ;
37+
signal rx_timestamp : unsigned(63 downto 0) := (others =>'0') ;
38+
signal tx_timestamp : unsigned(63 downto 0) := (others =>'0') ;
39+
3440
-- TX Signalling
3541
signal tx_enable : std_logic ;
3642
signal tx_native_i : signed(11 downto 0) ;
@@ -69,12 +75,12 @@ architecture arch of sample_stream_tb is
6975
-- FIFO type
7076
type fifo_t is record
7177
aclr : std_logic ;
72-
data : std_logic_vector(31 downto 0) ;
78+
data : std_logic_vector ;
7379
rdclk : std_logic ;
7480
rdreq : std_logic ;
7581
wrclk : std_logic ;
7682
wrreq : std_logic ;
77-
q : std_logic_vector(31 downto 0) ;
83+
q : std_logic_vector ;
7884
rdempty : std_logic ;
7985
rdfull : std_logic ;
8086
rdusedw : std_logic_vector ;
@@ -83,15 +89,42 @@ architecture arch of sample_stream_tb is
8389
wrusedw : std_logic_vector ;
8490
end record ;
8591

86-
-- TX FIFO
87-
signal txfifo : fifo_t( rdusedw(11 downto 0), wrusedw(11 downto 0) ) ;
88-
signal rxfifo : fifo_t( rdusedw( 9 downto 0), wrusedw( 9 downto 0) ) ;
92+
-- FIFOs
93+
signal txfifo : fifo_t( data( 31 downto 0), q( 31 downto 0), rdusedw(11 downto 0), wrusedw(11 downto 0) ) ;
94+
signal rxfifo : fifo_t( data( 31 downto 0), q( 31 downto 0), rdusedw(11 downto 0), wrusedw(11 downto 0) ) ;
95+
signal txmeta : fifo_t( data( 31 downto 0), q(127 downto 0), rdusedw( 2 downto 0), wrusedw( 4 downto 0) ) ;
96+
signal rxmeta : fifo_t( data(127 downto 0), q( 31 downto 0), rdusedw( 6 downto 0), wrusedw( 4 downto 0) ) ;
8997

9098
alias lms_tx_clock : std_logic is tx_clock ;
9199
alias lms_rx_clock : std_logic is rx_clock ;
92100

93101
begin
94102

103+
usb_speed <= '0' ;
104+
meta_en <= '1' ;
105+
106+
increment_tx_ts : process(tx_clock)
107+
variable ping : boolean := true ;
108+
begin
109+
if( rising_edge(tx_clock) ) then
110+
ping := not ping ;
111+
if( ping = true ) then
112+
tx_timestamp <= tx_timestamp + 1 ;
113+
end if ;
114+
end if ;
115+
end process ;
116+
117+
increment_rx_ts : process(rx_clock)
118+
variable ping : boolean := true ;
119+
begin
120+
if( rising_edge(rx_clock) ) then
121+
ping := not ping ;
122+
if( ping = true ) then
123+
rx_timestamp <= rx_timestamp + 1 ;
124+
end if ;
125+
end if ;
126+
end process ;
127+
95128
-- Clock creation
96129
fx3_clock <= not fx3_clock after FX3_HALF_PERIOD ;
97130
tx_clock <= not tx_clock after TX_HALF_PERIOD ;
@@ -118,6 +151,26 @@ begin
118151
wrusedw => txfifo.wrusedw
119152
) ;
120153

154+
-- TX Meta FIFO
155+
txmeta.rdclk <= tx_clock ;
156+
txmeta.wrclk <= fx3_clock ;
157+
U_tx_meta_fifo : entity work.tx_meta_fifo
158+
port map (
159+
aclr => txmeta.aclr,
160+
data => txmeta.data,
161+
rdclk => txmeta.rdclk,
162+
rdreq => txmeta.rdreq,
163+
wrclk => txmeta.wrclk,
164+
wrreq => txmeta.wrreq,
165+
q => txmeta.q,
166+
rdempty => txmeta.rdempty,
167+
rdfull => txmeta.rdfull,
168+
rdusedw => txmeta.rdusedw,
169+
wrempty => txmeta.wrempty,
170+
wrfull => txmeta.wrfull,
171+
wrusedw => txmeta.wrusedw
172+
) ;
173+
121174
-- RX FIFO
122175
rxfifo.rdclk <= fx3_clock ;
123176
rxfifo.wrclk <= rx_clock ;
@@ -138,17 +191,47 @@ begin
138191
wrusedw => rxfifo.wrusedw
139192
) ;
140193

194+
-- RX Meta FIFO
195+
rxmeta.rdclk <= fx3_clock ;
196+
rxmeta.wrclk <= rx_clock ;
197+
U_rx_meta_fifo : entity work.rx_meta_fifo
198+
port map (
199+
aclr => rxmeta.aclr,
200+
data => rxmeta.data,
201+
rdclk => rxmeta.rdclk,
202+
rdreq => rxmeta.rdreq,
203+
wrclk => rxmeta.wrclk,
204+
wrreq => rxmeta.wrreq,
205+
q => rxmeta.q,
206+
rdempty => rxmeta.rdempty,
207+
rdfull => rxmeta.rdfull,
208+
rdusedw => rxmeta.rdusedw,
209+
wrempty => rxmeta.wrempty,
210+
wrfull => rxmeta.wrfull,
211+
wrusedw => rxmeta.wrusedw
212+
) ;
213+
141214
-- TX FIFO Reader
142215
U_fifo_reader : entity work.fifo_reader
143216
port map (
144217
clock => tx_clock,
145218
reset => reset,
146219
enable => tx_enable,
147220

221+
usb_speed => usb_speed,
222+
meta_en => meta_en,
223+
timestamp => tx_timestamp,
224+
225+
fifo_usedw => txfifo.rdusedw,
148226
fifo_read => txfifo.rdreq,
149227
fifo_empty => txfifo.rdempty,
150228
fifo_data => txfifo.q,
151229

230+
meta_fifo_usedw => txmeta.rdusedw,
231+
meta_fifo_read => txmeta.rdreq,
232+
meta_fifo_empty => txmeta.rdempty,
233+
meta_fifo_data => txmeta.q,
234+
152235
out_i => tx_sample_i,
153236
out_q => tx_sample_q,
154237
out_valid => tx_sample_valid,
@@ -157,13 +240,18 @@ begin
157240
underflow_count => underflow_count,
158241
underflow_duration => underflow_duration
159242
) ;
243+
160244
-- RX FIFO Writer
161245
U_fifo_writer : entity work.fifo_writer
162246
port map (
163247
clock => rx_clock,
164248
reset => reset,
165249
enable => rx_enable,
166250

251+
usb_speed => usb_speed,
252+
meta_en => meta_en,
253+
timestamp => rx_timestamp,
254+
167255
in_i => rx_sample_i,
168256
in_q => rx_sample_q,
169257
in_valid => rx_sample_valid,
@@ -172,6 +260,12 @@ begin
172260
fifo_write => rxfifo.wrreq,
173261
fifo_full => rxfifo.wrfull,
174262
fifo_data => rxfifo.data,
263+
fifo_usedw => rxfifo.wrusedw,
264+
265+
meta_fifo_full => rxmeta.wrfull,
266+
meta_fifo_usedw => rxmeta.wrusedw,
267+
meta_fifo_data => rxmeta.data,
268+
meta_fifo_write => rxmeta.wrreq,
175269

176270
overflow_led => overflow_led,
177271
overflow_count => overflow_count,
@@ -243,27 +337,57 @@ begin
243337
variable dang : real := MATH_PI/100.0 ;
244338
variable sample_i : signed(15 downto 0) ;
245339
variable sample_q : signed(15 downto 0) ;
340+
variable ts : integer ;
246341
begin
247342
if( reset = '1' ) then
248343
txfifo.data <= (others =>'0') ;
249344
txfifo.wrreq <= '0' ;
250345
wait until reset = '0' ;
251346
end if ;
252-
while true loop
253-
wait until rising_edge(fx3_clock) and unsigned(txfifo.wrusedw) < 512 ;
254-
for i in 1 to 512 loop
255-
sample_i := to_signed(integer(2047.0*cos(ang)),sample_i'length);
256-
sample_q := to_signed(integer(2047.0*sin(ang)),sample_q'length);
257-
txfifo.data <= std_logic_vector(sample_q & sample_i) ;
258-
txfifo.wrreq <= '1' ;
259-
nop( fx3_clock, 1 );
260-
ang := (ang + dang) mod MATH_2_PI ;
347+
for i in 1 to 100 loop
348+
wait until rising_edge(fx3_clock) ;
349+
end loop ;
350+
for j in 1 to 5 loop
351+
ts := 16#1000# + (j-1)*10000 ;
352+
for i in 1 to 5 loop
353+
wait until rising_edge(fx3_clock) and unsigned(txfifo.wrusedw) < 512 ;
354+
txmeta.data <= (others =>'0') ;
355+
txmeta.data <= x"12345678" ;
356+
txmeta.wrreq <= '1' ;
357+
wait until rising_edge(fx3_clock) ;
358+
txmeta.data <= x"00000000" ;
359+
wait until rising_edge(fx3_clock) ;
360+
txmeta.data <= std_logic_vector(to_unsigned(ts,txmeta.data'length)) ;
361+
ts := ts + 508 ;
362+
wait until rising_edge(fx3_clock) ;
363+
txmeta.data <= x"00000000" ;
364+
wait until rising_edge(fx3_clock) ;
365+
txmeta.wrreq <= '0' ;
366+
txmeta.data <= (others =>'0') ;
367+
for r in 1 to 508 loop
368+
if( r = 1 or r = 508 ) then
369+
sample_i := (others =>'0') ;
370+
sample_q := (others =>'0') ;
371+
else
372+
sample_i := to_signed(2047, sample_i'length) ;
373+
sample_q := to_signed(2047, sample_q'length) ;
374+
end if ;
375+
--sample_i := to_signed(integer(2047.0*cos(ang)),sample_i'length);
376+
--sample_q := to_signed(integer(2047.0*sin(ang)),sample_q'length);
377+
txfifo.data <= std_logic_vector(sample_q & sample_i) after 0.1 ns ;
378+
txfifo.wrreq <= '1' after 0.1 ns ;
379+
nop( fx3_clock, 1 );
380+
txfifo.wrreq <= '0' after 0.1 ns ;
381+
ang := (ang + dang) mod MATH_2_PI ;
382+
end loop ;
383+
if( CHECK_UNDERFLOW ) then
384+
nop( fx3_clock, 3000 ) ;
385+
end if ;
386+
txfifo.data <= (others =>'X') after 0.1 ns ;
261387
end loop ;
262-
txfifo.wrreq <= '0' ;
263-
if( CHECK_UNDERFLOW ) then
264-
nop( fx3_clock, 3000 ) ;
265-
end if ;
388+
nop(fx3_clock, 100000) ;
266389
end loop ;
390+
wait ;
267391
end process ;
268392

269393
-- RX FIFO Reader
@@ -299,7 +423,7 @@ begin
299423
nop( fx3_clock, 10 ) ;
300424
rx_enable <= '1' ;
301425
tx_enable <= '1' ;
302-
nop( fx3_clock, 100000 ) ;
426+
nop( fx3_clock, 2000000 ) ;
303427
report "-- End of Simulation --" ;
304428
stop(2) ;
305429
wait ;

‎hdl/fpga/ip/nuand/synthesis/fifo_reader.vhd‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,6 @@ architecture simple of fifo_reader is
3939
signal meta_time_eq : std_logic ;
4040
signal meta_time_hit : signed(15 downto 0) ;
4141
signal meta_p_time : unsigned(63 downto 0);
42-
signal meta_p_sec : unsigned(31 downto 0);
4342
signal meta_loaded : std_logic;
4443

4544

@@ -74,9 +73,9 @@ begin
7473
elsif(rising_edge(clock)) then
7574
if (meta_time_eq = '1') then
7675
if (usb_speed = '0') then
77-
meta_time_hit <= to_signed(1014, meta_time_hit'length);
76+
meta_time_hit <= to_signed(1015, meta_time_hit'length);
7877
else
79-
meta_time_hit <= to_signed(502, meta_time_hit'length);
78+
meta_time_hit <= to_signed(503, meta_time_hit'length);
8079
end if;
8180
else
8281
if (meta_time_hit > 0) then
@@ -106,10 +105,6 @@ begin
106105
end if ;
107106
end process ;
108107

109-
-- Muxed values so empty reads come out as zeroes
110-
out_i <= resize(signed(fifo_data(11 downto 0)),out_i'length) when fifo_empty = '0' else (others =>'0') ;
111-
out_q <= resize(signed(fifo_data(27 downto 16)),out_q'length) when fifo_empty = '0' else (others =>'0') ;
112-
113108
register_out_valid : process(clock, reset)
114109
constant COUNT_RESET : natural := 11 ;
115110
variable prev_enable : std_logic := '0' ;
@@ -120,6 +115,13 @@ begin
120115
prev_enable := '0' ;
121116
downcount := COUNT_RESET ;
122117
elsif( rising_edge(clock) ) then
118+
if( fifo_empty = '1' ) then
119+
out_i <= (others =>'0') ;
120+
out_q <= (others =>'0') ;
121+
else
122+
out_i <= resize(signed(fifo_data(11 downto 0)),out_i'length) ;
123+
out_q <= resize(signed(fifo_data(27 downto 16)),out_q'length) ;
124+
end if ;
123125
if( enable = '1' ) then
124126
if( downcount > 0 ) then
125127
if( downcount mod 2 = 1 ) then

‎hdl/fpga/ip/nuand/synthesis/fifo_writer.vhd‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ begin
4949
process( clock, reset)
5050
begin
5151
if( reset = '1') then
52-
dma_downcount <= dma_buf_sz;
52+
dma_downcount <= (others =>'0') ;
5353
meta_written <= '0' ;
5454
elsif( rising_edge( clock ) ) then
5555
if (enable = '1' and meta_en = '1') then

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