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Commit 8593773

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author
Jon Szymaniak
committed
nios, lms, libbladeRF: Utilize FPGA support for atomic NINT/NFRAC write
Both the host and NIOS II FPGA retuning modes now make use of FPGA v0.4.0's atomic write of the LMS6002D NINT and NFRAC PLL registers. This helps avoid changing the PLL multiple times when attempting to configure it.
1 parent 612f323 commit 8593773

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5 files changed

+28
-6
lines changed

5 files changed

+28
-6
lines changed

fpga_common/src/lms.c

+16-4
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@
5151

5252
#ifndef BLADERF_NIOS_BUILD
5353
# include "bladerf_priv.h"
54+
# include "capabilities.h"
5455
# include "log.h"
5556
# include "rel_assert.h"
5657

@@ -2284,10 +2285,21 @@ int lms_set_precalculated_frequency(struct bladerf *dev, bladerf_module mod,
22842285
{
22852286
/* Select the base address based on which PLL we are configuring */
22862287
const uint8_t base = (mod == BLADERF_MODULE_RX) ? 0x20 : 0x10;
2288+
22872289
uint8_t data;
22882290
uint8_t vcocap_reg_state;
22892291
int status, dsm_status;
22902292

2293+
/* Utilize atomic writes to the PLL registers, if possible. This
2294+
* "multiwrite" is indicated by the MSB being set. */
2295+
# ifdef BLADERF_NIOS_BUILD
2296+
const uint8_t pll_base = base | 0x80;
2297+
# else
2298+
const uint8_t pll_base =
2299+
have_cap(dev, BLADERF_CAP_ATOMIC_NINT_NFRAC_WRITE) ?
2300+
(base | 0x80) : base;
2301+
# endif
2302+
22912303
f->vcocap_result = 0xff;
22922304

22932305
/* Turn on the DSMs */
@@ -2324,25 +2336,25 @@ int lms_set_precalculated_frequency(struct bladerf *dev, bladerf_module mod,
23242336
}
23252337

23262338
data = f->nint >> 1;
2327-
status = LMS_WRITE(dev, base + 0, data);
2339+
status = LMS_WRITE(dev, pll_base + 0, data);
23282340
if (status != 0) {
23292341
goto error;
23302342
}
23312343

23322344
data = ((f->nint & 1) << 7) | ((f->nfrac >> 16) & 0x7f);
2333-
status = LMS_WRITE(dev, base + 1, data);
2345+
status = LMS_WRITE(dev, pll_base + 1, data);
23342346
if (status != 0) {
23352347
goto error;
23362348
}
23372349

23382350
data = ((f->nfrac >> 8) & 0xff);
2339-
status = LMS_WRITE(dev, base + 2, data);
2351+
status = LMS_WRITE(dev, pll_base + 2, data);
23402352
if (status != 0) {
23412353
goto error;
23422354
}
23432355

23442356
data = (f->nfrac & 0xff);
2345-
status = LMS_WRITE(dev, base + 3, data);
2357+
status = LMS_WRITE(dev, pll_base + 3, data);
23462358
if (status != 0) {
23472359
goto error;
23482360
}

hdl/fpga/ip/altera/nios_system/software/bladeRF_nios/src/fpga_version.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77

88
#define FPGA_VERSION_ID 0x7777
99
#define FPGA_VERSION_MAJOR 0
10-
#define FPGA_VERSION_MINOR 3
11-
#define FPGA_VERSION_PATCH 5
10+
#define FPGA_VERSION_MINOR 4
11+
#define FPGA_VERSION_PATCH 0
1212
#define FPGA_VERSION ((uint32_t)( FPGA_VERSION_MAJOR | \
1313
(FPGA_VERSION_MINOR << 8) | \
1414
(FPGA_VERSION_PATCH << 16) ) )

host/libraries/libbladeRF/src/capabilities.c

+4
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,10 @@ void capabilities_init_post_fpga_load(struct bladerf *dev)
6868
dev->capabilities |= BLADERF_CAP_VCTCXO_TRIMDAC_READ;
6969
}
7070

71+
if (version_greater_or_equal(&dev->fpga_version, 0, 4, 0)) {
72+
dev->capabilities |= BLADERF_CAP_ATOMIC_NINT_NFRAC_WRITE;
73+
}
74+
7175
log_verbose("Capability mask after FPGA load: 0x%016"PRIx64"\n",
7276
dev->capabilities);
7377
}

host/libraries/libbladeRF/src/capabilities.h

+5
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,11 @@
7373
*/
7474
#define BLADERF_CAP_VCTCXO_TRIMDAC_READ (1 << 5)
7575

76+
/**
77+
* FPGA v0.4.0 introduced the ability to write LMS6002D TX/RX PLL
78+
* NINT & NFRAC regiters atomically.
79+
*/
80+
#define BLADERF_CAP_ATOMIC_NINT_NFRAC_WRITE (1 << 6)
7681

7782
/**
7883
* Firmware 1.7.1 introduced firmware-based loopback

host/libraries/libbladeRF/src/version_compat.c

+1
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ static const struct compat fw_compat_tbl[] = {
4949

5050
static const struct compat fpga_compat_tbl[] = {
5151
/* FPGA requires >= Firmware */
52+
{ VERSION(0, 4, 0), VERSION(1, 6, 1) },
5253
{ VERSION(0, 3, 5), VERSION(1, 6, 1) },
5354
{ VERSION(0, 3, 4), VERSION(1, 6, 1) },
5455
{ VERSION(0, 3, 3), VERSION(1, 6, 1) },

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