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nios, lms, libbladeRF: Utilize FPGA support for atomic NINT/NFRAC write

Both the host and NIOS II FPGA retuning modes now make use of
FPGA v0.4.0's atomic write of the LMS6002D NINT and NFRAC PLL registers.

This helps avoid changing the PLL multiple times when attempting to
configure it.
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Jon Szymaniak
Jon Szymaniak committed Aug 25, 2015
1 parent 612f323 commit 859377326bd5cbf0f4f821aade1438cc57e1b7d3
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@@ -51,6 +51,7 @@
#ifndef BLADERF_NIOS_BUILD
# include "bladerf_priv.h"
# include "capabilities.h"
# include "log.h"
# include "rel_assert.h"
@@ -2284,10 +2285,21 @@ int lms_set_precalculated_frequency(struct bladerf *dev, bladerf_module mod,
{
/* Select the base address based on which PLL we are configuring */
const uint8_t base = (mod == BLADERF_MODULE_RX) ? 0x20 : 0x10;
uint8_t data;
uint8_t vcocap_reg_state;
int status, dsm_status;
/* Utilize atomic writes to the PLL registers, if possible. This
* "multiwrite" is indicated by the MSB being set. */
# ifdef BLADERF_NIOS_BUILD
const uint8_t pll_base = base | 0x80;
# else
const uint8_t pll_base =
have_cap(dev, BLADERF_CAP_ATOMIC_NINT_NFRAC_WRITE) ?
(base | 0x80) : base;
# endif
f->vcocap_result = 0xff;
/* Turn on the DSMs */
@@ -2324,25 +2336,25 @@ int lms_set_precalculated_frequency(struct bladerf *dev, bladerf_module mod,
}
data = f->nint >> 1;
status = LMS_WRITE(dev, base + 0, data);
status = LMS_WRITE(dev, pll_base + 0, data);
if (status != 0) {
goto error;
}
data = ((f->nint & 1) << 7) | ((f->nfrac >> 16) & 0x7f);
status = LMS_WRITE(dev, base + 1, data);
status = LMS_WRITE(dev, pll_base + 1, data);
if (status != 0) {
goto error;
}
data = ((f->nfrac >> 8) & 0xff);
status = LMS_WRITE(dev, base + 2, data);
status = LMS_WRITE(dev, pll_base + 2, data);
if (status != 0) {
goto error;
}
data = (f->nfrac & 0xff);
status = LMS_WRITE(dev, base + 3, data);
status = LMS_WRITE(dev, pll_base + 3, data);
if (status != 0) {
goto error;
}
@@ -7,8 +7,8 @@
#define FPGA_VERSION_ID 0x7777
#define FPGA_VERSION_MAJOR 0
#define FPGA_VERSION_MINOR 3
#define FPGA_VERSION_PATCH 5
#define FPGA_VERSION_MINOR 4
#define FPGA_VERSION_PATCH 0
#define FPGA_VERSION ((uint32_t)( FPGA_VERSION_MAJOR | \
(FPGA_VERSION_MINOR << 8) | \
(FPGA_VERSION_PATCH << 16) ) )
@@ -68,6 +68,10 @@ void capabilities_init_post_fpga_load(struct bladerf *dev)
dev->capabilities |= BLADERF_CAP_VCTCXO_TRIMDAC_READ;
}
if (version_greater_or_equal(&dev->fpga_version, 0, 4, 0)) {
dev->capabilities |= BLADERF_CAP_ATOMIC_NINT_NFRAC_WRITE;
}
log_verbose("Capability mask after FPGA load: 0x%016"PRIx64"\n",
dev->capabilities);
}
@@ -73,6 +73,11 @@
*/
#define BLADERF_CAP_VCTCXO_TRIMDAC_READ (1 << 5)
/**
* FPGA v0.4.0 introduced the ability to write LMS6002D TX/RX PLL
* NINT & NFRAC regiters atomically.
*/
#define BLADERF_CAP_ATOMIC_NINT_NFRAC_WRITE (1 << 6)
/**
* Firmware 1.7.1 introduced firmware-based loopback
@@ -49,6 +49,7 @@ static const struct compat fw_compat_tbl[] = {
static const struct compat fpga_compat_tbl[] = {
/* FPGA requires >= Firmware */
{ VERSION(0, 4, 0), VERSION(1, 6, 1) },
{ VERSION(0, 3, 5), VERSION(1, 6, 1) },
{ VERSION(0, 3, 4), VERSION(1, 6, 1) },
{ VERSION(0, 3, 3), VERSION(1, 6, 1) },

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