hdl: Updated FPGA version to v0.3.2

Patch version bumped due to bug fix.

Author: jynik

hdl/CHANGELOG

@@ -5,6 +5,12 @@ For more detailed information, please see the git change log and issue tracker
 hosted on GitHub: https://github.com/nuand/bladeRF
 ================================================================================
 
+--------------------------------
+v0.3.2 (2015-06-23)
+--------------------------------
+ * Fixed VCTCXO readback
+
+--------------------------------
 v0.3.1 (2015-06-17)
 --------------------------------
  * Added faster, custom SPI block for LMS6 communication.

hdl/fpga/ip/altera/nios_system/software/bladeRF_nios/src/fpga_version.h

@@ -8,7 +8,7 @@
 #define FPGA_VERSION_ID         0x7777
 #define FPGA_VERSION_MAJOR      0
 #define FPGA_VERSION_MINOR      3
-#define FPGA_VERSION_PATCH      1
+#define FPGA_VERSION_PATCH      2
 #define FPGA_VERSION ((uint32_t)( FPGA_VERSION_MAJOR        | \
                                  (FPGA_VERSION_MINOR << 8)  | \
                                  (FPGA_VERSION_PATCH << 16) ) )