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hdl: Updated FPGA version to v0.3.2
Patch version bumped due to bug fix.
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hdl/CHANGELOG

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@@ -5,6 +5,12 @@ For more detailed information, please see the git change log and issue tracker
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hosted on GitHub: https://github.com/nuand/bladeRF
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================================================================================
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v0.3.2 (2015-06-23)
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--------------------------------
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* Fixed VCTCXO readback
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v0.3.1 (2015-06-17)
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* Added faster, custom SPI block for LMS6 communication.

hdl/fpga/ip/altera/nios_system/software/bladeRF_nios/src/fpga_version.h

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#define FPGA_VERSION_ID 0x7777
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#define FPGA_VERSION_MAJOR 0
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#define FPGA_VERSION_MINOR 3
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#define FPGA_VERSION_PATCH 1
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#define FPGA_VERSION_PATCH 2
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#define FPGA_VERSION ((uint32_t)( FPGA_VERSION_MAJOR | \
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(FPGA_VERSION_MINOR << 8) | \
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(FPGA_VERSION_PATCH << 16) ) )

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