hdl: Updating LMS SPI component.

Changing the LMS SPI component to have a clock phase/polarity of [0,0] instead of [1,1], modifying the SDC to constrain the interface which was done by mistake and caused timing errors and missed bits. Also increasing the SCLK frequency to 40MHz.
Nuand · Oct 22, 2014 · 9c0bbfe · 9c0bbfe
1 parent 97a44f9
commit 9c0bbfe
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Showing 2 changed files with 25 additions and 25 deletions.
diff --git a/hdl/fpga/ip/altera/nios_system/nios_system.qsys b/hdl/fpga/ip/altera/nios_system/nios_system.qsys
@@ -124,19 +124,19 @@
          type = "int";
       }
    }
-   element timer_0.s1
+   element pio_0.s1
    {
       datum baseAddress
       {
-         value = "36864";
+         value = "36928";
          type = "String";
       }
    }
-   element iq_corr_tx_phase_gain.s1
+   element pio_1.s1
    {
       datum baseAddress
       {
-         value = "37088";
+         value = "37072";
          type = "String";
       }
    }
@@ -148,43 +148,43 @@
          type = "String";
       }
    }
-   element iq_corr_rx_phase_gain.s1
+   element iq_corr_tx_phase_gain.s1
    {
       datum baseAddress
       {
-         value = "37104";
+         value = "37088";
          type = "String";
       }
    }
-   element pio_0.s1
+   element iq_corr_rx_phase_gain.s1
    {
       datum baseAddress
       {
-         value = "36928";
+         value = "37104";
          type = "String";
       }
    }
-   element pio_1.s1
+   element pio_2.s1
    {
       datum baseAddress
       {
-         value = "37072";
+         value = "37056";
          type = "String";
       }
    }
-   element pio_2.s1
+   element onchip_memory2_0.s1
    {
       datum baseAddress
       {
-         value = "37056";
+         value = "16384";
          type = "String";
       }
    }
-   element onchip_memory2_0.s1
+   element timer_0.s1
    {
       datum baseAddress
       {
-         value = "16384";
+         value = "36864";
          type = "String";
       }
    }
@@ -204,19 +204,19 @@
          type = "int";
       }
    }
-   element spi_0.spi_control_port
+   element spi_1.spi_control_port
    {
       datum baseAddress
       {
-         value = "37024";
+         value = "36960";
          type = "String";
       }
    }
-   element spi_1.spi_control_port
+   element spi_0.spi_control_port
    {
       datum baseAddress
       {
-         value = "36960";
+         value = "37024";
          type = "String";
       }
    }
@@ -443,8 +443,8 @@
   <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
  </module>
  <module kind="altera_avalon_spi" version="13.1" enabled="1" name="spi_0">
-  <parameter name="clockPhase" value="1" />
-  <parameter name="clockPolarity" value="1" />
+  <parameter name="clockPhase" value="0" />
+  <parameter name="clockPolarity" value="0" />
   <parameter name="dataWidth" value="8" />
   <parameter name="disableAvalonFlowControl" value="false" />
   <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
@@ -453,8 +453,8 @@
   <parameter name="masterSPI" value="true" />
   <parameter name="numberOfSlaves" value="1" />
   <parameter name="syncRegDepth" value="2" />
-  <parameter name="targetClockRate" value="20000000" />
-  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
+  <parameter name="targetClockRate" value="40000000" />
+  <parameter name="targetSlaveSelectToSClkDelay" value="2.0" />
   <parameter name="avalonSpec" value="2.0" />
   <parameter name="inputClockRate" value="80000000" />
  </module>

diff --git a/hdl/fpga/platforms/bladerf/constraints/bladerf.sdc b/hdl/fpga/platforms/bladerf/constraints/bladerf.sdc
@@ -52,11 +52,11 @@ set_input_delay -clock [get_clocks {U_pll|altpll_component|auto_generated|pll1|c
 set_input_delay -clock [get_clocks {U_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.0 [get_ports {fx3_uart_txd}] -add_delay
 
 # LMS SPI interface
-set_input_delay  -clock [get_clocks U_pll*0*] -min  1.0 [get_ports lms_sdo]
-set_input_delay  -clock [get_clocks U_pll*0*] -max  1.0 [get_ports lms_sdo] -add_delay
+set_input_delay  -clock [get_clocks U_pll*0*] -min  1.0 [get_ports {lms_sdo}]
+set_input_delay  -clock [get_clocks U_pll*0*] -max  9.0 [get_ports {lms_sdo}] -add_delay
 
 set_output_delay -clock [get_clocks U_pll*0*] -min  1.0 [get_ports {lms_sen lms_sdio lms_sclk}]
-set_output_delay -clock [get_clocks U_pll*0*] -max  1.0 [get_ports {lms_sen lms_sdio lms_sclk}] -add_delay
+set_output_delay -clock [get_clocks U_pll*0*] -max  4.0 [get_ports {lms_sen lms_sdio lms_sclk}] -add_delay
 
 # Si5338 interface
 set_input_delay -clock [get_clocks U_pll*0*] -min  1.0 [get_ports {si_scl si_sda}]