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bpadalinojynik
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hdl: Updating LMS SPI component.
Changing the LMS SPI component to have a clock phase/polarity of [0,0] instead of [1,1], modifying the SDC to constrain the interface which was done by mistake and caused timing errors and missed bits. Also increasing the SCLK frequency to 40MHz.
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+25
-25
lines changed

2 files changed

+25
-25
lines changed

hdl/fpga/ip/altera/nios_system/nios_system.qsys

+22-22
Original file line numberDiff line numberDiff line change
@@ -124,19 +124,19 @@
124124
type = "int";
125125
}
126126
}
127-
element timer_0.s1
127+
element pio_0.s1
128128
{
129129
datum baseAddress
130130
{
131-
value = "36864";
131+
value = "36928";
132132
type = "String";
133133
}
134134
}
135-
element iq_corr_tx_phase_gain.s1
135+
element pio_1.s1
136136
{
137137
datum baseAddress
138138
{
139-
value = "37088";
139+
value = "37072";
140140
type = "String";
141141
}
142142
}
@@ -148,43 +148,43 @@
148148
type = "String";
149149
}
150150
}
151-
element iq_corr_rx_phase_gain.s1
151+
element iq_corr_tx_phase_gain.s1
152152
{
153153
datum baseAddress
154154
{
155-
value = "37104";
155+
value = "37088";
156156
type = "String";
157157
}
158158
}
159-
element pio_0.s1
159+
element iq_corr_rx_phase_gain.s1
160160
{
161161
datum baseAddress
162162
{
163-
value = "36928";
163+
value = "37104";
164164
type = "String";
165165
}
166166
}
167-
element pio_1.s1
167+
element pio_2.s1
168168
{
169169
datum baseAddress
170170
{
171-
value = "37072";
171+
value = "37056";
172172
type = "String";
173173
}
174174
}
175-
element pio_2.s1
175+
element onchip_memory2_0.s1
176176
{
177177
datum baseAddress
178178
{
179-
value = "37056";
179+
value = "16384";
180180
type = "String";
181181
}
182182
}
183-
element onchip_memory2_0.s1
183+
element timer_0.s1
184184
{
185185
datum baseAddress
186186
{
187-
value = "16384";
187+
value = "36864";
188188
type = "String";
189189
}
190190
}
@@ -204,19 +204,19 @@
204204
type = "int";
205205
}
206206
}
207-
element spi_0.spi_control_port
207+
element spi_1.spi_control_port
208208
{
209209
datum baseAddress
210210
{
211-
value = "37024";
211+
value = "36960";
212212
type = "String";
213213
}
214214
}
215-
element spi_1.spi_control_port
215+
element spi_0.spi_control_port
216216
{
217217
datum baseAddress
218218
{
219-
value = "36960";
219+
value = "37024";
220220
type = "String";
221221
}
222222
}
@@ -443,8 +443,8 @@
443443
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
444444
</module>
445445
<module kind="altera_avalon_spi" version="13.1" enabled="1" name="spi_0">
446-
<parameter name="clockPhase" value="1" />
447-
<parameter name="clockPolarity" value="1" />
446+
<parameter name="clockPhase" value="0" />
447+
<parameter name="clockPolarity" value="0" />
448448
<parameter name="dataWidth" value="8" />
449449
<parameter name="disableAvalonFlowControl" value="false" />
450450
<parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
@@ -453,8 +453,8 @@
453453
<parameter name="masterSPI" value="true" />
454454
<parameter name="numberOfSlaves" value="1" />
455455
<parameter name="syncRegDepth" value="2" />
456-
<parameter name="targetClockRate" value="20000000" />
457-
<parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
456+
<parameter name="targetClockRate" value="40000000" />
457+
<parameter name="targetSlaveSelectToSClkDelay" value="2.0" />
458458
<parameter name="avalonSpec" value="2.0" />
459459
<parameter name="inputClockRate" value="80000000" />
460460
</module>

hdl/fpga/platforms/bladerf/constraints/bladerf.sdc

+3-3
Original file line numberDiff line numberDiff line change
@@ -52,11 +52,11 @@ set_input_delay -clock [get_clocks {U_pll|altpll_component|auto_generated|pll1|c
5252
set_input_delay -clock [get_clocks {U_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.0 [get_ports {fx3_uart_txd}] -add_delay
5353

5454
# LMS SPI interface
55-
set_input_delay -clock [get_clocks U_pll*0*] -min 1.0 [get_ports lms_sdo]
56-
set_input_delay -clock [get_clocks U_pll*0*] -max 1.0 [get_ports lms_sdo] -add_delay
55+
set_input_delay -clock [get_clocks U_pll*0*] -min 1.0 [get_ports {lms_sdo}]
56+
set_input_delay -clock [get_clocks U_pll*0*] -max 9.0 [get_ports {lms_sdo}] -add_delay
5757

5858
set_output_delay -clock [get_clocks U_pll*0*] -min 1.0 [get_ports {lms_sen lms_sdio lms_sclk}]
59-
set_output_delay -clock [get_clocks U_pll*0*] -max 1.0 [get_ports {lms_sen lms_sdio lms_sclk}] -add_delay
59+
set_output_delay -clock [get_clocks U_pll*0*] -max 4.0 [get_ports {lms_sen lms_sdio lms_sclk}] -add_delay
6060

6161
# Si5338 interface
6262
set_input_delay -clock [get_clocks U_pll*0*] -min 1.0 [get_ports {si_scl si_sda}]

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