hdl, nios: Bumped FPGA version to v0.5.0

Updated minor revision to denote added functionality and host <-> FPGA
interface additions (e.g., an 8x8 packet ID) for VCTCXO tamer.

Author: jynik

hdl/CHANGELOG

@@ -5,6 +5,13 @@ For more detailed information, please see the git change log and issue tracker
 hosted on GitHub: https://github.com/nuand/bladeRF
 ================================================================================
 
+--------------------------------
+v0.5.0 (2015-11-23)
+--------------------------------
+ * Added support for 1 PPS and 10 MHz input to tame VCTCXO
+ * Added FIFO between TX and RX for digital loopback mode for clock
+   synchronization and additional sample buffering.
+
 --------------------------------
 v0.4.1 (2015-09-01)
 --------------------------------

hdl/fpga/ip/altera/nios_system/software/bladeRF_nios/src/fpga_version.h

@@ -7,8 +7,8 @@
 
 #define FPGA_VERSION_ID         0x7777
 #define FPGA_VERSION_MAJOR      0
-#define FPGA_VERSION_MINOR      4
-#define FPGA_VERSION_PATCH      2
+#define FPGA_VERSION_MINOR      5
+#define FPGA_VERSION_PATCH      0
 #define FPGA_VERSION ((uint32_t)( FPGA_VERSION_MAJOR        | \
                                  (FPGA_VERSION_MINOR << 8)  | \
                                  (FPGA_VERSION_PATCH << 16) ) )