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hdl, nios: Bumped FPGA version to v0.5.0

Updated minor revision to denote added functionality and host <-> FPGA
interface additions (e.g., an 8x8 packet ID) for VCTCXO tamer.
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jynik authored and Jon Szymaniak committed Nov 24, 2015
1 parent 8fba7b0 commit 9f72b2e98cb9b86aaaa3c7613e92cc08e30221ca
Showing with 9 additions and 2 deletions.
  1. +7 −0 hdl/CHANGELOG
  2. +2 −2 hdl/fpga/ip/altera/nios_system/software/bladeRF_nios/src/fpga_version.h
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@@ -5,6 +5,13 @@ For more detailed information, please see the git change log and issue tracker
hosted on GitHub: https://github.com/nuand/bladeRF
================================================================================
--------------------------------
v0.5.0 (2015-11-23)
--------------------------------
* Added support for 1 PPS and 10 MHz input to tame VCTCXO
* Added FIFO between TX and RX for digital loopback mode for clock
synchronization and additional sample buffering.
--------------------------------
v0.4.1 (2015-09-01)
--------------------------------
@@ -7,8 +7,8 @@
#define FPGA_VERSION_ID 0x7777
#define FPGA_VERSION_MAJOR 0
#define FPGA_VERSION_MINOR 4
#define FPGA_VERSION_PATCH 2
#define FPGA_VERSION_MINOR 5
#define FPGA_VERSION_PATCH 0
#define FPGA_VERSION ((uint32_t)( FPGA_VERSION_MAJOR | \
(FPGA_VERSION_MINOR << 8) | \
(FPGA_VERSION_PATCH << 16) ) )

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