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hdl: Modified constraints of GPIF drive strength.
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+5
-1
lines changed

2 files changed

+5
-1
lines changed

hdl/fpga/platforms/bladerf/constraints/bladerf.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ set_input_delay -clock [get_clocks fx3_virtual] -max 8.0 [get_ports {fx3_gpif* f
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set_input_delay -clock [get_clocks fx3_virtual] -min 0.5 [get_ports {fx3_gpif* fx3_ctl*}] -add_delay
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set_output_delay -clock [get_clocks fx3_virtual] -max 2.0 [get_ports {fx3_gpif* fx3_ctl*}]
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set_output_delay -clock [get_clocks fx3_virtual] -min 1.5 [get_ports {fx3_gpif* fx3_ctl*}] -add_delay
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set_output_delay -clock [get_clocks fx3_virtual] -min -0.5 [get_ports {fx3_gpif* fx3_ctl*}] -add_delay
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# LMS sample interface
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set_input_delay -clock [get_clocks lms_rx_virtual] -max 6.0 [get_ports {lms_rx_data* lms_rx_iq_select}]

hdl/fpga/platforms/bladerf/constraints/pins.tcl

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -306,3 +306,7 @@ set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE AS RE
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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# Drive Strength and Slew Rate
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set_instance_assignment -name SLEW_RATE 2 -to fx3_gpif[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to fx3_gpif[*]
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