hdl: Modified constraints of GPIF drive strength.

Nuand · Feb 1, 2014 · bc88a82090fc90397b34a71a446eae2a3e259f04 · bc88a82
1 parent a827282
commit bc88a82090fc90397b34a71a446eae2a3e259f04
Unified Split

Showing with 5 additions and 1 deletion.

+1 −1 hdl/fpga/platforms/bladerf/constraints/bladerf.sdc

+4 −0 hdl/fpga/platforms/bladerf/constraints/pins.tcl
diff --git a/hdl/fpga/platforms/bladerf/constraints/bladerf.sdc b/hdl/fpga/platforms/bladerf/constraints/bladerf.sdc
@@ -26,7 +26,7 @@ set_input_delay -clock [get_clocks fx3_virtual] -max 8.0 [get_ports {fx3_gpif* f
 set_input_delay -clock [get_clocks fx3_virtual] -min 0.5 [get_ports {fx3_gpif* fx3_ctl*}] -add_delay
 
 set_output_delay -clock [get_clocks fx3_virtual] -max 2.0 [get_ports {fx3_gpif* fx3_ctl*}]
-set_output_delay -clock [get_clocks fx3_virtual] -min 1.5 [get_ports {fx3_gpif* fx3_ctl*}] -add_delay
+set_output_delay -clock [get_clocks fx3_virtual] -min -0.5 [get_ports {fx3_gpif* fx3_ctl*}] -add_delay
 
 # LMS sample interface
 set_input_delay -clock [get_clocks lms_rx_virtual] -max  6.0 [get_ports {lms_rx_data* lms_rx_iq_select}]

diff --git a/hdl/fpga/platforms/bladerf/constraints/pins.tcl b/hdl/fpga/platforms/bladerf/constraints/pins.tcl
@@ -306,3 +306,7 @@ set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE AS RE
 set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 
+# Drive Strength and Slew Rate
+set_instance_assignment -name SLEW_RATE 2 -to fx3_gpif[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to fx3_gpif[*]
+