hdl: Bumped FPGA version to v0.1.2

Author: jynik

hdl/CHANGELOG

@@ -5,6 +5,11 @@ For more detailed information, please see the git change log and issue tracker
 hosted on GitHub: https://github.com/nuand/bladeRF
 ================================================================================
 
+v0.1.2 (2014-10-22)
+--------------------------------
+ * Fixed issues with TX_NOW and dropped messages. This fixes issues
+   #334 and #335.
+
 v0.1.1 (2014-10-22)
 --------------------------------
  * Fixed timing errors that caused failures in SPI communication with the

hdl/fpga/ip/altera/nios_system/software/lms_spi_controller/lms_spi_controller.c

@@ -47,7 +47,7 @@
 #define FPGA_VERSION_ID         0x7777
 #define FPGA_VERSION_MAJOR      0
 #define FPGA_VERSION_MINOR      1
-#define FPGA_VERSION_PATCH      1
+#define FPGA_VERSION_PATCH      2
 #define FPGA_VERSION            (FPGA_VERSION_MAJOR | (FPGA_VERSION_MINOR << 8) | (FPGA_VERSION_PATCH << 16))
 
 #define TIME_TAMER              TIME_TAMER_0_BASE

host/libraries/libbladeRF/src/version_compat.c

@@ -49,6 +49,7 @@ static const struct compat fw_compat_tbl[] = {
 
 static const struct compat fpga_compat_tbl[] = {
     /*    FPGA          requires >=        Firmware */
+    { VERSION(0, 1, 2),                 VERSION(1, 6, 1) },
     { VERSION(0, 1, 1),                 VERSION(1, 6, 1) },
     { VERSION(0, 1, 0),                 VERSION(1, 6, 1) },
     { VERSION(0, 0, 6),                 VERSION(1, 6, 1) },