From 9be27ce536aad179aca363f22451144d26a16a0c Mon Sep 17 00:00:00 2001 From: Levent Karakaya Date: Wed, 3 Apr 2024 18:36:47 +0300 Subject: [PATCH] eth over pcie for ep --- drivers/pci/controller/dwc/pcie-tegra194.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 0b810fff0425..81147dfc82fc 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2235,7 +2235,9 @@ static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp) val |= APPL_INTR_EN_L1_8_INTX_EN; val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN; val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN; + #if 0 val |= APPL_INTR_EN_L1_8_EDMA_INT_EN; + #endif if (IS_ENABLED(CONFIG_PCIEAER)) val |= APPL_INTR_EN_L1_8_AER_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); @@ -3624,11 +3626,11 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val |= APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN; val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); - +#if 0 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0); val |= APPL_INTR_EN_L1_8_EDMA_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); - +#endif if (pcie->enable_cdm_check) { val = appl_readl(pcie, APPL_INTR_EN_L0_0); val |= pcie->of_data->cdm_chk_int_en; @@ -3935,7 +3937,7 @@ tegra_pcie_ep_get_features(struct dw_pcie_ep *ep) { return &tegra_pcie_epc_features; } - +#if 0 /* Reserve BAR0_BASE + BAR0_MSI_OFFSET of size SZ_64K as MSI page */ static int tegra_pcie_ep_set_bar(struct dw_pcie_ep *ep, u8 func_no, struct pci_epf_bar *epf_bar) @@ -3959,11 +3961,10 @@ static int tegra_pcie_ep_set_bar(struct dw_pcie_ep *ep, u8 func_no, return 0; } - +#endif static struct dw_pcie_ep_ops pcie_ep_ops = { .raise_irq = tegra_pcie_ep_raise_irq, .get_features = tegra_pcie_ep_get_features, - .set_bar = tegra_pcie_ep_set_bar, }; static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie, -- 2.25.1