From ef247b854a348bcc5707ac2c5085138380083d83 Mon Sep 17 00:00:00 2001 From: MICHELE GAZZETTI Date: Sun, 3 Sep 2023 18:23:02 +0100 Subject: [PATCH] add cxl redfish tree mockup Signed-off-by: MICHELE GAZZETTI --- .../ConnectionMethods/CXL/index.json | 11 ++++ .../ConnectionMethods/index.json | 12 ++++ .../CXLAgent/AggregationService/index.json | 14 +++++ .../CXLAgent/Chassis/CXL-Chassis/index.json | 33 ++++++++++ .../1/CXLLogicalDevices/1/index.json | 35 +++++++++++ .../1/CXLLogicalDevices/index.json | 12 ++++ .../PCIeDevices/1/PCIeFunctions/1/index.json | 37 +++++++++++ .../PCIeDevices/1/PCIeFunctions/index.json | 12 ++++ .../Chassis/CXL1/PCIeDevices/1/index.json | 40 ++++++++++++ .../Chassis/CXL1/PCIeDevices/index.json | 12 ++++ .../Chassis/CXL1/Processors/FPGA/index.json | 37 +++++++++++ .../Chassis/CXL1/Processors/index.json | 12 ++++ Resources/CXLAgent/Chassis/CXL1/index.json | 25 ++++++++ .../Chassis/CXL2/Memory/HBM/index.json | 27 ++++++++ .../CXLAgent/Chassis/CXL2/Memory/index.json | 13 ++++ .../MemoryDomains/1/MemoryChunks/1/index.json | 25 ++++++++ .../MemoryDomains/1/MemoryChunks/index.json | 12 ++++ .../Chassis/CXL2/MemoryDomains/1/index.json | 36 +++++++++++ .../Chassis/CXL2/MemoryDomains/index.json | 12 ++++ .../1/CXLLogicalDevices/1/index.json | 46 ++++++++++++++ .../1/CXLLogicalDevices/index.json | 12 ++++ .../PCIeDevices/1/PCIeFunctions/1/index.json | 37 +++++++++++ .../PCIeDevices/1/PCIeFunctions/index.json | 12 ++++ .../Chassis/CXL2/PCIeDevices/1/index.json | 40 ++++++++++++ .../Chassis/CXL2/PCIeDevices/index.json | 12 ++++ .../Chassis/CXL2/Processors/GPU/index.json | 48 +++++++++++++++ .../Chassis/CXL2/Processors/index.json | 12 ++++ Resources/CXLAgent/Chassis/CXL2/index.json | 32 ++++++++++ .../Chassis/CXL3/Memory/3DXP/index.json | 19 ++++++ .../CXLAgent/Chassis/CXL3/Memory/index.json | 13 ++++ .../MemoryDomains/1/MemoryChunks/1/index.json | 25 ++++++++ .../MemoryDomains/1/MemoryChunks/index.json | 12 ++++ .../Chassis/CXL3/MemoryDomains/1/index.json | 41 +++++++++++++ .../Chassis/CXL3/MemoryDomains/index.json | 12 ++++ .../1/CXLLogicalDevices/1/index.json | 45 ++++++++++++++ .../1/CXLLogicalDevices/index.json | 12 ++++ .../PCIeDevices/1/PCIeFunctions/1/index.json | 37 +++++++++++ .../PCIeDevices/1/PCIeFunctions/index.json | 12 ++++ .../Chassis/CXL3/PCIeDevices/1/index.json | 40 ++++++++++++ .../Chassis/CXL3/PCIeDevices/index.json | 12 ++++ Resources/CXLAgent/Chassis/CXL3/index.json | 29 +++++++++ .../PCXL1/FabricAdapters/1/Ports/1/index.json | 48 +++++++++++++++ .../PCXL1/FabricAdapters/1/Ports/index.json | 12 ++++ .../Chassis/PCXL1/FabricAdapters/1/index.json | 31 ++++++++++ .../Chassis/PCXL1/FabricAdapters/index.json | 12 ++++ .../1/CXLLogicalDevices/1/index.json | 40 ++++++++++++ .../1/CXLLogicalDevices/index.json | 12 ++++ .../PCIeDevices/1/PCIeFunctions/1/index.json | 37 +++++++++++ .../PCIeDevices/1/PCIeFunctions/index.json | 12 ++++ .../Chassis/PCXL1/PCIeDevices/1/index.json | 40 ++++++++++++ .../Chassis/PCXL1/PCIeDevices/index.json | 12 ++++ .../Chassis/PCXL1/Processors/FPGA/index.json | 42 +++++++++++++ .../Chassis/PCXL1/Processors/index.json | 12 ++++ Resources/CXLAgent/Chassis/PCXL1/index.json | 23 +++++++ .../PCXL2/FabricAdapters/1/Ports/1/index.json | 48 +++++++++++++++ .../PCXL2/FabricAdapters/1/Ports/index.json | 12 ++++ .../Chassis/PCXL2/FabricAdapters/1/index.json | 36 +++++++++++ .../Chassis/PCXL2/FabricAdapters/index.json | 12 ++++ .../Chassis/PCXL2/Memory/HBM/index.json | 27 ++++++++ .../CXLAgent/Chassis/PCXL2/Memory/index.json | 13 ++++ .../MemoryDomains/1/MemoryChunks/1/index.json | 30 +++++++++ .../MemoryDomains/1/MemoryChunks/index.json | 12 ++++ .../Chassis/PCXL2/MemoryDomains/1/index.json | 41 +++++++++++++ .../Chassis/PCXL2/MemoryDomains/index.json | 12 ++++ .../1/CXLLogicalDevices/1/index.json | 51 ++++++++++++++++ .../1/CXLLogicalDevices/index.json | 12 ++++ .../PCIeDevices/1/PCIeFunctions/1/index.json | 37 +++++++++++ .../PCIeDevices/1/PCIeFunctions/index.json | 12 ++++ .../Chassis/PCXL2/PCIeDevices/1/index.json | 40 ++++++++++++ .../Chassis/PCXL2/PCIeDevices/index.json | 12 ++++ .../Chassis/PCXL2/Processors/GPU/index.json | 53 ++++++++++++++++ .../Chassis/PCXL2/Processors/index.json | 12 ++++ Resources/CXLAgent/Chassis/PCXL2/index.json | 30 +++++++++ .../PCXL3/FabricAdapters/1/Ports/1/index.json | 48 +++++++++++++++ .../PCXL3/FabricAdapters/1/Ports/index.json | 12 ++++ .../Chassis/PCXL3/FabricAdapters/1/index.json | 31 ++++++++++ .../Chassis/PCXL3/FabricAdapters/index.json | 12 ++++ .../Chassis/PCXL3/Memory/3DXP/index.json | 19 ++++++ .../CXLAgent/Chassis/PCXL3/Memory/index.json | 13 ++++ .../MemoryDomains/1/MemoryChunks/1/index.json | 30 +++++++++ .../MemoryDomains/1/MemoryChunks/index.json | 12 ++++ .../Chassis/PCXL3/MemoryDomains/1/index.json | 46 ++++++++++++++ .../Chassis/PCXL3/MemoryDomains/index.json | 12 ++++ .../1/CXLLogicalDevices/1/index.json | 50 +++++++++++++++ .../1/CXLLogicalDevices/index.json | 12 ++++ .../PCIeDevices/1/PCIeFunctions/1/index.json | 37 +++++++++++ .../PCIeDevices/1/PCIeFunctions/index.json | 12 ++++ .../Chassis/PCXL3/PCIeDevices/1/index.json | 40 ++++++++++++ .../Chassis/PCXL3/PCIeDevices/index.json | 12 ++++ Resources/CXLAgent/Chassis/PCXL3/index.json | 27 ++++++++ Resources/CXLAgent/Chassis/index.json | 30 +++++++++ .../Fabrics/CXL/Connections/12/index.json | 37 +++++++++++ .../Fabrics/CXL/Connections/13/index.json | 37 +++++++++++ .../Fabrics/CXL/Connections/index.json | 15 +++++ .../Fabrics/CXL/Endpoints/1/index.json | 19 ++++++ .../Fabrics/CXL/Endpoints/I1/index.json | 37 +++++++++++ .../Fabrics/CXL/Endpoints/I2/index.json | 49 +++++++++++++++ .../Fabrics/CXL/Endpoints/I3/index.json | 49 +++++++++++++++ .../Fabrics/CXL/Endpoints/T1/index.json | 44 +++++++++++++ .../Fabrics/CXL/Endpoints/T2/index.json | 56 +++++++++++++++++ .../Fabrics/CXL/Endpoints/T3/index.json | 49 +++++++++++++++ .../CXLAgent/Fabrics/CXL/Endpoints/index.json | 30 +++++++++ .../CXL/Switches/CXL/Ports/D1/index.json | 43 +++++++++++++ .../CXL/Switches/CXL/Ports/D2/index.json | 43 +++++++++++++ .../CXL/Switches/CXL/Ports/D3/index.json | 43 +++++++++++++ .../CXL/Switches/CXL/Ports/U1/index.json | 49 +++++++++++++++ .../Fabrics/CXL/Switches/CXL/Ports/index.json | 22 +++++++ .../Fabrics/CXL/Switches/CXL/index.json | 25 ++++++++ .../CXLAgent/Fabrics/CXL/Switches/index.json | 10 +++ .../CXLAgent/Fabrics/CXL/Zones/1/index.json | 27 ++++++++ .../CXLAgent/Fabrics/CXL/Zones/2/index.json | 27 ++++++++ .../CXLAgent/Fabrics/CXL/Zones/3/index.json | 27 ++++++++ .../CXLAgent/Fabrics/CXL/Zones/index.json | 18 ++++++ Resources/CXLAgent/Fabrics/CXL/index.json | 26 ++++++++ Resources/CXLAgent/Fabrics/index.json | 12 ++++ .../Systems/CXL-System/Memory/CXL2/index.json | 22 +++++++ .../Systems/CXL-System/Memory/CXL3/index.json | 22 +++++++ .../CXL-System/Memory/RCXL2/index.json | 29 +++++++++ .../CXL-System/Memory/RCXL3/index.json | 29 +++++++++ .../Systems/CXL-System/Memory/index.json | 22 +++++++ .../CXL/MemoryChunks/1/index.json | 40 ++++++++++++ .../MemoryDomains/CXL/MemoryChunks/index.json | 13 ++++ .../CXL-System/MemoryDomains/CXL/index.json | 38 ++++++++++++ .../CXL-System/MemoryDomains/index.json | 13 ++++ .../Processors/CPU/Ports/1/index.json | 54 ++++++++++++++++ .../Processors/CPU/Ports/index.json | 14 +++++ .../CXL-System/Processors/CPU/index.json | 56 +++++++++++++++++ .../Systems/CXL-System/Processors/index.json | 18 ++++++ .../CXLAgent/Systems/CXL-System/index.json | 61 +++++++++++++++++++ Resources/CXLAgent/Systems/index.json | 12 ++++ Resources/CXLAgent/index.json | 21 +++++++ 131 files changed, 3525 insertions(+) create mode 100644 Resources/CXLAgent/AggregationService/ConnectionMethods/CXL/index.json create mode 100644 Resources/CXLAgent/AggregationService/ConnectionMethods/index.json create mode 100644 Resources/CXLAgent/AggregationService/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL-Chassis/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL1/PCIeDevices/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL1/Processors/FPGA/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL1/Processors/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/Memory/HBM/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/Memory/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/MemoryChunks/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/MemoryChunks/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/MemoryDomains/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/PCIeDevices/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/Processors/GPU/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/Processors/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL2/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/Memory/3DXP/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/Memory/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/MemoryChunks/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/MemoryChunks/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/MemoryDomains/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/PCIeDevices/index.json create mode 100755 Resources/CXLAgent/Chassis/CXL3/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/Ports/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/Ports/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/Processors/FPGA/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/Processors/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/Ports/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/Ports/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/Memory/HBM/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/Memory/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/Processors/GPU/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/Processors/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL2/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/1/Ports/1/index.json create mode 100755 Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/1/Ports/index.json create mode 100755 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Resources/CXLAgent/Fabrics/CXL/Endpoints/T2/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Endpoints/T3/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Endpoints/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D1/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D2/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D3/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/U1/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Switches/CXL/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Switches/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Zones/1/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Zones/2/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Zones/3/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/Zones/index.json create mode 100755 Resources/CXLAgent/Fabrics/CXL/index.json create mode 100755 Resources/CXLAgent/Fabrics/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/Memory/CXL2/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/Memory/CXL3/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/Memory/RCXL2/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/Memory/RCXL3/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/Memory/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks/1/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/MemoryDomains/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/Processors/CPU/Ports/1/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/Processors/CPU/Ports/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/Processors/CPU/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/Processors/index.json create mode 100755 Resources/CXLAgent/Systems/CXL-System/index.json create mode 100755 Resources/CXLAgent/Systems/index.json create mode 100644 Resources/CXLAgent/index.json diff --git a/Resources/CXLAgent/AggregationService/ConnectionMethods/CXL/index.json b/Resources/CXLAgent/AggregationService/ConnectionMethods/CXL/index.json new file mode 100644 index 00000000..2e82ef49 --- /dev/null +++ b/Resources/CXLAgent/AggregationService/ConnectionMethods/CXL/index.json @@ -0,0 +1,11 @@ + { + "@odata.type": "#ConnectionMethod.v1_1_0.ConnectionMethod", + "Id": "NVMeoF", + "Name": "ConnectionMethod for Agent CXL", + "ConnectionMethodType": "Redfish", + "ConnectionMethodVariant": "Contoso", + "Links": { + "AggregationSources": [] + }, + "@odata.id": "/redfish/v1/AggregationService/ConnectionMethods/CXL" + } diff --git a/Resources/CXLAgent/AggregationService/ConnectionMethods/index.json b/Resources/CXLAgent/AggregationService/ConnectionMethods/index.json new file mode 100644 index 00000000..6cd0e74f --- /dev/null +++ b/Resources/CXLAgent/AggregationService/ConnectionMethods/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#ConnectionMethodCollection.ConnectionMethodCollection", + "Name": "ConnectionMethod Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/AggregationService/ConnectionMethods/CXL" + } + ], + "@odata.id": "/redfish/v1/ConnectionMethods", + "@Redfish.Copyright": "Copyright 2015-2022 SNIA. All rights reserved." +} diff --git a/Resources/CXLAgent/AggregationService/index.json b/Resources/CXLAgent/AggregationService/index.json new file mode 100644 index 00000000..14f4caaf --- /dev/null +++ b/Resources/CXLAgent/AggregationService/index.json @@ -0,0 +1,14 @@ +{ + "@odata.type": "#AggregationService.v1_0_1.AggregationService", + "Id": "AggregationService", + "Name": "Aggregation Service", + "Description": "Open Fabric Manager Aggregation Service", + "Status": { + "State": "Enabled", + "Health": "OK" + }, + "ServiceEnabled": true, + + "@odata.id": "/redfish/v1/AggregationService", + "@Redfish.Copyright": "Copyright 2023 OpenFabrics Alliance. All rights reserved." +} \ No newline at end of file diff --git a/Resources/CXLAgent/Chassis/CXL-Chassis/index.json b/Resources/CXLAgent/Chassis/CXL-Chassis/index.json new file mode 100755 index 00000000..53aae786 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL-Chassis/index.json @@ -0,0 +1,33 @@ +{ + "@odata.type": "#Chassis.v1_20_0.Chassis", + "Id": "CXL-Chassis", + "Name": "CXL System chassis containig CXL cards", + "PowerState": "On", + "ChassisType": "Blade", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "Links": { + "ComputerSystems": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System" + } + ], + "Contains": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL2" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL3" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL-Chassis", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/1/index.json b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/1/index.json new file mode 100755 index 00000000..7b6836f1 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/1/index.json @@ -0,0 +1,35 @@ +{ + "@odata.type": "#CXLLogicalDevice.v1_0_0.CXLLogicalDevice", + "Id": "1", + "Name": "CXL Logical Device Type 1", + "Description": "Locally attached CXL Logical Device Type 1", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "Identifiers": [ + { + "DurableName": "4C-1D-96-FF-FE-DD-D8-35:1", + "DurableNameFormat": "GCXLID" + } + ], + "CXLSemanticsSupported": [ + "CXLio", + "CXLcache" + ], + "Links": { + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1" + }, + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/index.json b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/index.json new file mode 100755 index 00000000..6c3c0872 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#CXLLogicalDeviceCollection.CXLLogicalDeviceCollection", + "Name": "CXL Logical Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1/index.json b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1/index.json new file mode 100755 index 00000000..642811d6 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1/index.json @@ -0,0 +1,37 @@ +{ + "@odata.type": "#PCIeFunction.v1_4_0.PCIeFunction", + "Id": "1", + "Name": "CXL Function", + "Description": "PCIe Function with CXL extensions representing FPGA", + "FunctionId": 1, + "FunctionType": "Physical", + "DeviceClass": "Processor", + "DeviceId": "0xABCD", + "VendorId": "0xABCD", + "ClassCode": "0x0B4000", + "RevisionId": "0x00", + "SubsystemId": "0xABCD", + "SubsystemVendorId": "0xABCD", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "FunctionProtocol": "CXL", + "Links": { + "Processors": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1/Processors/FPGA" + } + ], + "CXLLogicalDevice": { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/1" + }, + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1" + } + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/index.json b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/index.json new file mode 100755 index 00000000..3ea9c023 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeFunctionCollection.PCIeFunctionCollection", + "Name": "PCIe Function Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/index.json b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/index.json new file mode 100755 index 00000000..a0c6a8b6 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/index.json @@ -0,0 +1,40 @@ +{ + "@odata.type": "#PCIeDevice.v1_10_0.PCIeDevice", + "Id": "1", + "Name": "CXL Device", + "Description": "CXL Physcial Device Type 1", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeInterface": { + "PCIeType": "Gen5", + "MaxPCIeType": "Gen5", + "LanesInUse": 8, + "MaxLanes": 16 + }, + "PCIeFunctions": { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions" + }, + "CXLDevice":{ + "CurrentProtocolVersion": "V2_0", + "CapableProtocolVersion": "V2_0", + "DeviceType": "Type1", + "MultiLogicalDevice": false + }, + "CXLLogicalDevices": { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices" + }, + "Links": { + "Chassis": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/index.json b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/index.json new file mode 100755 index 00000000..06154de4 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL1/PCIeDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeDeviceCollection.PCIeDeviceCollection", + "Name": "PCIe Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL1/Processors/FPGA/index.json b/Resources/CXLAgent/Chassis/CXL1/Processors/FPGA/index.json new file mode 100755 index 00000000..30ba417c --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL1/Processors/FPGA/index.json @@ -0,0 +1,37 @@ +{ + "@odata.type": "#Processor.v1_15_0.Processor", + "Id": "FPGA", + "Name": "FPGA with cache", + "Description": "FPGA with cache", + "ProcessorType": "FPGA", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "ProcessorMemory": [ + { + "IntegratedMemory": true, + "MemoryType": "Cache", + "CapacityMiB": 64 + } + ], + "MemorySummary": { + "TotalMemorySizeMiB": 0, + "TotalCacheSizeMiB": 64 + }, + "Links": { + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1" + } + ], + "ConnectedProcessors": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU" + } + ] + }, + "@odata.id": "/redfish/v1/Chassis/CXL1/Processors/FPGA", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL1/Processors/index.json b/Resources/CXLAgent/Chassis/CXL1/Processors/index.json new file mode 100755 index 00000000..4361b240 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL1/Processors/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#ProcessorCollection.ProcessorCollection", + "Name": "Processor Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1/Processors/FPGA" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL1/Processors", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL1/index.json b/Resources/CXLAgent/Chassis/CXL1/index.json new file mode 100755 index 00000000..ceed1096 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL1/index.json @@ -0,0 +1,25 @@ +{ + "@odata.type": "#Chassis.v1_20_0.Chassis", + "Id": "CXL1", + "Name": "CXL Device Type 1 module", + "ChassisType": "Module", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeDevices": { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices" + }, + "Processors": { + "@odata.id": "/redfish/v1/Chassis/CXL1/Processors" + }, + "Links": { + "ContainedBy": { + "@odata.id": "/redfish/v1/Chassis/CXL-Chassis" + } + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/Memory/HBM/index.json b/Resources/CXLAgent/Chassis/CXL2/Memory/HBM/index.json new file mode 100755 index 00000000..5a447d23 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/Memory/HBM/index.json @@ -0,0 +1,27 @@ +{ + "@odata.type": "#Memory.v1_15_0.Memory", + "Id": "HBM", + "MemoryType": "DRAM", + "MemoryDeviceType": "HBM2", + "MemoryMedia": [ + "DRAM" + ], + "Name": "HBM memory", + "CapacityMiB": 16384, + "OperatingSpeedMhz": 1333, + "Status": { + "Health": "OK", + "State": "Enabled", + "HealthRollup": "OK" + }, + "Links": { + "Processors": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/Processors/GPU" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL2/Memory/HBM", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/Memory/index.json b/Resources/CXLAgent/Chassis/CXL2/Memory/index.json new file mode 100755 index 00000000..572edd96 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/Memory/index.json @@ -0,0 +1,13 @@ +{ + "@odata.type": "#MemoryCollection.MemoryCollection", + "Name": "Memory Collection", + "Description": "Memory Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/Memory/HBM" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL2/Memory", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/MemoryChunks/1/index.json b/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/MemoryChunks/1/index.json new file mode 100755 index 00000000..83370990 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/MemoryChunks/1/index.json @@ -0,0 +1,25 @@ +{ + "@odata.type": "#MemoryChunks.v1_5_0.MemoryChunks", + "Id": "1", + "Name": "Memory Chunk 1", + "Description": "Memory chunk accessible through CXL", + "Status": { + "State": "Enabled", + "Health": "OK" + }, + "MemoryChunkSizeMiB": 4096, + "AddressRangeType": "Volatile", + "AddressRangeOffsetMiB": 1024, + "MediaLocation": "Local", + "OperationalState": "Online", + "Links": { + "CXLLogicalDevices": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1/MemoryChunks/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/MemoryChunks/index.json b/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/MemoryChunks/index.json new file mode 100755 index 00000000..ecb8f4b1 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/MemoryChunks/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#MemoryChunksCollection.MemoryChunksCollection", + "Name": "Memory Chunks Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1/MemoryChunks/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1/MemoryChunks", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/index.json b/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/index.json new file mode 100755 index 00000000..f6d2720d --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/index.json @@ -0,0 +1,36 @@ +{ + "@odata.type": "#MemoryDomain.v1_4_0.MemoryDomain", + "Id": "1", + "Name": "GPU HBM Memory Domain", + "Description": "GPU HBM Memory Domain accessible through CXL", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "MemoryChunks": { + "@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1/MemoryChunks" + }, + "AllowsMemoryChunkCreation": true, + "MinMemoryChunkSizeMiB": 64, + "MemoryChunkIncrementMiB": 64, + "InterleavableMemorySets": [ + { + "MemorySet": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/Memory/HBM" + } + ] + } + ], + "Links":{ + "CXLLogicalDevices": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/index.json b/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/index.json new file mode 100755 index 00000000..7cef19e5 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/MemoryDomains/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#MemoryDomainCollection.MemoryDomainCollection", + "Name": "Memory Domain Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/1/index.json b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/1/index.json new file mode 100755 index 00000000..ebcc34e1 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/1/index.json @@ -0,0 +1,46 @@ +{ + "@odata.type": "#CXLLogicalDevice.v1_0_0.CXLLogicalDevice", + "Id": "1", + "Name": "CXL Logical Device Type 2", + "Description": "Locally attached CXL Logical Device Type 2", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "Identifiers": [ + { + "DurableName": "4C-1D-96-FF-FE-DD-D8-35:1", + "DurableNameFormat": "GCXLID" + } + ], + "CXLSemanticsSupported": [ + "CXLio", + "CXLcache", + "CXLmem" + ], + "Links": { + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1" + }, + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/1" + } + ], + "MemoryDomains": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1" + } + ], + "MemoryChunks": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1/MemoryChunks/1" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/index.json b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/index.json new file mode 100755 index 00000000..41214300 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#CXLLogicalDeviceCollection.CXLLogicalDeviceCollection", + "Name": "CXL Logical Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/1/index.json b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/1/index.json new file mode 100755 index 00000000..48c56310 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/1/index.json @@ -0,0 +1,37 @@ +{ + "@odata.type": "#PCIeFunction.v1_4_0.PCIeFunction", + "Id": "1", + "Name": "CXL Function", + "Description": "PCIe Function with CXL extensions representing GPU", + "FunctionId": 1, + "FunctionType": "Physical", + "DeviceClass": "ProcessingAccelerators", + "DeviceId": "0xABCD", + "VendorId": "0xABCD", + "ClassCode": "0x120000", + "RevisionId": "0x00", + "SubsystemId": "0xABCD", + "SubsystemVendorId": "0xABCD", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "FunctionProtocol": "CXL", + "Links": { + "Processors": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/Processors/GPU" + } + ], + "CXLLogicalDevice": { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/1" + }, + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1" + } + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/index.json b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/index.json new file mode 100755 index 00000000..c0b3bffa --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeFunctionCollection.PCIeFunctionCollection", + "Name": "PCIe Function Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/PCIeFunctions", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/index.json b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/index.json new file mode 100755 index 00000000..b4e45048 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/1/index.json @@ -0,0 +1,40 @@ +{ + "@odata.type": "#PCIeDevice.v1_10_0.PCIeDevice", + "Id": "1", + "Name": "CXL Device", + "Description": "CXL Physcial Device Type 2", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeInterface": { + "PCIeType": "Gen5", + "MaxPCIeType": "Gen5", + "LanesInUse": 8, + "MaxLanes": 16 + }, + "PCIeFunctions": { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/PCIeFunctions" + }, + "CXLDevice":{ + "CurrentProtocolVersion": "V2_0", + "CapableProtocolVersion": "V2_0", + "DeviceType": "Type2", + "MultiLogicalDevice": false + }, + "CXLLogicalDevices": { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices" + }, + "Links": { + "Chassis": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/index.json b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/index.json new file mode 100755 index 00000000..664feda2 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/PCIeDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeDeviceCollection.PCIeDeviceCollection", + "Name": "PCIe Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/Processors/GPU/index.json b/Resources/CXLAgent/Chassis/CXL2/Processors/GPU/index.json new file mode 100755 index 00000000..ba254dab --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/Processors/GPU/index.json @@ -0,0 +1,48 @@ +{ + "@odata.type": "#Processor.v1_15_0.Processor", + "Id": "GPU", + "Name": "GPU with HBM memory", + "Description": "GPU with cache and HBM memory", + "ProcessorType": "GPU", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "ProcessorMemory": [ + { + "IntegratedMemory": false, + "MemoryType": "HBM2", + "CapacityMiB": 16384, + "SpeedMHz": 1033 + }, + { + "IntegratedMemory": true, + "MemoryType": "Cache", + "CapacityMiB": 64 + } + ], + "MemorySummary": { + "TotalMemorySizeMiB": 16384, + "TotalCacheSizeMiB": 64 + }, + "Links": { + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/1" + } + ], + "Memory": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/Memory/HBM" + } + ], + "ConnectedProcessors": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU" + } + ] + }, + "@odata.id": "/redfish/v1/Chassis/CXL2/Processors/GPU", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/Processors/index.json b/Resources/CXLAgent/Chassis/CXL2/Processors/index.json new file mode 100755 index 00000000..f30e1e18 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/Processors/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#ProcessorCollection.ProcessorCollection", + "Name": "Processor Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/Processors/GPU" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL2/Processors", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL2/index.json b/Resources/CXLAgent/Chassis/CXL2/index.json new file mode 100755 index 00000000..14daac74 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL2/index.json @@ -0,0 +1,32 @@ +{ + "@odata.type": "#Chassis.v1_20_0.Chassis", + "Id": "CXL2", + "Name": "CXL Device Type 2 module", + "PowerState": "On", + "ChassisType": "Module", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeDevices": { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices" + }, + "Processors": { + "@odata.id": "/redfish/v1/Chassis/CXL2/Processors" + }, + "Memory": { + "@odata.id": "/redfish/v1/Chassis/CXL2/Memory" + }, + "MemoryDomains": { + "@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains" + }, + "Links": { + "ContainedBy": { + "@odata.id": "/redfish/v1/Chassis/CXL-Chassis" + } + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL2", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/Memory/3DXP/index.json b/Resources/CXLAgent/Chassis/CXL3/Memory/3DXP/index.json new file mode 100755 index 00000000..83f74511 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/Memory/3DXP/index.json @@ -0,0 +1,19 @@ +{ + "@odata.type": "#Memory.v1_15_0.Memory", + "Id": "3DXP", + "Name": "3DXP memory", + "MemoryType": "IntelOptane", + "MemoryMedia": [ + "Intel3DXPoint" + ], + "CapacityMiB": 16384, + "OperatingSpeedMhz": 1333, + "Status": { + "Health": "OK", + "State": "Enabled", + "HealthRollup": "OK" + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL3/Memory/3DXP", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/Memory/index.json b/Resources/CXLAgent/Chassis/CXL3/Memory/index.json new file mode 100755 index 00000000..13493cc0 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/Memory/index.json @@ -0,0 +1,13 @@ +{ + "@odata.type": "#MemoryCollection.MemoryCollection", + "Name": "Memory Collection", + "Description": "Memory Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/Memory/3DXP" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL3/Memory", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/MemoryChunks/1/index.json b/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/MemoryChunks/1/index.json new file mode 100755 index 00000000..decc8cc3 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/MemoryChunks/1/index.json @@ -0,0 +1,25 @@ +{ + "@odata.type": "#MemoryChunks.v1_5_0.MemoryChunks", + "Id": "1", + "Name": "Memory Chunk 1", + "Description": "Memory chunk accessible through CXL", + "Status": { + "State": "Enabled", + "Health": "OK" + }, + "MemoryChunkSizeMiB": 4096, + "AddressRangeType": "PMEM", + "AddressRangeOffsetMiB": 1024, + "MediaLocation": "Local", + "OperationalState": "Online", + "Links": { + "CXLLogicalDevices": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains/1/MemoryChunks/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/MemoryChunks/index.json b/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/MemoryChunks/index.json new file mode 100755 index 00000000..f0b8dd73 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/MemoryChunks/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#MemoryChunksCollection.MemoryChunksCollection", + "Name": "Memory Chunks Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains/1/MemoryChunks/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains/1/MemoryChunks", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/index.json b/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/index.json new file mode 100755 index 00000000..db51ec75 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/1/index.json @@ -0,0 +1,41 @@ +{ + "@odata.type": "#MemoryDomain.v1_4_0.MemoryDomain", + "Id": "1", + "Name": "CXL 3DXP Memory Domain", + "Description": "3DXP Memory Domain accessible through CXL", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "MemoryChunks": { + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains/1/MemoryChunks" + }, + "AllowsMemoryChunkCreation": true, + "MinMemoryChunkSizeMiB": 64, + "MemoryChunkIncrementMiB": 64, + "InterleavableMemorySets": [ + { + "MemorySet": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/Memory/3DXP" + } + ] + } + ], + "Links": { + "CXLLogicalDevices": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/1" + } + ], + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/index.json b/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/index.json new file mode 100755 index 00000000..56998cc2 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/MemoryDomains/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#MemoryDomainCollection.MemoryDomainCollection", + "Name": "Memory Domain Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/1/index.json b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/1/index.json new file mode 100755 index 00000000..5d9b700b --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/1/index.json @@ -0,0 +1,45 @@ +{ + "@odata.type": "#CXLLogicalDevice.v1_0_0.CXLLogicalDevice", + "Id": "1", + "Name": "CXL Logical Device Type 3", + "Description": "Locally attached CXL Logical Device Type 3", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "Identifiers": [ + { + "DurableName": "4C-1D-96-FF-FE-DD-D8-35:1", + "DurableNameFormat": "GCXLID" + } + ], + "CXLSemanticsSupported": [ + "CXLio", + "CXLmem" + ], + "Links": { + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1" + }, + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/1" + } + ], + "MemoryDomains": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains/1" + } + ], + "MemoryChunks": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains/1/MemoryChunks/1" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/index.json b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/index.json new file mode 100755 index 00000000..1599bd40 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#CXLLogicalDeviceCollection.CXLLogicalDeviceCollection", + "Name": "CXL Logical Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/1/index.json b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/1/index.json new file mode 100755 index 00000000..916207f6 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/1/index.json @@ -0,0 +1,37 @@ +{ + "@odata.type": "#PCIeFunction.v1_4_0.PCIeFunction", + "Id": "1", + "Name": "CXL Function", + "Description": "PCIe Function with CXL extensions representing Memory Controller", + "FunctionId": 1, + "FunctionType": "Physical", + "DeviceClass": "MemoryController", + "DeviceId": "0xABCD", + "VendorId": "0xABCD", + "ClassCode": "0x050210", + "RevisionId": "0x00", + "SubsystemId": "0xABCD", + "SubsystemVendorId": "0xABCD", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "FunctionProtocol": "CXL", + "Links": { + "MemoryControllers": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains/1" + } + ], + "CXLLogicalDevice": { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices/1" + }, + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1" + } + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/index.json b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/index.json new file mode 100755 index 00000000..16068144 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeFunctionCollection.PCIeFunctionCollection", + "Name": "PCIe Function Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/PCIeFunctions", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/index.json b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/index.json new file mode 100755 index 00000000..9278fc80 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/1/index.json @@ -0,0 +1,40 @@ +{ + "@odata.type": "#PCIeDevice.v1_10_0.PCIeDevice", + "Id": "1", + "Name": "CXL Device", + "Description": "CXL Physcial Device Type 3", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeInterface": { + "PCIeType": "Gen5", + "MaxPCIeType": "Gen5", + "LanesInUse": 8, + "MaxLanes": 16 + }, + "PCIeFunctions": { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/PCIeFunctions" + }, + "CXLDevice":{ + "CurrentProtocolVersion": "V2_0", + "CapableProtocolVersion": "V2_0", + "DeviceType": "Type3", + "MultiLogicalDevice": false + }, + "CXLLogicalDevices": { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/CXLLogicalDevices" + }, + "Links": { + "Chassis": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/index.json b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/index.json new file mode 100755 index 00000000..959e2ba6 --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/PCIeDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeDeviceCollection.PCIeDeviceCollection", + "Name": "PCIe Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/CXL3/index.json b/Resources/CXLAgent/Chassis/CXL3/index.json new file mode 100755 index 00000000..bdaa94ef --- /dev/null +++ b/Resources/CXLAgent/Chassis/CXL3/index.json @@ -0,0 +1,29 @@ +{ + "@odata.type": "#Chassis.v1_20_0.Chassis", + "Id": "CXL3", + "Name": "CXL Device Type 3 module", + "PowerState": "On", + "ChassisType": "Module", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeDevices": { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices" + }, + "Memory": { + "@odata.id": "/redfish/v1/Chassis/CXL3/Memory" + }, + "MemoryDomains": { + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains" + }, + "Links": { + "ContainedBy": { + "@odata.id": "/redfish/v1/Chassis/CXL-Chassis" + } + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/CXL3", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/Ports/1/index.json b/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/Ports/1/index.json new file mode 100755 index 00000000..50ef19cc --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/Ports/1/index.json @@ -0,0 +1,48 @@ +{ + "@odata.type": "#Port.v1_7_0.Port", + "Id": "1", + "Name": "CXL Port 1", + "Description": "CXL Port 1 in Fabric Adapter", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PortId": "4C-1D-96-FF-FE-DD-D8-D1", + "RemotePortId": "D1", + "PortProtocol": "CXL", + "CurrentProtocolVersion": "2.0", + "CapableProtocolVersions": [ + "1.1", "2.0" + ], + "PortType": "UpstreamPort", + "PortMedium": "Optical", + "CurrentSpeedGbps": 256, + "Width": 8, + "MaxSpeedGbps": 128, + "ActiveWidth": 4, + "LinkState": "Enabled", + "LinkStatus": "LinkUp", + "InterfaceEnabled": true, + "LinkNetworkTechnology": "PCIe", + "Links": { + "AssociatedEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T1" + } + ], + "ConnectedSwitches": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL" + } + ], + "ConnectedSwitchPorts": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/D1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL1/FabricAdapters/1/Ports/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/Ports/index.json b/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/Ports/index.json new file mode 100755 index 00000000..9740a40b --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/Ports/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PortCollection.PortCollection", + "Name": "CXL Port Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/FabricAdapters/1/Ports/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL1/FabricAdapters/1/Ports", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/index.json b/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/index.json new file mode 100755 index 00000000..bb50b6e1 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/1/index.json @@ -0,0 +1,31 @@ +{ + "@odata.type": "#FabricAdapter.v1_3_0.FabricAdapter", + "Id": "1", + "Name": "CXL Fabric Adapter 1", + "Description": "CXL Fabric Adapter for FPGA system", + "Manufacturer": "Contoso", + "Model": "CXL Fabric Adapter Model X", + "PartNumber": "975999-001", + "SparePartNumber": "152111-A01", + "SKU": "Contoso 2-port CXL Adapter Bridge", + "SerialNumber": "2M220100SL", + "FirmwareVersion": "7.4.10", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "Ports": { + "@odata.id": "/redfish/v1/Chassis/PCXL1/FabricAdapters/1/Ports" + }, + "Links": { + "Processors": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/Processors/FPGA" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL1/FabricAdapters/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/index.json b/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/index.json new file mode 100755 index 00000000..b45fd3e9 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/FabricAdapters/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#FabricAdapterCollection.FabricAdapterCollection", + "Name": "Fabric Adapter Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/FabricAdapters/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL1/FabricAdapters", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/1/index.json b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/1/index.json new file mode 100755 index 00000000..e6832e2f --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/1/index.json @@ -0,0 +1,40 @@ +{ + "@odata.type": "#CXLLogicalDevice.v1_0_0.CXLLogicalDevice", + "Id": "1", + "Name": "CXL Logical Device Type 1", + "Description": "CXL Logical Device Type 1 attached through CXL fabric", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "Identifiers": [ + { + "DurableName": "4C-1D-96-FF-FE-DD-D8-35:1", + "DurableNameFormat": "GCXLID" + } + ], + "CXLSemanticsSupported": [ + "CXLio", + "CXLcache" + ], + "Links": { + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1" + }, + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/1" + } + ], + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T1" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/index.json b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/index.json new file mode 100755 index 00000000..778be815 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#CXLLogicalDeviceCollection.CXLLogicalDeviceCollection", + "Name": "CXL Logical Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/1/index.json b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/1/index.json new file mode 100755 index 00000000..24b6a046 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/1/index.json @@ -0,0 +1,37 @@ +{ + "@odata.type": "#PCIeFunction.v1_4_0.PCIeFunction", + "Id": "1", + "Name": "CXL Function", + "Description": "PCIe Function with CXL extensions representing FPGA", + "FunctionId": 1, + "FunctionType": "Physical", + "DeviceClass": "Processor", + "DeviceId": "0xABCD", + "VendorId": "0xABCD", + "ClassCode": "0x0B4000", + "RevisionId": "0x00", + "SubsystemId": "0xABCD", + "SubsystemVendorId": "0xABCD", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "FunctionProtocol": "CXL", + "Links": { + "Processors": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/Processors/FPGA" + } + ], + "CXLLogicalDevice": { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/1" + }, + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1" + } + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/index.json b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/index.json new file mode 100755 index 00000000..4090e4da --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeFunctionCollection.PCIeFunctionCollection", + "Name": "PCIe Function Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/index.json b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/index.json new file mode 100755 index 00000000..5c7a0f03 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/1/index.json @@ -0,0 +1,40 @@ +{ + "@odata.type": "#PCIeDevice.v1_10_0.PCIeDevice", + "Id": "1", + "Name": "CXL Device", + "Description": "CXL Physcial Device Type 1", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeInterface": { + "PCIeType": "Gen5", + "MaxPCIeType": "Gen5", + "LanesInUse": 4, + "MaxLanes": 8 + }, + "PCIeFunctions": { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions" + }, + "CXLDevice":{ + "CurrentProtocolVersion": "V2_0", + "CapableProtocolVersion": "V2_0", + "DeviceType": "Type1", + "MultiLogicalDevice": false + }, + "CXLLogicalDevices": { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices" + }, + "Links": { + "Chassis": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/index.json b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/index.json new file mode 100755 index 00000000..facefdf4 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/PCIeDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeDeviceCollection.PCIeDeviceCollection", + "Name": "PCIe Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/Processors/FPGA/index.json b/Resources/CXLAgent/Chassis/PCXL1/Processors/FPGA/index.json new file mode 100755 index 00000000..a8ffd98c --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/Processors/FPGA/index.json @@ -0,0 +1,42 @@ +{ + "@odata.type": "#Processor.v1_15_0.Processor", + "Id": "FPGA", + "Name": "FPGA with cache", + "Description": "FPGA with cache accessible through CXL fabric", + "ProcessorType": "FPGA", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "ProcessorMemory": [ + { + "IntegratedMemory": true, + "MemoryType": "Cache", + "CapacityMiB": 64 + } + ], + "MemorySummary": { + "TotalMemorySizeMiB": 0, + "TotalCacheSizeMiB": 64 + }, + "Links": { + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/PCIeFunctions/1" + } + ], + "FabricAdapters": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/FabricAdapters/1" + } + ], + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T1" + } + ] + }, + "@odata.id": "/redfish/v1/Chassis/PCXL1/Processors/FPGA", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/Processors/index.json b/Resources/CXLAgent/Chassis/PCXL1/Processors/index.json new file mode 100755 index 00000000..0fe0aac9 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/Processors/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#ProcessorCollection.ProcessorCollection", + "Name": "Processor Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/Processors/FPGA" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL1/Processors", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL1/index.json b/Resources/CXLAgent/Chassis/PCXL1/index.json new file mode 100755 index 00000000..11dcbd99 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL1/index.json @@ -0,0 +1,23 @@ +{ + "@odata.type": "#Chassis.v1_20_0.Chassis", + "Id": "PCXL1", + "Name": "Pooled CXL Device Type 1 chassis", + "ChassisType": "Blade", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeDevices": { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices" + }, + "Processors": { + "@odata.id": "/redfish/v1/Chassis/PCXL1/Processors" + }, + "FabricAdapters": { + "@odata.id": "/redfish/v1/Chassis/PCXL1/FabricAdapters" + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/Ports/1/index.json b/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/Ports/1/index.json new file mode 100755 index 00000000..952d4cd1 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/Ports/1/index.json @@ -0,0 +1,48 @@ +{ + "@odata.type": "#Port.v1_7_0.Port", + "Id": "1", + "Name": "CXL Port 1", + "Description": "CXL Port 1 in Fabric Adapter", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PortId": "4C-1D-96-FF-FE-DD-D8-D2", + "RemotePortId": "D2", + "PortProtocol": "CXL", + "CurrentProtocolVersion": "2.0", + "CapableProtocolVersions": [ + "1.1", "2.0" + ], + "PortType": "UpstreamPort", + "PortMedium": "Optical", + "CurrentSpeedGbps": 256, + "Width": 8, + "MaxSpeedGbps": 128, + "ActiveWidth": 4, + "LinkState": "Enabled", + "LinkStatus": "LinkUp", + "InterfaceEnabled": true, + "LinkNetworkTechnology": "PCIe", + "Links": { + "AssociatedEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T2" + } + ], + "ConnectedSwitches": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL" + } + ], + "ConnectedSwitchPorts": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/D2" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters/1/Ports/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/Ports/index.json b/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/Ports/index.json new file mode 100755 index 00000000..927cad40 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/Ports/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PortCollection.PortCollection", + "Name": "CXL Port Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters/1/Ports/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters/1/Ports", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/index.json b/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/index.json new file mode 100755 index 00000000..8e4d83c8 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/1/index.json @@ -0,0 +1,36 @@ +{ + "@odata.type": "#FabricAdapter.v1_3_0.FabricAdapter", + "Id": "1", + "Name": "CXL Fabric Adapter 1", + "Description": "CXL Fabric Adapter for memory system", + "Manufacturer": "Contoso", + "Model": "CXL Fabric Adapter Model X", + "PartNumber": "975999-001", + "SparePartNumber": "152111-A01", + "SKU": "Contoso 2-port CXL Adapter Bridge", + "SerialNumber": "2M220100SL", + "FirmwareVersion": "7.4.10", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "Ports": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters/1/Ports" + }, + "Links": { + "Processors": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/Processors/GPU" + } + ], + "MemoryDomains": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/index.json b/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/index.json new file mode 100755 index 00000000..36bff067 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/FabricAdapters/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#FabricAdapterCollection.FabricAdapterCollection", + "Name": "Fabric Adapter Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/Memory/HBM/index.json b/Resources/CXLAgent/Chassis/PCXL2/Memory/HBM/index.json new file mode 100755 index 00000000..12642b15 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/Memory/HBM/index.json @@ -0,0 +1,27 @@ +{ + "@odata.type": "#Memory.v1_15_0.Memory", + "Id": "HBM", + "MemoryType": "DRAM", + "MemoryDeviceType": "HBM2", + "MemoryMedia": [ + "DRAM" + ], + "Name": "HBM memory", + "CapacityMiB": 16384, + "OperatingSpeedMhz": 1333, + "Status": { + "Health": "OK", + "State": "Enabled", + "HealthRollup": "OK" + }, + "Links": { + "Processors": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/Processors/GPU" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL2/Memory/HBM", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/Memory/index.json b/Resources/CXLAgent/Chassis/PCXL2/Memory/index.json new file mode 100755 index 00000000..b04ee566 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/Memory/index.json @@ -0,0 +1,13 @@ +{ + "@odata.type": "#MemoryCollection.MemoryCollection", + "Name": "Memory Collection", + "Description": "Memory Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/Memory/HBM" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL2/Memory", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/1/index.json b/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/1/index.json new file mode 100755 index 00000000..694f249e --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/1/index.json @@ -0,0 +1,30 @@ +{ + "@odata.type": "#MemoryChunks.v1_5_0.MemoryChunks", + "Id": "1", + "Name": "Memory Chunk 1", + "Description": "Memory chunk accessible through CXL", + "Status": { + "State": "Enabled", + "Health": "OK" + }, + "MemoryChunkSizeMiB": 4096, + "AddressRangeType": "Volatile", + "AddressRangeOffsetMiB": 1024, + "MediaLocation": "Local", + "OperationalState": "Online", + "Links": { + "CXLLogicalDevices": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/1" + } + ], + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T2" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/index.json b/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/index.json new file mode 100755 index 00000000..f9a868e8 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#MemoryChunksCollection.MemoryChunksCollection", + "Name": "Memory Chunks Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1/MemoryChunks", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/index.json b/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/index.json new file mode 100755 index 00000000..f72912b0 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/1/index.json @@ -0,0 +1,41 @@ +{ + "@odata.type": "#MemoryDomain.v1_4_0.MemoryDomain", + "Id": "1", + "Name": "GPU HBM Memory Domain", + "Description": "GPU HBM Memory Domain accessible through CXL fabric", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "MemoryChunks": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1/MemoryChunks" + }, + "AllowsMemoryChunkCreation": true, + "MinMemoryChunkSizeMiB": 64, + "MemoryChunkIncrementMiB": 64, + "InterleavableMemorySets": [ + { + "MemorySet": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/Memory/HBM" + } + ] + } + ], + "Links": { + "FabricAdapters": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters/1" + } + ], + "CXLLogicalDevices": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/index.json b/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/index.json new file mode 100755 index 00000000..ad7307cb --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/MemoryDomains/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#MemoryDomainCollection.MemoryDomainCollection", + "Name": "Memory Domain Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/1/index.json b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/1/index.json new file mode 100755 index 00000000..e9618e91 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/1/index.json @@ -0,0 +1,51 @@ +{ + "@odata.type": "#CXLLogicalDevice.v1_0_0.CXLLogicalDevice", + "Id": "1", + "Name": "CXL Logical Device Type 2", + "Description": "CXL Logical Device Type 2 attached through CXL fabric", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "Identifiers": [ + { + "DurableName": "4C-1D-96-FF-FE-DD-D8-35:1", + "DurableNameFormat": "GCXLID" + } + ], + "CXLSemanticsSupported": [ + "CXLio", + "CXLcache", + "CXLmem" + ], + "Links": { + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1" + }, + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/1" + } + ], + "MemoryChunks": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/1" + } + ], + "MemoryDomains": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1" + } + ], + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T2" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/index.json b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/index.json new file mode 100755 index 00000000..bab8d20d --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#CXLLogicalDeviceCollection.CXLLogicalDeviceCollection", + "Name": "CXL Logical Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/1/index.json b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/1/index.json new file mode 100755 index 00000000..c59bd297 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/1/index.json @@ -0,0 +1,37 @@ +{ + "@odata.type": "#PCIeFunction.v1_4_0.PCIeFunction", + "Id": "1", + "Name": "CXL Function", + "Description": "PCIe Function with CXL extensions representing GPU", + "FunctionId": 1, + "FunctionType": "Physical", + "DeviceClass": "ProcessingAccelerators", + "DeviceId": "0xABCD", + "VendorId": "0xABCD", + "ClassCode": "0x120000", + "RevisionId": "0x00", + "SubsystemId": "0xABCD", + "SubsystemVendorId": "0xABCD", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "FunctionProtocol": "CXL", + "Links": { + "Processors": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/Processors/GPU" + } + ], + "CXLLogicalDevice": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/1" + }, + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1" + } + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/index.json b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/index.json new file mode 100755 index 00000000..c1dcb6d6 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeFunctionCollection.PCIeFunctionCollection", + "Name": "PCIe Function Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/index.json b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/index.json new file mode 100755 index 00000000..a3cd5a01 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/1/index.json @@ -0,0 +1,40 @@ +{ + "@odata.type": "#PCIeDevice.v1_10_0.PCIeDevice", + "Id": "1", + "Name": "CXL Device", + "Description": "CXL Physcial Device Type 2", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeInterface": { + "PCIeType": "Gen5", + "MaxPCIeType": "Gen5", + "LanesInUse": 4, + "MaxLanes": 8 + }, + "PCIeFunctions": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions" + }, + "CXLDevice":{ + "CurrentProtocolVersion": "V2_0", + "CapableProtocolVersion": "V2_0", + "DeviceType": "Type2", + "MultiLogicalDevice": false + }, + "CXLLogicalDevices": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices" + }, + "Links": { + "Chassis": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/index.json b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/index.json new file mode 100755 index 00000000..2c340e44 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/PCIeDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeDeviceCollection.PCIeDeviceCollection", + "Name": "PCIe Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/Processors/GPU/index.json b/Resources/CXLAgent/Chassis/PCXL2/Processors/GPU/index.json new file mode 100755 index 00000000..8d5df5ee --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/Processors/GPU/index.json @@ -0,0 +1,53 @@ +{ + "@odata.type": "#Processor.v1_15_0.Processor", + "Id": "GPU", + "Name": "GPU with HBM memory", + "Description": "GPU with cache and HBM memory accessible through CXL fabric", + "ProcessorType": "GPU", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "ProcessorMemory": [ + { + "IntegratedMemory": false, + "MemoryType": "HBM2", + "CapacityMiB": 16384, + "SpeedMHz": 1033 + }, + { + "IntegratedMemory": true, + "MemoryType": "Cache", + "CapacityMiB": 64 + } + ], + "MemorySummary": { + "TotalMemorySizeMiB": 16384, + "TotalCacheSizeMiB": 64 + }, + "Links": { + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/PCIeFunctions/1" + } + ], + "FabricAdapters": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters/1" + } + ], + "Memory": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/Memory/HBM" + } + ], + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T2" + } + ] + }, + "@odata.id": "/redfish/v1/Chassis/PCXL2/Processors/GPU", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/Processors/index.json b/Resources/CXLAgent/Chassis/PCXL2/Processors/index.json new file mode 100755 index 00000000..4bd86359 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/Processors/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#ProcessorCollection.ProcessorCollection", + "Name": "Processor Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/Processors/GPU" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL2/Processors", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL2/index.json b/Resources/CXLAgent/Chassis/PCXL2/index.json new file mode 100755 index 00000000..598d0dfb --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL2/index.json @@ -0,0 +1,30 @@ +{ + "@odata.type": "#Chassis.v1_20_0.Chassis", + "Id": "PCXL2", + "Name": "Pooled CXL Device Type 2 chassis", + "PowerState": "On", + "ChassisType": "Blade", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeDevices": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices" + }, + "FabricAdapters": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters" + }, + "Processors": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/Processors" + }, + "Memory": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/Memory" + }, + "MemoryDomains": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains" + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL2", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/1/Ports/1/index.json b/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/1/Ports/1/index.json new file mode 100755 index 00000000..14ebc607 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/1/Ports/1/index.json @@ -0,0 +1,48 @@ +{ + "@odata.type": "#Port.v1_7_0.Port", + "Id": "1", + "Name": "CXL Port 1", + "Description": "CXL Port 1 in Fabric Adapter", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PortId": "4C-1D-96-FF-FE-DD-D8-D3", + "RemotePortId": "D3", + "PortProtocol": "CXL", + "CurrentProtocolVersion": "2.0", + "CapableProtocolVersions": [ + "1.1", "2.0" + ], + "PortType": "UpstreamPort", + "PortMedium": "Optical", + "CurrentSpeedGbps": 256, + "Width": 8, + "MaxSpeedGbps": 128, + "ActiveWidth": 4, + "LinkState": "Enabled", + "LinkStatus": "LinkUp", + "InterfaceEnabled": true, + "LinkNetworkTechnology": "PCIe", + "Links": { + "AssociatedEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T3" + } + ], + "ConnectedSwitches": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL" + } + ], + "ConnectedSwitchPorts": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/D3" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL3/FabricAdapters/1/Ports/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/1/Ports/index.json b/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/1/Ports/index.json new file mode 100755 index 00000000..b84ea014 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/1/Ports/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PortCollection.PortCollection", + "Name": "CXL Port Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/FabricAdapters/1/Ports/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL3/FabricAdapters/1/Ports", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/1/index.json b/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/1/index.json new file mode 100755 index 00000000..7be7dc40 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/1/index.json @@ -0,0 +1,31 @@ +{ + "@odata.type": "#FabricAdapter.v1_3_0.FabricAdapter", + "Id": "1", + "Name": "CXL Fabric Adapter 1", + "Description": "CXL Fabric Adapter for memory system", + "Manufacturer": "Contoso", + "Model": "CXL Fabric Adapter Model X", + "PartNumber": "975999-001", + "SparePartNumber": "152111-A01", + "SKU": "Contoso 2-port CXL Adapter Bridge", + "SerialNumber": "2M220100SL", + "FirmwareVersion": "7.4.10", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "Ports": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/FabricAdapters/1/Ports" + }, + "Links": { + "MemoryDomains": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL3/FabricAdapters/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/index.json b/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/index.json new file mode 100755 index 00000000..2498cee9 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/FabricAdapters/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#FabricAdapterCollection.FabricAdapterCollection", + "Name": "Fabric Adapter Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/FabricAdapters/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL3/FabricAdapters", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/Memory/3DXP/index.json b/Resources/CXLAgent/Chassis/PCXL3/Memory/3DXP/index.json new file mode 100755 index 00000000..676ee162 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/Memory/3DXP/index.json @@ -0,0 +1,19 @@ +{ + "@odata.type": "#Memory.v1_15_0.Memory", + "Id": "3DXP", + "Name": "3DXP memory", + "MemoryType": "IntelOptane", + "MemoryMedia": [ + "Intel3DXPoint" + ], + "CapacityMiB": 16384, + "OperatingSpeedMhz": 1333, + "Status": { + "Health": "OK", + "State": "Enabled", + "HealthRollup": "OK" + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL3/Memory/3DXP", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/Memory/index.json b/Resources/CXLAgent/Chassis/PCXL3/Memory/index.json new file mode 100755 index 00000000..a996641a --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/Memory/index.json @@ -0,0 +1,13 @@ +{ + "@odata.type": "#MemoryCollection.MemoryCollection", + "Name": "Memory Collection", + "Description": "Memory Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/Memory/3DXP" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL3/Memory", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/1/index.json b/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/1/index.json new file mode 100755 index 00000000..54f71a85 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/1/index.json @@ -0,0 +1,30 @@ +{ + "@odata.type": "#MemoryChunks.v1_5_0.MemoryChunks", + "Id": "1", + "Name": "Memory Chunk 1", + "Description": "Memory chunk accessible through CXL fabric", + "Status": { + "State": "Enabled", + "Health": "OK" + }, + "MemoryChunkSizeMiB": 4096, + "AddressRangeType": "PMEM", + "AddressRangeOffsetMiB": 1024, + "MediaLocation": "Local", + "OperationalState": "Online", + "Links": { + "CXLLogicalDevices": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/1" + } + ], + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T3" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/index.json b/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/index.json new file mode 100755 index 00000000..f5f9ea67 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#MemoryChunksCollection.MemoryChunksCollection", + "Name": "Memory Chunks Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1/MemoryChunks", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/1/index.json b/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/1/index.json new file mode 100755 index 00000000..61e0a2fa --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/1/index.json @@ -0,0 +1,46 @@ +{ + "@odata.type": "#MemoryDomain.v1_4_0.MemoryDomain", + "Id": "1", + "Name": "CXL 3DXP Memory Domain", + "Description": "3DXP Memory Domain accessible through CXL fabric", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "MemoryChunks": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1/MemoryChunks" + }, + "AllowsMemoryChunkCreation": true, + "MinMemoryChunkSizeMiB": 64, + "MemoryChunkIncrementMiB": 64, + "InterleavableMemorySets": [ + { + "MemorySet": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/Memory/3DXP" + } + ] + } + ], + "Links": { + "FabricAdapters": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/FabricAdapters/1" + } + ], + "CXLLogicalDevices": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/1" + } + ], + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/index.json b/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/index.json new file mode 100755 index 00000000..c4b81a5b --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/MemoryDomains/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#MemoryDomainCollection.MemoryDomainCollection", + "Name": "Memory Domain Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/1/index.json b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/1/index.json new file mode 100755 index 00000000..12482c41 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/1/index.json @@ -0,0 +1,50 @@ +{ + "@odata.type": "#CXLLogicalDevice.v1_0_0.CXLLogicalDevice", + "Id": "1", + "Name": "CXL Logical Device Type 3", + "Description": "CXL Logical Device Type 3 accessible through CXL fabric", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "Identifiers": [ + { + "DurableName": "4C-1D-96-FF-FE-DD-D8-35:1", + "DurableNameFormat": "GCXLID" + } + ], + "CXLSemanticsSupported": [ + "CXLio", + "CXLmem" + ], + "Links": { + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1" + }, + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions/1" + } + ], + "MemoryChunks": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/1" + } + ], + "MemoryDomains": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1" + } + ], + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T3" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/index.json b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/index.json new file mode 100755 index 00000000..9c290e1c --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#CXLLogicalDeviceCollection.CXLLogicalDeviceCollection", + "Name": "CXL Logical Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions/1/index.json b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions/1/index.json new file mode 100755 index 00000000..54f857ce --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions/1/index.json @@ -0,0 +1,37 @@ +{ + "@odata.type": "#PCIeFunction.v1_4_0.PCIeFunction", + "Id": "1", + "Name": "CXL Function", + "Description": "PCIe Function with CXL extensions representing Memory Controller", + "FunctionId": 1, + "FunctionType": "Physical", + "DeviceClass": "MemoryController", + "DeviceId": "0xABCD", + "VendorId": "0xABCD", + "ClassCode": "0x050210", + "RevisionId": "0x00", + "SubsystemId": "0xABCD", + "SubsystemVendorId": "0xABCD", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "FunctionProtocol": "CXL", + "Links": { + "MemoryControllers": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1" + } + ], + "CXLLogicalDevice": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/1" + }, + "PCIeDevice": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1" + } + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions/index.json b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions/index.json new file mode 100755 index 00000000..6a9cbefc --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeFunctionCollection.PCIeFunctionCollection", + "Name": "PCIe Function Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/index.json b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/index.json new file mode 100755 index 00000000..a50b8b23 --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/1/index.json @@ -0,0 +1,40 @@ +{ + "@odata.type": "#PCIeDevice.v1_10_0.PCIeDevice", + "Id": "1", + "Name": "CXL Device", + "Description": "CXL Physcial Device Type 3", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeInterface": { + "PCIeType": "Gen5", + "MaxPCIeType": "Gen5", + "LanesInUse": 8, + "MaxLanes": 16 + }, + "PCIeFunctions": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/PCIeFunctions" + }, + "CXLDevice":{ + "CurrentProtocolVersion": "V2_0", + "CapableProtocolVersion": "V2_0", + "DeviceType": "Type3", + "MultiLogicalDevice": true + }, + "CXLLogicalDevices": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices" + }, + "Links": { + "Chassis": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3" + } + ], + "Oem": {} + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/index.json b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/index.json new file mode 100755 index 00000000..99f0010f --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/PCIeDevices/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#PCIeDeviceCollection.PCIeDeviceCollection", + "Name": "PCIe Device Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1" + } + ], + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/PCXL3/index.json b/Resources/CXLAgent/Chassis/PCXL3/index.json new file mode 100755 index 00000000..168c15ed --- /dev/null +++ b/Resources/CXLAgent/Chassis/PCXL3/index.json @@ -0,0 +1,27 @@ +{ + "@odata.type": "#Chassis.v1_20_0.Chassis", + "Id": "PCXL3", + "Name": "Pooled CXL Device Type 3 chassis", + "PowerState": "On", + "ChassisType": "Module", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PCIeDevices": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices" + }, + "FabricAdapters": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/FabricAdapters" + }, + "Memory": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/Memory" + }, + "MemoryDomains": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains" + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Chassis/PCXL3", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Chassis/index.json b/Resources/CXLAgent/Chassis/index.json new file mode 100755 index 00000000..c7f0ceea --- /dev/null +++ b/Resources/CXLAgent/Chassis/index.json @@ -0,0 +1,30 @@ +{ + "@odata.type": "#ChassisCollection.ChassisCollection", + "Name": "Chassis Collection", + "Members@odata.count": 7, + "Members": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL-Chassis" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL1" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL2" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL3" + }, + { + "@odata.id": "/redfish/v1/Chassis/PCXL1" + }, + { + "@odata.id": "/redfish/v1/Chassis/PCXL2" + }, + { + "@odata.id": "/redfish/v1/Chassis/PCXL3" + } + ], + "@odata.id": "/redfish/v1/Chassis", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} \ No newline at end of file diff --git a/Resources/CXLAgent/Fabrics/CXL/Connections/12/index.json b/Resources/CXLAgent/Fabrics/CXL/Connections/12/index.json new file mode 100755 index 00000000..cf7ff7ef --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Connections/12/index.json @@ -0,0 +1,37 @@ +{ + "@odata.type": "#Connection.v1_1_0.Connection", + "Id": "12", + "Name": "Connection 12", + "Description": "CXL Connection 12 Information", + "ConnectionType": "Memory", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "MemoryChunkInfo": [ + { + "AccessCapabilities": [ + "Read", + "Write" + ], + "MemoryChunk": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/1" + } + } + ], + "Links": { + "InitiatorEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I2" + } + ], + "TargetEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T2" + } + ] + }, + "@odata.id": "/redfish/v1/Fabrics/CXL/Connections/12", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Connections/13/index.json b/Resources/CXLAgent/Fabrics/CXL/Connections/13/index.json new file mode 100755 index 00000000..2c8b30ca --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Connections/13/index.json @@ -0,0 +1,37 @@ +{ + "@odata.type": "#Connection.v1_1_0.Connection", + "Id": "13", + "Name": "Connection 13", + "Description": "CXL Connection 13 Information", + "ConnectionType": "Memory", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "MemoryChunkInfo": [ + { + "AccessCapabilities": [ + "Read", + "Write" + ], + "MemoryChunk": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/1" + } + } + ], + "Links": { + "InitiatorEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I3" + } + ], + "TargetEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T3" + } + ] + }, + "@odata.id": "/redfish/v1/Fabrics/CXL/Connections/13", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Connections/index.json b/Resources/CXLAgent/Fabrics/CXL/Connections/index.json new file mode 100755 index 00000000..13df61c4 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Connections/index.json @@ -0,0 +1,15 @@ +{ + "@odata.type": "#ConnectionCollection.ConnectionCollection", + "Name": "CXL Connection Collection", + "Members@odata.count": 2, + "Members": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Connections/12" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Connections/13" + } + ], + "@odata.id": "/redfish/v1/Fabrics/CXL/Connections", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Endpoints/1/index.json b/Resources/CXLAgent/Fabrics/CXL/Endpoints/1/index.json new file mode 100755 index 00000000..ed5f3812 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Endpoints/1/index.json @@ -0,0 +1,19 @@ +{ + "@odata.type": "#Endpoint.v1_7_0.Endpoint", + "Id": "1", + "Name": "CXL Switch", + "Description": "CXL Switch endpoint", + "EndpointProtocol": "CXL", + "ConnectedEntities": [ + { + "EntityType": "Switch", + "EntityRole": "Target", + "EntityLink": { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL" + } + } + ], + "Oem": { }, + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Endpoints/I1/index.json b/Resources/CXLAgent/Fabrics/CXL/Endpoints/I1/index.json new file mode 100755 index 00000000..19d11a1d --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Endpoints/I1/index.json @@ -0,0 +1,37 @@ +{ + "@odata.type": "#Endpoint.v1_7_0.Endpoint", + "Id": "I1", + "Name": "CXL-System Initiator", + "Description": "CXL-System Initiator Endpoint for remote Type 1 CXL device ", + "EndpointProtocol": "CXL", + "ConnectedEntities": [ + { + "EntityType": "Processor", + "EntityRole": "Initiator", + "Identifiers": [ + { + "DurableName": "86D53A7B-D29A-3287-BA23-EF43A27BC6B9", + "DurableNameFormat": "UUID" + } + ], + "EntityLink": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU" + } + } + ], + "Links": { + "Ports": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU/Ports/1" + } + ], + "Zones": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Endpoints/I2/index.json b/Resources/CXLAgent/Fabrics/CXL/Endpoints/I2/index.json new file mode 100755 index 00000000..ed28214b --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Endpoints/I2/index.json @@ -0,0 +1,49 @@ +{ + "@odata.type": "#Endpoint.v1_7_0.Endpoint", + "Id": "I2", + "Name": "CXL-System Initiator", + "Description": "CXL-System Initiator Endpoint for remote Type 2 CXL device ", + "EndpointProtocol": "CXL", + "ConnectedEntities": [ + { + "EntityType": "Processor", + "EntityRole": "Initiator", + "Identifiers": [ + { + "DurableName": "86D53A7B-D29A-3287-BA23-EF43A27BC6B9", + "DurableNameFormat": "UUID" + } + ], + "EntityLink": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU" + } + }, + { + "EntityType": "Memory", + "EntityRole": "Initiator", + "EntityLink": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL2" + } + } + ], + "Links": { + "Ports": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU/Ports/1" + } + ], + "Zones": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/2" + } + ], + "Connections": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Connections/12" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I2", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Endpoints/I3/index.json b/Resources/CXLAgent/Fabrics/CXL/Endpoints/I3/index.json new file mode 100755 index 00000000..1e664e64 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Endpoints/I3/index.json @@ -0,0 +1,49 @@ +{ + "@odata.type": "#Endpoint.v1_7_0.Endpoint", + "Id": "I3", + "Name": "CXL-System Initiator", + "Description": "CXL-System Initiator Endpoint for remote Type 3 CXL device ", + "EndpointProtocol": "CXL", + "ConnectedEntities": [ + { + "EntityType": "Processor", + "EntityRole": "Initiator", + "Identifiers": [ + { + "DurableName": "86D53A7B-D29A-3287-BA23-EF43A27BC6B9", + "DurableNameFormat": "UUID" + } + ], + "EntityLink": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU" + } + }, + { + "EntityType": "Memory", + "EntityRole": "Initiator", + "EntityLink": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL3" + } + } + ], + "Links": { + "Ports": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU/Ports/1" + } + ], + "Zones": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/3" + } + ], + "Connections": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Connections/13" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I3", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Endpoints/T1/index.json b/Resources/CXLAgent/Fabrics/CXL/Endpoints/T1/index.json new file mode 100755 index 00000000..c34d374f --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Endpoints/T1/index.json @@ -0,0 +1,44 @@ +{ + "@odata.type": "#Endpoint.v1_7_0.Endpoint", + "Id": "T1", + "Name": "CXL Device Type 1 endpoint", + "Description": "CXL Device Type 1 target endpoint", + "EndpointProtocol": "CXL", + "ConnectedEntities": [ + { + "EntityType": "CXLDevice", + "EntityRole": "Target", + "Identifiers": [ + { + "DurableName": "4C-1D-96-FF-FE-DD-D8-35:1", + "DurableNameFormat": "GCXLID" + } + ], + "EntityLink": { + "@odata.id": "/redfish/v1/Chassis/PCXL1/PCIeDevices/1/CXLLogicalDevices/1" + } + }, + { + "EntityType": "Processor", + "EntityRole": "Target", + "EntityLink": { + "@odata.id": "/redfish/v1/Chassis/PCXL1/Processors/FPGA" + } + } + ], + "Links": { + "Ports": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/FabricAdapters/1/Ports/1" + } + ], + "Zones": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Endpoints/T2/index.json b/Resources/CXLAgent/Fabrics/CXL/Endpoints/T2/index.json new file mode 100755 index 00000000..0e96bc7a --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Endpoints/T2/index.json @@ -0,0 +1,56 @@ +{ + "@odata.type": "#Endpoint.v1_7_0.Endpoint", + "Id": "T2", + "Name": "CXL Device Type 2 endpoint", + "Description": "CXL Device Type 2 target endpoint", + "EndpointProtocol": "CXL", + "ConnectedEntities": [ + { + "EntityType": "CXLDevice", + "EntityRole": "Target", + "Identifiers": [ + { + "DurableName": "4C-1D-96-FF-FE-DD-D8-35:1", + "DurableNameFormat": "GCXLID" + } + ], + "EntityLink": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/PCIeDevices/1/CXLLogicalDevices/1" + } + }, + { + "EntityType": "Processor", + "EntityRole": "Target", + "EntityLink": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/Processors/GPU" + } + }, + { + "EntityType": "MemoryChunk", + "EntityRole": "Target", + "EntityLink": { + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/1" + } + } + ], + "Links": { + "Ports": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters/1/Ports/1" + } + ], + "Zones": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/2" + } + ], + "Connections": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Connections/12" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T2", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Endpoints/T3/index.json b/Resources/CXLAgent/Fabrics/CXL/Endpoints/T3/index.json new file mode 100755 index 00000000..e122bb00 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Endpoints/T3/index.json @@ -0,0 +1,49 @@ +{ + "@odata.type": "#Endpoint.v1_7_0.Endpoint", + "Id": "T3", + "Name": "CXL Device Type 3 endpoint", + "Description": "CXL Device Type 3 target endpoint", + "EndpointProtocol": "CXL", + "ConnectedEntities": [ + { + "EntityType": "CXLDevice", + "EntityRole": "Target", + "Identifiers": [ + { + "DurableName": "4C-1D-96-FF-FE-DD-D8-35:1", + "DurableNameFormat": "GCXLID" + } + ], + "EntityLink": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/PCIeDevices/1/CXLLogicalDevices/1" + } + }, + { + "EntityType": "MemoryChunk", + "EntityRole": "Target", + "EntityLink": { + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/1" + } + } + ], + "Links": { + "Ports": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/FabricAdapters/1/Ports/1" + } + ], + "Zones": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/3" + } + ], + "Connections": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Connections/13" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T3", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Endpoints/index.json b/Resources/CXLAgent/Fabrics/CXL/Endpoints/index.json new file mode 100755 index 00000000..8bdae0fd --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Endpoints/index.json @@ -0,0 +1,30 @@ +{ + "@odata.type": "#EndpointCollection.EndpointCollection", + "Name": "CXL Endpoint Collection", + "Members@odata.count": 7, + "Members": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I1" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T1" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I2" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T2" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I3" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T3" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/1" + } + ], + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D1/index.json b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D1/index.json new file mode 100755 index 00000000..8f9f4307 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D1/index.json @@ -0,0 +1,43 @@ +{ + "@odata.type": "#Port.v1_7_0.Port", + "Id": "D1", + "Name": "CXL Port 1", + "Description": "CXL Downstream Port 1 in switch", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PortId": "D1", + "RemotePortId": "4C-1D-96-FF-FE-DD-D8-D1", + "PortProtocol": "CXL", + "CurrentProtocolVersion": "2.0", + "CapableProtocolVersions": [ + "1.1", "2.0" + ], + "PortType": "DownstreamPort", + "PortMedium": "Optical", + "CurrentSpeedGbps": 256, + "Width": 8, + "MaxSpeedGbps": 512, + "ActiveWidth": 16, + "LinkState": "Enabled", + "LinkStatus": "LinkUp", + "InterfaceEnabled": true, + "LinkNetworkTechnology": "PCIe", + "Links": { + "AssociatedEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T1" + } + ], + "ConnectedPorts": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL1/FabricAdapters/1/Ports/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/D1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D2/index.json b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D2/index.json new file mode 100755 index 00000000..43857c1d --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D2/index.json @@ -0,0 +1,43 @@ +{ + "@odata.type": "#Port.v1_7_0.Port", + "Id": "D2", + "Name": "CXL Port 2", + "Description": "CXL Downstream Port 2 in switch", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PortId": "D2", + "RemotePortId": "4C-1D-96-FF-FE-DD-D8-D2", + "PortProtocol": "CXL", + "CurrentProtocolVersion": "2.0", + "CapableProtocolVersions": [ + "1.1", "2.0" + ], + "PortType": "DownstreamPort", + "PortMedium": "Optical", + "CurrentSpeedGbps": 256, + "Width": 8, + "MaxSpeedGbps": 512, + "ActiveWidth": 16, + "LinkState": "Enabled", + "LinkStatus": "LinkUp", + "InterfaceEnabled": true, + "LinkNetworkTechnology": "PCIe", + "Links": { + "AssociatedEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T2" + } + ], + "ConnectedPorts": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/FabricAdapters/1/Ports/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/D2", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D3/index.json b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D3/index.json new file mode 100755 index 00000000..34f309a9 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/D3/index.json @@ -0,0 +1,43 @@ +{ + "@odata.type": "#Port.v1_7_0.Port", + "Id": "D3", + "Name": "CXL Port 3", + "Description": "CXL Downstream Port 3 in switch", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PortId": "D3", + "RemotePortId": "4C-1D-96-FF-FE-DD-D8-D3", + "PortProtocol": "CXL", + "CurrentProtocolVersion": "2.0", + "CapableProtocolVersions": [ + "1.1", "2.0" + ], + "PortType": "DownstreamPort", + "PortMedium": "Optical", + "CurrentSpeedGbps": 256, + "Width": 8, + "MaxSpeedGbps": 512, + "ActiveWidth": 16, + "LinkState": "Enabled", + "LinkStatus": "LinkUp", + "InterfaceEnabled": true, + "LinkNetworkTechnology": "PCIe", + "Links": { + "AssociatedEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T3" + } + ], + "ConnectedPorts": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/FabricAdapters/1/Ports/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/D3", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/U1/index.json b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/U1/index.json new file mode 100755 index 00000000..b3ada9f0 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/U1/index.json @@ -0,0 +1,49 @@ +{ + "@odata.type": "#Port.v1_7_0.Port", + "Id": "U1", + "Name": "CXL Port 1", + "Description": "CXL Upstream Port 1 in switch", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PortId": "4C-1D-96-FF-FE-DD-D8-D0", + "RemotePortId": "1", + "PortProtocol": "CXL", + "CurrentProtocolVersion": "2.0", + "CapableProtocolVersions": [ + "1.1", "2.0" + ], + "PortType": "UpstreamPort", + "PortMedium": "Optical", + "CurrentSpeedGbps": 512, + "Width": 16, + "MaxSpeedGbps": 512, + "ActiveWidth": 16, + "LinkState": "Enabled", + "LinkStatus": "LinkUp", + "InterfaceEnabled": true, + "LinkNetworkTechnology": "PCIe", + "Links": { + "AssociatedEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I1" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I2" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I3" + } + ], + "ConnectedPorts": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU/Ports/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/U1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/index.json b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/index.json new file mode 100755 index 00000000..ab40ea60 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/Ports/index.json @@ -0,0 +1,22 @@ +{ + "@odata.type": "#PortCollection.PortCollection", + "Name": "CXL Port Collection", + "Members@odata.count": 4, + "Members": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/U1" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/D1" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/D2" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/D3" + } + ], + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/index.json b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/index.json new file mode 100755 index 00000000..67a3d70d --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Switches/CXL/index.json @@ -0,0 +1,25 @@ +{ + "@odata.type": "#Switch.v1_7_0.Switch", + "Id": "CXL", + "Name": "CXL Switch", + "SwitchType": "CXL", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "UUID": "1ad59fe9-49f9-52fa-9a93-e349f9477fe0", + "Ports": { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports" + } , + "Links": { + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/1" + } + ] + }, + "Oem": { }, + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Switches/index.json b/Resources/CXLAgent/Fabrics/CXL/Switches/index.json new file mode 100755 index 00000000..19d2555a --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Switches/index.json @@ -0,0 +1,10 @@ +{ + "@odata.type": "#SwitchCollection.SwitchCollection", + "Name": "Switch Collection", + "Members@odata.count": 1, + "Members": [ + { "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL" } + ], + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Zones/1/index.json b/Resources/CXLAgent/Fabrics/CXL/Zones/1/index.json new file mode 100755 index 00000000..d6ace804 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Zones/1/index.json @@ -0,0 +1,27 @@ +{ + "@odata.type": "#Zone.v1_6_1.Zone", + "Id": "1", + "Name": "CXL Zone 1", + "Description": "CXL Zone 1", + "Status": { + "State": "Enabled", + "Health": "OK" + }, + "ZoneType": "ZoneOfEndpoints", + "Links": { + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I1" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T1" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Zones/2/index.json b/Resources/CXLAgent/Fabrics/CXL/Zones/2/index.json new file mode 100755 index 00000000..a9ff68b8 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Zones/2/index.json @@ -0,0 +1,27 @@ +{ + "@odata.type": "#Zone.v1_6_1.Zone", + "Id": "2", + "Name": "CXL Zone 2", + "Description": "CXL Zone 2", + "Status": { + "State": "Enabled", + "Health": "OK" + }, + "ZoneType": "ZoneOfEndpoints", + "Links": { + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I2" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T2" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/2", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Zones/3/index.json b/Resources/CXLAgent/Fabrics/CXL/Zones/3/index.json new file mode 100755 index 00000000..8cbe3d18 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Zones/3/index.json @@ -0,0 +1,27 @@ +{ + "@odata.type": "#Zone.v1_6_1.Zone", + "Id": "3", + "Name": "CXL Zone 3", + "Description": "CXL Zone 3", + "Status": { + "State": "Enabled", + "Health": "OK" + }, + "ZoneType": "ZoneOfEndpoints", + "Links": { + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I3" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T3" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/3", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/Zones/index.json b/Resources/CXLAgent/Fabrics/CXL/Zones/index.json new file mode 100755 index 00000000..702d8e93 --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/Zones/index.json @@ -0,0 +1,18 @@ +{ + "@odata.type": "#ZoneCollection.ZoneCollection", + "Name": "CXL Fabric Zone Collection", + "Members@odata.count": 3, + "Members": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/1" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/2" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones/3" + } + ], + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/CXL/index.json b/Resources/CXLAgent/Fabrics/CXL/index.json new file mode 100755 index 00000000..44b2baea --- /dev/null +++ b/Resources/CXLAgent/Fabrics/CXL/index.json @@ -0,0 +1,26 @@ +{ + "@odata.type": "#Fabric.v1_2_2.Fabric", + "Id": "CXL", + "Name": "CXL Fabric", + "Description": "CXL Fabric", + "FabricType": "CXL", + "Status": { + "State": "Enabled", + "Health": "OK" + }, + "Switches": { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches" + }, + "Connections": { + "@odata.id": "/redfish/v1/Fabrics/CXL/Connections" + }, + "Endpoints": { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints" + }, + "Zones": { + "@odata.id": "/redfish/v1/Fabrics/CXL/Zones" + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Fabrics/CXL", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Fabrics/index.json b/Resources/CXLAgent/Fabrics/index.json new file mode 100755 index 00000000..4b5022ff --- /dev/null +++ b/Resources/CXLAgent/Fabrics/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#FabricCollection.FabricCollection", + "Name": "Fabric Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL" + } + ], + "@odata.id": "/redfish/v1/Fabrics", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} \ No newline at end of file diff --git a/Resources/CXLAgent/Systems/CXL-System/Memory/CXL2/index.json b/Resources/CXLAgent/Systems/CXL-System/Memory/CXL2/index.json new file mode 100755 index 00000000..fd9f099b --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/Memory/CXL2/index.json @@ -0,0 +1,22 @@ +{ + "@odata.type": "#Memory.v1_15_0.Memory", + "Id": "CXL2", + "Name": "CXL Device memory", + "Description": "Local CXL device memory", + "Status": { + "Health": "OK", + "State": "Enabled", + "HealthRollup": "OK" + }, + "CapacityMiB": 4096, + "MemoryMedia": [ + "CXL" + ], + "MemoryMediaSources": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1/MemoryChunks/1" + } + ], + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/CXL2", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/Memory/CXL3/index.json b/Resources/CXLAgent/Systems/CXL-System/Memory/CXL3/index.json new file mode 100755 index 00000000..7afad8be --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/Memory/CXL3/index.json @@ -0,0 +1,22 @@ +{ + "@odata.type": "#Memory.v1_15_0.Memory", + "Id": "CXL3", + "Name": "CXL Device memory", + "Description": "Local CXL device memory", + "Status": { + "Health": "OK", + "State": "Enabled", + "HealthRollup": "OK" + }, + "CapacityMiB": 4096, + "MemoryMedia": [ + "CXL" + ], + "MemoryMediaSources": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL3/MemoryDomains/1/MemoryChunks/1" + } + ], + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/CXL3", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/Memory/RCXL2/index.json b/Resources/CXLAgent/Systems/CXL-System/Memory/RCXL2/index.json new file mode 100755 index 00000000..e58585ab --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/Memory/RCXL2/index.json @@ -0,0 +1,29 @@ +{ + "@odata.type": "#Memory.v1_15_0.Memory", + "Id": "RCXL2", + "Name": "CXL Device memory", + "Description": "Remote CXL device memory", + "Status": { + "Health": "OK", + "State": "Enabled", + "HealthRollup": "OK" + }, + "CapacityMiB": 4096, + "MemoryMedia": [ + "Fabric" + ], + "MemoryMediaSources": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL2/MemoryDomains/1/MemoryChunks/1" + } + ], + "Links": { + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I2" + } + ] + }, + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL2", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/Memory/RCXL3/index.json b/Resources/CXLAgent/Systems/CXL-System/Memory/RCXL3/index.json new file mode 100755 index 00000000..695b5e2f --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/Memory/RCXL3/index.json @@ -0,0 +1,29 @@ +{ + "@odata.type": "#Memory.v1_15_0.Memory", + "Id": "RCXL3", + "Name": "CXL Device memory", + "Description": "Remote CXL device memory", + "Status": { + "Health": "OK", + "State": "Enabled", + "HealthRollup": "OK" + }, + "CapacityMiB": 4096, + "MemoryMedia": [ + "Fabric" + ], + "MemoryMediaSources": [ + { + "@odata.id": "/redfish/v1/Chassis/PCXL3/MemoryDomains/1/MemoryChunks/1" + } + ], + "Links": { + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I3" + } + ] + }, + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL3", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/Memory/index.json b/Resources/CXLAgent/Systems/CXL-System/Memory/index.json new file mode 100755 index 00000000..5c145c66 --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/Memory/index.json @@ -0,0 +1,22 @@ +{ + "@odata.type": "#MemoryCollection.MemoryCollection", + "Name": "Memory Collection", + "Description": "Memory Collection", + "Members@odata.count": 4, + "Members": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/CXL2" + }, + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/CXL3" + }, + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL2" + }, + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL3" + } + ], + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks/1/index.json b/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks/1/index.json new file mode 100755 index 00000000..c70d799f --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks/1/index.json @@ -0,0 +1,40 @@ +{ + "@odata.type": "#MemoryChunks.v1_5_0.MemoryChunks", + "Id": "1", + "Name": "Memory Chunk 1", + "Description": "All CXL Memory chunk", + "Status": { + "State": "Enabled", + "Health": "OK" + }, + "MemoryChunkSizeMiB": 16384, + "AddressRangeType": "Volatile", + "AddressRangeOffsetMiB": 65536, + "MediaLocation": "Mixed", + "OperationalState": "Online", + "InterleaveSets": [ + { + "Memory": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/CXL2" + } + }, + { + "Memory": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/CXL3" + } + }, + { + "Memory": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL2" + } + }, + { + "Memory": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL3" + } + } + ], + "Oem": {}, + "@odata.id": "/redfish/v1/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks/index.json b/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks/index.json new file mode 100755 index 00000000..bc885437 --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks/index.json @@ -0,0 +1,13 @@ +{ + "@odata.type": "#MemoryChunksCollection.MemoryChunksCollection", + "Name": "Memory Chunks Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks/1" + } + ], + "Oem": {}, + "@odata.id": "/redfish/v1/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/index.json b/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/index.json new file mode 100755 index 00000000..868dfe20 --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/CXL/index.json @@ -0,0 +1,38 @@ +{ + "@odata.type": "#MemoryDomain.v1_4_0.MemoryDomain", + "Id": "CXL", + "Name": "CXL Memory Domain", + "Description": "Local and Remote CXL Memory Domain", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "MemoryChunks": { + "@odata.id": "/redfish/v1/Systems/CXL-System/MemoryDomains/CXL/MemoryChunks" + }, + "AllowsMemoryChunkCreation": true, + "MinMemoryChunkSizeMiB": 64, + "MemoryChunkIncrementMiB": 64, + "InterleavableMemorySets": [ + { + "MemorySet": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/CXL2" + }, + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/CXL3" + }, + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL2" + }, + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL3" + } + ] + } + ], + "Oem": {}, + "@odata.id": "/redfish/v1/Systems/CXL-System/MemoryDomains/CXL", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/index.json b/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/index.json new file mode 100755 index 00000000..5c7c12f0 --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/MemoryDomains/index.json @@ -0,0 +1,13 @@ +{ + "@odata.type": "#MemoryDomainCollection.MemoryDomainCollection", + "Name": "Memory Domain Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/MemoryDomains/CXL" + } + ], + "Oem": {}, + "@odata.id": "/redfish/v1/Systems/CXL-System/MemoryDomains", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/Processors/CPU/Ports/1/index.json b/Resources/CXLAgent/Systems/CXL-System/Processors/CPU/Ports/1/index.json new file mode 100755 index 00000000..a9e0d7ff --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/Processors/CPU/Ports/1/index.json @@ -0,0 +1,54 @@ +{ + "@odata.type": "#Port.v1_7_0.Port", + "Id": "1", + "Name": "CXL Port 1", + "Description": "CXL Port in CPU connected to CXL switch", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PortId": "1", + "RemotePortId": "4C-1D-96-FF-FE-DD-D8-D0", + "PortProtocol": "CXL", + "CurrentProtocolVersion": "2.0", + "CapableProtocolVersions": [ + "1.1", "2.0" + ], + "PortType": "DownstreamPort", + "PortMedium": "Optical", + "CurrentSpeedGbps": 512, + "Width": 16, + "MaxSpeedGbps": 512, + "ActiveWidth": 16, + "LinkState": "Enabled", + "LinkStatus": "LinkUp", + "InterfaceEnabled": true, + "LinkNetworkTechnology": "PCIe", + "Links": { + "AssociatedEndpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I1" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I2" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I3" + } + ], + "ConnectedSwitches": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL" + } + ], + "ConnectedSwitchPorts": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/U1" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU/Ports/1", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/Processors/CPU/Ports/index.json b/Resources/CXLAgent/Systems/CXL-System/Processors/CPU/Ports/index.json new file mode 100755 index 00000000..96e9fd12 --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/Processors/CPU/Ports/index.json @@ -0,0 +1,14 @@ +{ + "@odata.type": "#PortCollection.PortCollection", + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU/Ports", + "Name": "CXL Port Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU/Ports/1" + } + ], + "Oem": {}, + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU/Ports", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/Processors/CPU/index.json b/Resources/CXLAgent/Systems/CXL-System/Processors/CPU/index.json new file mode 100755 index 00000000..b3372e45 --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/Processors/CPU/index.json @@ -0,0 +1,56 @@ +{ + "@odata.type": "#Processor.v1_15_0.Processor", + "Id": "CPU", + "Name": "CPU with CXL ports", + "Description": "CPU with CXL ports", + "ProcessorType": "CPU", + "ProcessorArchitecture": "x86", + "InstructionSet": "x86-64", + "Manufacturer": "Intel(R) Corporation", + "UUID": "86D53A7B-D29A-3287-BA23-EF43A27BC6B9", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "Ports": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU/Ports" + }, + "Links": { + "ConnectedProcessors": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1/Processors/FPGA" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL2/Processors/GPU" + } + ], + "Memory": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/CXL2" + }, + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/CXL3" + }, + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL2" + }, + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory/RCXL3" + } + ], + "Endpoints": [ + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I1" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I2" + }, + { + "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I3" + } + ] + }, + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/Processors/index.json b/Resources/CXLAgent/Systems/CXL-System/Processors/index.json new file mode 100755 index 00000000..673d61e5 --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/Processors/index.json @@ -0,0 +1,18 @@ +{ + "@odata.type": "#ProcessorCollection.ProcessorCollection", + "Name": "Processors Collection", + "Members@odata.count": 3, + "Members": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL1/Processors/FPGA" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL2/Processors/GPU" + } + ], + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/CXL-System/index.json b/Resources/CXLAgent/Systems/CXL-System/index.json new file mode 100755 index 00000000..e535de06 --- /dev/null +++ b/Resources/CXLAgent/Systems/CXL-System/index.json @@ -0,0 +1,61 @@ +{ + "@odata.type": "#ComputerSystem.v1_16_0.ComputerSystem", + "Id": "CXL-System", + "Name": "CXL System", + "Description": "CXL System supporting local and remote CXL devices", + "SystemType": "Physical", + "UUID": "68D5E212-165B-4CA0-909B-C86B9CEE0112", + "Status": { + "State": "Enabled", + "Health": "OK", + "HealthRollup": "OK" + }, + "PowerState": "On", + "ProcessorSummary": { + "Count": 3 + }, + "MemorySummary": { + "TotalSystemMemoryGiB": 36 + }, + "Processors": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Processors" + }, + "Memory": { + "@odata.id": "/redfish/v1/Systems/CXL-System/Memory" + }, + "MemoryDomains": { + "@odata.id": "/redfish/v1/Systems/CXL-System/MemoryDomains" + }, + "PCIeDevices": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1" + } + ], + "PCIeFunctions": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/PCIeFunctions/1" + }, + { + "@odata.id": "/redfish/v1/Chassis/CXL3/PCIeDevices/1/PCIeFunctions/1" + } + ], + "Links": { + "Chassis": [ + { + "@odata.id": "/redfish/v1/Chassis/CXL-Chassis" + } + ] + }, + "Oem": {}, + "@odata.id": "/redfish/v1/Systems/CXL-System", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} diff --git a/Resources/CXLAgent/Systems/index.json b/Resources/CXLAgent/Systems/index.json new file mode 100755 index 00000000..a6aac9af --- /dev/null +++ b/Resources/CXLAgent/Systems/index.json @@ -0,0 +1,12 @@ +{ + "@odata.type": "#ComputerSystemCollection.ComputerSystemCollection", + "Name": "Computer System Collection", + "Members@odata.count": 1, + "Members": [ + { + "@odata.id": "/redfish/v1/Systems/CXL-System" + } + ], + "@odata.id": "/redfish/v1/Systems", + "@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." +} \ No newline at end of file diff --git a/Resources/CXLAgent/index.json b/Resources/CXLAgent/index.json new file mode 100644 index 00000000..c6114167 --- /dev/null +++ b/Resources/CXLAgent/index.json @@ -0,0 +1,21 @@ +{ + "@odata.type": "#ServiceRoot.v1_14_0.ServiceRoot", + "Id": "RootService", + "Name": "Root Service", + "RedfishVersion": "1.14.0", + "UUID": "92384634-2938-2342-8820-489239905423", + "AggregationService": { + "@odata.id": "/redfish/v1/AggregationService" + }, + "Chassis": { + "@odata.id": "/redfish/v1/Chassis" + }, + "Fabrics": { + "@odata.id": "/redfish/v1/Fabrics" + }, + "Systems": { + "@odata.id": "/redfish/v1/Systems" + }, + "@odata.id": "/redfish/v1", + "@Redfish.Copyright": "Copyright 2015-2022 SNIA. All rights reserved." +}