From 3a0a0b2470d096797c06c2de953f882dd0d1698d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Date: Mon, 7 Jun 2021 18:41:20 +0200 Subject: [PATCH] plat-sam: move pl310 related code to its own file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup main.c by moving pl310 code to sam_pl310.c file. Signed-off-by: Clément Léger Acked-by: Jerome Forissier Acked-by: Etienne Carriere --- core/arch/arm/plat-sam/main.c | 45 +------------ core/arch/arm/plat-sam/platform_config.h | 1 - core/arch/arm/plat-sam/sam_pl310.c | 80 ++++++++++++++++++++++++ core/arch/arm/plat-sam/sam_sfr.h | 16 +++++ core/arch/arm/plat-sam/sub.mk | 1 + 5 files changed, 99 insertions(+), 44 deletions(-) create mode 100644 core/arch/arm/plat-sam/sam_pl310.c create mode 100644 core/arch/arm/plat-sam/sam_sfr.h diff --git a/core/arch/arm/plat-sam/main.c b/core/arch/arm/plat-sam/main.c index a8e843a9332..a6584d22c5e 100644 --- a/core/arch/arm/plat-sam/main.c +++ b/core/arch/arm/plat-sam/main.c @@ -34,12 +34,12 @@ #include #include #include -#include #include #include #include #include #include +#include #include #include #include @@ -54,10 +54,9 @@ void console_init(void) register_serial_console(&console_data.chip); } -register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE); register_phys_mem_pgdir(MEM_AREA_IO_SEC, SFR_BASE, CORE_MMU_PGDIR_SIZE); -static vaddr_t sfr_base(void) +vaddr_t sam_sfr_base(void) { static void *va; @@ -69,46 +68,6 @@ static vaddr_t sfr_base(void) return SFR_BASE; } -enum ram_config {RAMC_SRAM = 0, RAMC_L2CC}; - -static void l2_sram_config(enum ram_config setting) -{ - if (setting == RAMC_L2CC) - io_write32(sfr_base() + SFR_L2CC_HRAMC, 0x1); - else - io_write32(sfr_base() + SFR_L2CC_HRAMC, 0x0); -} - -vaddr_t pl310_base(void) -{ - static void *va; - - if (cpu_mmu_enabled()) { - if (!va) - va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); - return (vaddr_t)va; - } - return PL310_BASE; -} - -void arm_cl2_config(vaddr_t pl310_base) -{ - io_write32(pl310_base + PL310_CTRL, 0); - l2_sram_config(RAMC_L2CC); - io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); - io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); - io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); - - /* invalidate all cache ways */ - arm_cl2_invbyway(pl310_base); -} - -void arm_cl2_enable(vaddr_t pl310_base) -{ - /* Enable PL310 ctrl -> only set lsb bit */ - io_write32(pl310_base + PL310_CTRL, 1); -} - register_phys_mem_pgdir(MEM_AREA_IO_SEC, AT91C_BASE_MATRIX32, CORE_MMU_PGDIR_SIZE); register_phys_mem_pgdir(MEM_AREA_IO_SEC, AT91C_BASE_MATRIX64, diff --git a/core/arch/arm/plat-sam/platform_config.h b/core/arch/arm/plat-sam/platform_config.h index e1b741d4754..1931727a06a 100644 --- a/core/arch/arm/plat-sam/platform_config.h +++ b/core/arch/arm/plat-sam/platform_config.h @@ -44,7 +44,6 @@ #define PL310_BASE (AT91C_BASE_L2CC) #define SFR_BASE (AT91C_BASE_SFR) -#define SFR_L2CC_HRAMC (0x58) /* * PL310 Auxiliary Control Register diff --git a/core/arch/arm/plat-sam/sam_pl310.c b/core/arch/arm/plat-sam/sam_pl310.c new file mode 100644 index 00000000000..b9123ea58c1 --- /dev/null +++ b/core/arch/arm/plat-sam/sam_pl310.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (C) 2017 Timesys Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE); + +enum ram_config {RAMC_SRAM = 0, RAMC_L2CC}; + +static void l2_sram_config(enum ram_config setting) +{ + vaddr_t sfr_base = sam_sfr_base(); + + if (setting == RAMC_L2CC) + io_write32(sfr_base + AT91_SFR_L2CC_HRAMC, 0x1); + else + io_write32(sfr_base + AT91_SFR_L2CC_HRAMC, 0x0); +} + +vaddr_t pl310_base(void) +{ + static void *va; + + if (cpu_mmu_enabled()) { + if (!va) + va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); + return (vaddr_t)va; + } + return PL310_BASE; +} + +void arm_cl2_config(vaddr_t pl310_base) +{ + io_write32(pl310_base + PL310_CTRL, 0); + l2_sram_config(RAMC_L2CC); + io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); + io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); + io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); + + /* invalidate all cache ways */ + arm_cl2_invbyway(pl310_base); +} + +void arm_cl2_enable(vaddr_t pl310_base) +{ + /* Enable PL310 ctrl -> only set lsb bit */ + io_write32(pl310_base + PL310_CTRL, 1); +} diff --git a/core/arch/arm/plat-sam/sam_sfr.h b/core/arch/arm/plat-sam/sam_sfr.h new file mode 100644 index 00000000000..295e23d59aa --- /dev/null +++ b/core/arch/arm/plat-sam/sam_sfr.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2021, Bootlin + */ + +#ifndef SAM_SFR_H +#define SAM_SFR_H + +#include + +/* L2 cache RAM used as an internal SRAM */ +#define AT91_SFR_L2CC_HRAMC 0x58 + +vaddr_t sam_sfr_base(void); + +#endif diff --git a/core/arch/arm/plat-sam/sub.mk b/core/arch/arm/plat-sam/sub.mk index bc0a46d27ab..060ddf4ffb5 100644 --- a/core/arch/arm/plat-sam/sub.mk +++ b/core/arch/arm/plat-sam/sub.mk @@ -1,3 +1,4 @@ global-incdirs-y += . srcs-y += main.c srcs-$(CFG_AT91_MATRIX) += matrix.c +srcs-$(CFG_PL310) += sam_pl310.c