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Add support for Xilinx UltraScale+ Zynq MPSoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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PLATFORM_FLAVOR ?= zcu102 | ||
PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) := y | ||
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# 32-bit flags | ||
arm32-platform-cpuarch := cortex-a53 | ||
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch) | ||
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch) | ||
arm32-platform-aflags += -mfpu=neon | ||
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$(call force,CFG_CDNS_UART,y) | ||
$(call force,CFG_GENERIC_BOOT,y) | ||
$(call force,CFG_GIC,y) | ||
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y) | ||
$(call force,CFG_PM_STUBS,y) | ||
$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) | ||
$(call force,CFG_WITH_ARM_TRUSTED_FW,y) | ||
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ta-targets = ta_arm32 | ||
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ifeq ($(CFG_ARM64_core),y) | ||
$(call force,CFG_WITH_LPAE,y) | ||
ta-targets += ta_arm64 | ||
else | ||
$(call force,CFG_ARM32_core,y) | ||
endif | ||
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CFG_TEE_CORE_EMBED_INTERNAL_TESTS ?= y | ||
CFG_TEE_FS_KEY_MANAGER_TEST ?= y | ||
CFG_WITH_STACK_CANARIES ?= y | ||
CFG_WITH_STATS ?= y | ||
CFG_CRYPTO_WITH_CE ?= y |
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#include "../kernel/kern.ld.S" |
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include core/arch/arm/kernel/link.mk |
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/* | ||
* Copyright (c) 2016, Xilinx Inc. | ||
* All rights reserved. | ||
* | ||
* Redistribution and use in source and binary forms, with or without | ||
* modification, are permitted provided that the following conditions are met: | ||
* | ||
* 1. Redistributions of source code must retain the above copyright notice, | ||
* this list of conditions and the following disclaimer. | ||
* | ||
* 2. Redistributions in binary form must reproduce the above copyright notice, | ||
* this list of conditions and the following disclaimer in the documentation | ||
* and/or other materials provided with the distribution. | ||
* | ||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE | ||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | ||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | ||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | ||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||
* POSSIBILITY OF SUCH DAMAGE. | ||
*/ | ||
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#include <platform_config.h> | ||
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#include <stdint.h> | ||
#include <string.h> | ||
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#include <drivers/gic.h> | ||
#include <drivers/cdns_uart.h> | ||
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#include <arm.h> | ||
#include <console.h> | ||
#include <kernel/generic_boot.h> | ||
#include <kernel/pm_stubs.h> | ||
#include <kernel/misc.h> | ||
#include <kernel/tee_time.h> | ||
#include <mm/core_memprot.h> | ||
#include <tee/entry_fast.h> | ||
#include <tee/entry_std.h> | ||
#include <trace.h> | ||
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static void main_fiq(void); | ||
static struct gic_data gic_data; | ||
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static const struct thread_handlers handlers = { | ||
.std_smc = tee_entry_std, | ||
.fast_smc = tee_entry_fast, | ||
.fiq = main_fiq, | ||
#if defined(CFG_WITH_ARM_TRUSTED_FW) | ||
.cpu_on = cpu_on_handler, | ||
.cpu_off = pm_do_nothing, | ||
.cpu_suspend = pm_do_nothing, | ||
.cpu_resume = pm_do_nothing, | ||
.system_off = pm_do_nothing, | ||
.system_reset = pm_do_nothing, | ||
#else | ||
.cpu_on = pm_panic, | ||
.cpu_off = pm_panic, | ||
.cpu_suspend = pm_panic, | ||
.cpu_resume = pm_panic, | ||
.system_off = pm_panic, | ||
.system_reset = pm_panic, | ||
#endif | ||
}; | ||
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const struct thread_handlers *generic_boot_get_handlers(void) | ||
{ | ||
return &handlers; | ||
} | ||
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void main_init_gic(void) | ||
{ | ||
vaddr_t gicc_base, gicd_base; | ||
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gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, | ||
MEM_AREA_IO_SEC); | ||
gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, | ||
MEM_AREA_IO_SEC); | ||
/* On ARMv8, GIC configuration is initialized in ARM-TF */ | ||
gic_init_base_addr(&gic_data, gicc_base, gicd_base); | ||
} | ||
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static void main_fiq(void) | ||
{ | ||
gic_it_handle(&gic_data); | ||
} | ||
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static vaddr_t console_base(void) | ||
{ | ||
static void *va; | ||
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if (cpu_mmu_enabled()) { | ||
if (!va) | ||
va = phys_to_virt(CONSOLE_UART_BASE, MEM_AREA_IO_SEC); | ||
return (vaddr_t)va; | ||
} | ||
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return CONSOLE_UART_BASE; | ||
} | ||
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void console_init(void) | ||
{ | ||
cdns_uart_init(console_base(), CONSOLE_UART_CLK_IN_HZ, | ||
CONSOLE_BAUDRATE); | ||
} | ||
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void console_putc(int ch) | ||
{ | ||
cdns_uart_putc(ch, console_base()); | ||
if (ch == '\n') | ||
cdns_uart_putc('\r', console_base()); | ||
} | ||
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void console_flush(void) | ||
{ | ||
cdns_uart_flush(console_base()); | ||
} |
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/* | ||
* Copyright (c) 2016, Xilinx Inc. | ||
* All rights reserved. | ||
* | ||
* Redistribution and use in source and binary forms, with or without | ||
* modification, are permitted provided that the following conditions are met: | ||
* | ||
* 1. Redistributions of source code must retain the above copyright notice, | ||
* this list of conditions and the following disclaimer. | ||
* | ||
* 2. Redistributions in binary form must reproduce the above copyright notice, | ||
* this list of conditions and the following disclaimer in the documentation | ||
* and/or other materials provided with the distribution. | ||
* | ||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE | ||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | ||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | ||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | ||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||
* POSSIBILITY OF SUCH DAMAGE. | ||
*/ | ||
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#ifndef PLATFORM_CONFIG_H | ||
#define PLATFORM_CONFIG_H | ||
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#define PLATFORM_FLAVOR_ID_zc1751_dc1 0 | ||
#define PLATFORM_FLAVOR_ID_zc1751_dc2 1 | ||
#define PLATFORM_FLAVOR_ID_zcu102 2 | ||
#define PLATFORM_FLAVOR_IS(flav) \ | ||
(PLATFORM_FLAVOR_ID_ ## flav == PLATFORM_FLAVOR) | ||
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/* Make stacks aligned to data cache line length */ | ||
#define STACK_ALIGNMENT 64 | ||
#define HEAP_SIZE (24 * 1024) | ||
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#ifdef CFG_WITH_PAGER | ||
#error "Pager not supported for zynqmp" | ||
#endif | ||
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#if PLATFORM_FLAVOR_IS(zc1751_dc1) || PLATFORM_FLAVOR_IS(zc1751_dc2) || \ | ||
PLATFORM_FLAVOR_IS(zcu102) | ||
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#define GIC_BASE 0xF9010000 | ||
#define UART0_BASE 0xFF000000 | ||
#define UART1_BASE 0xFF001000 | ||
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#define IT_UART0 53 | ||
#define IT_UART1 54 | ||
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#define UART0_CLK_IN_HZ 100000000 | ||
#define UART1_CLK_IN_HZ 100000000 | ||
#define CONSOLE_UART_BASE UART0_BASE | ||
#define IT_CONSOLE_UART IT_UART0 | ||
#define CONSOLE_UART_CLK_IN_HZ UART0_CLK_IN_HZ | ||
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#define DRAM0_BASE 0 | ||
#define DRAM0_SIZE 0x80000000 | ||
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/* Location of trusted dram */ | ||
#define TZDRAM_BASE 0x60000000 | ||
#define TZDRAM_SIZE 0x10000000 | ||
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#define CFG_SHMEM_START 0x70000000 | ||
#define CFG_SHMEM_SIZE 0x10000000 | ||
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#define GICD_OFFSET 0 | ||
#define GICC_OFFSET 0x20000 | ||
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#else | ||
#error "Unknown platform flavor" | ||
#endif | ||
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#define CFG_TEE_CORE_NB_CORE 4 | ||
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#define CFG_TEE_RAM_VA_SIZE (1024 * 1024) | ||
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#ifndef CFG_TEE_LOAD_ADDR | ||
#define CFG_TEE_LOAD_ADDR CFG_TEE_RAM_START | ||
#endif | ||
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/* | ||
* Assumes that either TZSRAM isn't large enough or TZSRAM doesn't exist, | ||
* everything is in TZDRAM. | ||
* +------------------+ | ||
* | | TEE_RAM | | ||
* + TZDRAM +---------+ | ||
* | | TA_RAM | | ||
* +--------+---------+ | ||
*/ | ||
#define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE | ||
#define CFG_TEE_RAM_START TZDRAM_BASE | ||
#define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \ | ||
CORE_MMU_DEVICE_SIZE) | ||
#define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \ | ||
CORE_MMU_DEVICE_SIZE) | ||
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#define DEVICE0_PA_BASE ROUNDDOWN(CONSOLE_UART_BASE, \ | ||
CORE_MMU_DEVICE_SIZE) | ||
#define DEVICE0_VA_BASE DEVICE0_PA_BASE | ||
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#define DEVICE0_SIZE CORE_MMU_DEVICE_SIZE | ||
#define DEVICE0_TYPE MEM_AREA_IO_NSEC | ||
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#define DEVICE1_PA_BASE ROUNDDOWN(GIC_BASE, CORE_MMU_DEVICE_SIZE) | ||
#define DEVICE1_VA_BASE DEVICE1_PA_BASE | ||
#define DEVICE1_SIZE CORE_MMU_DEVICE_SIZE | ||
#define DEVICE1_TYPE MEM_AREA_IO_SEC | ||
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#define DEVICE2_PA_BASE ROUNDDOWN(GIC_BASE + GICD_OFFSET, \ | ||
CORE_MMU_DEVICE_SIZE) | ||
#define DEVICE2_VA_BASE DEVICE2_PA_BASE | ||
#define DEVICE2_SIZE CORE_MMU_DEVICE_SIZE | ||
#define DEVICE2_TYPE MEM_AREA_IO_SEC | ||
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#ifndef UART_BAUDRATE | ||
#define UART_BAUDRATE 115200 | ||
#endif | ||
#ifndef CONSOLE_BAUDRATE | ||
#define CONSOLE_BAUDRATE UART_BAUDRATE | ||
#endif | ||
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/* For virtual platforms where there isn't a clock */ | ||
#ifndef CONSOLE_UART_CLK_IN_HZ | ||
#define CONSOLE_UART_CLK_IN_HZ 1 | ||
#endif | ||
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#endif /*PLATFORM_CONFIG_H*/ |
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global-incdirs-y += . | ||
srcs-y += main.c |