From dc57f5a0e8f3b502fc958bc64a5ec0b0f46ef11a Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Sun, 15 Nov 2015 11:05:18 -0800 Subject: [PATCH] Add support for ZynqMP Add support for Xilinx UltraScale+ Zynq MPSoC. Signed-off-by: Soren Brinkmann Reviewed-by: Joakim Bech Reviewed-by: Jerome Forissier Reviewed-by: Jens Wiklander --- MAINTAINERS.md | 1 + README.md | 1 + core/arch/arm/plat-zynqmp/conf.mk | 31 +++++ core/arch/arm/plat-zynqmp/kern.ld.S | 1 + core/arch/arm/plat-zynqmp/link.mk | 1 + core/arch/arm/plat-zynqmp/main.c | 122 ++++++++++++++++++ core/arch/arm/plat-zynqmp/platform_config.h | 133 ++++++++++++++++++++ core/arch/arm/plat-zynqmp/sub.mk | 2 + 8 files changed, 292 insertions(+) create mode 100644 core/arch/arm/plat-zynqmp/conf.mk create mode 100644 core/arch/arm/plat-zynqmp/kern.ld.S create mode 100644 core/arch/arm/plat-zynqmp/link.mk create mode 100644 core/arch/arm/plat-zynqmp/main.c create mode 100644 core/arch/arm/plat-zynqmp/platform_config.h create mode 100644 core/arch/arm/plat-zynqmp/sub.mk diff --git a/MAINTAINERS.md b/MAINTAINERS.md index eef8117166d..f3b08821932 100644 --- a/MAINTAINERS.md +++ b/MAINTAINERS.md @@ -18,3 +18,4 @@ for these platforms. | STMicroelectronics b2120 - h310 / h410|`Linaro `| | STMicroelectronics b2020-h416 |`Linaro `| | Texas Instruments DRA7xx |`Harinarayan Bhatta `| +| Xilinx Zynq UltraScale+ MPSOC |`Sören Brinkmann + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void main_fiq(void); +static struct gic_data gic_data; + +static const struct thread_handlers handlers = { + .std_smc = tee_entry_std, + .fast_smc = tee_entry_fast, + .fiq = main_fiq, +#if defined(CFG_WITH_ARM_TRUSTED_FW) + .cpu_on = cpu_on_handler, + .cpu_off = pm_do_nothing, + .cpu_suspend = pm_do_nothing, + .cpu_resume = pm_do_nothing, + .system_off = pm_do_nothing, + .system_reset = pm_do_nothing, +#else + .cpu_on = pm_panic, + .cpu_off = pm_panic, + .cpu_suspend = pm_panic, + .cpu_resume = pm_panic, + .system_off = pm_panic, + .system_reset = pm_panic, +#endif +}; + +const struct thread_handlers *generic_boot_get_handlers(void) +{ + return &handlers; +} + +void main_init_gic(void) +{ + vaddr_t gicc_base, gicd_base; + + gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, + MEM_AREA_IO_SEC); + gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, + MEM_AREA_IO_SEC); + /* On ARMv8, GIC configuration is initialized in ARM-TF */ + gic_init_base_addr(&gic_data, gicc_base, gicd_base); +} + +static void main_fiq(void) +{ + gic_it_handle(&gic_data); +} + +static vaddr_t console_base(void) +{ + static void *va; + + if (cpu_mmu_enabled()) { + if (!va) + va = phys_to_virt(CONSOLE_UART_BASE, MEM_AREA_IO_SEC); + return (vaddr_t)va; + } + + return CONSOLE_UART_BASE; +} + +void console_init(void) +{ + cdns_uart_init(console_base(), CONSOLE_UART_CLK_IN_HZ, + CONSOLE_BAUDRATE); +} + +void console_putc(int ch) +{ + cdns_uart_putc(ch, console_base()); + if (ch == '\n') + cdns_uart_putc('\r', console_base()); +} + +void console_flush(void) +{ + cdns_uart_flush(console_base()); +} diff --git a/core/arch/arm/plat-zynqmp/platform_config.h b/core/arch/arm/plat-zynqmp/platform_config.h new file mode 100644 index 00000000000..711c406a758 --- /dev/null +++ b/core/arch/arm/plat-zynqmp/platform_config.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2016, Xilinx Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PLATFORM_CONFIG_H +#define PLATFORM_CONFIG_H + +#define PLATFORM_FLAVOR_ID_zc1751_dc1 0 +#define PLATFORM_FLAVOR_ID_zc1751_dc2 1 +#define PLATFORM_FLAVOR_ID_zcu102 2 +#define PLATFORM_FLAVOR_IS(flav) \ + (PLATFORM_FLAVOR_ID_ ## flav == PLATFORM_FLAVOR) + +/* Make stacks aligned to data cache line length */ +#define STACK_ALIGNMENT 64 +#define HEAP_SIZE (24 * 1024) + +#ifdef CFG_WITH_PAGER +#error "Pager not supported for zynqmp" +#endif + +#if PLATFORM_FLAVOR_IS(zc1751_dc1) || PLATFORM_FLAVOR_IS(zc1751_dc2) || \ + PLATFORM_FLAVOR_IS(zcu102) + +#define GIC_BASE 0xF9010000 +#define UART0_BASE 0xFF000000 +#define UART1_BASE 0xFF001000 + +#define IT_UART0 53 +#define IT_UART1 54 + +#define UART0_CLK_IN_HZ 100000000 +#define UART1_CLK_IN_HZ 100000000 +#define CONSOLE_UART_BASE UART0_BASE +#define IT_CONSOLE_UART IT_UART0 +#define CONSOLE_UART_CLK_IN_HZ UART0_CLK_IN_HZ + +#define DRAM0_BASE 0 +#define DRAM0_SIZE 0x80000000 + +/* Location of trusted dram */ +#define TZDRAM_BASE 0x60000000 +#define TZDRAM_SIZE 0x10000000 + +#define CFG_SHMEM_START 0x70000000 +#define CFG_SHMEM_SIZE 0x10000000 + +#define GICD_OFFSET 0 +#define GICC_OFFSET 0x20000 + +#else +#error "Unknown platform flavor" +#endif + +#define CFG_TEE_CORE_NB_CORE 4 + +#define CFG_TEE_RAM_VA_SIZE (1024 * 1024) + +#ifndef CFG_TEE_LOAD_ADDR +#define CFG_TEE_LOAD_ADDR CFG_TEE_RAM_START +#endif + +/* + * Assumes that either TZSRAM isn't large enough or TZSRAM doesn't exist, + * everything is in TZDRAM. + * +------------------+ + * | | TEE_RAM | + * + TZDRAM +---------+ + * | | TA_RAM | + * +--------+---------+ + */ +#define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE +#define CFG_TEE_RAM_START TZDRAM_BASE +#define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \ + CORE_MMU_DEVICE_SIZE) +#define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \ + CORE_MMU_DEVICE_SIZE) + + +#define DEVICE0_PA_BASE ROUNDDOWN(CONSOLE_UART_BASE, \ + CORE_MMU_DEVICE_SIZE) +#define DEVICE0_VA_BASE DEVICE0_PA_BASE + +#define DEVICE0_SIZE CORE_MMU_DEVICE_SIZE +#define DEVICE0_TYPE MEM_AREA_IO_NSEC + +#define DEVICE1_PA_BASE ROUNDDOWN(GIC_BASE, CORE_MMU_DEVICE_SIZE) +#define DEVICE1_VA_BASE DEVICE1_PA_BASE +#define DEVICE1_SIZE CORE_MMU_DEVICE_SIZE +#define DEVICE1_TYPE MEM_AREA_IO_SEC + +#define DEVICE2_PA_BASE ROUNDDOWN(GIC_BASE + GICD_OFFSET, \ + CORE_MMU_DEVICE_SIZE) +#define DEVICE2_VA_BASE DEVICE2_PA_BASE +#define DEVICE2_SIZE CORE_MMU_DEVICE_SIZE +#define DEVICE2_TYPE MEM_AREA_IO_SEC + +#ifndef UART_BAUDRATE +#define UART_BAUDRATE 115200 +#endif +#ifndef CONSOLE_BAUDRATE +#define CONSOLE_BAUDRATE UART_BAUDRATE +#endif + +/* For virtual platforms where there isn't a clock */ +#ifndef CONSOLE_UART_CLK_IN_HZ +#define CONSOLE_UART_CLK_IN_HZ 1 +#endif + +#endif /*PLATFORM_CONFIG_H*/ diff --git a/core/arch/arm/plat-zynqmp/sub.mk b/core/arch/arm/plat-zynqmp/sub.mk new file mode 100644 index 00000000000..8ddc2fd45c3 --- /dev/null +++ b/core/arch/arm/plat-zynqmp/sub.mk @@ -0,0 +1,2 @@ +global-incdirs-y += . +srcs-y += main.c