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Update Secure Timer Registers with OPTEE #1728
Two months before I asked one question about running secure-only process without involving the normal world activities. In that post, I got a possible solution which is configuring the secure timer registers to raise secure interrupt for world switching.
Here are some results I got:
Then I add code for updating timer registers. After writing, I read the registers again:
As you can see, at the EL3 level it looks like I updated the registers correctly. However, once it's done and I generate the FIQ again, all the registers go back to the default 0 value.
I really don't have any idea about what the problem might be so I decided to put it out here and see if anyone else could help me out.
Thank you in advance. Any suggestion is welcome!
I define these functions as global functions and call them in the code I mentioned above.
If I understand you correctly you have to re-enable (setting
There is a good example of handling the secure timer interrupt in the Test Secure Payload Dispatcher (TSPD) service in ARM trusted firmware.
Implementation of handler is here https://github.com/ARM-software/arm-trusted-firmware/blob/master/bl32/tsp/tsp_timer.c#L42, pay attention on:
Hope it helps
Hi @igoropaniuk ,
Actually I have tried to re-enable the
In this case, I'm thinking maybe my write is lost or re-write by some part of the OPTEE-SPD but I can't find any related document to solve the issue.
Thank you for the reply.
I'm not sure I understand what actually you mean by "the interrupt handler is done and return to the normal world and switch back" (you are checking
BTW, did you receive in SW output error messages like "unhandled interrupt" etc:
@igoropaniuk , I add the code for updating
For the SW output error question, I did see the message during booting time after
Now I have changed my SP/SPD to the